Re: [PATCH v2 08/12] phy: tegra: xusb: t210: support wake and sleepwalk
Hi Thierry, Thanks for review. On 8/31/20 8:37 PM, Thierry Reding wrote: > On Mon, Aug 31, 2020 at 12:40:39PM +0800, JC Kuo wrote: >> This commit implements Tegra210 XUSB PADCTL wake and sleepwalk >> routines. Sleepwalk logic is in PMC (always-on) hardware block. >> PMC driver provides managed access to the sleepwalk registers >> via regmap framework. >> >> Signed-off-by: JC Kuo >> --- >> drivers/phy/tegra/xusb-tegra210.c | 1094 - >> 1 file changed, 1079 insertions(+), 15 deletions(-) >> >> diff --git a/drivers/phy/tegra/xusb-tegra210.c >> b/drivers/phy/tegra/xusb-tegra210.c >> index fe1ab440424d..1c03f4ec4b59 100644 >> --- a/drivers/phy/tegra/xusb-tegra210.c >> +++ b/drivers/phy/tegra/xusb-tegra210.c >> @@ -16,6 +16,8 @@ >> #include >> #include >> #include >> +#include >> +#include >> >> #include >> >> @@ -52,6 +54,20 @@ >> #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5)) >> #define XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED 0x7 >> >> +#define XUSB_PADCTL_ELPG_PROGRAM_0 0x20 >> +#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x)) >> +#define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7) >> +#define SS_PORT_WAKE_INTERRUPT_ENABLE(x)BIT((x) + 14) >> +#define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21) >> +#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28) >> +#define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30) >> +#define ALL_WAKE_EVENTS ( \ >> +USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \ >> +USB2_PORT_WAKEUP_EVENT(2) | USB2_PORT_WAKEUP_EVENT(3) | \ >> +SS_PORT_WAKEUP_EVENT(0) | SS_PORT_WAKEUP_EVENT(1) | \ >> +SS_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(3) | \ >> +USB2_HSIC_PORT_WAKEUP_EVENT(0)) >> + >> #define XUSB_PADCTL_ELPG_PROGRAM1 0x024 >> #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31) >> #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30) >> @@ -90,6 +106,8 @@ >> #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2) >> #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1) >> #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0) >> +#define RPD_CTRL(x) (((x) & 0x1f) << 26) >> +#define RPD_CTRL_VALUE(x)(((x) >> 26) & 0x1f) >> >> #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284 >> #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 11) >> @@ -108,6 +126,8 @@ >> #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT 12 >> #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f >> #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e >> +#define TCTRL_VALUE(x)(((x) & 0x3f) >> 0) >> +#define PCTRL_VALUE(x)(((x) >> 6) & 0x3f) >> >> #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20) >> #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE (1 << 18) >> @@ -251,16 +271,161 @@ >> #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING 8 >> #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED 0 >> >> +/* USB2 SLEEPWALK registers */ >> +#define UTMIP(_port, _offset1, _offset2) \ >> +(((_port) <= 2) ? (_offset1) : (_offset2)) >> + >> +#define PMC_UTMIP_UHSIC_SLEEP_CFG(x)UTMIP(x, 0x1fc, 0x4d0) >> +#define UTMIP_MASTER_ENABLE(x)UTMIP(x, BIT(8 * (x)), BIT(0)) >> +#define UTMIP_FSLS_USE_PMC(x) UTMIP(x, BIT(8 * (x) + >> 1), \ >> +BIT(1)) >> +#define UTMIP_PCTRL_USE_PMC(x)UTMIP(x, BIT(8 * (x) + 2), \ >> +BIT(2)) >> +#define UTMIP_TCTRL_USE_PMC(x)UTMIP(x, BIT(8 * (x) + 3), \ >> +BIT(3)) >> +#define UTMIP_WAKE_VAL(_port, _value) (((_value) & 0xf) << \ >> +(UTMIP(_port, 8 * (_port) + 4, 4))) >> +#define UTMIP_WAKE_VAL_NONE(_port)UTMIP_WAKE_VAL(_port, >> 12) >> +#define UTMIP_WAKE_VAL_ANY(_port) UTMIP_WAKE_VAL(_port, 15) >> + >> +#define PMC_UTMIP_UHSIC_SLEEP_CFG1 (0x4d0) >> +#define UTMIP_RPU_SWITC_LOW_USE_PMC_PX(x) BIT((x) + 8) >> +#define UTMIP_RPD_CTRL_USE_PMC_PX(x) BIT((x) + 16) >> + >> +#define PMC_UTMIP_MASTER_CONFIG (0x274) >> +#define UTMIP_PWR(x) UTMIP(x, BIT(x), BIT(4)) >> +#define UHSIC_PWR(x) BIT(3) >> + >> +#define PMC_USB_DEBOUNCE_DEL(0xec) >> +#define DEBOUNCE_VAL(x) (((x) & 0x) << 0) >> +#define UTMIP_LINE_DEB_CNT(x) (((x) & 0xf) << 16) >> +#define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 20) >> + >> +#define PMC_UTMIP_UHSIC_FAKE(x) UTMIP(x, 0x218, 0x294) >> +#define UTMIP_FAKE_USBOP_VAL(x) UTMIP(x, BIT(4 * (x)), BIT(8)) >> +#define
Re: [PATCH v2 08/12] phy: tegra: xusb: t210: support wake and sleepwalk
Hi JC,
I love your patch! Perhaps something to improve:
[auto build test WARNING on tegra/for-next]
[also build test WARNING on robh/for-next usb/usb-testing
char-misc/char-misc-testing staging/staging-testing
driver-core/driver-core-testing v5.9-rc3 next-20200828]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/JC-Kuo/Tegra-XHCI-controller-ELPG-support/20200831-124234
base: https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next
config: arm64-randconfig-r014-20200901 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
c10e63677f5d20f18010f8f68c631ddc97546f7d)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/phy/tegra/xusb-tegra210.c:1368:5: warning: no previous prototype for
>> function 'tegra_pmc_utmi_enable_phy_sleepwalk' [-Wmissing-prototypes]
int tegra_pmc_utmi_enable_phy_sleepwalk(struct phy *phy,
^
drivers/phy/tegra/xusb-tegra210.c:1368:1: note: declare 'static' if the
function is not intended to be used outside of this translation unit
int tegra_pmc_utmi_enable_phy_sleepwalk(struct phy *phy,
^
static
>> drivers/phy/tegra/xusb-tegra210.c:1527:5: warning: no previous prototype for
>> function 'tegra_pmc_utmi_disable_phy_sleepwalk' [-Wmissing-prototypes]
int tegra_pmc_utmi_disable_phy_sleepwalk(struct phy *phy)
^
drivers/phy/tegra/xusb-tegra210.c:1527:1: note: declare 'static' if the
function is not intended to be used outside of this translation unit
int tegra_pmc_utmi_disable_phy_sleepwalk(struct phy *phy)
^
static
>> drivers/phy/tegra/xusb-tegra210.c:1577:5: warning: no previous prototype for
>> function 'tegra_pmc_hsic_enable_phy_sleepwalk' [-Wmissing-prototypes]
int tegra_pmc_hsic_enable_phy_sleepwalk(struct phy *phy)
^
drivers/phy/tegra/xusb-tegra210.c:1577:1: note: declare 'static' if the
function is not intended to be used outside of this translation unit
int tegra_pmc_hsic_enable_phy_sleepwalk(struct phy *phy)
^
static
>> drivers/phy/tegra/xusb-tegra210.c:1680:5: warning: no previous prototype for
>> function 'tegra_pmc_hsic_disable_phy_sleepwalk' [-Wmissing-prototypes]
int tegra_pmc_hsic_disable_phy_sleepwalk(struct phy *phy)
^
drivers/phy/tegra/xusb-tegra210.c:1680:1: note: declare 'static' if the
function is not intended to be used outside of this translation unit
int tegra_pmc_hsic_disable_phy_sleepwalk(struct phy *phy)
^
static
>> drivers/phy/tegra/xusb-tegra210.c:3036:5: warning: no previous prototype for
>> function 'tegra210_xusb_padctl_remote_wake_detected' [-Wmissing-prototypes]
int tegra210_xusb_padctl_remote_wake_detected(struct phy *phy)
^
drivers/phy/tegra/xusb-tegra210.c:3036:1: note: declare 'static' if the
function is not intended to be used outside of this translation unit
int tegra210_xusb_padctl_remote_wake_detected(struct phy *phy)
^
static
5 warnings generated.
#
https://github.com/0day-ci/linux/commit/85501cb657fc0bbb792dc08358e31fad69c8b13c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
JC-Kuo/Tegra-XHCI-controller-ELPG-support/20200831-124234
git checkout 85501cb657fc0bbb792dc08358e31fad69c8b13c
vim +/tegra_pmc_utmi_enable_phy_sleepwalk +1368
drivers/phy/tegra/xusb-tegra210.c
1366
1367 /* T210 USB2 SLEEPWALK APIs */
> 1368 int tegra_pmc_utmi_enable_phy_sleepwalk(struct phy *phy,
1369 enum usb_device_speed speed)
1370 {
1371 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1372 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1373 struct tegra210_xusb_padctl *priv =
to_tegra210_xusb_padctl(padctl);
1374 struct device *dev = padctl->dev;
1375 unsigned int port = lane->index;
1376 u32 val, tctrl, pctrl, rpd_ctrl;
1377
1378 if (speed > USB_SPEED_HIGH)
1379 return -EINVAL;
1380
1381 dev_dbg(dev, "phy enable sleepwalk usb2 %d speed %d\n", port,
speed);
1382
1383 val = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1384 tctrl = TCTRL_VALUE(val);
1385 pctrl = PCTRL_VALUE(val);
1386
1387 val =
Re: [PATCH v2 08/12] phy: tegra: xusb: t210: support wake and sleepwalk
On Mon, Aug 31, 2020 at 12:40:39PM +0800, JC Kuo wrote: > This commit implements Tegra210 XUSB PADCTL wake and sleepwalk > routines. Sleepwalk logic is in PMC (always-on) hardware block. > PMC driver provides managed access to the sleepwalk registers > via regmap framework. > > Signed-off-by: JC Kuo > --- > drivers/phy/tegra/xusb-tegra210.c | 1094 - > 1 file changed, 1079 insertions(+), 15 deletions(-) > > diff --git a/drivers/phy/tegra/xusb-tegra210.c > b/drivers/phy/tegra/xusb-tegra210.c > index fe1ab440424d..1c03f4ec4b59 100644 > --- a/drivers/phy/tegra/xusb-tegra210.c > +++ b/drivers/phy/tegra/xusb-tegra210.c > @@ -16,6 +16,8 @@ > #include > #include > #include > +#include > +#include > > #include > > @@ -52,6 +54,20 @@ > #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5)) > #define XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED 0x7 > > +#define XUSB_PADCTL_ELPG_PROGRAM_0 0x20 > +#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x)) > +#define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7) > +#define SS_PORT_WAKE_INTERRUPT_ENABLE(x)BIT((x) + 14) > +#define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21) > +#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28) > +#define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30) > +#define ALL_WAKE_EVENTS ( \ > + USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \ > + USB2_PORT_WAKEUP_EVENT(2) | USB2_PORT_WAKEUP_EVENT(3) | \ > + SS_PORT_WAKEUP_EVENT(0) | SS_PORT_WAKEUP_EVENT(1) | \ > + SS_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(3) | \ > + USB2_HSIC_PORT_WAKEUP_EVENT(0)) > + > #define XUSB_PADCTL_ELPG_PROGRAM1 0x024 > #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31) > #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30) > @@ -90,6 +106,8 @@ > #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2) > #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1) > #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0) > +#define RPD_CTRL(x) (((x) & 0x1f) << 26) > +#define RPD_CTRL_VALUE(x)(((x) >> 26) & 0x1f) > > #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284 > #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 11) > @@ -108,6 +126,8 @@ > #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT 12 > #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f > #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e > +#define TCTRL_VALUE(x)(((x) & 0x3f) >> 0) > +#define PCTRL_VALUE(x)(((x) >> 6) & 0x3f) > > #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20) > #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE (1 << 18) > @@ -251,16 +271,161 @@ > #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING 8 > #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED 0 > > +/* USB2 SLEEPWALK registers */ > +#define UTMIP(_port, _offset1, _offset2) \ > + (((_port) <= 2) ? (_offset1) : (_offset2)) > + > +#define PMC_UTMIP_UHSIC_SLEEP_CFG(x) UTMIP(x, 0x1fc, 0x4d0) > +#define UTMIP_MASTER_ENABLE(x) UTMIP(x, BIT(8 * (x)), BIT(0)) > +#define UTMIP_FSLS_USE_PMC(x) UTMIP(x, BIT(8 * (x) + > 1), \ > + BIT(1)) > +#define UTMIP_PCTRL_USE_PMC(x) UTMIP(x, BIT(8 * (x) + 2), \ > + BIT(2)) > +#define UTMIP_TCTRL_USE_PMC(x) UTMIP(x, BIT(8 * (x) + 3), \ > + BIT(3)) > +#define UTMIP_WAKE_VAL(_port, _value) (((_value) & 0xf) << \ > + (UTMIP(_port, 8 * (_port) + 4, 4))) > +#define UTMIP_WAKE_VAL_NONE(_port) UTMIP_WAKE_VAL(_port, 12) > +#define UTMIP_WAKE_VAL_ANY(_port) UTMIP_WAKE_VAL(_port, 15) > + > +#define PMC_UTMIP_UHSIC_SLEEP_CFG1 (0x4d0) > +#define UTMIP_RPU_SWITC_LOW_USE_PMC_PX(x) BIT((x) + 8) > +#define UTMIP_RPD_CTRL_USE_PMC_PX(x) BIT((x) + 16) > + > +#define PMC_UTMIP_MASTER_CONFIG (0x274) > +#define UTMIP_PWR(x) UTMIP(x, BIT(x), BIT(4)) > +#define UHSIC_PWR(x) BIT(3) > + > +#define PMC_USB_DEBOUNCE_DEL (0xec) > +#define DEBOUNCE_VAL(x)(((x) & 0x) << 0) > +#define UTMIP_LINE_DEB_CNT(x) (((x) & 0xf) << 16) > +#define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 20) > + > +#define PMC_UTMIP_UHSIC_FAKE(x) UTMIP(x, 0x218, 0x294) > +#define UTMIP_FAKE_USBOP_VAL(x)UTMIP(x, BIT(4 * (x)), BIT(8)) > +#define UTMIP_FAKE_USBON_VAL(x)UTMIP(x, BIT(4 * (x) + 1), \ > + BIT(9)) > +#define UTMIP_FAKE_USBOP_EN(x)
