Re: [PATCH v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
On Wed, Sep 04, 2013 at 09:18:40AM -0700, Sudeep Dutt wrote: > On Wed, 2013-08-21 at 10:51 -0700, Sudeep Dutt wrote: > > ChangeLog: > > = > > > > v2 => v3: > > a) Patch 1 data structure cleanups, header file include cleanups, > >IDA interface reuse and switching to device_create_with_groups(..) > >as per feedback from Greg Kroah-Hartman. > > b) Patch 7 signal documentation, sleep workaround removal and sysfs > >access API cleanups as per feedback from Michael S. Tsirkin. > > > > v1 => v2: @ http://lwn.net/Articles/563131/ > > a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring > >into 3 smaller patches and function renames, as per feedback from > >Greg Kroah-Hartman. > > b) Use VRINGH infrastructure for accessing virtio rings from the host > >in patch 5, as per feedback from Michael S. Tsirkin. > > > > v1: Initial post @ https://lwn.net/Articles/561314/ > > > > Hi Greg, > > It has been a couple of weeks since we posted v3 @ > https://lwn.net/Articles/564795 which addresses all feedback received so > far. Have you had a chance to review this version? Please let us know > your thoughts. I don't have this around anymore, I got 7 copies and thought your patch-send script went crazy so I deleted them :( Care to send them again? But note, this is the merge window, so I'll not be able to do anythign for at least 2 weeks with them. thanks, greg k-h -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
On Wed, 2013-08-21 at 10:51 -0700, Sudeep Dutt wrote: > ChangeLog: > = > > v2 => v3: > a) Patch 1 data structure cleanups, header file include cleanups, >IDA interface reuse and switching to device_create_with_groups(..) >as per feedback from Greg Kroah-Hartman. > b) Patch 7 signal documentation, sleep workaround removal and sysfs >access API cleanups as per feedback from Michael S. Tsirkin. > > v1 => v2: @ http://lwn.net/Articles/563131/ > a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring >into 3 smaller patches and function renames, as per feedback from >Greg Kroah-Hartman. > b) Use VRINGH infrastructure for accessing virtio rings from the host >in patch 5, as per feedback from Michael S. Tsirkin. > > v1: Initial post @ https://lwn.net/Articles/561314/ > Hi Greg, It has been a couple of weeks since we posted v3 @ https://lwn.net/Articles/564795 which addresses all feedback received so far. Have you had a chance to review this version? Please let us know your thoughts. Thanks in advance, Sudeep Dutt > Description: > > > An Intel MIC X100 device is a PCIe form factor add-in coprocessor > card based on the Intel Many Integrated Core (MIC) architecture > that runs a Linux OS. It is a PCIe endpoint in a platform and therefore > implements the three required standard address spaces i.e. configuration, > memory and I/O. The host OS loads a device driver as is typical for > PCIe devices. The card itself runs a bootstrap after reset that > transfers control to the card OS downloaded from the host driver. > The card OS as shipped by Intel is a Linux kernel with modifications > for the X100 devices. > > Since it is a PCIe card, it does not have the ability to host hardware > devices for networking, storage and console. We provide these devices > on X100 coprocessors thus enabling a self-bootable equivalent environment > for applications. A key benefit of our solution is that it leverages > the standard virtio framework for network, disk and console devices, > though in our case the virtio framework is used across a PCIe bus. > > Here is a block diagram of the various components described above. The > virtio backends are situated on the host rather than the card given better > single threaded performance for the host compared to MIC, the ability of > the host to initiate DMA's to/from the card using the MIC DMA engine and > the fact that the virtio block storage backend can only be on the host. > >+--+ | +--+ >| Card OS | | | Host OS | >+--+ | +--+ > | > +---+ ++ +--+ | +-+ ++ ++ > | Virtio| |Virtio | |Virtio| | |Virtio | |Virtio | |Virtio | > | Net | |Console | |Block | | |Net | |Console | |Block | > | Driver| |Driver | |Driver| | |backend | |backend | |backend | > +---+ ++ +--+ | +-+ ++ ++ > | | | | || | > | | | |User || | > | | | |--||-|--- > +---+ |Kernel +--+ > | | | Virtio over PCIe IOCTLs | > | | +--+ > +--+| | > |Intel MIC ||+---+ > |Card Driver |||Intel MIC | > +--+||Host Driver| > | |+---+ > | | | > +-+ > | | > |PCIe Bus | > +-+ > > The following series of patches are partitioned as follows: > > Patch 1: This patch introduces the "Intel MIC Host Driver" in the block > diagram which does the following: > a) Initializes the Intel MIC X100 PCIe devices. > b) Provides sysfs entries for family and stepping information. > > Patch 2: This patch enables the following features in the > "Intel MIC Host Driver" in the block diagram: > a) MSIx, MSI and legacy interrupt support. > b) System Memory Page Table(SMPT) support. SMPT enables system memory >access from the card. On X100 devices the host can program 32 SMPT >registers each capable of accessing 16GB of system memory >address space from X100 devices. The registers can thereby be used >to access a cumulative 512GB of system memory address space from >X100 devices at any point in time. > > Patch 3: This patch enables the
Re: [PATCH v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
On Wed, 2013-08-21 at 10:51 -0700, Sudeep Dutt wrote: ChangeLog: = v2 = v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 = v2: @ http://lwn.net/Articles/563131/ a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring into 3 smaller patches and function renames, as per feedback from Greg Kroah-Hartman. b) Use VRINGH infrastructure for accessing virtio rings from the host in patch 5, as per feedback from Michael S. Tsirkin. v1: Initial post @ https://lwn.net/Articles/561314/ Hi Greg, It has been a couple of weeks since we posted v3 @ https://lwn.net/Articles/564795 which addresses all feedback received so far. Have you had a chance to review this version? Please let us know your thoughts. Thanks in advance, Sudeep Dutt Description: An Intel MIC X100 device is a PCIe form factor add-in coprocessor card based on the Intel Many Integrated Core (MIC) architecture that runs a Linux OS. It is a PCIe endpoint in a platform and therefore implements the three required standard address spaces i.e. configuration, memory and I/O. The host OS loads a device driver as is typical for PCIe devices. The card itself runs a bootstrap after reset that transfers control to the card OS downloaded from the host driver. The card OS as shipped by Intel is a Linux kernel with modifications for the X100 devices. Since it is a PCIe card, it does not have the ability to host hardware devices for networking, storage and console. We provide these devices on X100 coprocessors thus enabling a self-bootable equivalent environment for applications. A key benefit of our solution is that it leverages the standard virtio framework for network, disk and console devices, though in our case the virtio framework is used across a PCIe bus. Here is a block diagram of the various components described above. The virtio backends are situated on the host rather than the card given better single threaded performance for the host compared to MIC, the ability of the host to initiate DMA's to/from the card using the MIC DMA engine and the fact that the virtio block storage backend can only be on the host. +--+ | +--+ | Card OS | | | Host OS | +--+ | +--+ | +---+ ++ +--+ | +-+ ++ ++ | Virtio| |Virtio | |Virtio| | |Virtio | |Virtio | |Virtio | | Net | |Console | |Block | | |Net | |Console | |Block | | Driver| |Driver | |Driver| | |backend | |backend | |backend | +---+ ++ +--+ | +-+ ++ ++ | | | | || | | | | |User || | | | | |--||-|--- +---+ |Kernel +--+ | | | Virtio over PCIe IOCTLs | | | +--+ +--+| | |Intel MIC ||+---+ |Card Driver |||Intel MIC | +--+||Host Driver| | |+---+ | | | +-+ | | |PCIe Bus | +-+ The following series of patches are partitioned as follows: Patch 1: This patch introduces the Intel MIC Host Driver in the block diagram which does the following: a) Initializes the Intel MIC X100 PCIe devices. b) Provides sysfs entries for family and stepping information. Patch 2: This patch enables the following features in the Intel MIC Host Driver in the block diagram: a) MSIx, MSI and legacy interrupt support. b) System Memory Page Table(SMPT) support. SMPT enables system memory access from the card. On X100 devices the host can program 32 SMPT registers each capable of accessing 16GB of system memory address space from X100 devices. The registers can thereby be used to access a cumulative 512GB of system memory address space from X100 devices at any point in time. Patch 3: This patch enables the following features in the Intel MIC Host Driver in the block diagram: a) Boots and shuts down the
Re: [PATCH v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
On Wed, Sep 04, 2013 at 09:18:40AM -0700, Sudeep Dutt wrote: On Wed, 2013-08-21 at 10:51 -0700, Sudeep Dutt wrote: ChangeLog: = v2 = v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 = v2: @ http://lwn.net/Articles/563131/ a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring into 3 smaller patches and function renames, as per feedback from Greg Kroah-Hartman. b) Use VRINGH infrastructure for accessing virtio rings from the host in patch 5, as per feedback from Michael S. Tsirkin. v1: Initial post @ https://lwn.net/Articles/561314/ Hi Greg, It has been a couple of weeks since we posted v3 @ https://lwn.net/Articles/564795 which addresses all feedback received so far. Have you had a chance to review this version? Please let us know your thoughts. I don't have this around anymore, I got 7 copies and thought your patch-send script went crazy so I deleted them :( Care to send them again? But note, this is the merge window, so I'll not be able to do anythign for at least 2 weeks with them. thanks, greg k-h -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
Sincere apologies for the spam. This patches series got sent out 7 times by mistake due to script bug at my end. I will ensure this never happens again. Apologies again. Sudeep Dutt On Wed, 2013-08-21 at 10:52 -0700, Sudeep Dutt wrote: > ChangeLog: > = > > v2 => v3: > a) Patch 1 data structure cleanups, header file include cleanups, >IDA interface reuse and switching to device_create_with_groups(..) >as per feedback from Greg Kroah-Hartman. > b) Patch 7 signal documentation, sleep workaround removal and sysfs >access API cleanups as per feedback from Michael S. Tsirkin. > > v1 => v2: @ http://lwn.net/Articles/563131/ > a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring >into 3 smaller patches and function renames, as per feedback from >Greg Kroah-Hartman. > b) Use VRINGH infrastructure for accessing virtio rings from the host >in patch 5, as per feedback from Michael S. Tsirkin. > > v1: Initial post @ https://lwn.net/Articles/561314/ > > Description: > > > An Intel MIC X100 device is a PCIe form factor add-in coprocessor > card based on the Intel Many Integrated Core (MIC) architecture > that runs a Linux OS. It is a PCIe endpoint in a platform and therefore > implements the three required standard address spaces i.e. configuration, > memory and I/O. The host OS loads a device driver as is typical for > PCIe devices. The card itself runs a bootstrap after reset that > transfers control to the card OS downloaded from the host driver. > The card OS as shipped by Intel is a Linux kernel with modifications > for the X100 devices. > > Since it is a PCIe card, it does not have the ability to host hardware > devices for networking, storage and console. We provide these devices > on X100 coprocessors thus enabling a self-bootable equivalent environment > for applications. A key benefit of our solution is that it leverages > the standard virtio framework for network, disk and console devices, > though in our case the virtio framework is used across a PCIe bus. > > Here is a block diagram of the various components described above. The > virtio backends are situated on the host rather than the card given better > single threaded performance for the host compared to MIC, the ability of > the host to initiate DMA's to/from the card using the MIC DMA engine and > the fact that the virtio block storage backend can only be on the host. > >+--+ | +--+ >| Card OS | | | Host OS | >+--+ | +--+ > | > +---+ ++ +--+ | +-+ ++ ++ > | Virtio| |Virtio | |Virtio| | |Virtio | |Virtio | |Virtio | > | Net | |Console | |Block | | |Net | |Console | |Block | > | Driver| |Driver | |Driver| | |backend | |backend | |backend | > +---+ ++ +--+ | +-+ ++ ++ > | | | | || | > | | | |User || | > | | | |--||-|--- > +---+ |Kernel +--+ > | | | Virtio over PCIe IOCTLs | > | | +--+ > +--+| | > |Intel MIC ||+---+ > |Card Driver |||Intel MIC | > +--+||Host Driver| > | |+---+ > | | | > +-+ > | | > |PCIe Bus | > +-+ > > The following series of patches are partitioned as follows: > > Patch 1: This patch introduces the "Intel MIC Host Driver" in the block > diagram which does the following: > a) Initializes the Intel MIC X100 PCIe devices. > b) Provides sysfs entries for family and stepping information. > > Patch 2: This patch enables the following features in the > "Intel MIC Host Driver" in the block diagram: > a) MSIx, MSI and legacy interrupt support. > b) System Memory Page Table(SMPT) support. SMPT enables system memory >access from the card. On X100 devices the host can program 32 SMPT >registers each capable of accessing 16GB of system memory >address space from X100 devices. The registers can thereby be used >to access a cumulative 512GB of system memory address space from >X100 devices at any point in time. > > Patch 3: This patch enables the following features in the > "Intel MIC Host Driver" in the block diagram: >
Re: [PATCH v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
Sincere apologies for the spam. This patches series got sent out 7 times by mistake due to script bug at my end. I will ensure this never happens again. Apologies again. Sudeep Dutt On Wed, 2013-08-21 at 10:52 -0700, Sudeep Dutt wrote: ChangeLog: = v2 = v3: a) Patch 1 data structure cleanups, header file include cleanups, IDA interface reuse and switching to device_create_with_groups(..) as per feedback from Greg Kroah-Hartman. b) Patch 7 signal documentation, sleep workaround removal and sysfs access API cleanups as per feedback from Michael S. Tsirkin. v1 = v2: @ http://lwn.net/Articles/563131/ a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring into 3 smaller patches and function renames, as per feedback from Greg Kroah-Hartman. b) Use VRINGH infrastructure for accessing virtio rings from the host in patch 5, as per feedback from Michael S. Tsirkin. v1: Initial post @ https://lwn.net/Articles/561314/ Description: An Intel MIC X100 device is a PCIe form factor add-in coprocessor card based on the Intel Many Integrated Core (MIC) architecture that runs a Linux OS. It is a PCIe endpoint in a platform and therefore implements the three required standard address spaces i.e. configuration, memory and I/O. The host OS loads a device driver as is typical for PCIe devices. The card itself runs a bootstrap after reset that transfers control to the card OS downloaded from the host driver. The card OS as shipped by Intel is a Linux kernel with modifications for the X100 devices. Since it is a PCIe card, it does not have the ability to host hardware devices for networking, storage and console. We provide these devices on X100 coprocessors thus enabling a self-bootable equivalent environment for applications. A key benefit of our solution is that it leverages the standard virtio framework for network, disk and console devices, though in our case the virtio framework is used across a PCIe bus. Here is a block diagram of the various components described above. The virtio backends are situated on the host rather than the card given better single threaded performance for the host compared to MIC, the ability of the host to initiate DMA's to/from the card using the MIC DMA engine and the fact that the virtio block storage backend can only be on the host. +--+ | +--+ | Card OS | | | Host OS | +--+ | +--+ | +---+ ++ +--+ | +-+ ++ ++ | Virtio| |Virtio | |Virtio| | |Virtio | |Virtio | |Virtio | | Net | |Console | |Block | | |Net | |Console | |Block | | Driver| |Driver | |Driver| | |backend | |backend | |backend | +---+ ++ +--+ | +-+ ++ ++ | | | | || | | | | |User || | | | | |--||-|--- +---+ |Kernel +--+ | | | Virtio over PCIe IOCTLs | | | +--+ +--+| | |Intel MIC ||+---+ |Card Driver |||Intel MIC | +--+||Host Driver| | |+---+ | | | +-+ | | |PCIe Bus | +-+ The following series of patches are partitioned as follows: Patch 1: This patch introduces the Intel MIC Host Driver in the block diagram which does the following: a) Initializes the Intel MIC X100 PCIe devices. b) Provides sysfs entries for family and stepping information. Patch 2: This patch enables the following features in the Intel MIC Host Driver in the block diagram: a) MSIx, MSI and legacy interrupt support. b) System Memory Page Table(SMPT) support. SMPT enables system memory access from the card. On X100 devices the host can program 32 SMPT registers each capable of accessing 16GB of system memory address space from X100 devices. The registers can thereby be used to access a cumulative 512GB of system memory address space from X100 devices at any point in time. Patch 3: This patch enables the following features in the Intel MIC Host Driver in the block diagram: a) Boots and shuts down the card via sysfs entries. b) Allocates and maps a device page for
