Re: [PATCH v3 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips

[Vivek Gautam]

Hi Stephen,

On Thu, Dec 29, 2016 at 12:27 PM, Vivek Gautam
 wrote:
> On Thu, Dec 29, 2016 at 4:31 AM, Stephen Boyd  wrote:
>> On 12/20, Vivek Gautam wrote:
>>> PHY transceiver driver for QUSB2 phy controller that provides
>>> HighSpeed functionality for DWC3 controller present on
>>> Qualcomm chipsets.
>>>
>>> Signed-off-by: Vivek Gautam 
>>
>> One comment below, but otherwise
>>
>> Reviewed-by: Stephen Boyd 

Thanks for the review.


Best Regards
Vivek

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips

[Vivek Gautam]

Hi Stephen,

On Thu, Dec 29, 2016 at 12:27 PM, Vivek Gautam
 wrote:
> On Thu, Dec 29, 2016 at 4:31 AM, Stephen Boyd  wrote:
>> On 12/20, Vivek Gautam wrote:
>>> PHY transceiver driver for QUSB2 phy controller that provides
>>> HighSpeed functionality for DWC3 controller present on
>>> Qualcomm chipsets.
>>>
>>> Signed-off-by: Vivek Gautam 
>>
>> One comment below, but otherwise
>>
>> Reviewed-by: Stephen Boyd 

Thanks for the review.


Best Regards
Vivek

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips

[Vivek Gautam]

On Thu, Dec 29, 2016 at 4:31 AM, Stephen Boyd  wrote:
> On 12/20, Vivek Gautam wrote:
>> PHY transceiver driver for QUSB2 phy controller that provides
>> HighSpeed functionality for DWC3 controller present on
>> Qualcomm chipsets.
>>
>> Signed-off-by: Vivek Gautam 
>
> One comment below, but otherwise
>
> Reviewed-by: Stephen Boyd 
>
>> +static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
>> +{
>> + struct device *dev = >phy->dev;
>> + u8 *val;
>> +
>> + /*
>> +  * Read efuse register having TUNE2 parameter's high nibble.
>> +  * If efuse register shows value as 0x0, or if we fail to find
>> +  * a valid efuse register settings, then use default value
>> +  * as 0xB for high nibble that we have already set while
>> +  * configuring phy.
>> +  */
>> + val = nvmem_cell_read(qphy->cell, NULL);
>> + if (IS_ERR(val) || !val[0]) {
>> + dev_dbg(dev, "failed to read a valid hs-tx trim value, %ld\n",
>> + PTR_ERR(val));
>
> If val is 0 PTR_ERR(0) will be junk? I guess that's ok for debug
> print.

May be -EINVAL is better for debug print. Even when val[0]
is 0, val will still be a valid pointer, and so PTR_ERR(val) will
essentially be the pointer casted to long.



Thanks
Vivek
-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips

[Vivek Gautam]

On Thu, Dec 29, 2016 at 4:31 AM, Stephen Boyd  wrote:
> On 12/20, Vivek Gautam wrote:
>> PHY transceiver driver for QUSB2 phy controller that provides
>> HighSpeed functionality for DWC3 controller present on
>> Qualcomm chipsets.
>>
>> Signed-off-by: Vivek Gautam 
>
> One comment below, but otherwise
>
> Reviewed-by: Stephen Boyd 
>
>> +static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
>> +{
>> + struct device *dev = >phy->dev;
>> + u8 *val;
>> +
>> + /*
>> +  * Read efuse register having TUNE2 parameter's high nibble.
>> +  * If efuse register shows value as 0x0, or if we fail to find
>> +  * a valid efuse register settings, then use default value
>> +  * as 0xB for high nibble that we have already set while
>> +  * configuring phy.
>> +  */
>> + val = nvmem_cell_read(qphy->cell, NULL);
>> + if (IS_ERR(val) || !val[0]) {
>> + dev_dbg(dev, "failed to read a valid hs-tx trim value, %ld\n",
>> + PTR_ERR(val));
>
> If val is 0 PTR_ERR(0) will be junk? I guess that's ok for debug
> print.

May be -EINVAL is better for debug print. Even when val[0]
is 0, val will still be a valid pointer, and so PTR_ERR(val) will
essentially be the pointer casted to long.



Thanks
Vivek
-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips

[Stephen Boyd]

On 12/20, Vivek Gautam wrote:
> PHY transceiver driver for QUSB2 phy controller that provides
> HighSpeed functionality for DWC3 controller present on
> Qualcomm chipsets.
> 
> Signed-off-by: Vivek Gautam 

One comment below, but otherwise

Reviewed-by: Stephen Boyd 

> +static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
> +{
> + struct device *dev = >phy->dev;
> + u8 *val;
> +
> + /*
> +  * Read efuse register having TUNE2 parameter's high nibble.
> +  * If efuse register shows value as 0x0, or if we fail to find
> +  * a valid efuse register settings, then use default value
> +  * as 0xB for high nibble that we have already set while
> +  * configuring phy.
> +  */
> + val = nvmem_cell_read(qphy->cell, NULL);
> + if (IS_ERR(val) || !val[0]) {
> + dev_dbg(dev, "failed to read a valid hs-tx trim value, %ld\n",
> + PTR_ERR(val));

If val is 0 PTR_ERR(0) will be junk? I guess that's ok for debug
print.

> + return;
> + }
> +
> + /* Fused TUNE2 value is the higher nibble only */
> + qusb2_setbits(qphy->base + QUSB2PHY_PORT_TUNE2, val[0] << 0x4);
> +}

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips

[Stephen Boyd]

On 12/20, Vivek Gautam wrote:
> PHY transceiver driver for QUSB2 phy controller that provides
> HighSpeed functionality for DWC3 controller present on
> Qualcomm chipsets.
> 
> Signed-off-by: Vivek Gautam 

One comment below, but otherwise

Reviewed-by: Stephen Boyd 

> +static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
> +{
> + struct device *dev = >phy->dev;
> + u8 *val;
> +
> + /*
> +  * Read efuse register having TUNE2 parameter's high nibble.
> +  * If efuse register shows value as 0x0, or if we fail to find
> +  * a valid efuse register settings, then use default value
> +  * as 0xB for high nibble that we have already set while
> +  * configuring phy.
> +  */
> + val = nvmem_cell_read(qphy->cell, NULL);
> + if (IS_ERR(val) || !val[0]) {
> + dev_dbg(dev, "failed to read a valid hs-tx trim value, %ld\n",
> + PTR_ERR(val));

If val is 0 PTR_ERR(0) will be junk? I guess that's ok for debug
print.

> + return;
> + }
> +
> + /* Fused TUNE2 value is the higher nibble only */
> + qusb2_setbits(qphy->base + QUSB2PHY_PORT_TUNE2, val[0] << 0x4);
> +}

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project