Re: [PATCH v4] mfd: Add support for Merrifield Basin Cove PMIC
On Mon, Sep 02, 2019 at 09:38:59AM +0100, Lee Jones wrote: > On Thu, 01 Aug 2019, Andy Shevchenko wrote: > > > Add an MFD driver for Intel Merrifield Basin Cove PMIC. > > > > Firmware on the platforms which are using Basin Cove PMIC is "smarter" > > than on the rest supported by vanilla kernel. It handles first level > > of interrupt itself, while others do it on OS level. > > > > The driver is done in the same way as the rest of Intel PMIC MFD drivers > > in the kernel to support the initial design. The design allows to use > > one driver among few PMICs without knowing implementation details of > > the each hardware version or generation. > > > > Signed-off-by: Andy Shevchenko > > --- > > v4: elaborate in the commit message the design choice > > drivers/mfd/Kconfig | 11 ++ > > drivers/mfd/Makefile | 1 + > > drivers/mfd/intel_soc_pmic_mrfld.c | 157 +++ > > include/linux/mfd/intel_soc_pmic_mrfld.h | 81 > > 4 files changed, 250 insertions(+) > > create mode 100644 drivers/mfd/intel_soc_pmic_mrfld.c > > create mode 100644 include/linux/mfd/intel_soc_pmic_mrfld.h > > Reluctantly applied, thanks. Thank you very much! If any better solution comes to your mind in the future, I would be glad to amend the driver. Btw, can you provide an immutable branch for IIO subsystem to take individual ADC driver? -- With Best Regards, Andy Shevchenko
Re: [PATCH v4] mfd: Add support for Merrifield Basin Cove PMIC
On Thu, 01 Aug 2019, Andy Shevchenko wrote: > Add an MFD driver for Intel Merrifield Basin Cove PMIC. > > Firmware on the platforms which are using Basin Cove PMIC is "smarter" > than on the rest supported by vanilla kernel. It handles first level > of interrupt itself, while others do it on OS level. > > The driver is done in the same way as the rest of Intel PMIC MFD drivers > in the kernel to support the initial design. The design allows to use > one driver among few PMICs without knowing implementation details of > the each hardware version or generation. > > Signed-off-by: Andy Shevchenko > --- > v4: elaborate in the commit message the design choice > drivers/mfd/Kconfig | 11 ++ > drivers/mfd/Makefile | 1 + > drivers/mfd/intel_soc_pmic_mrfld.c | 157 +++ > include/linux/mfd/intel_soc_pmic_mrfld.h | 81 > 4 files changed, 250 insertions(+) > create mode 100644 drivers/mfd/intel_soc_pmic_mrfld.c > create mode 100644 include/linux/mfd/intel_soc_pmic_mrfld.h Reluctantly applied, thanks. -- Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog
Re: [PATCH v4] mfd: Add support for Merrifield Basin Cove PMIC
On Mon, Aug 12, 2019 at 10:53:38AM +0100, Lee Jones wrote:
> On Thu, 01 Aug 2019, Andy Shevchenko wrote:
>
> > Add an MFD driver for Intel Merrifield Basin Cove PMIC.
> >
> > Firmware on the platforms which are using Basin Cove PMIC is "smarter"
> > than on the rest supported by vanilla kernel. It handles first level
> > of interrupt itself, while others do it on OS level.
> >
> > The driver is done in the same way as the rest of Intel PMIC MFD drivers
> > in the kernel to support the initial design. The design allows to use
> > one driver among few PMICs without knowing implementation details of
> > the each hardware version or generation.
> >
> > Signed-off-by: Andy Shevchenko
> > ---
> > v4: elaborate in the commit message the design choice
> > drivers/mfd/Kconfig | 11 ++
> > drivers/mfd/Makefile | 1 +
> > drivers/mfd/intel_soc_pmic_mrfld.c | 157 +++
> > include/linux/mfd/intel_soc_pmic_mrfld.h | 81
> > 4 files changed, 250 insertions(+)
> > create mode 100644 drivers/mfd/intel_soc_pmic_mrfld.c
> > create mode 100644 include/linux/mfd/intel_soc_pmic_mrfld.h
> >
> > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> > index f129f9678940..adf178ad5e7b 100644
> > --- a/drivers/mfd/Kconfig
> > +++ b/drivers/mfd/Kconfig
> > @@ -597,6 +597,17 @@ config INTEL_SOC_PMIC_CHTDC_TI
> > Select this option for supporting Dollar Cove (TI version) PMIC
> > device that is found on some Intel Cherry Trail systems.
> >
> > +config INTEL_SOC_PMIC_MRFLD
> > + tristate "Support for Intel Merrifield Basin Cove PMIC"
> > + depends on GPIOLIB
> > + depends on ACPI
> > + depends on INTEL_SCU_IPC
> > + select MFD_CORE
> > + select REGMAP_IRQ
> > + help
> > + Select this option for supporting Basin Cove PMIC device
> > + that is found on Intel Merrifield systems.
> > +
> > config MFD_INTEL_LPSS
> > tristate
> > select COMMON_CLK
> > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> > index f026ada68f6a..637ecf6b12de 100644
> > --- a/drivers/mfd/Makefile
> > +++ b/drivers/mfd/Makefile
> > @@ -241,6 +241,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC)+= intel-soc-pmic.o
> > obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o
> > obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o
> > obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o
> > +obj-$(CONFIG_INTEL_SOC_PMIC_MRFLD) += intel_soc_pmic_mrfld.o
> > obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
> >
> > obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
> > diff --git a/drivers/mfd/intel_soc_pmic_mrfld.c
> > b/drivers/mfd/intel_soc_pmic_mrfld.c
> > new file mode 100644
> > index ..26a1551c5faf
> > --- /dev/null
> > +++ b/drivers/mfd/intel_soc_pmic_mrfld.c
> > @@ -0,0 +1,157 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device access for Basin Cove PMIC
> > + *
> > + * Copyright (c) 2019, Intel Corporation.
> > + * Author: Andy Shevchenko
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include
> > +
> > +/*
> > + * Level 2 IRQs
> > + *
> > + * Firmware on the systems with Basin Cove PMIC services Level 1 IRQs
> > + * without an assistance. Thus, each of the Level 1 IRQ is represented
> > + * as a separate RTE in IOAPIC.
> > + */
> > +static struct resource irq_level2_resources[] = {
> > + DEFINE_RES_IRQ(0), /* power button */
> > + DEFINE_RES_IRQ(0), /* TMU */
> > + DEFINE_RES_IRQ(0), /* thermal */
> > + DEFINE_RES_IRQ(0), /* BCU */
> > + DEFINE_RES_IRQ(0), /* ADC */
> > + DEFINE_RES_IRQ(0), /* charger */
> > + DEFINE_RES_IRQ(0), /* GPIO */
> > +};
> > +
> > +static const struct mfd_cell bcove_dev[] = {
> > + {
> > + .name = "mrfld_bcove_pwrbtn",
> > + .num_resources = 1,
> > + .resources = _level2_resources[0],
> > + }, {
> > + .name = "mrfld_bcove_tmu",
> > + .num_resources = 1,
> > + .resources = _level2_resources[1],
> > + }, {
> > + .name = "mrfld_bcove_thermal",
> > + .num_resources = 1,
> > + .resources = _level2_resources[2],
> > + }, {
> > + .name = "mrfld_bcove_bcu",
> > + .num_resources = 1,
> > + .resources = _level2_resources[3],
> > + }, {
> > + .name = "mrfld_bcove_adc",
> > + .num_resources = 1,
> > + .resources = _level2_resources[4],
> > + }, {
> > + .name = "mrfld_bcove_charger",
> > + .num_resources = 1,
> > + .resources = _level2_resources[5],
> > + }, {
> > + .name = "mrfld_bcove_pwrsrc",
> > + .num_resources = 1,
> > + .resources = _level2_resources[5],
> > + }, {
> > + .name = "mrfld_bcove_gpio",
> > + .num_resources = 1,
> > + .resources = _level2_resources[6],
> > + },
> >
Re: [PATCH v4] mfd: Add support for Merrifield Basin Cove PMIC
On Thu, 01 Aug 2019, Andy Shevchenko wrote:
> Add an MFD driver for Intel Merrifield Basin Cove PMIC.
>
> Firmware on the platforms which are using Basin Cove PMIC is "smarter"
> than on the rest supported by vanilla kernel. It handles first level
> of interrupt itself, while others do it on OS level.
>
> The driver is done in the same way as the rest of Intel PMIC MFD drivers
> in the kernel to support the initial design. The design allows to use
> one driver among few PMICs without knowing implementation details of
> the each hardware version or generation.
>
> Signed-off-by: Andy Shevchenko
> ---
> v4: elaborate in the commit message the design choice
> drivers/mfd/Kconfig | 11 ++
> drivers/mfd/Makefile | 1 +
> drivers/mfd/intel_soc_pmic_mrfld.c | 157 +++
> include/linux/mfd/intel_soc_pmic_mrfld.h | 81
> 4 files changed, 250 insertions(+)
> create mode 100644 drivers/mfd/intel_soc_pmic_mrfld.c
> create mode 100644 include/linux/mfd/intel_soc_pmic_mrfld.h
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index f129f9678940..adf178ad5e7b 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -597,6 +597,17 @@ config INTEL_SOC_PMIC_CHTDC_TI
> Select this option for supporting Dollar Cove (TI version) PMIC
> device that is found on some Intel Cherry Trail systems.
>
> +config INTEL_SOC_PMIC_MRFLD
> + tristate "Support for Intel Merrifield Basin Cove PMIC"
> + depends on GPIOLIB
> + depends on ACPI
> + depends on INTEL_SCU_IPC
> + select MFD_CORE
> + select REGMAP_IRQ
> + help
> + Select this option for supporting Basin Cove PMIC device
> + that is found on Intel Merrifield systems.
> +
> config MFD_INTEL_LPSS
> tristate
> select COMMON_CLK
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index f026ada68f6a..637ecf6b12de 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -241,6 +241,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
> obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o
> obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o
> obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI)+= intel_soc_pmic_chtdc_ti.o
> +obj-$(CONFIG_INTEL_SOC_PMIC_MRFLD) += intel_soc_pmic_mrfld.o
> obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
>
> obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
> diff --git a/drivers/mfd/intel_soc_pmic_mrfld.c
> b/drivers/mfd/intel_soc_pmic_mrfld.c
> new file mode 100644
> index ..26a1551c5faf
> --- /dev/null
> +++ b/drivers/mfd/intel_soc_pmic_mrfld.c
> @@ -0,0 +1,157 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device access for Basin Cove PMIC
> + *
> + * Copyright (c) 2019, Intel Corporation.
> + * Author: Andy Shevchenko
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +
> +/*
> + * Level 2 IRQs
> + *
> + * Firmware on the systems with Basin Cove PMIC services Level 1 IRQs
> + * without an assistance. Thus, each of the Level 1 IRQ is represented
> + * as a separate RTE in IOAPIC.
> + */
> +static struct resource irq_level2_resources[] = {
> + DEFINE_RES_IRQ(0), /* power button */
> + DEFINE_RES_IRQ(0), /* TMU */
> + DEFINE_RES_IRQ(0), /* thermal */
> + DEFINE_RES_IRQ(0), /* BCU */
> + DEFINE_RES_IRQ(0), /* ADC */
> + DEFINE_RES_IRQ(0), /* charger */
> + DEFINE_RES_IRQ(0), /* GPIO */
> +};
> +
> +static const struct mfd_cell bcove_dev[] = {
> + {
> + .name = "mrfld_bcove_pwrbtn",
> + .num_resources = 1,
> + .resources = _level2_resources[0],
> + }, {
> + .name = "mrfld_bcove_tmu",
> + .num_resources = 1,
> + .resources = _level2_resources[1],
> + }, {
> + .name = "mrfld_bcove_thermal",
> + .num_resources = 1,
> + .resources = _level2_resources[2],
> + }, {
> + .name = "mrfld_bcove_bcu",
> + .num_resources = 1,
> + .resources = _level2_resources[3],
> + }, {
> + .name = "mrfld_bcove_adc",
> + .num_resources = 1,
> + .resources = _level2_resources[4],
> + }, {
> + .name = "mrfld_bcove_charger",
> + .num_resources = 1,
> + .resources = _level2_resources[5],
> + }, {
> + .name = "mrfld_bcove_pwrsrc",
> + .num_resources = 1,
> + .resources = _level2_resources[5],
> + }, {
> + .name = "mrfld_bcove_gpio",
> + .num_resources = 1,
> + .resources = _level2_resources[6],
> + },
> + { .name = "mrfld_bcove_region", },
> +};
> +
> +static int bcove_ipc_byte_reg_read(void *context, unsigned int reg,
> + unsigned int *val)
> +{
> + u8 ipc_out;
> +
