Re: [PATCH v4 1/9] RISC-V: Implement ptrace regs and stack API

2020-11-05 Thread Guo Ren
On Fri, Nov 6, 2020 at 9:03 AM Palmer Dabbelt  wrote:
>
> On Sat, 17 Oct 2020 00:06:09 PDT (-0700), guo...@kernel.org wrote:
> > From: Patrick Stählin 
> >
> > Needed for kprobes support. Copied and adapted from arm64 code.
> >
> > Guo Ren fixup pt_regs type for linux-5.8-rc1.
> >
> > Signed-off-by: Patrick Stählin 
> > Signed-off-by: Guo Ren 
> > Reviewed-by: Pekka Enberg 
> > Reviewed-by: Zong Li 
> > Reviewed-by: Masami Hiramatsu 
> > ---
> >  arch/riscv/Kconfig  |  1 +
> >  arch/riscv/include/asm/ptrace.h | 29 
> >  arch/riscv/kernel/ptrace.c  | 99 
> > +
> >  3 files changed, 129 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index b7821ac..e6424d8b 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -87,6 +87,7 @@ config RISCV
> >   select SPARSE_IRQ
> >   select SYSCTL_EXCEPTION_TRACE
> >   select THREAD_INFO_IN_TASK
> > + select HAVE_REGS_AND_STACK_ACCESS_API
>
> We alphabetize these now -- I'd usually just fix it, but there's a
> Signed-off-by issue later in the patch set.
ok, I'll fix it and rebase 5.10-rc2.


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/


Re: [PATCH v4 1/9] RISC-V: Implement ptrace regs and stack API

2020-11-05 Thread Palmer Dabbelt

On Sat, 17 Oct 2020 00:06:09 PDT (-0700), guo...@kernel.org wrote:

From: Patrick Stählin 

Needed for kprobes support. Copied and adapted from arm64 code.

Guo Ren fixup pt_regs type for linux-5.8-rc1.

Signed-off-by: Patrick Stählin 
Signed-off-by: Guo Ren 
Reviewed-by: Pekka Enberg 
Reviewed-by: Zong Li 
Reviewed-by: Masami Hiramatsu 
---
 arch/riscv/Kconfig  |  1 +
 arch/riscv/include/asm/ptrace.h | 29 
 arch/riscv/kernel/ptrace.c  | 99 +
 3 files changed, 129 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b7821ac..e6424d8b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -87,6 +87,7 @@ config RISCV
select SPARSE_IRQ
select SYSCTL_EXCEPTION_TRACE
select THREAD_INFO_IN_TASK
+   select HAVE_REGS_AND_STACK_ACCESS_API


We alphabetize these now -- I'd usually just fix it, but there's a
Signed-off-by issue later in the patch set.



 config ARCH_MMAP_RND_BITS_MIN
default 18 if 64BIT
diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h
index ee49f80..23372bb 100644
--- a/arch/riscv/include/asm/ptrace.h
+++ b/arch/riscv/include/asm/ptrace.h
@@ -8,6 +8,7 @@

 #include 
 #include 
+#include 

 #ifndef __ASSEMBLY__

@@ -60,6 +61,7 @@ struct pt_regs {

 #define user_mode(regs) (((regs)->status & SR_PP) == 0)

+#define MAX_REG_OFFSET offsetof(struct pt_regs, orig_a0)

 /* Helpers for working with the instruction pointer */
 static inline unsigned long instruction_pointer(struct pt_regs *regs)
@@ -85,6 +87,12 @@ static inline void user_stack_pointer_set(struct pt_regs 
*regs,
regs->sp =  val;
 }

+/* Valid only for Kernel mode traps. */
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+   return regs->sp;
+}
+
 /* Helpers for working with the frame pointer */
 static inline unsigned long frame_pointer(struct pt_regs *regs)
 {
@@ -101,6 +109,27 @@ static inline unsigned long regs_return_value(struct 
pt_regs *regs)
return regs->a0;
 }

+extern int regs_query_register_offset(const char *name);
+extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
+  unsigned int n);
+
+/**
+ * regs_get_register() - get register value from its offset
+ * @regs:  pt_regs from which register value is gotten
+ * @offset:offset of the register.
+ *
+ * regs_get_register returns the value of a register whose offset from @regs.
+ * The @offset is the offset of the register in struct pt_regs.
+ * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
+ */
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+ unsigned int offset)
+{
+   if (unlikely(offset > MAX_REG_OFFSET))
+   return 0;
+
+   return *(unsigned long *)((unsigned long)regs + offset);
+}
 #endif /* __ASSEMBLY__ */

 #endif /* _ASM_RISCV_PTRACE_H */
diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index 2d6395f..1a85305 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -114,6 +114,105 @@ const struct user_regset_view 
*task_user_regset_view(struct task_struct *task)
return _user_native_view;
 }

+struct pt_regs_offset {
+   const char *name;
+   int offset;
+};
+
+#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
+#define REG_OFFSET_END {.name = NULL, .offset = 0}
+
+static const struct pt_regs_offset regoffset_table[] = {
+   REG_OFFSET_NAME(epc),
+   REG_OFFSET_NAME(ra),
+   REG_OFFSET_NAME(sp),
+   REG_OFFSET_NAME(gp),
+   REG_OFFSET_NAME(tp),
+   REG_OFFSET_NAME(t0),
+   REG_OFFSET_NAME(t1),
+   REG_OFFSET_NAME(t2),
+   REG_OFFSET_NAME(s0),
+   REG_OFFSET_NAME(s1),
+   REG_OFFSET_NAME(a0),
+   REG_OFFSET_NAME(a1),
+   REG_OFFSET_NAME(a2),
+   REG_OFFSET_NAME(a3),
+   REG_OFFSET_NAME(a4),
+   REG_OFFSET_NAME(a5),
+   REG_OFFSET_NAME(a6),
+   REG_OFFSET_NAME(a7),
+   REG_OFFSET_NAME(s2),
+   REG_OFFSET_NAME(s3),
+   REG_OFFSET_NAME(s4),
+   REG_OFFSET_NAME(s5),
+   REG_OFFSET_NAME(s6),
+   REG_OFFSET_NAME(s7),
+   REG_OFFSET_NAME(s8),
+   REG_OFFSET_NAME(s9),
+   REG_OFFSET_NAME(s10),
+   REG_OFFSET_NAME(s11),
+   REG_OFFSET_NAME(t3),
+   REG_OFFSET_NAME(t4),
+   REG_OFFSET_NAME(t5),
+   REG_OFFSET_NAME(t6),
+   REG_OFFSET_NAME(status),
+   REG_OFFSET_NAME(badaddr),
+   REG_OFFSET_NAME(cause),
+   REG_OFFSET_NAME(orig_a0),
+   REG_OFFSET_END,
+};
+
+/**
+ * regs_query_register_offset() - query register offset from its name
+ * @name:  the name of a register
+ *
+ * regs_query_register_offset() returns the offset of a register in struct
+ * pt_regs from its name. If the name is invalid, this returns -EINVAL;
+ */
+int regs_query_register_offset(const char *name)
+{
+