Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
Hi Lars,
I love your patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v5.9-rc2 next-20200824]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Lars-Povlsen/mmc-Adding-support-for-Microchip-Sparx5-SoC/20200824-231355
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross
ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/mmc/host/sdhci-of-sparx5.c:158:5: warning: no previous prototype for
>> 'sdhci_sparx5_probe' [-Wmissing-prototypes]
158 | int sdhci_sparx5_probe(struct platform_device *pdev)
| ^~
#
https://github.com/0day-ci/linux/commit/dd46278eff00cacc114d229429f51fbdbcb2e8f2
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Lars-Povlsen/mmc-Adding-support-for-Microchip-Sparx5-SoC/20200824-231355
git checkout dd46278eff00cacc114d229429f51fbdbcb2e8f2
vim +/sdhci_sparx5_probe +158 drivers/mmc/host/sdhci-of-sparx5.c
157
> 158 int sdhci_sparx5_probe(struct platform_device *pdev)
159 {
160 int ret;
161 const char *syscon = "microchip,sparx5-cpu-syscon";
162 struct sdhci_host *host;
163 struct sdhci_pltfm_host *pltfm_host;
164 struct sdhci_sparx5_data *sdhci_sparx5;
165 struct device_node *np = pdev->dev.of_node;
166 u32 value;
167 u32 extra;
168
169 host = sdhci_pltfm_init(pdev, _sparx5_pdata,
170 sizeof(*sdhci_sparx5));
171
172 if (IS_ERR(host))
173 return PTR_ERR(host);
174
175 /*
176 * extra adma table cnt for cross 128M boundary handling.
177 */
178 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(>dev),
SZ_128M);
179 if (extra > SDHCI_MAX_SEGS)
180 extra = SDHCI_MAX_SEGS;
181 host->adma_table_cnt += extra;
182
183 pltfm_host = sdhci_priv(host);
184 sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
185 sdhci_sparx5->host = host;
186
187 pltfm_host->clk = devm_clk_get(>dev, "core");
188 if (IS_ERR(pltfm_host->clk)) {
189 ret = PTR_ERR(pltfm_host->clk);
190 dev_err(>dev, "failed to get core clk: %d\n",
ret);
191 goto free_pltfm;
192 }
193 ret = clk_prepare_enable(pltfm_host->clk);
194 if (ret)
195 goto free_pltfm;
196
197 if (!of_property_read_u32(np, "microchip,clock-delay", )
&&
198 (value > 0 && value <= MSHC_DLY_CC_MAX))
199 sdhci_sparx5->delay_clock = value;
200
201 sdhci_get_of_property(pdev);
202
203 ret = mmc_of_parse(host->mmc);
204 if (ret)
205 goto err_clk;
206
207 sdhci_sparx5->cpu_ctrl =
syscon_regmap_lookup_by_compatible(syscon);
208 if (IS_ERR(sdhci_sparx5->cpu_ctrl)) {
209 dev_err(>dev, "No CPU syscon regmap !\n");
210 ret = PTR_ERR(sdhci_sparx5->cpu_ctrl);
211 goto err_clk;
212 }
213
214 if (sdhci_sparx5->delay_clock >= 0)
215 sparx5_set_delay(host, sdhci_sparx5->delay_clock);
216
217 if (!mmc_card_is_removable(host->mmc)) {
218 /* Do a HW reset of eMMC card */
219 sdhci_sparx5_reset_emmc(host);
220 /* Update EMMC_CTRL */
221 sdhci_sparx5_set_emmc(host);
222 /* If eMMC, disable SD and SDIO */
223 host->mmc->caps2 |= (MMC_CAP2_NO_SDIO|MMC_CAP2_NO_SD);
224 }
225
226 ret = sdhci_add_host(host);
227 if (ret)
228 goto err_clk;
229
230 /* Set AXI bus master to use un-cached access (for DMA) */
231 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA) &&
232 IS_ENABLED(CONFIG_DMA_DECLARE_COHERENT))
233 sparx5_set_cacheable(host, ACP_CACHE_FORCE_ENA);
234
Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
On 24/08/20 6:10 pm, Lars Povlsen wrote:
> This adds the eMMC driver for the Sparx5 SoC. It is based upon the
> designware IP, but requires some extra initialization and quirks.
>
> Signed-off-by: Lars Povlsen
Already acked this, still:
Acked-by: Adrian Hunter
> ---
> drivers/mmc/host/Kconfig | 13 ++
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/sdhci-of-sparx5.c | 269 +
> 3 files changed, 283 insertions(+)
> create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c
>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 3b706af35ec31..a3bad4b4ed7ea 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -213,6 +213,19 @@ config MMC_SDHCI_OF_DWCMSHC
> If you have a controller with this interface, say Y or M here.
> If unsure, say N.
>
> +config MMC_SDHCI_OF_SPARX5
> + tristate "SDHCI OF support for the MCHP Sparx5 SoC"
> + depends on MMC_SDHCI_PLTFM
> + depends on ARCH_SPARX5
> + select MMC_SDHCI_IO_ACCESSORS
> + help
> + This selects the Secure Digital Host Controller Interface (SDHCI)
> + found in the MCHP Sparx5 SoC.
> +
> + If you have a Sparx5 SoC with this interface, say Y or M here.
> +
> + If unsure, say N.
> +
> config MMC_SDHCI_CADENCE
> tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
> depends on MMC_SDHCI_PLTFM
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 4d5bcb0144a0a..451c25fc2c692 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -94,6 +94,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) +=
> sdhci-of-at91.o
> obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
> obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
> obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o
> +obj-$(CONFIG_MMC_SDHCI_OF_SPARX5)+= sdhci-of-sparx5.o
> obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
> obj-$(CONFIG_MMC_SDHCI_IPROC)+= sdhci-iproc.o
> obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
> diff --git a/drivers/mmc/host/sdhci-of-sparx5.c
> b/drivers/mmc/host/sdhci-of-sparx5.c
> new file mode 100644
> index 0..2b262c12e5530
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-of-sparx5.c
> @@ -0,0 +1,269 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * drivers/mmc/host/sdhci-of-sparx5.c
> + *
> + * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
> + *
> + * Copyright (c) 2019 Microchip Inc.
> + *
> + * Author: Lars Povlsen
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "sdhci-pltfm.h"
> +
> +#define CPU_REGS_GENERAL_CTRL(0x22 * 4)
> +#define MSHC_DLY_CC_MASKGENMASK(16, 13)
> +#define MSHC_DLY_CC_SHIFT 13
> +#define MSHC_DLY_CC_MAX 15
> +
> +#define CPU_REGS_PROC_CTRL (0x2C * 4)
> +#define ACP_CACHE_FORCE_ENA BIT(4)
> +#define ACP_AWCACHE BIT(3)
> +#define ACP_ARCACHE BIT(2)
> +#define ACP_CACHE_MASK
> (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE)
> +
> +#define MSHC2_VERSION0x500 /* Off 0x140, reg 0x0 */
> +#define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
> +#define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
> +#define MSHC2_EMMC_CTRL_EMMC_RST_N BIT(2)
> +#define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
> +
> +struct sdhci_sparx5_data {
> + struct sdhci_host *host;
> + struct regmap *cpu_ctrl;
> + int delay_clock;
> +};
> +
> +#define BOUNDARY_OK(addr, len) \
> + ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
> +
> +/*
> + * If DMA addr spans 128MB boundary, we split the DMA transfer into two
> + * so that each DMA transfer doesn't exceed the boundary.
> + */
> +static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void
> **desc,
> + dma_addr_t addr, int len,
> + unsigned int cmd)
> +{
> + int tmplen, offset;
> +
> + if (likely(!len || BOUNDARY_OK(addr, len))) {
> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
> + return;
> + }
> +
> + pr_debug("%s: write_desc: splitting dma len %d, offset 0x%0llx\n",
> + mmc_hostname(host->mmc), len, addr);
> +
> + offset = addr & (SZ_128M - 1);
> + tmplen = SZ_128M - offset;
> + sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
> +
> + addr += tmplen;
> + len -= tmplen;
> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
> +}
> +
> +static void sparx5_set_cacheable(struct sdhci_host *host, u32 value)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
> +
> + pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc),
Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
On Fri, 24 Jul 2020 at 13:32, Lars Povlsen wrote: > > > Ulf Hansson writes: > > > On Wed, 22 Jul 2020 at 13:54, Lars Povlsen > > wrote: > >> > >> > >> Adrian Hunter writes: > >> > >> > On 18/06/20 5:13 pm, Lars Povlsen wrote: > >> >> This adds the eMMC driver for the Sparx5 SoC. It is based upon the > >> >> designware IP, but requires some extra initialization and quirks. > >> >> > >> >> Signed-off-by: Lars Povlsen > >> > > >> > Acked-by: Adrian Hunter > >> > > >> > >> Adrian, > >> > >> Thanks for the ack. I was expecting to see this in linux-next, anything > >> holding it back? > >> > >> pinctrl and hwmon drivers have been merged. > >> > >> Thanks, > > > > Hi Lars, > > > > Looks like you got some feedback on the DT patch (patch1/3) from Rob. > > I didn't find that you have addressed them and therefore I am holding > > back on the $subject patch as well. > > > > Uffe, thank you for responding. > > The automated checker complains about the inclusion of a header file > (#include ) in the example. The > header file itself is part of the "parent" patch series sent to arm-soc, > but is needed to make the example complete. > > I e-mailed Rob about how to handle this, but never got a reply. > > Can you suggest how to deal with this? I have checked the schema with > dt_binding_check manually - with the header file in place. I see, thanks for clarifying. When this kind of dependy happens, we have a couple of options. 1. Wait for a new rc to have the dependent changes included. 2. Share the changes between maintainers's git trees, through immutable branches. Looks like 1) would be easiest here. So, I suggest you re-post the series when v5.9-rc1 is out. > > I can of course remove the include and associated properties, but that > will make the example incomplete and irrelevant. No, that doesn't sound right. [...] Kind regards Uffe
Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
Ulf Hansson writes: > On Wed, 22 Jul 2020 at 13:54, Lars Povlsen wrote: >> >> >> Adrian Hunter writes: >> >> > On 18/06/20 5:13 pm, Lars Povlsen wrote: >> >> This adds the eMMC driver for the Sparx5 SoC. It is based upon the >> >> designware IP, but requires some extra initialization and quirks. >> >> >> >> Signed-off-by: Lars Povlsen >> > >> > Acked-by: Adrian Hunter >> > >> >> Adrian, >> >> Thanks for the ack. I was expecting to see this in linux-next, anything >> holding it back? >> >> pinctrl and hwmon drivers have been merged. >> >> Thanks, > > Hi Lars, > > Looks like you got some feedback on the DT patch (patch1/3) from Rob. > I didn't find that you have addressed them and therefore I am holding > back on the $subject patch as well. > Uffe, thank you for responding. The automated checker complains about the inclusion of a header file (#include ) in the example. The header file itself is part of the "parent" patch series sent to arm-soc, but is needed to make the example complete. I e-mailed Rob about how to handle this, but never got a reply. Can you suggest how to deal with this? I have checked the schema with dt_binding_check manually - with the header file in place. I can of course remove the include and associated properties, but that will make the example incomplete and irrelevant. ---Lars > Please fix the DT patch and re-submit a new version of the series. > > Kind regards > Uffe > > >> >> ---Lars >> >> >> --- >> >> drivers/mmc/host/Kconfig | 13 ++ >> >> drivers/mmc/host/Makefile | 1 + >> >> drivers/mmc/host/sdhci-of-sparx5.c | 269 + >> >> 3 files changed, 283 insertions(+) >> >> create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c >> >> >> >> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig >> >> index 3b706af35ec31..a3bad4b4ed7ea 100644 >> >> --- a/drivers/mmc/host/Kconfig >> >> +++ b/drivers/mmc/host/Kconfig >> >> @@ -213,6 +213,19 @@ config MMC_SDHCI_OF_DWCMSHC >> >> If you have a controller with this interface, say Y or M here. >> >> If unsure, say N. >> >> >> >> +config MMC_SDHCI_OF_SPARX5 >> >> + tristate "SDHCI OF support for the MCHP Sparx5 SoC" >> >> + depends on MMC_SDHCI_PLTFM >> >> + depends on ARCH_SPARX5 >> >> + select MMC_SDHCI_IO_ACCESSORS >> >> + help >> >> + This selects the Secure Digital Host Controller Interface (SDHCI) >> >> + found in the MCHP Sparx5 SoC. >> >> + >> >> + If you have a Sparx5 SoC with this interface, say Y or M here. >> >> + >> >> + If unsure, say N. >> >> + >> >> config MMC_SDHCI_CADENCE >> >> tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" >> >> depends on MMC_SDHCI_PLTFM >> >> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile >> >> index 4d5bcb0144a0a..451c25fc2c692 100644 >> >> --- a/drivers/mmc/host/Makefile >> >> +++ b/drivers/mmc/host/Makefile >> >> @@ -94,6 +94,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) += >> >> sdhci-of-at91.o >> >> obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o >> >> obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o >> >> obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o >> >> +obj-$(CONFIG_MMC_SDHCI_OF_SPARX5)+= sdhci-of-sparx5.o >> >> obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o >> >> obj-$(CONFIG_MMC_SDHCI_IPROC)+= sdhci-iproc.o >> >> obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o >> >> diff --git a/drivers/mmc/host/sdhci-of-sparx5.c >> >> b/drivers/mmc/host/sdhci-of-sparx5.c >> >> new file mode 100644 >> >> index 0..2b262c12e5530 >> >> --- /dev/null >> >> +++ b/drivers/mmc/host/sdhci-of-sparx5.c >> >> @@ -0,0 +1,269 @@ >> >> +// SPDX-License-Identifier: GPL-2.0-or-later >> >> +/* >> >> + * drivers/mmc/host/sdhci-of-sparx5.c >> >> + * >> >> + * MCHP Sparx5 SoC Secure Digital Host Controller Interface. >> >> + * >> >> + * Copyright (c) 2019 Microchip Inc. >> >> + * >> >> + * Author: Lars Povlsen >> >> + */ >> >> + >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> + >> >> +#include "sdhci-pltfm.h" >> >> + >> >> +#define CPU_REGS_GENERAL_CTRL(0x22 * 4) >> >> +#define MSHC_DLY_CC_MASKGENMASK(16, 13) >> >> +#define MSHC_DLY_CC_SHIFT 13 >> >> +#define MSHC_DLY_CC_MAX 15 >> >> + >> >> +#define CPU_REGS_PROC_CTRL (0x2C * 4) >> >> +#define ACP_CACHE_FORCE_ENA BIT(4) >> >> +#define ACP_AWCACHE BIT(3) >> >> +#define ACP_ARCACHE BIT(2) >> >> +#define ACP_CACHE_MASK >> >> (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE) >> >> + >> >> +#define MSHC2_VERSION0x500 /* Off 0x140, reg >> >> 0x0 */ >> >> +#define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */ >> >> +#define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg >> >> 0xB */ >> >> +#define MSHC2_EMMC_CTRL_EMMC_RST_N
Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
On Wed, 22 Jul 2020 at 13:54, Lars Povlsen wrote:
>
>
> Adrian Hunter writes:
>
> > On 18/06/20 5:13 pm, Lars Povlsen wrote:
> >> This adds the eMMC driver for the Sparx5 SoC. It is based upon the
> >> designware IP, but requires some extra initialization and quirks.
> >>
> >> Signed-off-by: Lars Povlsen
> >
> > Acked-by: Adrian Hunter
> >
>
> Adrian,
>
> Thanks for the ack. I was expecting to see this in linux-next, anything
> holding it back?
>
> pinctrl and hwmon drivers have been merged.
>
> Thanks,
Hi Lars,
Looks like you got some feedback on the DT patch (patch1/3) from Rob.
I didn't find that you have addressed them and therefore I am holding
back on the $subject patch as well.
Please fix the DT patch and re-submit a new version of the series.
Kind regards
Uffe
>
> ---Lars
>
> >> ---
> >> drivers/mmc/host/Kconfig | 13 ++
> >> drivers/mmc/host/Makefile | 1 +
> >> drivers/mmc/host/sdhci-of-sparx5.c | 269 +
> >> 3 files changed, 283 insertions(+)
> >> create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c
> >>
> >> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> >> index 3b706af35ec31..a3bad4b4ed7ea 100644
> >> --- a/drivers/mmc/host/Kconfig
> >> +++ b/drivers/mmc/host/Kconfig
> >> @@ -213,6 +213,19 @@ config MMC_SDHCI_OF_DWCMSHC
> >> If you have a controller with this interface, say Y or M here.
> >> If unsure, say N.
> >>
> >> +config MMC_SDHCI_OF_SPARX5
> >> + tristate "SDHCI OF support for the MCHP Sparx5 SoC"
> >> + depends on MMC_SDHCI_PLTFM
> >> + depends on ARCH_SPARX5
> >> + select MMC_SDHCI_IO_ACCESSORS
> >> + help
> >> + This selects the Secure Digital Host Controller Interface (SDHCI)
> >> + found in the MCHP Sparx5 SoC.
> >> +
> >> + If you have a Sparx5 SoC with this interface, say Y or M here.
> >> +
> >> + If unsure, say N.
> >> +
> >> config MMC_SDHCI_CADENCE
> >> tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
> >> depends on MMC_SDHCI_PLTFM
> >> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> >> index 4d5bcb0144a0a..451c25fc2c692 100644
> >> --- a/drivers/mmc/host/Makefile
> >> +++ b/drivers/mmc/host/Makefile
> >> @@ -94,6 +94,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) +=
> >> sdhci-of-at91.o
> >> obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
> >> obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
> >> obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o
> >> +obj-$(CONFIG_MMC_SDHCI_OF_SPARX5)+= sdhci-of-sparx5.o
> >> obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
> >> obj-$(CONFIG_MMC_SDHCI_IPROC)+= sdhci-iproc.o
> >> obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
> >> diff --git a/drivers/mmc/host/sdhci-of-sparx5.c
> >> b/drivers/mmc/host/sdhci-of-sparx5.c
> >> new file mode 100644
> >> index 0..2b262c12e5530
> >> --- /dev/null
> >> +++ b/drivers/mmc/host/sdhci-of-sparx5.c
> >> @@ -0,0 +1,269 @@
> >> +// SPDX-License-Identifier: GPL-2.0-or-later
> >> +/*
> >> + * drivers/mmc/host/sdhci-of-sparx5.c
> >> + *
> >> + * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
> >> + *
> >> + * Copyright (c) 2019 Microchip Inc.
> >> + *
> >> + * Author: Lars Povlsen
> >> + */
> >> +
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +
> >> +#include "sdhci-pltfm.h"
> >> +
> >> +#define CPU_REGS_GENERAL_CTRL(0x22 * 4)
> >> +#define MSHC_DLY_CC_MASKGENMASK(16, 13)
> >> +#define MSHC_DLY_CC_SHIFT 13
> >> +#define MSHC_DLY_CC_MAX 15
> >> +
> >> +#define CPU_REGS_PROC_CTRL (0x2C * 4)
> >> +#define ACP_CACHE_FORCE_ENA BIT(4)
> >> +#define ACP_AWCACHE BIT(3)
> >> +#define ACP_ARCACHE BIT(2)
> >> +#define ACP_CACHE_MASK
> >> (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE)
> >> +
> >> +#define MSHC2_VERSION0x500 /* Off 0x140, reg
> >> 0x0 */
> >> +#define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
> >> +#define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg
> >> 0xB */
> >> +#define MSHC2_EMMC_CTRL_EMMC_RST_N BIT(2)
> >> +#define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
> >> +
> >> +struct sdhci_sparx5_data {
> >> + struct sdhci_host *host;
> >> + struct regmap *cpu_ctrl;
> >> + int delay_clock;
> >> +};
> >> +
> >> +#define BOUNDARY_OK(addr, len) \
> >> + ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
> >> +
> >> +/*
> >> + * If DMA addr spans 128MB boundary, we split the DMA transfer into two
> >> + * so that each DMA transfer doesn't exceed the boundary.
> >> + */
> >> +static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void
> >> **desc,
> >> + dma_addr_t addr, int len,
> >> + unsigned int cmd)
> >> +{
> >> +
Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
Adrian Hunter writes:
> On 18/06/20 5:13 pm, Lars Povlsen wrote:
>> This adds the eMMC driver for the Sparx5 SoC. It is based upon the
>> designware IP, but requires some extra initialization and quirks.
>>
>> Signed-off-by: Lars Povlsen
>
> Acked-by: Adrian Hunter
>
Adrian,
Thanks for the ack. I was expecting to see this in linux-next, anything
holding it back?
pinctrl and hwmon drivers have been merged.
Thanks,
---Lars
>> ---
>> drivers/mmc/host/Kconfig | 13 ++
>> drivers/mmc/host/Makefile | 1 +
>> drivers/mmc/host/sdhci-of-sparx5.c | 269 +
>> 3 files changed, 283 insertions(+)
>> create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c
>>
>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> index 3b706af35ec31..a3bad4b4ed7ea 100644
>> --- a/drivers/mmc/host/Kconfig
>> +++ b/drivers/mmc/host/Kconfig
>> @@ -213,6 +213,19 @@ config MMC_SDHCI_OF_DWCMSHC
>> If you have a controller with this interface, say Y or M here.
>> If unsure, say N.
>>
>> +config MMC_SDHCI_OF_SPARX5
>> + tristate "SDHCI OF support for the MCHP Sparx5 SoC"
>> + depends on MMC_SDHCI_PLTFM
>> + depends on ARCH_SPARX5
>> + select MMC_SDHCI_IO_ACCESSORS
>> + help
>> + This selects the Secure Digital Host Controller Interface (SDHCI)
>> + found in the MCHP Sparx5 SoC.
>> +
>> + If you have a Sparx5 SoC with this interface, say Y or M here.
>> +
>> + If unsure, say N.
>> +
>> config MMC_SDHCI_CADENCE
>> tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
>> depends on MMC_SDHCI_PLTFM
>> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
>> index 4d5bcb0144a0a..451c25fc2c692 100644
>> --- a/drivers/mmc/host/Makefile
>> +++ b/drivers/mmc/host/Makefile
>> @@ -94,6 +94,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) +=
>> sdhci-of-at91.o
>> obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
>> obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
>> obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o
>> +obj-$(CONFIG_MMC_SDHCI_OF_SPARX5)+= sdhci-of-sparx5.o
>> obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
>> obj-$(CONFIG_MMC_SDHCI_IPROC)+= sdhci-iproc.o
>> obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
>> diff --git a/drivers/mmc/host/sdhci-of-sparx5.c
>> b/drivers/mmc/host/sdhci-of-sparx5.c
>> new file mode 100644
>> index 0..2b262c12e5530
>> --- /dev/null
>> +++ b/drivers/mmc/host/sdhci-of-sparx5.c
>> @@ -0,0 +1,269 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +/*
>> + * drivers/mmc/host/sdhci-of-sparx5.c
>> + *
>> + * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
>> + *
>> + * Copyright (c) 2019 Microchip Inc.
>> + *
>> + * Author: Lars Povlsen
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "sdhci-pltfm.h"
>> +
>> +#define CPU_REGS_GENERAL_CTRL(0x22 * 4)
>> +#define MSHC_DLY_CC_MASKGENMASK(16, 13)
>> +#define MSHC_DLY_CC_SHIFT 13
>> +#define MSHC_DLY_CC_MAX 15
>> +
>> +#define CPU_REGS_PROC_CTRL (0x2C * 4)
>> +#define ACP_CACHE_FORCE_ENA BIT(4)
>> +#define ACP_AWCACHE BIT(3)
>> +#define ACP_ARCACHE BIT(2)
>> +#define ACP_CACHE_MASK
>> (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE)
>> +
>> +#define MSHC2_VERSION0x500 /* Off 0x140, reg 0x0
>> */
>> +#define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
>> +#define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB
>> */
>> +#define MSHC2_EMMC_CTRL_EMMC_RST_N BIT(2)
>> +#define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
>> +
>> +struct sdhci_sparx5_data {
>> + struct sdhci_host *host;
>> + struct regmap *cpu_ctrl;
>> + int delay_clock;
>> +};
>> +
>> +#define BOUNDARY_OK(addr, len) \
>> + ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
>> +
>> +/*
>> + * If DMA addr spans 128MB boundary, we split the DMA transfer into two
>> + * so that each DMA transfer doesn't exceed the boundary.
>> + */
>> +static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void
>> **desc,
>> + dma_addr_t addr, int len,
>> + unsigned int cmd)
>> +{
>> + int tmplen, offset;
>> +
>> + if (likely(!len || BOUNDARY_OK(addr, len))) {
>> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
>> + return;
>> + }
>> +
>> + pr_debug("%s: write_desc: splitting dma len %d, offset 0x%0llx\n",
>> + mmc_hostname(host->mmc), len, addr);
>> +
>> + offset = addr & (SZ_128M - 1);
>> + tmplen = SZ_128M - offset;
>> + sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
>> +
>> + addr += tmplen;
>> + len -= tmplen;
>> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
>> +}
>>
Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
On 18/06/20 5:13 pm, Lars Povlsen wrote:
> This adds the eMMC driver for the Sparx5 SoC. It is based upon the
> designware IP, but requires some extra initialization and quirks.
>
> Signed-off-by: Lars Povlsen
Acked-by: Adrian Hunter
> ---
> drivers/mmc/host/Kconfig | 13 ++
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/sdhci-of-sparx5.c | 269 +
> 3 files changed, 283 insertions(+)
> create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c
>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 3b706af35ec31..a3bad4b4ed7ea 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -213,6 +213,19 @@ config MMC_SDHCI_OF_DWCMSHC
> If you have a controller with this interface, say Y or M here.
> If unsure, say N.
>
> +config MMC_SDHCI_OF_SPARX5
> + tristate "SDHCI OF support for the MCHP Sparx5 SoC"
> + depends on MMC_SDHCI_PLTFM
> + depends on ARCH_SPARX5
> + select MMC_SDHCI_IO_ACCESSORS
> + help
> + This selects the Secure Digital Host Controller Interface (SDHCI)
> + found in the MCHP Sparx5 SoC.
> +
> + If you have a Sparx5 SoC with this interface, say Y or M here.
> +
> + If unsure, say N.
> +
> config MMC_SDHCI_CADENCE
> tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
> depends on MMC_SDHCI_PLTFM
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 4d5bcb0144a0a..451c25fc2c692 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -94,6 +94,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) +=
> sdhci-of-at91.o
> obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
> obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
> obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o
> +obj-$(CONFIG_MMC_SDHCI_OF_SPARX5)+= sdhci-of-sparx5.o
> obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
> obj-$(CONFIG_MMC_SDHCI_IPROC)+= sdhci-iproc.o
> obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
> diff --git a/drivers/mmc/host/sdhci-of-sparx5.c
> b/drivers/mmc/host/sdhci-of-sparx5.c
> new file mode 100644
> index 0..2b262c12e5530
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-of-sparx5.c
> @@ -0,0 +1,269 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * drivers/mmc/host/sdhci-of-sparx5.c
> + *
> + * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
> + *
> + * Copyright (c) 2019 Microchip Inc.
> + *
> + * Author: Lars Povlsen
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "sdhci-pltfm.h"
> +
> +#define CPU_REGS_GENERAL_CTRL(0x22 * 4)
> +#define MSHC_DLY_CC_MASKGENMASK(16, 13)
> +#define MSHC_DLY_CC_SHIFT 13
> +#define MSHC_DLY_CC_MAX 15
> +
> +#define CPU_REGS_PROC_CTRL (0x2C * 4)
> +#define ACP_CACHE_FORCE_ENA BIT(4)
> +#define ACP_AWCACHE BIT(3)
> +#define ACP_ARCACHE BIT(2)
> +#define ACP_CACHE_MASK
> (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE)
> +
> +#define MSHC2_VERSION0x500 /* Off 0x140, reg 0x0 */
> +#define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
> +#define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
> +#define MSHC2_EMMC_CTRL_EMMC_RST_N BIT(2)
> +#define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
> +
> +struct sdhci_sparx5_data {
> + struct sdhci_host *host;
> + struct regmap *cpu_ctrl;
> + int delay_clock;
> +};
> +
> +#define BOUNDARY_OK(addr, len) \
> + ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
> +
> +/*
> + * If DMA addr spans 128MB boundary, we split the DMA transfer into two
> + * so that each DMA transfer doesn't exceed the boundary.
> + */
> +static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void
> **desc,
> + dma_addr_t addr, int len,
> + unsigned int cmd)
> +{
> + int tmplen, offset;
> +
> + if (likely(!len || BOUNDARY_OK(addr, len))) {
> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
> + return;
> + }
> +
> + pr_debug("%s: write_desc: splitting dma len %d, offset 0x%0llx\n",
> + mmc_hostname(host->mmc), len, addr);
> +
> + offset = addr & (SZ_128M - 1);
> + tmplen = SZ_128M - offset;
> + sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
> +
> + addr += tmplen;
> + len -= tmplen;
> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
> +}
> +
> +static void sparx5_set_cacheable(struct sdhci_host *host, u32 value)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
> +
> + pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value);
> +
> + /* Update
