Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-26 Thread Liviu Dudau 
On Tue, Mar 25, 2014 at 10:12:14PM +, Tanmay Inamdar wrote:
> Hello Liviu,
> 
> Thanks for taking a look. Please see inline.
> 
> On Tue, Mar 25, 2014 at 7:02 AM, Liviu Dudau  wrote:
> > On Wed, Mar 19, 2014 at 11:12:39PM +, Tanmay Inamdar wrote:
> >> This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
> >> X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
> >> X-Gene SOC supports maximum 5 PCIe ports.
> >>
> >> Signed-off-by: Tanmay Inamdar 
> >
> > Hi Tanmay,
> >
> > Some comments below.
> >
> >> ---
> >>  drivers/pci/host/Kconfig |   10 +
> >>  drivers/pci/host/Makefile|1 +
> >>  drivers/pci/host/pci-xgene.c |  725 
> >> ++
> >>  3 files changed, 736 insertions(+)
> >>  create mode 100644 drivers/pci/host/pci-xgene.c
> >>
> >> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> >> index 47d46c6..19ce97d 100644
> >> --- a/drivers/pci/host/Kconfig
> >> +++ b/drivers/pci/host/Kconfig
> >> @@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
> >>   There are 3 internal PCI controllers available with a single
> >>   built-in EHCI/OHCI host controller present on each one.
> >>
> >> +config PCI_XGENE
> >> +   bool "X-Gene PCIe controller"
> >> +   depends on ARCH_XGENE
> >> +   depends on OF
> >> +   select PCIEPORTBUS
> >> +   help
> >> + Say Y here if you want internal PCI support on APM X-Gene SoC.
> >> + There are 5 internal PCIe ports available. Each port is GEN3 
> >> capable
> >> + and have varied lanes from x1 to x8.
> >> +
> >>  endmenu
> >> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> >> index 13fb333..34c7c36 100644
> >> --- a/drivers/pci/host/Makefile
> >> +++ b/drivers/pci/host/Makefile
> >> @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
> >>  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
> >>  obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
> >>  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
> >> +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
> >> diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
> >> new file mode 100644
> >> index 000..9e312f6
> >> --- /dev/null
> >> +++ b/drivers/pci/host/pci-xgene.c
> >> @@ -0,0 +1,725 @@
> >> +/**
> >> + * APM X-Gene PCIe Driver
> >> + *
> >> + * Copyright (c) 2013 Applied Micro Circuits Corporation.
> >> + *
> >> + * Author: Tanmay Inamdar .
> >> + *
> >> + * This program is free software; you can redistribute  it and/or modify 
> >> it
> >> + * under  the terms of  the GNU General  Public License as published by 
> >> the
> >> + * Free Software Foundation;  either version 2 of the  License, or (at 
> >> your
> >> + * option) any later version.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >> + * GNU General Public License for more details.
> >> + *
> >> + */
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +
> >> +#define PCIECORE_LTSSM 0x4c
> >> +#define PCIECORE_CTLANDSTATUS  0x50
> >> +#define INTXSTATUSMASK 0x6c
> >> +#define PIM1_1L0x80
> >> +#define IBAR2  0x98
> >> +#define IR2MSK 0x9c
> >> +#define PIM2_1L0xa0
> >> +#define IBAR3L 0xb4
> >> +#define IR3MSKL0xbc
> >> +#define PIM3_1L0xc4
> >> +#define OMR1BARL   0x100
> >> +#define OMR2BARL   0x118
> >> +#define OMR3BARL   0x130
> >> +#define CFGBARL0x154
> >> +#define CFGBARH0x158
> >> +#define CFGCTL 0x15c
> >> +#define RTDID  0x160
> >> +#define BRIDGE_CFG_0   0x2000
> >> +#define BRIDGE_CFG_1   0x2004
> >> +#define BRIDGE_CFG_4   0x2010
> >> +#define BRIDGE_CFG_32  0x2030
> >> +#define BRIDGE_CFG_14  0x2038
> >> +#define BRIDGE_CTRL_1  0x2204
> >> +#define BRIDGE_CTRL_2  0x2208
> >> +#define BRIDGE_CTRL_5  0x2214
> >> +#define BRIDGE_STATUS_00x2600
> >> +#define MEM_RAM_SHUTDOWN0xd070
> >> +#define BLOCK_MEM_RDY   0xd074
> >> +
> >> +#define DEVICE_PORT_TYPE_MASK  0x03c0
> >> +#define PM_FORCE_RP_MODE_MASK  0x0400
> >> +#define SWITCH_PORT_MODE_MASK  0x0800
> >> +#define CLASS_CODE_MASK0xff00
> >> +#define LINK_UP_MASK

Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-26 Thread Liviu Dudau 
On Tue, Mar 25, 2014 at 10:12:14PM +, Tanmay Inamdar wrote:
 Hello Liviu,
 
 Thanks for taking a look. Please see inline.
 
 On Tue, Mar 25, 2014 at 7:02 AM, Liviu Dudau liviu.du...@arm.com wrote:
  On Wed, Mar 19, 2014 at 11:12:39PM +, Tanmay Inamdar wrote:
  This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
  X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
  X-Gene SOC supports maximum 5 PCIe ports.
 
  Signed-off-by: Tanmay Inamdar tinam...@apm.com
 
  Hi Tanmay,
 
  Some comments below.
 
  ---
   drivers/pci/host/Kconfig |   10 +
   drivers/pci/host/Makefile|1 +
   drivers/pci/host/pci-xgene.c |  725 
  ++
   3 files changed, 736 insertions(+)
   create mode 100644 drivers/pci/host/pci-xgene.c
 
  diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
  index 47d46c6..19ce97d 100644
  --- a/drivers/pci/host/Kconfig
  +++ b/drivers/pci/host/Kconfig
  @@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
 
  +config PCI_XGENE
  +   bool X-Gene PCIe controller
  +   depends on ARCH_XGENE
  +   depends on OF
  +   select PCIEPORTBUS
  +   help
  + Say Y here if you want internal PCI support on APM X-Gene SoC.
  + There are 5 internal PCIe ports available. Each port is GEN3 
  capable
  + and have varied lanes from x1 to x8.
  +
   endmenu
  diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
  index 13fb333..34c7c36 100644
  --- a/drivers/pci/host/Makefile
  +++ b/drivers/pci/host/Makefile
  @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
   obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
   obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
   obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
  +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
  diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
  new file mode 100644
  index 000..9e312f6
  --- /dev/null
  +++ b/drivers/pci/host/pci-xgene.c
  @@ -0,0 +1,725 @@
  +/**
  + * APM X-Gene PCIe Driver
  + *
  + * Copyright (c) 2013 Applied Micro Circuits Corporation.
  + *
  + * Author: Tanmay Inamdar tinam...@apm.com.
  + *
  + * This program is free software; you can redistribute  it and/or modify 
  it
  + * under  the terms of  the GNU General  Public License as published by 
  the
  + * Free Software Foundation;  either version 2 of the  License, or (at 
  your
  + * option) any later version.
  + *
  + * This program is distributed in the hope that it will be useful,
  + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  + * GNU General Public License for more details.
  + *
  + */
  +#include linux/clk-private.h
  +#include linux/delay.h
  +#include linux/io.h
  +#include linux/jiffies.h
  +#include linux/memblock.h
  +#include linux/module.h
  +#include linux/of.h
  +#include linux/of_address.h
  +#include linux/of_irq.h
  +#include linux/of_pci.h
  +#include linux/pci.h
  +#include linux/platform_device.h
  +#include linux/slab.h
  +
  +#define PCIECORE_LTSSM 0x4c
  +#define PCIECORE_CTLANDSTATUS  0x50
  +#define INTXSTATUSMASK 0x6c
  +#define PIM1_1L0x80
  +#define IBAR2  0x98
  +#define IR2MSK 0x9c
  +#define PIM2_1L0xa0
  +#define IBAR3L 0xb4
  +#define IR3MSKL0xbc
  +#define PIM3_1L0xc4
  +#define OMR1BARL   0x100
  +#define OMR2BARL   0x118
  +#define OMR3BARL   0x130
  +#define CFGBARL0x154
  +#define CFGBARH0x158
  +#define CFGCTL 0x15c
  +#define RTDID  0x160
  +#define BRIDGE_CFG_0   0x2000
  +#define BRIDGE_CFG_1   0x2004
  +#define BRIDGE_CFG_4   0x2010
  +#define BRIDGE_CFG_32  0x2030
  +#define BRIDGE_CFG_14  0x2038
  +#define BRIDGE_CTRL_1  0x2204
  +#define BRIDGE_CTRL_2  0x2208
  +#define BRIDGE_CTRL_5  0x2214
  +#define BRIDGE_STATUS_00x2600
  +#define MEM_RAM_SHUTDOWN0xd070
  +#define BLOCK_MEM_RDY   0xd074
  +
  +#define DEVICE_PORT_TYPE_MASK  0x03c0
  +#define PM_FORCE_RP_MODE_MASK  0x0400
  +#define SWITCH_PORT_MODE_MASK  0x0800
  +#define CLASS_CODE_MASK0xff00
  +#define LINK_UP_MASK   0x0100
  +#define AER_OPTIONAL_ERROR_EN  0xffc0
  +#define XGENE_PCIE_DEV_CTRL0x2f0f

Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-25 Thread Tanmay Inamdar 
Hello Liviu,

Thanks for taking a look. Please see inline.

On Tue, Mar 25, 2014 at 7:02 AM, Liviu Dudau  wrote:
> On Wed, Mar 19, 2014 at 11:12:39PM +, Tanmay Inamdar wrote:
>> This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
>> X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
>> X-Gene SOC supports maximum 5 PCIe ports.
>>
>> Signed-off-by: Tanmay Inamdar 
>
> Hi Tanmay,
>
> Some comments below.
>
>> ---
>>  drivers/pci/host/Kconfig |   10 +
>>  drivers/pci/host/Makefile|1 +
>>  drivers/pci/host/pci-xgene.c |  725 
>> ++
>>  3 files changed, 736 insertions(+)
>>  create mode 100644 drivers/pci/host/pci-xgene.c
>>
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index 47d46c6..19ce97d 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
>>   There are 3 internal PCI controllers available with a single
>>   built-in EHCI/OHCI host controller present on each one.
>>
>> +config PCI_XGENE
>> +   bool "X-Gene PCIe controller"
>> +   depends on ARCH_XGENE
>> +   depends on OF
>> +   select PCIEPORTBUS
>> +   help
>> + Say Y here if you want internal PCI support on APM X-Gene SoC.
>> + There are 5 internal PCIe ports available. Each port is GEN3 
>> capable
>> + and have varied lanes from x1 to x8.
>> +
>>  endmenu
>> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
>> index 13fb333..34c7c36 100644
>> --- a/drivers/pci/host/Makefile
>> +++ b/drivers/pci/host/Makefile
>> @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
>>  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
>>  obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
>>  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
>> +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
>> diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
>> new file mode 100644
>> index 000..9e312f6
>> --- /dev/null
>> +++ b/drivers/pci/host/pci-xgene.c
>> @@ -0,0 +1,725 @@
>> +/**
>> + * APM X-Gene PCIe Driver
>> + *
>> + * Copyright (c) 2013 Applied Micro Circuits Corporation.
>> + *
>> + * Author: Tanmay Inamdar .
>> + *
>> + * This program is free software; you can redistribute  it and/or modify it
>> + * under  the terms of  the GNU General  Public License as published by the
>> + * Free Software Foundation;  either version 2 of the  License, or (at your
>> + * option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + */
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define PCIECORE_LTSSM 0x4c
>> +#define PCIECORE_CTLANDSTATUS  0x50
>> +#define INTXSTATUSMASK 0x6c
>> +#define PIM1_1L0x80
>> +#define IBAR2  0x98
>> +#define IR2MSK 0x9c
>> +#define PIM2_1L0xa0
>> +#define IBAR3L 0xb4
>> +#define IR3MSKL0xbc
>> +#define PIM3_1L0xc4
>> +#define OMR1BARL   0x100
>> +#define OMR2BARL   0x118
>> +#define OMR3BARL   0x130
>> +#define CFGBARL0x154
>> +#define CFGBARH0x158
>> +#define CFGCTL 0x15c
>> +#define RTDID  0x160
>> +#define BRIDGE_CFG_0   0x2000
>> +#define BRIDGE_CFG_1   0x2004
>> +#define BRIDGE_CFG_4   0x2010
>> +#define BRIDGE_CFG_32  0x2030
>> +#define BRIDGE_CFG_14  0x2038
>> +#define BRIDGE_CTRL_1  0x2204
>> +#define BRIDGE_CTRL_2  0x2208
>> +#define BRIDGE_CTRL_5  0x2214
>> +#define BRIDGE_STATUS_00x2600
>> +#define MEM_RAM_SHUTDOWN0xd070
>> +#define BLOCK_MEM_RDY   0xd074
>> +
>> +#define DEVICE_PORT_TYPE_MASK  0x03c0
>> +#define PM_FORCE_RP_MODE_MASK  0x0400
>> +#define SWITCH_PORT_MODE_MASK  0x0800
>> +#define CLASS_CODE_MASK0xff00
>> +#define LINK_UP_MASK   0x0100
>> +#define AER_OPTIONAL_ERROR_EN  0xffc0
>> +#define XGENE_PCIE_DEV_CTRL0x2f0f
>> +#define AXI_EP_CFG_ACCESS  0x1
>> +#define ENABLE_ASPM0x0800
>> +#define XGENE_PORT_TYPE_RC 0x0500
>> +#define BLOCK_MEM_RDY_VAL

Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-25 Thread Tanmay Inamdar 
Hello Phil,

Thanks for reviewing. Please see inline.

On Tue, Mar 25, 2014 at 1:52 AM,   wrote:
> Hi Tanmay,
>
> On: 19/03/2014 23:15, Tanmay wrote:
>> Subject: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver
>> Sent by: linux-pci-ow...@vger.kernel.org
>>
>> This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
>> X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
>> X-Gene SOC supports maximum 5 PCIe ports.
> 
>
>> +static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
>> +struct of_pci_range *range, u8 *ib_reg_mask)
>> +{
>> +   void __iomem *csr_base = port->csr_base;
>> +   void __iomem *cfg_base = port->cfg_base;
>> +   void *bar_addr;
>> +   void *pim_addr;
>> +   u64 restype = range->flags & IORESOURCE_TYPE_BITS;
>> +   u64 cpu_addr = range->cpu_addr;
>> +   u64 pci_addr = range->pci_addr;
>> +   u64 size = range->size;
>> +   u64 mask = ~(size - 1) | EN_REG;
>> +   u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
>> +   u32 bar_low;
>> +   int region;
>> +
>> +   region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
>> +   if (region < 0) {
>> +  dev_warn(port->dev, "invalid pcie dma-range config\n");
>> +  return;
>> +   }
>> +
>> +   if (restype == PCI_BASE_ADDRESS_MEM_PREFETCH)
>> +  flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
>
> Since IORESOURCE_TYPE_BITS is 0x1f00, and
> PCI_BASE_ADDRESS_MEM_PREFETCH is 0x08, this will never match. I think you
> are mixing up different sets of definitions here. Also, the address
> properties in range->flags are bitfields.

You are right. I will fix this.

>
> Regards
> Phil
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Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-25 Thread Bjorn Helgaas 
On Tue, Mar 25, 2014 at 8:05 AM, Liviu Dudau  wrote:

> ... I'm a bit baffled by pci_claim_resource()
> as it doesn't seem to be used by some architectures. Does it mean it
> is not needed unless you have some BIOS setting up resources for you
> and in that case you need to go and claim the resource?

Many architectures don't use pci_claim_resource() yet.  I'm trying to
unify this so all architectures do use it, but it's taking me a long
time to get this done.

Bjorn
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Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-25 Thread Liviu Dudau 
On Fri, Mar 21, 2014 at 06:23:27PM +, Tanmay Inamdar wrote:
> Hi Sunil,
> 
> I think 'pci_assign_unassigned_bus_resources' should take care of
> this. Liviu can comment more.

Tanmay, I think you are right. I'm a bit baffled by pci_claim_resource()
as it doesn't seem to be used by some architectures. Does it mean it
is not needed unless you have some BIOS setting up resources for you
and in that case you need to go and claim the resource?

Best regards,
Liviu

> 
> Thanks,
> Tanmay
> 
> On Fri, Mar 21, 2014 at 3:15 AM, Sunil Kovvuri  
> wrote:
> > Hi Tanmay,
> >
> > Didn't get how PCI resources are enabled for the device.
> > Liviu Dudau's ARM64 PCI architecture patch enables device resources
> > using genenic API.
> >
> > https://lkml.org/lkml/2014/3/14/276
> > + return pci_enable_resources(dev, mask);
> >
> > pci_enable_resources() checks if resource->parent is non-NULL.
> > And at the same time Liviu Dudau's patch doesn't use pci_claim_resource.
> >
> > Please look into below patches from Bjorn.
> > https://lkml.org/lkml/2014/2/26/629
> >
> > Thanks,
> > Sunil.
> >
> > On Thu, Mar 20, 2014 at 4:42 AM, Tanmay Inamdar  wrote:
> >> This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
> >> X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
> >> X-Gene SOC supports maximum 5 PCIe ports.
> >>
> >> Signed-off-by: Tanmay Inamdar 
> >> ---
> >>  drivers/pci/host/Kconfig |   10 +
> >>  drivers/pci/host/Makefile|1 +
> >>  drivers/pci/host/pci-xgene.c |  725 
> >> ++
> >>  3 files changed, 736 insertions(+)
> >>  create mode 100644 drivers/pci/host/pci-xgene.c
> >>
> >> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> >> index 47d46c6..19ce97d 100644
> >> --- a/drivers/pci/host/Kconfig
> >> +++ b/drivers/pci/host/Kconfig
> >> @@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
> >>   There are 3 internal PCI controllers available with a single
> >>   built-in EHCI/OHCI host controller present on each one.
> >>
> >> +config PCI_XGENE
> >> +   bool "X-Gene PCIe controller"
> >> +   depends on ARCH_XGENE
> >> +   depends on OF
> >> +   select PCIEPORTBUS
> >> +   help
> >> + Say Y here if you want internal PCI support on APM X-Gene SoC.
> >> + There are 5 internal PCIe ports available. Each port is GEN3 
> >> capable
> >> + and have varied lanes from x1 to x8.
> >> +
> >>  endmenu
> >> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> >> index 13fb333..34c7c36 100644
> >> --- a/drivers/pci/host/Makefile
> >> +++ b/drivers/pci/host/Makefile
> >> @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
> >>  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
> >>  obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
> >>  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
> >> +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
> >> diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
> >> new file mode 100644
> >> index 000..9e312f6
> >> --- /dev/null
> >> +++ b/drivers/pci/host/pci-xgene.c
> >> @@ -0,0 +1,725 @@
> >> +/**
> >> + * APM X-Gene PCIe Driver
> >> + *
> >> + * Copyright (c) 2013 Applied Micro Circuits Corporation.
> >> + *
> >> + * Author: Tanmay Inamdar .
> >> + *
> >> + * This program is free software; you can redistribute  it and/or modify 
> >> it
> >> + * under  the terms of  the GNU General  Public License as published by 
> >> the
> >> + * Free Software Foundation;  either version 2 of the  License, or (at 
> >> your
> >> + * option) any later version.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >> + * GNU General Public License for more details.
> >> + *
> >> + */
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +
> >> +#define PCIECORE_LTSSM 0x4c
> >> +#define PCIECORE_CTLANDSTATUS  0x50
> >> +#define INTXSTATUSMASK 0x6c
> >> +#define PIM1_1L0x80
> >> +#define IBAR2  0x98
> >> +#define IR2MSK 0x9c
> >> +#define PIM2_1L0xa0
> >> +#define IBAR3L 0xb4
> >> +#define IR3MSKL0xbc
> >> +#define PIM3_1L0xc4
> >> +#define OMR1BARL   0x100
> >> +#define OMR2BARL   0x118
> >> +#define OMR3BARL   0x130
> >> +#define CFGBARL0x154
> >> +#define CFGBARH0x158
> >> +#define CFGCTL 0x15c
> >> +#define RTDID  0x160
> >>

Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-25 Thread Liviu Dudau 
On Wed, Mar 19, 2014 at 11:12:39PM +, Tanmay Inamdar wrote:
> This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
> X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
> X-Gene SOC supports maximum 5 PCIe ports.
> 
> Signed-off-by: Tanmay Inamdar 

Hi Tanmay,

Some comments below.

> ---
>  drivers/pci/host/Kconfig |   10 +
>  drivers/pci/host/Makefile|1 +
>  drivers/pci/host/pci-xgene.c |  725 
> ++
>  3 files changed, 736 insertions(+)
>  create mode 100644 drivers/pci/host/pci-xgene.c
> 
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index 47d46c6..19ce97d 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
>   There are 3 internal PCI controllers available with a single
>   built-in EHCI/OHCI host controller present on each one.
> 
> +config PCI_XGENE
> +   bool "X-Gene PCIe controller"
> +   depends on ARCH_XGENE
> +   depends on OF
> +   select PCIEPORTBUS
> +   help
> + Say Y here if you want internal PCI support on APM X-Gene SoC.
> + There are 5 internal PCIe ports available. Each port is GEN3 capable
> + and have varied lanes from x1 to x8.
> +
>  endmenu
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index 13fb333..34c7c36 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
>  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
>  obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
>  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
> +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
> diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
> new file mode 100644
> index 000..9e312f6
> --- /dev/null
> +++ b/drivers/pci/host/pci-xgene.c
> @@ -0,0 +1,725 @@
> +/**
> + * APM X-Gene PCIe Driver
> + *
> + * Copyright (c) 2013 Applied Micro Circuits Corporation.
> + *
> + * Author: Tanmay Inamdar .
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define PCIECORE_LTSSM 0x4c
> +#define PCIECORE_CTLANDSTATUS  0x50
> +#define INTXSTATUSMASK 0x6c
> +#define PIM1_1L0x80
> +#define IBAR2  0x98
> +#define IR2MSK 0x9c
> +#define PIM2_1L0xa0
> +#define IBAR3L 0xb4
> +#define IR3MSKL0xbc
> +#define PIM3_1L0xc4
> +#define OMR1BARL   0x100
> +#define OMR2BARL   0x118
> +#define OMR3BARL   0x130
> +#define CFGBARL0x154
> +#define CFGBARH0x158
> +#define CFGCTL 0x15c
> +#define RTDID  0x160
> +#define BRIDGE_CFG_0   0x2000
> +#define BRIDGE_CFG_1   0x2004
> +#define BRIDGE_CFG_4   0x2010
> +#define BRIDGE_CFG_32  0x2030
> +#define BRIDGE_CFG_14  0x2038
> +#define BRIDGE_CTRL_1  0x2204
> +#define BRIDGE_CTRL_2  0x2208
> +#define BRIDGE_CTRL_5  0x2214
> +#define BRIDGE_STATUS_00x2600
> +#define MEM_RAM_SHUTDOWN0xd070
> +#define BLOCK_MEM_RDY   0xd074
> +
> +#define DEVICE_PORT_TYPE_MASK  0x03c0
> +#define PM_FORCE_RP_MODE_MASK  0x0400
> +#define SWITCH_PORT_MODE_MASK  0x0800
> +#define CLASS_CODE_MASK0xff00
> +#define LINK_UP_MASK   0x0100
> +#define AER_OPTIONAL_ERROR_EN  0xffc0
> +#define XGENE_PCIE_DEV_CTRL0x2f0f
> +#define AXI_EP_CFG_ACCESS  0x1
> +#define ENABLE_ASPM0x0800
> +#define XGENE_PORT_TYPE_RC 0x0500
> +#define BLOCK_MEM_RDY_VAL   0x
> +#define EN_COHERENCY   0xF000
> +#define EN_REG 0x0001
> +#define OB_LO_IO   0x0002
> +#define XGENE_PCIE_VENDORID0xE008
> +#define

Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-25 Thread Phil . Edworthy 
Hi Tanmay,

On: 19/03/2014 23:15, Tanmay wrote:
> Subject: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver
> Sent by: linux-pci-ow...@vger.kernel.org
> 
> This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
> X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
> X-Gene SOC supports maximum 5 PCIe ports.


> +static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
> +struct of_pci_range *range, u8 *ib_reg_mask)
> +{
> +   void __iomem *csr_base = port->csr_base;
> +   void __iomem *cfg_base = port->cfg_base;
> +   void *bar_addr;
> +   void *pim_addr;
> +   u64 restype = range->flags & IORESOURCE_TYPE_BITS;
> +   u64 cpu_addr = range->cpu_addr;
> +   u64 pci_addr = range->pci_addr;
> +   u64 size = range->size;
> +   u64 mask = ~(size - 1) | EN_REG;
> +   u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
> +   u32 bar_low;
> +   int region;
> +
> +   region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
> +   if (region < 0) {
> +  dev_warn(port->dev, "invalid pcie dma-range config\n");
> +  return;
> +   }
> +
> +   if (restype == PCI_BASE_ADDRESS_MEM_PREFETCH)
> +  flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;

Since IORESOURCE_TYPE_BITS is 0x1f00, and 
PCI_BASE_ADDRESS_MEM_PREFETCH is 0x08, this will never match. I think you 
are mixing up different sets of definitions here. Also, the address 
properties in range->flags are bitfields.

Regards
Phil
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Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-25 Thread Phil . Edworthy 
Hi Tanmay,

On: 19/03/2014 23:15, Tanmay wrote:
 Subject: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver
 Sent by: linux-pci-ow...@vger.kernel.org
 
 This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
 X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
 X-Gene SOC supports maximum 5 PCIe ports.
snip

 +static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
 +struct of_pci_range *range, u8 *ib_reg_mask)
 +{
 +   void __iomem *csr_base = port-csr_base;
 +   void __iomem *cfg_base = port-cfg_base;
 +   void *bar_addr;
 +   void *pim_addr;
 +   u64 restype = range-flags  IORESOURCE_TYPE_BITS;
 +   u64 cpu_addr = range-cpu_addr;
 +   u64 pci_addr = range-pci_addr;
 +   u64 size = range-size;
 +   u64 mask = ~(size - 1) | EN_REG;
 +   u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
 +   u32 bar_low;
 +   int region;
 +
 +   region = xgene_pcie_select_ib_reg(ib_reg_mask, range-size);
 +   if (region  0) {
 +  dev_warn(port-dev, invalid pcie dma-range config\n);
 +  return;
 +   }
 +
 +   if (restype == PCI_BASE_ADDRESS_MEM_PREFETCH)
 +  flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;

Since IORESOURCE_TYPE_BITS is 0x1f00, and 
PCI_BASE_ADDRESS_MEM_PREFETCH is 0x08, this will never match. I think you 
are mixing up different sets of definitions here. Also, the address 
properties in range-flags are bitfields.

Regards
Phil
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Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-25 Thread Liviu Dudau 
On Wed, Mar 19, 2014 at 11:12:39PM +, Tanmay Inamdar wrote:
 This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
 X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
 X-Gene SOC supports maximum 5 PCIe ports.
 
 Signed-off-by: Tanmay Inamdar tinam...@apm.com

Hi Tanmay,

Some comments below.

 ---
  drivers/pci/host/Kconfig |   10 +
  drivers/pci/host/Makefile|1 +
  drivers/pci/host/pci-xgene.c |  725 
 ++
  3 files changed, 736 insertions(+)
  create mode 100644 drivers/pci/host/pci-xgene.c
 
 diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
 index 47d46c6..19ce97d 100644
 --- a/drivers/pci/host/Kconfig
 +++ b/drivers/pci/host/Kconfig
 @@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
   There are 3 internal PCI controllers available with a single
   built-in EHCI/OHCI host controller present on each one.
 
 +config PCI_XGENE
 +   bool X-Gene PCIe controller
 +   depends on ARCH_XGENE
 +   depends on OF
 +   select PCIEPORTBUS
 +   help
 + Say Y here if you want internal PCI support on APM X-Gene SoC.
 + There are 5 internal PCIe ports available. Each port is GEN3 capable
 + and have varied lanes from x1 to x8.
 +
  endmenu
 diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
 index 13fb333..34c7c36 100644
 --- a/drivers/pci/host/Makefile
 +++ b/drivers/pci/host/Makefile
 @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
  obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
 +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
 diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
 new file mode 100644
 index 000..9e312f6
 --- /dev/null
 +++ b/drivers/pci/host/pci-xgene.c
 @@ -0,0 +1,725 @@
 +/**
 + * APM X-Gene PCIe Driver
 + *
 + * Copyright (c) 2013 Applied Micro Circuits Corporation.
 + *
 + * Author: Tanmay Inamdar tinam...@apm.com.
 + *
 + * This program is free software; you can redistribute  it and/or modify it
 + * under  the terms of  the GNU General  Public License as published by the
 + * Free Software Foundation;  either version 2 of the  License, or (at your
 + * option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + */
 +#include linux/clk-private.h
 +#include linux/delay.h
 +#include linux/io.h
 +#include linux/jiffies.h
 +#include linux/memblock.h
 +#include linux/module.h
 +#include linux/of.h
 +#include linux/of_address.h
 +#include linux/of_irq.h
 +#include linux/of_pci.h
 +#include linux/pci.h
 +#include linux/platform_device.h
 +#include linux/slab.h
 +
 +#define PCIECORE_LTSSM 0x4c
 +#define PCIECORE_CTLANDSTATUS  0x50
 +#define INTXSTATUSMASK 0x6c
 +#define PIM1_1L0x80
 +#define IBAR2  0x98
 +#define IR2MSK 0x9c
 +#define PIM2_1L0xa0
 +#define IBAR3L 0xb4
 +#define IR3MSKL0xbc
 +#define PIM3_1L0xc4
 +#define OMR1BARL   0x100
 +#define OMR2BARL   0x118
 +#define OMR3BARL   0x130
 +#define CFGBARL0x154
 +#define CFGBARH0x158
 +#define CFGCTL 0x15c
 +#define RTDID  0x160
 +#define BRIDGE_CFG_0   0x2000
 +#define BRIDGE_CFG_1   0x2004
 +#define BRIDGE_CFG_4   0x2010
 +#define BRIDGE_CFG_32  0x2030
 +#define BRIDGE_CFG_14  0x2038
 +#define BRIDGE_CTRL_1  0x2204
 +#define BRIDGE_CTRL_2  0x2208
 +#define BRIDGE_CTRL_5  0x2214
 +#define BRIDGE_STATUS_00x2600
 +#define MEM_RAM_SHUTDOWN0xd070
 +#define BLOCK_MEM_RDY   0xd074
 +
 +#define DEVICE_PORT_TYPE_MASK  0x03c0
 +#define PM_FORCE_RP_MODE_MASK  0x0400
 +#define SWITCH_PORT_MODE_MASK  0x0800
 +#define CLASS_CODE_MASK0xff00
 +#define LINK_UP_MASK   0x0100
 +#define AER_OPTIONAL_ERROR_EN  0xffc0
 +#define XGENE_PCIE_DEV_CTRL0x2f0f
 +#define AXI_EP_CFG_ACCESS  0x1
 +#define ENABLE_ASPM0x0800
 +#define XGENE_PORT_TYPE_RC 0x0500
 +#define BLOCK_MEM_RDY_VAL   0x
 +#define EN_COHERENCY   0xF000
 +#define EN_REG 0x0001
 +#define OB_LO_IO

Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-25 Thread Liviu Dudau 
On Fri, Mar 21, 2014 at 06:23:27PM +, Tanmay Inamdar wrote:
 Hi Sunil,
 
 I think 'pci_assign_unassigned_bus_resources' should take care of
 this. Liviu can comment more.

Tanmay, I think you are right. I'm a bit baffled by pci_claim_resource()
as it doesn't seem to be used by some architectures. Does it mean it
is not needed unless you have some BIOS setting up resources for you
and in that case you need to go and claim the resource?

Best regards,
Liviu

 
 Thanks,
 Tanmay
 
 On Fri, Mar 21, 2014 at 3:15 AM, Sunil Kovvuri sunil.kovv...@gmail.com 
 wrote:
  Hi Tanmay,
 
  Didn't get how PCI resources are enabled for the device.
  Liviu Dudau's ARM64 PCI architecture patch enables device resources
  using genenic API.
 
  https://lkml.org/lkml/2014/3/14/276
  + return pci_enable_resources(dev, mask);
 
  pci_enable_resources() checks if resource-parent is non-NULL.
  And at the same time Liviu Dudau's patch doesn't use pci_claim_resource.
 
  Please look into below patches from Bjorn.
  https://lkml.org/lkml/2014/2/26/629
 
  Thanks,
  Sunil.
 
  On Thu, Mar 20, 2014 at 4:42 AM, Tanmay Inamdar tinam...@apm.com wrote:
  This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
  X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
  X-Gene SOC supports maximum 5 PCIe ports.
 
  Signed-off-by: Tanmay Inamdar tinam...@apm.com
  ---
   drivers/pci/host/Kconfig |   10 +
   drivers/pci/host/Makefile|1 +
   drivers/pci/host/pci-xgene.c |  725 
  ++
   3 files changed, 736 insertions(+)
   create mode 100644 drivers/pci/host/pci-xgene.c
 
  diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
  index 47d46c6..19ce97d 100644
  --- a/drivers/pci/host/Kconfig
  +++ b/drivers/pci/host/Kconfig
  @@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
 
  +config PCI_XGENE
  +   bool X-Gene PCIe controller
  +   depends on ARCH_XGENE
  +   depends on OF
  +   select PCIEPORTBUS
  +   help
  + Say Y here if you want internal PCI support on APM X-Gene SoC.
  + There are 5 internal PCIe ports available. Each port is GEN3 
  capable
  + and have varied lanes from x1 to x8.
  +
   endmenu
  diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
  index 13fb333..34c7c36 100644
  --- a/drivers/pci/host/Makefile
  +++ b/drivers/pci/host/Makefile
  @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
   obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
   obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
   obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
  +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
  diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
  new file mode 100644
  index 000..9e312f6
  --- /dev/null
  +++ b/drivers/pci/host/pci-xgene.c
  @@ -0,0 +1,725 @@
  +/**
  + * APM X-Gene PCIe Driver
  + *
  + * Copyright (c) 2013 Applied Micro Circuits Corporation.
  + *
  + * Author: Tanmay Inamdar tinam...@apm.com.
  + *
  + * This program is free software; you can redistribute  it and/or modify 
  it
  + * under  the terms of  the GNU General  Public License as published by 
  the
  + * Free Software Foundation;  either version 2 of the  License, or (at 
  your
  + * option) any later version.
  + *
  + * This program is distributed in the hope that it will be useful,
  + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  + * GNU General Public License for more details.
  + *
  + */
  +#include linux/clk-private.h
  +#include linux/delay.h
  +#include linux/io.h
  +#include linux/jiffies.h
  +#include linux/memblock.h
  +#include linux/module.h
  +#include linux/of.h
  +#include linux/of_address.h
  +#include linux/of_irq.h
  +#include linux/of_pci.h
  +#include linux/pci.h
  +#include linux/platform_device.h
  +#include linux/slab.h
  +
  +#define PCIECORE_LTSSM 0x4c
  +#define PCIECORE_CTLANDSTATUS  0x50
  +#define INTXSTATUSMASK 0x6c
  +#define PIM1_1L0x80
  +#define IBAR2  0x98
  +#define IR2MSK 0x9c
  +#define PIM2_1L0xa0
  +#define IBAR3L 0xb4
  +#define IR3MSKL0xbc
  +#define PIM3_1L0xc4
  +#define OMR1BARL   0x100
  +#define OMR2BARL   0x118
  +#define OMR3BARL   0x130
  +#define CFGBARL0x154
  +#define CFGBARH0x158
  +#define CFGCTL 0x15c
  +#define RTDID  0x160
  +#define BRIDGE_CFG_0   0x2000
  +#define BRIDGE_CFG_1   0x2004

Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-25 Thread Bjorn Helgaas 
On Tue, Mar 25, 2014 at 8:05 AM, Liviu Dudau liviu.du...@arm.com wrote:

 ... I'm a bit baffled by pci_claim_resource()
 as it doesn't seem to be used by some architectures. Does it mean it
 is not needed unless you have some BIOS setting up resources for you
 and in that case you need to go and claim the resource?

Many architectures don't use pci_claim_resource() yet.  I'm trying to
unify this so all architectures do use it, but it's taking me a long
time to get this done.

Bjorn
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Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-25 Thread Tanmay Inamdar 
Hello Phil,

Thanks for reviewing. Please see inline.

On Tue, Mar 25, 2014 at 1:52 AM,  phil.edwor...@renesas.com wrote:
 Hi Tanmay,

 On: 19/03/2014 23:15, Tanmay wrote:
 Subject: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver
 Sent by: linux-pci-ow...@vger.kernel.org

 This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
 X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
 X-Gene SOC supports maximum 5 PCIe ports.
 snip

 +static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
 +struct of_pci_range *range, u8 *ib_reg_mask)
 +{
 +   void __iomem *csr_base = port-csr_base;
 +   void __iomem *cfg_base = port-cfg_base;
 +   void *bar_addr;
 +   void *pim_addr;
 +   u64 restype = range-flags  IORESOURCE_TYPE_BITS;
 +   u64 cpu_addr = range-cpu_addr;
 +   u64 pci_addr = range-pci_addr;
 +   u64 size = range-size;
 +   u64 mask = ~(size - 1) | EN_REG;
 +   u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
 +   u32 bar_low;
 +   int region;
 +
 +   region = xgene_pcie_select_ib_reg(ib_reg_mask, range-size);
 +   if (region  0) {
 +  dev_warn(port-dev, invalid pcie dma-range config\n);
 +  return;
 +   }
 +
 +   if (restype == PCI_BASE_ADDRESS_MEM_PREFETCH)
 +  flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;

 Since IORESOURCE_TYPE_BITS is 0x1f00, and
 PCI_BASE_ADDRESS_MEM_PREFETCH is 0x08, this will never match. I think you
 are mixing up different sets of definitions here. Also, the address
 properties in range-flags are bitfields.

You are right. I will fix this.


 Regards
 Phil
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Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-25 Thread Tanmay Inamdar 
Hello Liviu,

Thanks for taking a look. Please see inline.

On Tue, Mar 25, 2014 at 7:02 AM, Liviu Dudau liviu.du...@arm.com wrote:
 On Wed, Mar 19, 2014 at 11:12:39PM +, Tanmay Inamdar wrote:
 This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
 X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
 X-Gene SOC supports maximum 5 PCIe ports.

 Signed-off-by: Tanmay Inamdar tinam...@apm.com

 Hi Tanmay,

 Some comments below.

 ---
  drivers/pci/host/Kconfig |   10 +
  drivers/pci/host/Makefile|1 +
  drivers/pci/host/pci-xgene.c |  725 
 ++
  3 files changed, 736 insertions(+)
  create mode 100644 drivers/pci/host/pci-xgene.c

 diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
 index 47d46c6..19ce97d 100644
 --- a/drivers/pci/host/Kconfig
 +++ b/drivers/pci/host/Kconfig
 @@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
   There are 3 internal PCI controllers available with a single
   built-in EHCI/OHCI host controller present on each one.

 +config PCI_XGENE
 +   bool X-Gene PCIe controller
 +   depends on ARCH_XGENE
 +   depends on OF
 +   select PCIEPORTBUS
 +   help
 + Say Y here if you want internal PCI support on APM X-Gene SoC.
 + There are 5 internal PCIe ports available. Each port is GEN3 
 capable
 + and have varied lanes from x1 to x8.
 +
  endmenu
 diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
 index 13fb333..34c7c36 100644
 --- a/drivers/pci/host/Makefile
 +++ b/drivers/pci/host/Makefile
 @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
  obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
 +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
 diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
 new file mode 100644
 index 000..9e312f6
 --- /dev/null
 +++ b/drivers/pci/host/pci-xgene.c
 @@ -0,0 +1,725 @@
 +/**
 + * APM X-Gene PCIe Driver
 + *
 + * Copyright (c) 2013 Applied Micro Circuits Corporation.
 + *
 + * Author: Tanmay Inamdar tinam...@apm.com.
 + *
 + * This program is free software; you can redistribute  it and/or modify it
 + * under  the terms of  the GNU General  Public License as published by the
 + * Free Software Foundation;  either version 2 of the  License, or (at your
 + * option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + */
 +#include linux/clk-private.h
 +#include linux/delay.h
 +#include linux/io.h
 +#include linux/jiffies.h
 +#include linux/memblock.h
 +#include linux/module.h
 +#include linux/of.h
 +#include linux/of_address.h
 +#include linux/of_irq.h
 +#include linux/of_pci.h
 +#include linux/pci.h
 +#include linux/platform_device.h
 +#include linux/slab.h
 +
 +#define PCIECORE_LTSSM 0x4c
 +#define PCIECORE_CTLANDSTATUS  0x50
 +#define INTXSTATUSMASK 0x6c
 +#define PIM1_1L0x80
 +#define IBAR2  0x98
 +#define IR2MSK 0x9c
 +#define PIM2_1L0xa0
 +#define IBAR3L 0xb4
 +#define IR3MSKL0xbc
 +#define PIM3_1L0xc4
 +#define OMR1BARL   0x100
 +#define OMR2BARL   0x118
 +#define OMR3BARL   0x130
 +#define CFGBARL0x154
 +#define CFGBARH0x158
 +#define CFGCTL 0x15c
 +#define RTDID  0x160
 +#define BRIDGE_CFG_0   0x2000
 +#define BRIDGE_CFG_1   0x2004
 +#define BRIDGE_CFG_4   0x2010
 +#define BRIDGE_CFG_32  0x2030
 +#define BRIDGE_CFG_14  0x2038
 +#define BRIDGE_CTRL_1  0x2204
 +#define BRIDGE_CTRL_2  0x2208
 +#define BRIDGE_CTRL_5  0x2214
 +#define BRIDGE_STATUS_00x2600
 +#define MEM_RAM_SHUTDOWN0xd070
 +#define BLOCK_MEM_RDY   0xd074
 +
 +#define DEVICE_PORT_TYPE_MASK  0x03c0
 +#define PM_FORCE_RP_MODE_MASK  0x0400
 +#define SWITCH_PORT_MODE_MASK  0x0800
 +#define CLASS_CODE_MASK0xff00
 +#define LINK_UP_MASK   0x0100
 +#define AER_OPTIONAL_ERROR_EN  0xffc0
 +#define XGENE_PCIE_DEV_CTRL0x2f0f
 +#define AXI_EP_CFG_ACCESS  0x1
 +#define ENABLE_ASPM0x0800
 +#define XGENE_PORT_TYPE_RC 0x0500
 +#define BLOCK_MEM_RDY_VAL

Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-21 Thread Tanmay Inamdar 
Hi Sunil,

I think 'pci_assign_unassigned_bus_resources' should take care of
this. Liviu can comment more.

Thanks,
Tanmay

On Fri, Mar 21, 2014 at 3:15 AM, Sunil Kovvuri  wrote:
> Hi Tanmay,
>
> Didn't get how PCI resources are enabled for the device.
> Liviu Dudau's ARM64 PCI architecture patch enables device resources
> using genenic API.
>
> https://lkml.org/lkml/2014/3/14/276
> + return pci_enable_resources(dev, mask);
>
> pci_enable_resources() checks if resource->parent is non-NULL.
> And at the same time Liviu Dudau's patch doesn't use pci_claim_resource.
>
> Please look into below patches from Bjorn.
> https://lkml.org/lkml/2014/2/26/629
>
> Thanks,
> Sunil.
>
> On Thu, Mar 20, 2014 at 4:42 AM, Tanmay Inamdar  wrote:
>> This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
>> X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
>> X-Gene SOC supports maximum 5 PCIe ports.
>>
>> Signed-off-by: Tanmay Inamdar 
>> ---
>>  drivers/pci/host/Kconfig |   10 +
>>  drivers/pci/host/Makefile|1 +
>>  drivers/pci/host/pci-xgene.c |  725 
>> ++
>>  3 files changed, 736 insertions(+)
>>  create mode 100644 drivers/pci/host/pci-xgene.c
>>
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index 47d46c6..19ce97d 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
>>   There are 3 internal PCI controllers available with a single
>>   built-in EHCI/OHCI host controller present on each one.
>>
>> +config PCI_XGENE
>> +   bool "X-Gene PCIe controller"
>> +   depends on ARCH_XGENE
>> +   depends on OF
>> +   select PCIEPORTBUS
>> +   help
>> + Say Y here if you want internal PCI support on APM X-Gene SoC.
>> + There are 5 internal PCIe ports available. Each port is GEN3 
>> capable
>> + and have varied lanes from x1 to x8.
>> +
>>  endmenu
>> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
>> index 13fb333..34c7c36 100644
>> --- a/drivers/pci/host/Makefile
>> +++ b/drivers/pci/host/Makefile
>> @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
>>  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
>>  obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
>>  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
>> +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
>> diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
>> new file mode 100644
>> index 000..9e312f6
>> --- /dev/null
>> +++ b/drivers/pci/host/pci-xgene.c
>> @@ -0,0 +1,725 @@
>> +/**
>> + * APM X-Gene PCIe Driver
>> + *
>> + * Copyright (c) 2013 Applied Micro Circuits Corporation.
>> + *
>> + * Author: Tanmay Inamdar .
>> + *
>> + * This program is free software; you can redistribute  it and/or modify it
>> + * under  the terms of  the GNU General  Public License as published by the
>> + * Free Software Foundation;  either version 2 of the  License, or (at your
>> + * option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + */
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define PCIECORE_LTSSM 0x4c
>> +#define PCIECORE_CTLANDSTATUS  0x50
>> +#define INTXSTATUSMASK 0x6c
>> +#define PIM1_1L0x80
>> +#define IBAR2  0x98
>> +#define IR2MSK 0x9c
>> +#define PIM2_1L0xa0
>> +#define IBAR3L 0xb4
>> +#define IR3MSKL0xbc
>> +#define PIM3_1L0xc4
>> +#define OMR1BARL   0x100
>> +#define OMR2BARL   0x118
>> +#define OMR3BARL   0x130
>> +#define CFGBARL0x154
>> +#define CFGBARH0x158
>> +#define CFGCTL 0x15c
>> +#define RTDID  0x160
>> +#define BRIDGE_CFG_0   0x2000
>> +#define BRIDGE_CFG_1   0x2004
>> +#define BRIDGE_CFG_4   0x2010
>> +#define BRIDGE_CFG_32  0x2030
>> +#define BRIDGE_CFG_14  0x2038
>> +#define BRIDGE_CTRL_1  0x2204
>> +#define BRIDGE_CTRL_2  0x2208
>> +#define BRIDGE_CTRL_5  0x2214
>> +#define BRIDGE_STATUS_00x2600
>> +#define MEM_RAM_SHUTDOWN0xd070
>> +#define BLOCK_MEM_RDY   0xd074
>> +
>> +#define DEVICE_PORT_TYPE_MASK  0x03c0
>> +#define

Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-21 Thread Sunil Kovvuri 
Hi Tanmay,

Didn't get how PCI resources are enabled for the device.
Liviu Dudau's ARM64 PCI architecture patch enables device resources
using genenic API.

https://lkml.org/lkml/2014/3/14/276
+ return pci_enable_resources(dev, mask);

pci_enable_resources() checks if resource->parent is non-NULL.
And at the same time Liviu Dudau's patch doesn't use pci_claim_resource.

Please look into below patches from Bjorn.
https://lkml.org/lkml/2014/2/26/629

Thanks,
Sunil.

On Thu, Mar 20, 2014 at 4:42 AM, Tanmay Inamdar  wrote:
> This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
> X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
> X-Gene SOC supports maximum 5 PCIe ports.
>
> Signed-off-by: Tanmay Inamdar 
> ---
>  drivers/pci/host/Kconfig |   10 +
>  drivers/pci/host/Makefile|1 +
>  drivers/pci/host/pci-xgene.c |  725 
> ++
>  3 files changed, 736 insertions(+)
>  create mode 100644 drivers/pci/host/pci-xgene.c
>
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index 47d46c6..19ce97d 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
>   There are 3 internal PCI controllers available with a single
>   built-in EHCI/OHCI host controller present on each one.
>
> +config PCI_XGENE
> +   bool "X-Gene PCIe controller"
> +   depends on ARCH_XGENE
> +   depends on OF
> +   select PCIEPORTBUS
> +   help
> + Say Y here if you want internal PCI support on APM X-Gene SoC.
> + There are 5 internal PCIe ports available. Each port is GEN3 capable
> + and have varied lanes from x1 to x8.
> +
>  endmenu
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index 13fb333..34c7c36 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
>  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
>  obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
>  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
> +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
> diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
> new file mode 100644
> index 000..9e312f6
> --- /dev/null
> +++ b/drivers/pci/host/pci-xgene.c
> @@ -0,0 +1,725 @@
> +/**
> + * APM X-Gene PCIe Driver
> + *
> + * Copyright (c) 2013 Applied Micro Circuits Corporation.
> + *
> + * Author: Tanmay Inamdar .
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define PCIECORE_LTSSM 0x4c
> +#define PCIECORE_CTLANDSTATUS  0x50
> +#define INTXSTATUSMASK 0x6c
> +#define PIM1_1L0x80
> +#define IBAR2  0x98
> +#define IR2MSK 0x9c
> +#define PIM2_1L0xa0
> +#define IBAR3L 0xb4
> +#define IR3MSKL0xbc
> +#define PIM3_1L0xc4
> +#define OMR1BARL   0x100
> +#define OMR2BARL   0x118
> +#define OMR3BARL   0x130
> +#define CFGBARL0x154
> +#define CFGBARH0x158
> +#define CFGCTL 0x15c
> +#define RTDID  0x160
> +#define BRIDGE_CFG_0   0x2000
> +#define BRIDGE_CFG_1   0x2004
> +#define BRIDGE_CFG_4   0x2010
> +#define BRIDGE_CFG_32  0x2030
> +#define BRIDGE_CFG_14  0x2038
> +#define BRIDGE_CTRL_1  0x2204
> +#define BRIDGE_CTRL_2  0x2208
> +#define BRIDGE_CTRL_5  0x2214
> +#define BRIDGE_STATUS_00x2600
> +#define MEM_RAM_SHUTDOWN0xd070
> +#define BLOCK_MEM_RDY   0xd074
> +
> +#define DEVICE_PORT_TYPE_MASK  0x03c0
> +#define PM_FORCE_RP_MODE_MASK  0x0400
> +#define SWITCH_PORT_MODE_MASK  0x0800
> +#define CLASS_CODE_MASK0xff00
> +#define LINK_UP_MASK   0x0100
> +#define AER_OPTIONAL_ERROR_EN  0xffc0
> +#define XGENE_PCIE_DEV_CTRL0x2f0f
> +#define

Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-21 Thread Sunil Kovvuri 
Hi Tanmay,

Didn't get how PCI resources are enabled for the device.
Liviu Dudau's ARM64 PCI architecture patch enables device resources
using genenic API.

https://lkml.org/lkml/2014/3/14/276
+ return pci_enable_resources(dev, mask);

pci_enable_resources() checks if resource-parent is non-NULL.
And at the same time Liviu Dudau's patch doesn't use pci_claim_resource.

Please look into below patches from Bjorn.
https://lkml.org/lkml/2014/2/26/629

Thanks,
Sunil.

On Thu, Mar 20, 2014 at 4:42 AM, Tanmay Inamdar tinam...@apm.com wrote:
 This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
 X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
 X-Gene SOC supports maximum 5 PCIe ports.

 Signed-off-by: Tanmay Inamdar tinam...@apm.com
 ---
  drivers/pci/host/Kconfig |   10 +
  drivers/pci/host/Makefile|1 +
  drivers/pci/host/pci-xgene.c |  725 
 ++
  3 files changed, 736 insertions(+)
  create mode 100644 drivers/pci/host/pci-xgene.c

 diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
 index 47d46c6..19ce97d 100644
 --- a/drivers/pci/host/Kconfig
 +++ b/drivers/pci/host/Kconfig
 @@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
   There are 3 internal PCI controllers available with a single
   built-in EHCI/OHCI host controller present on each one.

 +config PCI_XGENE
 +   bool X-Gene PCIe controller
 +   depends on ARCH_XGENE
 +   depends on OF
 +   select PCIEPORTBUS
 +   help
 + Say Y here if you want internal PCI support on APM X-Gene SoC.
 + There are 5 internal PCIe ports available. Each port is GEN3 capable
 + and have varied lanes from x1 to x8.
 +
  endmenu
 diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
 index 13fb333..34c7c36 100644
 --- a/drivers/pci/host/Makefile
 +++ b/drivers/pci/host/Makefile
 @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
  obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
 +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
 diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
 new file mode 100644
 index 000..9e312f6
 --- /dev/null
 +++ b/drivers/pci/host/pci-xgene.c
 @@ -0,0 +1,725 @@
 +/**
 + * APM X-Gene PCIe Driver
 + *
 + * Copyright (c) 2013 Applied Micro Circuits Corporation.
 + *
 + * Author: Tanmay Inamdar tinam...@apm.com.
 + *
 + * This program is free software; you can redistribute  it and/or modify it
 + * under  the terms of  the GNU General  Public License as published by the
 + * Free Software Foundation;  either version 2 of the  License, or (at your
 + * option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + */
 +#include linux/clk-private.h
 +#include linux/delay.h
 +#include linux/io.h
 +#include linux/jiffies.h
 +#include linux/memblock.h
 +#include linux/module.h
 +#include linux/of.h
 +#include linux/of_address.h
 +#include linux/of_irq.h
 +#include linux/of_pci.h
 +#include linux/pci.h
 +#include linux/platform_device.h
 +#include linux/slab.h
 +
 +#define PCIECORE_LTSSM 0x4c
 +#define PCIECORE_CTLANDSTATUS  0x50
 +#define INTXSTATUSMASK 0x6c
 +#define PIM1_1L0x80
 +#define IBAR2  0x98
 +#define IR2MSK 0x9c
 +#define PIM2_1L0xa0
 +#define IBAR3L 0xb4
 +#define IR3MSKL0xbc
 +#define PIM3_1L0xc4
 +#define OMR1BARL   0x100
 +#define OMR2BARL   0x118
 +#define OMR3BARL   0x130
 +#define CFGBARL0x154
 +#define CFGBARH0x158
 +#define CFGCTL 0x15c
 +#define RTDID  0x160
 +#define BRIDGE_CFG_0   0x2000
 +#define BRIDGE_CFG_1   0x2004
 +#define BRIDGE_CFG_4   0x2010
 +#define BRIDGE_CFG_32  0x2030
 +#define BRIDGE_CFG_14  0x2038
 +#define BRIDGE_CTRL_1  0x2204
 +#define BRIDGE_CTRL_2  0x2208
 +#define BRIDGE_CTRL_5  0x2214
 +#define BRIDGE_STATUS_00x2600
 +#define MEM_RAM_SHUTDOWN0xd070
 +#define BLOCK_MEM_RDY   0xd074
 +
 +#define DEVICE_PORT_TYPE_MASK  0x03c0
 +#define PM_FORCE_RP_MODE_MASK  0x0400
 +#define SWITCH_PORT_MODE_MASK  0x0800
 +#define CLASS_CODE_MASK0xff00
 +#define LINK_UP_MASK

Re: [PATCH v5 1/4] pci: APM X-Gene PCIe controller driver

2014-03-21 Thread Tanmay Inamdar 
Hi Sunil,

I think 'pci_assign_unassigned_bus_resources' should take care of
this. Liviu can comment more.

Thanks,
Tanmay

On Fri, Mar 21, 2014 at 3:15 AM, Sunil Kovvuri sunil.kovv...@gmail.com wrote:
 Hi Tanmay,

 Didn't get how PCI resources are enabled for the device.
 Liviu Dudau's ARM64 PCI architecture patch enables device resources
 using genenic API.

 https://lkml.org/lkml/2014/3/14/276
 + return pci_enable_resources(dev, mask);

 pci_enable_resources() checks if resource-parent is non-NULL.
 And at the same time Liviu Dudau's patch doesn't use pci_claim_resource.

 Please look into below patches from Bjorn.
 https://lkml.org/lkml/2014/2/26/629

 Thanks,
 Sunil.

 On Thu, Mar 20, 2014 at 4:42 AM, Tanmay Inamdar tinam...@apm.com wrote:
 This patch adds the AppliedMicro X-Gene SOC PCIe controller driver.
 X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
 X-Gene SOC supports maximum 5 PCIe ports.

 Signed-off-by: Tanmay Inamdar tinam...@apm.com
 ---
  drivers/pci/host/Kconfig |   10 +
  drivers/pci/host/Makefile|1 +
  drivers/pci/host/pci-xgene.c |  725 
 ++
  3 files changed, 736 insertions(+)
  create mode 100644 drivers/pci/host/pci-xgene.c

 diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
 index 47d46c6..19ce97d 100644
 --- a/drivers/pci/host/Kconfig
 +++ b/drivers/pci/host/Kconfig
 @@ -33,4 +33,14 @@ config PCI_RCAR_GEN2
   There are 3 internal PCI controllers available with a single
   built-in EHCI/OHCI host controller present on each one.

 +config PCI_XGENE
 +   bool X-Gene PCIe controller
 +   depends on ARCH_XGENE
 +   depends on OF
 +   select PCIEPORTBUS
 +   help
 + Say Y here if you want internal PCI support on APM X-Gene SoC.
 + There are 5 internal PCIe ports available. Each port is GEN3 
 capable
 + and have varied lanes from x1 to x8.
 +
  endmenu
 diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
 index 13fb333..34c7c36 100644
 --- a/drivers/pci/host/Makefile
 +++ b/drivers/pci/host/Makefile
 @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
  obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
  obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
 +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
 diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
 new file mode 100644
 index 000..9e312f6
 --- /dev/null
 +++ b/drivers/pci/host/pci-xgene.c
 @@ -0,0 +1,725 @@
 +/**
 + * APM X-Gene PCIe Driver
 + *
 + * Copyright (c) 2013 Applied Micro Circuits Corporation.
 + *
 + * Author: Tanmay Inamdar tinam...@apm.com.
 + *
 + * This program is free software; you can redistribute  it and/or modify it
 + * under  the terms of  the GNU General  Public License as published by the
 + * Free Software Foundation;  either version 2 of the  License, or (at your
 + * option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + */
 +#include linux/clk-private.h
 +#include linux/delay.h
 +#include linux/io.h
 +#include linux/jiffies.h
 +#include linux/memblock.h
 +#include linux/module.h
 +#include linux/of.h
 +#include linux/of_address.h
 +#include linux/of_irq.h
 +#include linux/of_pci.h
 +#include linux/pci.h
 +#include linux/platform_device.h
 +#include linux/slab.h
 +
 +#define PCIECORE_LTSSM 0x4c
 +#define PCIECORE_CTLANDSTATUS  0x50
 +#define INTXSTATUSMASK 0x6c
 +#define PIM1_1L0x80
 +#define IBAR2  0x98
 +#define IR2MSK 0x9c
 +#define PIM2_1L0xa0
 +#define IBAR3L 0xb4
 +#define IR3MSKL0xbc
 +#define PIM3_1L0xc4
 +#define OMR1BARL   0x100
 +#define OMR2BARL   0x118
 +#define OMR3BARL   0x130
 +#define CFGBARL0x154
 +#define CFGBARH0x158
 +#define CFGCTL 0x15c
 +#define RTDID  0x160
 +#define BRIDGE_CFG_0   0x2000
 +#define BRIDGE_CFG_1   0x2004
 +#define BRIDGE_CFG_4   0x2010
 +#define BRIDGE_CFG_32  0x2030
 +#define BRIDGE_CFG_14  0x2038
 +#define BRIDGE_CTRL_1  0x2204
 +#define BRIDGE_CTRL_2  0x2208
 +#define BRIDGE_CTRL_5  0x2214
 +#define BRIDGE_STATUS_00x2600
 +#define MEM_RAM_SHUTDOWN0xd070
 +#define BLOCK_MEM_RDY   0xd074
 +
 +#define DEVICE_PORT_TYPE_MASK