Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On Wed, 28 Oct 2020 16:27:58 PDT (-0700), Atish Patra wrote:
Add initial DTS for Microchip ICICLE board having only
essential devcies (clocks, sdhci, ethernet, serial, etc).
This fails `make dtbs_check`. The fu540 fails too, so I guess it's not exactly
fair, though.
Signed-off-by: Atish Patra
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/microchip/Makefile| 2 +
.../microchip/microchip-icicle-kit-a000.dts | 313 ++
3 files changed, 316 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/Makefile
create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ca1f8cbd78c0..3ea94ea0a18a 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-y += kendryte
+subdir-y += microchip
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/microchip/Makefile
b/arch/riscv/boot/dts/microchip/Makefile
new file mode 100644
index ..55ad77521304
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
new file mode 100644
index ..5848920af55c
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC";
+ compatible = "microchip,polarfire-soc";
+
+ chosen {
+ stdout-path =
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = ;
+
+ cpu@0 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@1 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@2 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On Thu, Oct 29, 2020 at 6:42 PM Ben Dooks wrote:
>
> On 28/10/2020 23:27, Atish Patra wrote:
> > Add initial DTS for Microchip ICICLE board having only
> > essential devcies (clocks, sdhci, ethernet, serial, etc).
> >
> > Signed-off-by: Atish Patra
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/microchip/Makefile| 2 +
> > .../microchip/microchip-icicle-kit-a000.dts | 313 ++
> > 3 files changed, 316 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > create mode 100644
> > arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ca1f8cbd78c0..3ea94ea0a18a 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> > subdir-y += sifive
> > subdir-y += kendryte
> > +subdir-y += microchip
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > b/arch/riscv/boot/dts/microchip/Makefile
> > new file mode 100644
> > index ..55ad77521304
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> > diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > new file mode 100644
> > index ..5848920af55c
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > @@ -0,0 +1,313 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ 100
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip PolarFire-SoC";
> > + compatible = "microchip,polarfire-soc";
> > +
> > + chosen {
> > + stdout-path =
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = ;
> > +
> > + cpu@0 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <16384>;
> > + reg = <0>;
> > + riscv,isa = "rv64imac";
> > + status = "disabled";
> > +
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@1 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <1>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > +
> > + cpu1_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@2 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > +
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On Tue, Nov 3, 2020 at 10:50 AM wrote: > > On 11/3/20 6:38 PM, Atish Patra wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > > content is safe > > > > On Tue, Nov 3, 2020 at 10:19 AM wrote: > >> On 11/3/20 10:00 AM, Bin Meng wrote: > >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know > >>> the content is safe > >>> > >>> On Fri, Oct 30, 2020 at 5:08 PM Anup Patel wrote: > On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote: > > Add initial DTS for Microchip ICICLE board having only > > essential devcies (clocks, sdhci, ethernet, serial, etc). > > > > Signed-off-by: Atish Patra > > --- > >arch/riscv/boot/dts/Makefile | 1 + > >arch/riscv/boot/dts/microchip/Makefile| 2 + > >.../microchip/microchip-icicle-kit-a000.dts | 313 > > ++ > I suggest we split this DTS into two parts: > 1. SOC (microchip-polarfire.dtsi) > 2. Board (microchip-icicle-kit-a000.dts) > >>> I also doubt what is the correct board name. I suspect the -a000 comes > >>> from the SiFive board name convention, but does not apply to the > >>> Icicle Kit board. > >>> > >>> @Cyril, please confirm. > >>> > >> Correct. Sorry Padmarao, I missed that one. > >> > > Ok. I picked that one from U-Boot. What should be the correct board > > name in that case ? > > > > microchip-pfsoc-icicle-kit ? > > My preference would go for microchip-mpfs-icicle-kit. I prefer "mpfs" > over "pfsoc" as "mpfs" is the part number prefix for the PolarFire SoC > device family. > Sure. I will update accordingly. Thanks for the quick feedback. > > Regards, > > Cyril. > > -- Regards, Atish
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 11/3/20 6:38 PM, Atish Patra wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > On Tue, Nov 3, 2020 at 10:19 AM wrote: >> On 11/3/20 10:00 AM, Bin Meng wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the >>> content is safe >>> >>> On Fri, Oct 30, 2020 at 5:08 PM Anup Patel wrote: On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote: > Add initial DTS for Microchip ICICLE board having only > essential devcies (clocks, sdhci, ethernet, serial, etc). > > Signed-off-by: Atish Patra > --- >arch/riscv/boot/dts/Makefile | 1 + >arch/riscv/boot/dts/microchip/Makefile| 2 + >.../microchip/microchip-icicle-kit-a000.dts | 313 ++ I suggest we split this DTS into two parts: 1. SOC (microchip-polarfire.dtsi) 2. Board (microchip-icicle-kit-a000.dts) >>> I also doubt what is the correct board name. I suspect the -a000 comes >>> from the SiFive board name convention, but does not apply to the >>> Icicle Kit board. >>> >>> @Cyril, please confirm. >>> >> Correct. Sorry Padmarao, I missed that one. >> > Ok. I picked that one from U-Boot. What should be the correct board > name in that case ? > > microchip-pfsoc-icicle-kit ? My preference would go for microchip-mpfs-icicle-kit. I prefer "mpfs" over "pfsoc" as "mpfs" is the part number prefix for the PolarFire SoC device family. Regards, Cyril.
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 03/11/2020 18:40, cyril.j...@microchip.com wrote: On 11/3/20 6:28 PM, Ben Dooks wrote: EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe On 03/11/2020 18:10, cyril.j...@microchip.com wrote: On 11/3/20 3:07 PM, Atish Patra wrote: EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks wrote: ,snip[ @Cyril : Can we enable both eMMC & sdcard at the same time ? I would put /both/ in but only enable the one in use for the moment. Our boards are booting of eMMC as supplied, so this isn't going to work as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec instead of 22MB/sec. This performance is still not great, but losing half the data-rate is just not good. I am not sure what should be enabled by default. Updating sdcard is much easier than eMMC card and we use that approach. @Cyril: Is there a way that we can enable both ? Yes, we can enable both but this requires a modification to the FPGA design. One of the guys prototyped this while I was away. We will move this along. This will require reprogramming the FPGA with a new design and HSS version. Regards, Cyril. I either missed or couldn't find a way of forcing the boot mode to be from the SD slot. Have I missed something? At the moment we'd like to have more storage available as the ~7G free on the eMMC is not enough. Currently, you need to program a different FPGA bitstream on the board to boot from SD-card. The different bitstream configures muxes on the board to connect the SD slot to the FPGA and the HSS included in the bit stream configures the FPGA IOs correctly. Links to the programming files are found in this document: https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md Thanks, but i've no way of remotely re-writing the bitstream of the FPGA since the tools are x86 only and we're using a Pi3 to connect the boards we have to the network. -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On Tue, Nov 3, 2020 at 10:39 AM Ben Dooks wrote: > > On 03/11/2020 18:36, Atish Patra wrote: > > On Tue, Nov 3, 2020 at 10:28 AM Ben Dooks wrote: > >> > >> On 03/11/2020 18:10, cyril.j...@microchip.com wrote: > >>> On 11/3/20 3:07 PM, Atish Patra wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know > the content is safe > > On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks > wrote: > >> > >> ,snip[ > >> > >> @Cyril : Can we enable both eMMC & sdcard at the same time ? > > I would put /both/ in but only enable the one in use for the moment. > > Our boards are booting of eMMC as supplied, so this isn't going to work > > as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec > > instead of 22MB/sec. This performance is still not great, but losing > > half the data-rate is just not good. > > > I am not sure what should be enabled by default. Updating sdcard is much > easier than eMMC card and we use that approach. > > @Cyril: Is there a way that we can enable both ? > > >>> Yes, we can enable both but this requires a modification to the FPGA > >>> design. One of the guys prototyped this while I was away. We will move > >>> this along. This will require reprogramming the FPGA with a new design > >>> and HSS version. > >>> > >>> Regards, > >>> > >>> Cyril. > >> > >> I either missed or couldn't find a way of forcing the boot mode to be > >> from the SD slot. Have I missed something? At the moment we'd like to > >> have more storage available as the ~7G free on the eMMC is not enough. > >> > > > > I use tftpboot to load the kernel & DT from the network. SD card is > > enabled in this DT and Linux > > kernel uses SD slot instead of eMMC. > > > > To summarize, eMMC is used for HSS & U-Boot while SD card is used for > > Linux which makes > > more storage available to Linux. > > > > IMO, we should enable the sdcard for Linux DT until updated FPGA > > design & HSS is available. > > Interesting as for me the default is for Linux to use the eMMC as > well. I can't see any way for forcing the selection lines in the > DT to say eMMC vs SD. > because you are probably loading the DT passed by U-boot. I load the DTB built from the Linux source (the one present in this patch) by stopping the autoboot in U-Boot. The DT in U-Boot disables the SD card. > If there is a way of controlling the selection lines then it might > be possible to have both cards enabled with a bus selection MUX in > software. > > > -- > Ben Dooks http://www.codethink.co.uk/ > Senior Engineer Codethink - Providing Genius > > https://www.codethink.co.uk/privacy.html -- Regards, Atish
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 03/11/2020 18:36, Atish Patra wrote: On Tue, Nov 3, 2020 at 10:28 AM Ben Dooks wrote: On 03/11/2020 18:10, cyril.j...@microchip.com wrote: On 11/3/20 3:07 PM, Atish Patra wrote: EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks wrote: ,snip[ @Cyril : Can we enable both eMMC & sdcard at the same time ? I would put /both/ in but only enable the one in use for the moment. Our boards are booting of eMMC as supplied, so this isn't going to work as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec instead of 22MB/sec. This performance is still not great, but losing half the data-rate is just not good. I am not sure what should be enabled by default. Updating sdcard is much easier than eMMC card and we use that approach. @Cyril: Is there a way that we can enable both ? Yes, we can enable both but this requires a modification to the FPGA design. One of the guys prototyped this while I was away. We will move this along. This will require reprogramming the FPGA with a new design and HSS version. Regards, Cyril. I either missed or couldn't find a way of forcing the boot mode to be from the SD slot. Have I missed something? At the moment we'd like to have more storage available as the ~7G free on the eMMC is not enough. I use tftpboot to load the kernel & DT from the network. SD card is enabled in this DT and Linux kernel uses SD slot instead of eMMC. To summarize, eMMC is used for HSS & U-Boot while SD card is used for Linux which makes more storage available to Linux. IMO, we should enable the sdcard for Linux DT until updated FPGA design & HSS is available. Interesting as for me the default is for Linux to use the eMMC as well. I can't see any way for forcing the selection lines in the DT to say eMMC vs SD. If there is a way of controlling the selection lines then it might be possible to have both cards enabled with a bus selection MUX in software. -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 11/3/20 6:28 PM, Ben Dooks wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know > the content is safe > > On 03/11/2020 18:10, cyril.j...@microchip.com wrote: >> On 11/3/20 3:07 PM, Atish Patra wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you >>> know the content is safe >>> >>> On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks >>> wrote: > > ,snip[ > > @Cyril : Can we enable both eMMC & sdcard at the same time ? I would put /both/ in but only enable the one in use for the moment. Our boards are booting of eMMC as supplied, so this isn't going to work as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec instead of 22MB/sec. This performance is still not great, but losing half the data-rate is just not good. >>> I am not sure what should be enabled by default. Updating sdcard is >>> much >>> easier than eMMC card and we use that approach. >>> >>> @Cyril: Is there a way that we can enable both ? >>> >> Yes, we can enable both but this requires a modification to the FPGA >> design. One of the guys prototyped this while I was away. We will move >> this along. This will require reprogramming the FPGA with a new design >> and HSS version. >> >> Regards, >> >> Cyril. > > I either missed or couldn't find a way of forcing the boot mode to be > from the SD slot. Have I missed something? At the moment we'd like to > have more storage available as the ~7G free on the eMMC is not enough. > Currently, you need to program a different FPGA bitstream on the board to boot from SD-card. The different bitstream configures muxes on the board to connect the SD slot to the FPGA and the HSS included in the bit stream configures the FPGA IOs correctly. Links to the programming files are found in this document: https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md Regards, Cyril.
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On Tue, Nov 3, 2020 at 10:19 AM wrote: > > On 11/3/20 10:00 AM, Bin Meng wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > > content is safe > > > > On Fri, Oct 30, 2020 at 5:08 PM Anup Patel wrote: > >> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote: > >>> Add initial DTS for Microchip ICICLE board having only > >>> essential devcies (clocks, sdhci, ethernet, serial, etc). > >>> > >>> Signed-off-by: Atish Patra > >>> --- > >>> arch/riscv/boot/dts/Makefile | 1 + > >>> arch/riscv/boot/dts/microchip/Makefile| 2 + > >>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++ > >> I suggest we split this DTS into two parts: > >> 1. SOC (microchip-polarfire.dtsi) > >> 2. Board (microchip-icicle-kit-a000.dts) > > I also doubt what is the correct board name. I suspect the -a000 comes > > from the SiFive board name convention, but does not apply to the > > Icicle Kit board. > > > > @Cyril, please confirm. > > > Correct. Sorry Padmarao, I missed that one. > Ok. I picked that one from U-Boot. What should be the correct board name in that case ? microchip-pfsoc-icicle-kit ? > > Regards, > > Cyril. > > > ___ > linux-riscv mailing list > linux-ri...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv -- Regards, Atish
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On Tue, Nov 3, 2020 at 10:28 AM Ben Dooks wrote: > > On 03/11/2020 18:10, cyril.j...@microchip.com wrote: > > On 11/3/20 3:07 PM, Atish Patra wrote: > >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the > >> content is safe > >> > >> On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks > >> wrote: > > ,snip[ > > @Cyril : Can we enable both eMMC & sdcard at the same time ? > >>> I would put /both/ in but only enable the one in use for the moment. > >>> Our boards are booting of eMMC as supplied, so this isn't going to work > >>> as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec > >>> instead of 22MB/sec. This performance is still not great, but losing > >>> half the data-rate is just not good. > >>> > >> I am not sure what should be enabled by default. Updating sdcard is much > >> easier than eMMC card and we use that approach. > >> > >> @Cyril: Is there a way that we can enable both ? > >> > > Yes, we can enable both but this requires a modification to the FPGA > > design. One of the guys prototyped this while I was away. We will move > > this along. This will require reprogramming the FPGA with a new design > > and HSS version. > > > > Regards, > > > > Cyril. > > I either missed or couldn't find a way of forcing the boot mode to be > from the SD slot. Have I missed something? At the moment we'd like to > have more storage available as the ~7G free on the eMMC is not enough. > I use tftpboot to load the kernel & DT from the network. SD card is enabled in this DT and Linux kernel uses SD slot instead of eMMC. To summarize, eMMC is used for HSS & U-Boot while SD card is used for Linux which makes more storage available to Linux. IMO, we should enable the sdcard for Linux DT until updated FPGA design & HSS is available. > -- > Ben Dooks http://www.codethink.co.uk/ > Senior Engineer Codethink - Providing Genius > > https://www.codethink.co.uk/privacy.html -- Regards, Atish
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 03/11/2020 18:10, cyril.j...@microchip.com wrote: On 11/3/20 3:07 PM, Atish Patra wrote: EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks wrote: ,snip[ @Cyril : Can we enable both eMMC & sdcard at the same time ? I would put /both/ in but only enable the one in use for the moment. Our boards are booting of eMMC as supplied, so this isn't going to work as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec instead of 22MB/sec. This performance is still not great, but losing half the data-rate is just not good. I am not sure what should be enabled by default. Updating sdcard is much easier than eMMC card and we use that approach. @Cyril: Is there a way that we can enable both ? Yes, we can enable both but this requires a modification to the FPGA design. One of the guys prototyped this while I was away. We will move this along. This will require reprogramming the FPGA with a new design and HSS version. Regards, Cyril. I either missed or couldn't find a way of forcing the boot mode to be from the SD slot. Have I missed something? At the moment we'd like to have more storage available as the ~7G free on the eMMC is not enough. -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 11/3/20 10:00 AM, Bin Meng wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > On Fri, Oct 30, 2020 at 5:08 PM Anup Patel wrote: >> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote: >>> Add initial DTS for Microchip ICICLE board having only >>> essential devcies (clocks, sdhci, ethernet, serial, etc). >>> >>> Signed-off-by: Atish Patra >>> --- >>> arch/riscv/boot/dts/Makefile | 1 + >>> arch/riscv/boot/dts/microchip/Makefile| 2 + >>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++ >> I suggest we split this DTS into two parts: >> 1. SOC (microchip-polarfire.dtsi) >> 2. Board (microchip-icicle-kit-a000.dts) > I also doubt what is the correct board name. I suspect the -a000 comes > from the SiFive board name convention, but does not apply to the > Icicle Kit board. > > @Cyril, please confirm. > Correct. Sorry Padmarao, I missed that one. Regards, Cyril.
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 11/3/20 3:07 PM, Atish Patra wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks wrote:
>> On 30/10/2020 07:11, Atish Patra wrote:
>>> On Thu, Oct 29, 2020 at 3:24 AM Ben Dooks wrote:
On 28/10/2020 23:27, Atish Patra wrote:
> Add initial DTS for Microchip ICICLE board having only
> essential devcies (clocks, sdhci, ethernet, serial, etc).
>
> Signed-off-by: Atish Patra
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/microchip/Makefile| 2 +
> .../microchip/microchip-icicle-kit-a000.dts | 313 ++
> 3 files changed, 316 insertions(+)
> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> create mode 100644
> arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ca1f8cbd78c0..3ea94ea0a18a 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> subdir-y += sifive
> subdir-y += kendryte
> +subdir-y += microchip
>
> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/microchip/Makefile
> b/arch/riscv/boot/dts/microchip/Makefile
> new file mode 100644
> index ..55ad77521304
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> new file mode 100644
> index ..5848920af55c
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> @@ -0,0 +1,313 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/* Copyright (c) 2020 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define RTCCLK_FREQ 100
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "Microchip PolarFire-SoC";
> + compatible = "microchip,polarfire-soc";
> +
> + chosen {
> + stdout-path =
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = ;
> +
> + cpu@0 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <16384>;
> + reg = <0>;
> + riscv,isa = "rv64imac";
> + status = "disabled";
> +
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@1 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <1>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> +
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@2 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> +
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 03/11/2020 15:07, Atish Patra wrote: We could just modify the reg size but to allow more memory. I tried that for Linux but it didn't boot. Probably, DDR init code in HSS only initialized 1GB of memory. Yes, it is only looking at the low window which is 1GiB max. If it used the upper window it would get the 16GiB. I don't know how no-one noticed this issue before shipping a board out with this. I have updated the firmware on my second board but this only seems to currently fix a reboot issue with the eMMC. We can't update the DT for Linux until there is a public release of the updated firmware with 2GB enabled. Yeah, it is really annoying the boards turned up with a number of issues including the half memory. I assume there will be a new release of HSS and U-boot which at worse can insert new memory nodes into the device tree. -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On Tue, Nov 3, 2020 at 2:59 AM Ben Dooks wrote:
>
> On 30/10/2020 20:27, Atish Patra wrote:
> > On Fri, Oct 30, 2020 at 2:05 AM Anup Patel wrote:
> >>
> >> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote:
> >>>
> >>> Add initial DTS for Microchip ICICLE board having only
> >>> essential devcies (clocks, sdhci, ethernet, serial, etc).
> >>>
> >>> Signed-off-by: Atish Patra
> >>> ---
> >>> arch/riscv/boot/dts/Makefile | 1 +
> >>> arch/riscv/boot/dts/microchip/Makefile| 2 +
> >>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++
> >>
> >> I suggest we split this DTS into two parts:
> >> 1. SOC (microchip-polarfire.dtsi)
> >> 2. Board (microchip-icicle-kit-a000.dts)
> >>
> >> This will be much cleaner and aligned with what is done
> >> on other architectures.
> >>
> >
> > Sure. I will do that in v2.
> >
> >>> 3 files changed, 316 insertions(+)
> >>> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> >>> create mode 100644
> >>> arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>>
> >>> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> >>> index ca1f8cbd78c0..3ea94ea0a18a 100644
> >>> --- a/arch/riscv/boot/dts/Makefile
> >>> +++ b/arch/riscv/boot/dts/Makefile
> >>> @@ -1,5 +1,6 @@
> >>> # SPDX-License-Identifier: GPL-2.0
> >>> subdir-y += sifive
> >>> subdir-y += kendryte
> >>> +subdir-y += microchip
> >>>
> >>> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> >>> diff --git a/arch/riscv/boot/dts/microchip/Makefile
> >>> b/arch/riscv/boot/dts/microchip/Makefile
> >>> new file mode 100644
> >>> index ..55ad77521304
> >>> --- /dev/null
> >>> +++ b/arch/riscv/boot/dts/microchip/Makefile
> >>> @@ -0,0 +1,2 @@
> >>> +# SPDX-License-Identifier: GPL-2.0
> >>> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> >>> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>> b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>> new file mode 100644
> >>> index ..5848920af55c
> >>> --- /dev/null
> >>> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>> @@ -0,0 +1,313 @@
> >>> +// SPDX-License-Identifier: GPL-2.0+
> >>> +/* Copyright (c) 2020 Microchip Technology Inc */
> >>> +
> >>> +/dts-v1/;
> >>> +
> >>> +/* Clock frequency (in Hz) of the rtcclk */
> >>> +#define RTCCLK_FREQ100
> >>> +
> >>> +/ {
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> + model = "Microchip PolarFire-SoC";
> >>> + compatible = "microchip,polarfire-soc";
> >>> +
> >>> + chosen {
> >>> + stdout-path =
> >>> + };
> >>> +
> >>> + cpus {
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> + timebase-frequency = ;
> >>> +
> >>> + cpu@0 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <128>;
> >>> + i-cache-size = <16384>;
> >>> + reg = <0>;
> >>> + riscv,isa = "rv64imac";
> >>> + status = "disabled";
> >>> +
> >>> + cpu0_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> +
> >>> + cpu@1 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + d-cache-block-size = <64>;
> >>> + d-cache-sets = <64>;
> >>> + d-cache-size = <32768>;
> >>> + d-tlb-sets = <1>;
> >>> + d-tlb-size = <32>;
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <64>;
> >>> + i-cache-size = <32768>;
> >>> + i-tlb-sets = <1>;
> >>> + i-tlb-size = <32>;
> >>> + mmu-type = "riscv,sv39";
> >>> + reg = <1>;
> >>> + riscv,isa = "rv64imafdc";
> >>> + tlb-split;
> >>> + status = "okay";
> >>> +
> >>> + cpu1_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks wrote:
>
> On 30/10/2020 07:11, Atish Patra wrote:
> > On Thu, Oct 29, 2020 at 3:24 AM Ben Dooks wrote:
> >>
> >> On 28/10/2020 23:27, Atish Patra wrote:
> >>> Add initial DTS for Microchip ICICLE board having only
> >>> essential devcies (clocks, sdhci, ethernet, serial, etc).
> >>>
> >>> Signed-off-by: Atish Patra
> >>> ---
> >>>arch/riscv/boot/dts/Makefile | 1 +
> >>>arch/riscv/boot/dts/microchip/Makefile| 2 +
> >>>.../microchip/microchip-icicle-kit-a000.dts | 313 ++
> >>>3 files changed, 316 insertions(+)
> >>>create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> >>>create mode 100644
> >>> arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>>
> >>> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> >>> index ca1f8cbd78c0..3ea94ea0a18a 100644
> >>> --- a/arch/riscv/boot/dts/Makefile
> >>> +++ b/arch/riscv/boot/dts/Makefile
> >>> @@ -1,5 +1,6 @@
> >>># SPDX-License-Identifier: GPL-2.0
> >>>subdir-y += sifive
> >>>subdir-y += kendryte
> >>> +subdir-y += microchip
> >>>
> >>>obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> >>> diff --git a/arch/riscv/boot/dts/microchip/Makefile
> >>> b/arch/riscv/boot/dts/microchip/Makefile
> >>> new file mode 100644
> >>> index ..55ad77521304
> >>> --- /dev/null
> >>> +++ b/arch/riscv/boot/dts/microchip/Makefile
> >>> @@ -0,0 +1,2 @@
> >>> +# SPDX-License-Identifier: GPL-2.0
> >>> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> >>> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>> b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>> new file mode 100644
> >>> index ..5848920af55c
> >>> --- /dev/null
> >>> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>> @@ -0,0 +1,313 @@
> >>> +// SPDX-License-Identifier: GPL-2.0+
> >>> +/* Copyright (c) 2020 Microchip Technology Inc */
> >>> +
> >>> +/dts-v1/;
> >>> +
> >>> +/* Clock frequency (in Hz) of the rtcclk */
> >>> +#define RTCCLK_FREQ 100
> >>> +
> >>> +/ {
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> + model = "Microchip PolarFire-SoC";
> >>> + compatible = "microchip,polarfire-soc";
> >>> +
> >>> + chosen {
> >>> + stdout-path =
> >>> + };
> >>> +
> >>> + cpus {
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> + timebase-frequency = ;
> >>> +
> >>> + cpu@0 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <128>;
> >>> + i-cache-size = <16384>;
> >>> + reg = <0>;
> >>> + riscv,isa = "rv64imac";
> >>> + status = "disabled";
> >>> +
> >>> + cpu0_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> +
> >>> + cpu@1 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + d-cache-block-size = <64>;
> >>> + d-cache-sets = <64>;
> >>> + d-cache-size = <32768>;
> >>> + d-tlb-sets = <1>;
> >>> + d-tlb-size = <32>;
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <64>;
> >>> + i-cache-size = <32768>;
> >>> + i-tlb-sets = <1>;
> >>> + i-tlb-size = <32>;
> >>> + mmu-type = "riscv,sv39";
> >>> + reg = <1>;
> >>> + riscv,isa = "rv64imafdc";
> >>> + tlb-split;
> >>> + status = "okay";
> >>> +
> >>> + cpu1_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> +
> >>> + cpu@2 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + d-cache-block-size = <64>;
> >>> + d-cache-sets = <64>;
> >>> + d-cache-size = <32768>;
> >>> + d-tlb-sets = <1>;
> >>> +
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 30/10/2020 20:27, Atish Patra wrote:
On Fri, Oct 30, 2020 at 2:05 AM Anup Patel wrote:
On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote:
Add initial DTS for Microchip ICICLE board having only
essential devcies (clocks, sdhci, ethernet, serial, etc).
Signed-off-by: Atish Patra
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/microchip/Makefile| 2 +
.../microchip/microchip-icicle-kit-a000.dts | 313 ++
I suggest we split this DTS into two parts:
1. SOC (microchip-polarfire.dtsi)
2. Board (microchip-icicle-kit-a000.dts)
This will be much cleaner and aligned with what is done
on other architectures.
Sure. I will do that in v2.
3 files changed, 316 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/Makefile
create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ca1f8cbd78c0..3ea94ea0a18a 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-y += kendryte
+subdir-y += microchip
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/microchip/Makefile
b/arch/riscv/boot/dts/microchip/Makefile
new file mode 100644
index ..55ad77521304
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
new file mode 100644
index ..5848920af55c
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC";
+ compatible = "microchip,polarfire-soc";
+
+ chosen {
+ stdout-path =
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = ;
+
+ cpu@0 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@1 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@2 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On Fri, Oct 30, 2020 at 5:08 PM Anup Patel wrote: > > On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote: > > > > Add initial DTS for Microchip ICICLE board having only > > essential devcies (clocks, sdhci, ethernet, serial, etc). > > > > Signed-off-by: Atish Patra > > --- > > arch/riscv/boot/dts/Makefile | 1 + > > arch/riscv/boot/dts/microchip/Makefile| 2 + > > .../microchip/microchip-icicle-kit-a000.dts | 313 ++ > > I suggest we split this DTS into two parts: > 1. SOC (microchip-polarfire.dtsi) > 2. Board (microchip-icicle-kit-a000.dts) I also doubt what is the correct board name. I suspect the -a000 comes from the SiFive board name convention, but does not apply to the Icicle Kit board. @Cyril, please confirm. > > This will be much cleaner and aligned with what is done > on other architectures. > > > 3 files changed, 316 insertions(+) > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > > create mode 100644 > > arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts > > Regards, Bin
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 30/10/2020 07:11, Atish Patra wrote:
On Thu, Oct 29, 2020 at 3:24 AM Ben Dooks wrote:
On 28/10/2020 23:27, Atish Patra wrote:
Add initial DTS for Microchip ICICLE board having only
essential devcies (clocks, sdhci, ethernet, serial, etc).
Signed-off-by: Atish Patra
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/microchip/Makefile| 2 +
.../microchip/microchip-icicle-kit-a000.dts | 313 ++
3 files changed, 316 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/Makefile
create mode 100644
arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ca1f8cbd78c0..3ea94ea0a18a 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-y += kendryte
+subdir-y += microchip
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/microchip/Makefile
b/arch/riscv/boot/dts/microchip/Makefile
new file mode 100644
index ..55ad77521304
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
new file mode 100644
index ..5848920af55c
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ 100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC";
+ compatible = "microchip,polarfire-soc";
+
+ chosen {
+ stdout-path =
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = ;
+
+ cpu@0 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@1 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@2 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 30/10/2020 09:05, Anup Patel wrote: On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote: Add initial DTS for Microchip ICICLE board having only essential devcies (clocks, sdhci, ethernet, serial, etc). Signed-off-by: Atish Patra --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/microchip/Makefile| 2 + .../microchip/microchip-icicle-kit-a000.dts | 313 ++ I suggest we split this DTS into two parts: 1. SOC (microchip-polarfire.dtsi) 2. Board (microchip-icicle-kit-a000.dts) I was just going to suggest that. -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On Fri, Oct 30, 2020 at 2:05 AM Anup Patel wrote:
>
> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote:
> >
> > Add initial DTS for Microchip ICICLE board having only
> > essential devcies (clocks, sdhci, ethernet, serial, etc).
> >
> > Signed-off-by: Atish Patra
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/microchip/Makefile| 2 +
> > .../microchip/microchip-icicle-kit-a000.dts | 313 ++
>
> I suggest we split this DTS into two parts:
> 1. SOC (microchip-polarfire.dtsi)
> 2. Board (microchip-icicle-kit-a000.dts)
>
> This will be much cleaner and aligned with what is done
> on other architectures.
>
Sure. I will do that in v2.
> > 3 files changed, 316 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > create mode 100644
> > arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ca1f8cbd78c0..3ea94ea0a18a 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> > subdir-y += sifive
> > subdir-y += kendryte
> > +subdir-y += microchip
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > b/arch/riscv/boot/dts/microchip/Makefile
> > new file mode 100644
> > index ..55ad77521304
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> > diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > new file mode 100644
> > index ..5848920af55c
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > @@ -0,0 +1,313 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ100
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip PolarFire-SoC";
> > + compatible = "microchip,polarfire-soc";
> > +
> > + chosen {
> > + stdout-path =
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = ;
> > +
> > + cpu@0 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <16384>;
> > + reg = <0>;
> > + riscv,isa = "rv64imac";
> > + status = "disabled";
> > +
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@1 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <1>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > +
> > + cpu1_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@2 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > +
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote:
>
> Add initial DTS for Microchip ICICLE board having only
> essential devcies (clocks, sdhci, ethernet, serial, etc).
>
> Signed-off-by: Atish Patra
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/microchip/Makefile| 2 +
> .../microchip/microchip-icicle-kit-a000.dts | 313 ++
I suggest we split this DTS into two parts:
1. SOC (microchip-polarfire.dtsi)
2. Board (microchip-icicle-kit-a000.dts)
This will be much cleaner and aligned with what is done
on other architectures.
> 3 files changed, 316 insertions(+)
> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> create mode 100644
> arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ca1f8cbd78c0..3ea94ea0a18a 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> subdir-y += sifive
> subdir-y += kendryte
> +subdir-y += microchip
>
> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/microchip/Makefile
> b/arch/riscv/boot/dts/microchip/Makefile
> new file mode 100644
> index ..55ad77521304
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> new file mode 100644
> index ..5848920af55c
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> @@ -0,0 +1,313 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/* Copyright (c) 2020 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define RTCCLK_FREQ100
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "Microchip PolarFire-SoC";
> + compatible = "microchip,polarfire-soc";
> +
> + chosen {
> + stdout-path =
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = ;
> +
> + cpu@0 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <16384>;
> + reg = <0>;
> + riscv,isa = "rv64imac";
> + status = "disabled";
> +
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@1 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <1>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> +
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@2 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> +
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On Thu, Oct 29, 2020 at 3:24 AM Ben Dooks wrote:
>
> On 28/10/2020 23:27, Atish Patra wrote:
> > Add initial DTS for Microchip ICICLE board having only
> > essential devcies (clocks, sdhci, ethernet, serial, etc).
> >
> > Signed-off-by: Atish Patra
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/microchip/Makefile| 2 +
> > .../microchip/microchip-icicle-kit-a000.dts | 313 ++
> > 3 files changed, 316 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > create mode 100644
> > arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ca1f8cbd78c0..3ea94ea0a18a 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> > subdir-y += sifive
> > subdir-y += kendryte
> > +subdir-y += microchip
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > b/arch/riscv/boot/dts/microchip/Makefile
> > new file mode 100644
> > index ..55ad77521304
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> > diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > new file mode 100644
> > index ..5848920af55c
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > @@ -0,0 +1,313 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ 100
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip PolarFire-SoC";
> > + compatible = "microchip,polarfire-soc";
> > +
> > + chosen {
> > + stdout-path =
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = ;
> > +
> > + cpu@0 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <16384>;
> > + reg = <0>;
> > + riscv,isa = "rv64imac";
> > + status = "disabled";
> > +
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@1 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <1>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > +
> > + cpu1_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@2 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > +
Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 28/10/2020 23:27, Atish Patra wrote:
Add initial DTS for Microchip ICICLE board having only
essential devcies (clocks, sdhci, ethernet, serial, etc).
Signed-off-by: Atish Patra
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/microchip/Makefile| 2 +
.../microchip/microchip-icicle-kit-a000.dts | 313 ++
3 files changed, 316 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/Makefile
create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ca1f8cbd78c0..3ea94ea0a18a 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-y += kendryte
+subdir-y += microchip
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/microchip/Makefile
b/arch/riscv/boot/dts/microchip/Makefile
new file mode 100644
index ..55ad77521304
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
new file mode 100644
index ..5848920af55c
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC";
+ compatible = "microchip,polarfire-soc";
+
+ chosen {
+ stdout-path =
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = ;
+
+ cpu@0 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@1 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@2 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+
