Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
On 3/22/2016 12:44 PM, Doug Anderson wrote: > John, > > On Tue, Mar 22, 2016 at 12:26 PM, John Youn wrote: >> Thanks for the debug logs and everyones help. >> >> After reviewing with our hardware engineers, it seems this is likely >> to do with the IDDIG debounce filtering when switching between >> modes. You can see if this is enabled in your core by checking >> GHWCFG4.IddgFltr. >> >> From the databook: >> >> OTG_EN_IDDIG_FILTER >> >> Specifies whether to add a filter on the "iddig" input from the >> PHY. If your PHY already has a filter on iddig for de-bounce, then >> it is not necessary to enable the one in the DWC_otg. The filter >> is implemented in the DWC_otg_wpc module as a 20-bit counter that >> works on the PHY clock. In the case of the UTMI+ PHY, this pin is >> from the PHY. In the case of the ULPI PHY, this signal is >> generated by the ULPI Wrapper inside the core. >> >> >> This only affects OTG cores and the delay is 10ms for 30MHz PHY clock >> and 50ms with a 6MHz PHY clock. > > Wow, nice to have it so perfectly explained! :) > > >> The reason we see this after a reset is that by default the IDDIG >> indicates device mode. But if the id pin is set to host the core will >> immediately detect it after the reset and trigger the filtering delay >> before changing to host mode. >> >> This delay is also triggered by force mode. This is the origin of the >> 25 ms delay specified in the databook. The databook did not take into >> account that there might be a 6MHz clock so this delay could actually >> be up to 50 ms. So we aren't delaying enough time for those cases. >> >> I think this explains all the problems and platform differences we are >> seeing related to this. >> >> I think we can just add an IDDIG delay after a force mode, a clear >> force mode, and any time after reset where we don't do either a force >> or clear force mode immediately afterwards. Maybe set the delay time >> via a core parameter or measure it once on probe. Or we can probably >> just poll for the mode change in all of the above conditions. > > The driver seems to be able to figure out the PHY clock in most cases > in dwc2_calc_frame_interval(). It doesn't seem to handle 6MHz there, > though. I wonder if that's another bug? > The 6 MHz is from a dedicated FS PHY operating at low speed. So that must be the case for the platforms showing 50 ms delay. > Polling seems fine too, though. I'm thinking that's the way to go as it can be troublesome to figure out the correct PHY clock speed. Regards, John
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
On 3/22/2016 12:44 PM, Doug Anderson wrote: > John, > > On Tue, Mar 22, 2016 at 12:26 PM, John Youn wrote: >> Thanks for the debug logs and everyones help. >> >> After reviewing with our hardware engineers, it seems this is likely >> to do with the IDDIG debounce filtering when switching between >> modes. You can see if this is enabled in your core by checking >> GHWCFG4.IddgFltr. >> >> From the databook: >> >> OTG_EN_IDDIG_FILTER >> >> Specifies whether to add a filter on the "iddig" input from the >> PHY. If your PHY already has a filter on iddig for de-bounce, then >> it is not necessary to enable the one in the DWC_otg. The filter >> is implemented in the DWC_otg_wpc module as a 20-bit counter that >> works on the PHY clock. In the case of the UTMI+ PHY, this pin is >> from the PHY. In the case of the ULPI PHY, this signal is >> generated by the ULPI Wrapper inside the core. >> >> >> This only affects OTG cores and the delay is 10ms for 30MHz PHY clock >> and 50ms with a 6MHz PHY clock. > > Wow, nice to have it so perfectly explained! :) > > >> The reason we see this after a reset is that by default the IDDIG >> indicates device mode. But if the id pin is set to host the core will >> immediately detect it after the reset and trigger the filtering delay >> before changing to host mode. >> >> This delay is also triggered by force mode. This is the origin of the >> 25 ms delay specified in the databook. The databook did not take into >> account that there might be a 6MHz clock so this delay could actually >> be up to 50 ms. So we aren't delaying enough time for those cases. >> >> I think this explains all the problems and platform differences we are >> seeing related to this. >> >> I think we can just add an IDDIG delay after a force mode, a clear >> force mode, and any time after reset where we don't do either a force >> or clear force mode immediately afterwards. Maybe set the delay time >> via a core parameter or measure it once on probe. Or we can probably >> just poll for the mode change in all of the above conditions. > > The driver seems to be able to figure out the PHY clock in most cases > in dwc2_calc_frame_interval(). It doesn't seem to handle 6MHz there, > though. I wonder if that's another bug? > > Polling seems fine too, though. > > >> Are you able to continue looking into this? If not, I can take it up. > > I'm pretty much out of time at this point and it sounds like you've > though through all of the corner cases. If you can take it up that > would be wonderful! :) I'm happy to give the patches a test, though! > :) > Ok sure. I'll try to get something testable within a few days. Regards, John
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
John, On Tue, Mar 22, 2016 at 12:26 PM, John Youn wrote: > Thanks for the debug logs and everyones help. > > After reviewing with our hardware engineers, it seems this is likely > to do with the IDDIG debounce filtering when switching between > modes. You can see if this is enabled in your core by checking > GHWCFG4.IddgFltr. > > From the databook: > > OTG_EN_IDDIG_FILTER > > Specifies whether to add a filter on the "iddig" input from the > PHY. If your PHY already has a filter on iddig for de-bounce, then > it is not necessary to enable the one in the DWC_otg. The filter > is implemented in the DWC_otg_wpc module as a 20-bit counter that > works on the PHY clock. In the case of the UTMI+ PHY, this pin is > from the PHY. In the case of the ULPI PHY, this signal is > generated by the ULPI Wrapper inside the core. > > > This only affects OTG cores and the delay is 10ms for 30MHz PHY clock > and 50ms with a 6MHz PHY clock. Wow, nice to have it so perfectly explained! :) > The reason we see this after a reset is that by default the IDDIG > indicates device mode. But if the id pin is set to host the core will > immediately detect it after the reset and trigger the filtering delay > before changing to host mode. > > This delay is also triggered by force mode. This is the origin of the > 25 ms delay specified in the databook. The databook did not take into > account that there might be a 6MHz clock so this delay could actually > be up to 50 ms. So we aren't delaying enough time for those cases. > > I think this explains all the problems and platform differences we are > seeing related to this. > > I think we can just add an IDDIG delay after a force mode, a clear > force mode, and any time after reset where we don't do either a force > or clear force mode immediately afterwards. Maybe set the delay time > via a core parameter or measure it once on probe. Or we can probably > just poll for the mode change in all of the above conditions. The driver seems to be able to figure out the PHY clock in most cases in dwc2_calc_frame_interval(). It doesn't seem to handle 6MHz there, though. I wonder if that's another bug? Polling seems fine too, though. > Are you able to continue looking into this? If not, I can take it up. I'm pretty much out of time at this point and it sounds like you've though through all of the corner cases. If you can take it up that would be wonderful! :) I'm happy to give the patches a test, though! :) -Doug
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
On 3/18/2016 10:21 PM, Doug Anderson wrote:
> Hi,
>
> On Wed, Mar 16, 2016 at 11:28 AM, John Youn wrote:
>> On 3/10/2016 11:14 AM, John Youn wrote:
>>> On 3/9/2016 11:06 AM, Doug Anderson wrote:
Stefan,
On Wed, Mar 9, 2016 at 11:01 AM, Stefan Wahren
wrote:
>
>> Doug Anderson hat am 7. März 2016 um 22:30
>> geschrieben:
>>
>>
>> Stefan,
>>
>> On Mon, Mar 7, 2016 at 10:40 AM, Stefan Wahren
>> wrote:
>>> Hi Doug,
>>>
Douglas Anderson hat am 4. März 2016 um 19:23
geschrieben:
This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
bcm2835") now that we've found the root cause. See the change
titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
>>>
>>> adding a delay of 10 ms after a core reset might be a idea, but applying
>>> both
>>> patches breaks USB support on RPi :-(
>>>
>>> I'm getting the wrong register values ...
>>
>> Ugh. :(
>>
>> Just out of curiosity, if you loop and time long it takes for the
>> registers to get to the right state after reset, what do you get?
>> AKA, pick:
>>
>> https://chromium-review.googlesource.com/331260
>>
>> ...and let me know what it prints out.
>
> On my Raspberry Pi B i get the following:
>
> [2.084411] dwc2 2098.usb: mapped PA 2098 to VA cc88
> [2.084461] dwc2 2098.usb: cannot get otg clock
> [2.084549] dwc2 2098.usb: registering common handler for irq33
> [2.084713] dwc2 2098.usb: Configuration mismatch. dr_mode forced
> to host
> [2.153965] dwc2 2098.usb: Waited 49996 us, 0x00201000 =>
> 0x01001000,
> 0x => 0x02002000
> [2.174930] dwc2 2098.usb: Forcing mode to host
>
> So i changed the delay in patch #1 to msleep(50) and then both patches
> work like
> a charm.
Great news! :-)
John: it's pretty clear that there's something taking almost exactly
10ms on my system and almost exactly 50ms on Stefan's system. Is
there some register we could poll to see when this process is done?
...or can we look at the dwc2 revision number / feature register and
detect how long to delay?
>>>
>>> Hi Doug,
>>>
>>> I'll have to ask around to see if anyone knows about this. And I'll
>>> run some tests on the platforms I have available to me as well.
>>>
>>
>> There's still nothing definitive on our end as to why this is
>> happening. Also I don't think there is any other way to poll the
>> reset.
>
> One thing I noticed is that the delay was only needed on my OTG port
> (not my host-only port). ...I also noticed that while waiting the
> HPTXFSIZ was temporarily 0x while I was delaying. That seems
> to match Stephan.
>
> I wonder if perhaps the delay has to do with how long it took to
> detect that it needed to go into host mode?
>
> Ah, interesting. It looks as if "GOTGCTL" changes during this time
> too. To summarize:
>
> HOST-only (ff54.usb): needs no delay:
> GNPTXFSIZ: 0x04000400
> HPTXFSIZ: 0x02000800
> GOTGCTL: 0x002d
>
> OTG (ff58): needs 10ms delay. Before delay:
> GNPTXFSIZ: 0x00100400
> HPTXFSIZ: 0x
> GOTGCTL: 0x0001
> After delay:
> GNPTXFSIZ: 0x04000400
> HPTXFSIZ: 0x02000800
> GOTGCTL: 0x002c
>
> Could we loop until either BSesVld or ASesVld is set? Don't know much
> about OTG, but seems like that might be something sane?
>
>> Our hardware engineers asked for some more information to look
>> into it further. Doug, Stefan, Caesar, and anyone else with a related
>> platform, do you know the answers to the following:
>>
>> 1. What is the AHB Clock frequency? Is the AHB Clock gated during
>> Reset?
>
> According to commit 20bde643434d ("usb: dwc2: reduce dwc2 driver probe
> time"), our AHB clock is 150MHz. I'm nearly certain it is not gated.
>
>
>> 2. Also is the PHY clock stopped during the reset or is the PHY PLL
>> lock times high in the order of ms?
>
> I don't think so.
>
>
>> 3. In these cases, is the PHY actually an FS Transceiver and not a
>> UTMI/ULPI PHY?
>
> I don't think so. Should be answered by debug info spew below...
>
>
>> 4. Which version of the controller is being used in these cases?
>
> There are two controllers in my case and they behave differently. OTG
> takes 10ms and the host-only 0ms.
>
> Here is debug info:
>
> [1.752005] dwc2 ff54.usb: Core Release: 3.10a (snpsid=4f54310a)
> [1.758350] dwc2 ff54.usb: hwcfg1=
> [1.762807] dwc2 ff54.usb: hwcfg2=228fc856
> [1.767245] dwc2 ff54.usb: hwcfg3=03c0c068
> [1.771693] dwc2 ff54.usb: hwcfg4=c8004030
> [1.776149] dwc2 ff54.usb: grxfsiz=0400
> [1.780687] dwc2 ff54.usb: gnptxfsiz=04000400
> [1.785402] dwc2 ff54.usb: hptxfsiz=02000800
> [1.790024] dwc2 ff54.usb: De
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
On 3/10/2016 11:14 AM, John Youn wrote:
> On 3/9/2016 11:06 AM, Doug Anderson wrote:
>> Stefan,
>>
>> On Wed, Mar 9, 2016 at 11:01 AM, Stefan Wahren
>> wrote:
>>>
Doug Anderson hat am 7. März 2016 um 22:30
geschrieben:
Stefan,
On Mon, Mar 7, 2016 at 10:40 AM, Stefan Wahren
wrote:
> Hi Doug,
>
>> Douglas Anderson hat am 4. März 2016 um 19:23
>> geschrieben:
>>
>>
>> This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
>> bcm2835") now that we've found the root cause. See the change
>> titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
>
> adding a delay of 10 ms after a core reset might be a idea, but applying
> both
> patches breaks USB support on RPi :-(
>
> I'm getting the wrong register values ...
Ugh. :(
Just out of curiosity, if you loop and time long it takes for the
registers to get to the right state after reset, what do you get?
AKA, pick:
https://chromium-review.googlesource.com/331260
...and let me know what it prints out.
>>>
>>> On my Raspberry Pi B i get the following:
>>>
>>> [2.084411] dwc2 2098.usb: mapped PA 2098 to VA cc88
>>> [2.084461] dwc2 2098.usb: cannot get otg clock
>>> [2.084549] dwc2 2098.usb: registering common handler for irq33
>>> [2.084713] dwc2 2098.usb: Configuration mismatch. dr_mode forced to
>>> host
>>> [2.153965] dwc2 2098.usb: Waited 49996 us, 0x00201000 => 0x01001000,
>>> 0x => 0x02002000
>>> [2.174930] dwc2 2098.usb: Forcing mode to host
>>>
>>> So i changed the delay in patch #1 to msleep(50) and then both patches work
>>> like
>>> a charm.
>>
>> Great news! :-)
>>
>> John: it's pretty clear that there's something taking almost exactly
>> 10ms on my system and almost exactly 50ms on Stefan's system. Is
>> there some register we could poll to see when this process is done?
>> ...or can we look at the dwc2 revision number / feature register and
>> detect how long to delay?
>>
>
> Hi Doug,
>
> I'll have to ask around to see if anyone knows about this. And I'll
> run some tests on the platforms I have available to me as well.
>
There's still nothing definitive on our end as to why this is
happening. Also I don't think there is any other way to poll the
reset. Our hardware engineers asked for some more information to look
into it further. Doug, Stefan, Caesar, and anyone else with a related
platform, do you know the answers to the following:
1. What is the AHB Clock frequency? Is the AHB Clock gated during
Reset?
2. Also is the PHY clock stopped during the reset or is the PHY PLL
lock times high in the order of ms?
3. In these cases, is the PHY actually an FS Transceiver and not a
UTMI/ULPI PHY?
4. Which version of the controller is being used in these cases?
Regards,
John
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
Hi, > Martin Sperl hat am 19. März 2016 um 11:10 > geschrieben: > > > > On 19.03.2016, at 10:52, Stefan Wahren wrote: > > > > Hi, > > > >> Martin Sperl hat am 19. März 2016 um 08:44 > >> geschrieben: > >> > >> > >> > >>> On 19.03.2016, at 03:17, Eric Anholt wrote: > >>> > >>> Stefan Wahren writes: > >>> > Hi Eric, > hi Martin, > > > John Youn hat am 16. März 2016 um 19:28 > > geschrieben: > > > > > > On 3/10/2016 11:14 AM, John Youn wrote: > >> On 3/9/2016 11:06 AM, Doug Anderson wrote: > >>> > >>> John: it's pretty clear that there's something taking almost exactly > >>> 10ms on my system and almost exactly 50ms on Stefan's system. Is > >>> there some register we could poll to see when this process is done? > >>> ...or can we look at the dwc2 revision number / feature register and > >>> detect how long to delay? > >>> > >> > >> Maybe this difference is related to overclocking settings in the firmware? > >> > > > > 1. What is the AHB Clock frequency? Is the AHB Clock gated during > > Reset? > >>> > >>> Low confidence here as I'm tracing lines across a ton of modules, but it > >>> looks like it comes from the USB AXI clock in peri_image, which is a > >>> gate on the normal 250Mhz APB clock, but nothing should be touching that > >>> gate register as part of USB reset as far as I know. > >>> > >> Isn’t it possible that this clock (probably BCM2835_CLOCK_VPU) is > >> changed by the firmware due to overclocking settings in /boot/config.txt? > > > > i don't use any overclocking settings. > > > > Are you able to reproduce the behavior on your Pi? > > I did not have any problems with USB recently (using 4.5), > so I would not have any idea how to reproduce it. > > Note that I am using it with an AXIS USB-ethernet dongle plus USB-stick > all the time on my Compute Module connected via a tiny hub, > so I wonder if that qualifies as being able to trigger the issue... the probe problem appears after applying John's patch series (it's not in 4.5): [RFT PATCH 1/2] usb: dwc2: Add a 10 ms delay to dwc2_core_reset() [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835" Please follow the complete discussion here [1]. [1] - http://marc.info/?l=linux-kernel&m=145711582915801&w=2 > > Martin
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
> On 19.03.2016, at 10:52, Stefan Wahren wrote: > > Hi, > >> Martin Sperl hat am 19. März 2016 um 08:44 >> geschrieben: >> >> >> >>> On 19.03.2016, at 03:17, Eric Anholt wrote: >>> >>> Stefan Wahren writes: >>> Hi Eric, hi Martin, > John Youn hat am 16. März 2016 um 19:28 > geschrieben: > > > On 3/10/2016 11:14 AM, John Youn wrote: >> On 3/9/2016 11:06 AM, Doug Anderson wrote: >>> >>> John: it's pretty clear that there's something taking almost exactly >>> 10ms on my system and almost exactly 50ms on Stefan's system. Is >>> there some register we could poll to see when this process is done? >>> ...or can we look at the dwc2 revision number / feature register and >>> detect how long to delay? >>> >> >> Maybe this difference is related to overclocking settings in the firmware? >> > > 1. What is the AHB Clock frequency? Is the AHB Clock gated during > Reset? >>> >>> Low confidence here as I'm tracing lines across a ton of modules, but it >>> looks like it comes from the USB AXI clock in peri_image, which is a >>> gate on the normal 250Mhz APB clock, but nothing should be touching that >>> gate register as part of USB reset as far as I know. >>> >> Isn’t it possible that this clock (probably BCM2835_CLOCK_VPU) is >> changed by the firmware due to overclocking settings in /boot/config.txt? > > i don't use any overclocking settings. > > Are you able to reproduce the behavior on your Pi? I did not have any problems with USB recently (using 4.5), so I would not have any idea how to reproduce it. Note that I am using it with an AXIS USB-ethernet dongle plus USB-stick all the time on my Compute Module connected via a tiny hub, so I wonder if that qualifies as being able to trigger the issue... Martin
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
Hi, > Martin Sperl hat am 19. März 2016 um 08:44 > geschrieben: > > > > > On 19.03.2016, at 03:17, Eric Anholt wrote: > > > > Stefan Wahren writes: > > > >> Hi Eric, > >> hi Martin, > >> > >>> John Youn hat am 16. März 2016 um 19:28 > >>> geschrieben: > >>> > >>> > >>> On 3/10/2016 11:14 AM, John Youn wrote: > On 3/9/2016 11:06 AM, Doug Anderson wrote: > > > > John: it's pretty clear that there's something taking almost exactly > > 10ms on my system and almost exactly 50ms on Stefan's system. Is > > there some register we could poll to see when this process is done? > > ...or can we look at the dwc2 revision number / feature register and > > detect how long to delay? > > > > Maybe this difference is related to overclocking settings in the firmware? > > >>> > >>> 1. What is the AHB Clock frequency? Is the AHB Clock gated during > >>> Reset? > > > > Low confidence here as I'm tracing lines across a ton of modules, but it > > looks like it comes from the USB AXI clock in peri_image, which is a > > gate on the normal 250Mhz APB clock, but nothing should be touching that > > gate register as part of USB reset as far as I know. > > > Isn’t it possible that this clock (probably BCM2835_CLOCK_VPU) is > changed by the firmware due to overclocking settings in /boot/config.txt? i don't use any overclocking settings. Are you able to reproduce the behavior on your Pi? Stefan > > Martin > >
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
Hi,
> Eric Anholt hat am 19. März 2016 um 03:17 geschrieben:
>
>
> Stefan Wahren writes:
>
> > Hi Eric,
> > hi Martin,
> >
> >> John Youn hat am 16. März 2016 um 19:28
> >> geschrieben:
> >>
> >>
> >> On 3/10/2016 11:14 AM, John Youn wrote:
> >> > On 3/9/2016 11:06 AM, Doug Anderson wrote:
> >> >> Stefan,
> >> >>
> >> >> On Wed, Mar 9, 2016 at 11:01 AM, Stefan Wahren
> >> >> wrote:
> >> >>>
> >> Doug Anderson hat am 7. März 2016 um 22:30
> >> geschrieben:
> >>
> >>
> >> Stefan,
> >>
> >> On Mon, Mar 7, 2016 at 10:40 AM, Stefan Wahren
> >>
> >> wrote:
> >> > Hi Doug,
> >> >
> >> >> Douglas Anderson hat am 4. März 2016 um
> >> >> 19:23
> >> >> geschrieben:
> >> >>
> >> >>
> >> >> This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
> >> >> bcm2835") now that we've found the root cause. See the change
> >> >> titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
> >> >
> >> > adding a delay of 10 ms after a core reset might be a idea, but
> >> > applying
> >> > both
> >> > patches breaks USB support on RPi :-(
> >> >
> >> > I'm getting the wrong register values ...
> >>
> >> Ugh. :(
> >>
> >> Just out of curiosity, if you loop and time long it takes for the
> >> registers to get to the right state after reset, what do you get?
> >> AKA, pick:
> >>
> >> https://chromium-review.googlesource.com/331260
> >>
> >> ...and let me know what it prints out.
> >> >>>
> >> >>> On my Raspberry Pi B i get the following:
> >> >>>
> >> >>> [ 2.084411] dwc2 2098.usb: mapped PA 2098 to VA cc88
> >> >>> [ 2.084461] dwc2 2098.usb: cannot get otg clock
> >> >>> [ 2.084549] dwc2 2098.usb: registering common handler for irq33
> >> >>> [ 2.084713] dwc2 2098.usb: Configuration mismatch. dr_mode forced
> >> >>> to
> >> >>> host
> >> >>> [ 2.153965] dwc2 2098.usb: Waited 49996 us, 0x00201000 =>
> >> >>> 0x01001000,
> >> >>> 0x => 0x02002000
> >> >>> [ 2.174930] dwc2 2098.usb: Forcing mode to host
> >> >>>
> >> >>> So i changed the delay in patch #1 to msleep(50) and then both patches
> >> >>> work like
> >> >>> a charm.
> >> >>
> >> >> Great news! :-)
> >> >>
> >> >> John: it's pretty clear that there's something taking almost exactly
> >> >> 10ms on my system and almost exactly 50ms on Stefan's system. Is
> >> >> there some register we could poll to see when this process is done?
> >> >> ...or can we look at the dwc2 revision number / feature register and
> >> >> detect how long to delay?
> >> >>
> >> >
> >> > Hi Doug,
> >> >
> >> > I'll have to ask around to see if anyone knows about this. And I'll
> >> > run some tests on the platforms I have available to me as well.
> >> >
> >>
> >> There's still nothing definitive on our end as to why this is
> >> happening. Also I don't think there is any other way to poll the
> >> reset. Our hardware engineers asked for some more information to look
> >> into it further. Doug, Stefan, Caesar, and anyone else with a related
> >> platform, do you know the answers to the following:
> >>
> >> 1. What is the AHB Clock frequency? Is the AHB Clock gated during
> >> Reset?
>
> Low confidence here as I'm tracing lines across a ton of modules, but it
> looks like it comes from the USB AXI clock in peri_image, which is a
> gate on the normal 250Mhz APB clock, but nothing should be touching that
> gate register as part of USB reset as far as I know.
>
> >> 2. Also is the PHY clock stopped during the reset or is the PHY PLL
> >> lock times high in the order of ms?
>
> PHY PLL lock times should be about 40 us, and reset needs to be high for
> 40us. I haven't traced where GRSTCTL_CSFTRST (the reset I assume you're
> talking about here) goes, so I can't say if it's an input to PHY reset.
>
> >> 3. In these cases, is the PHY actually an FS Transceiver and not a
> >> UTMI/ULPI PHY?
>
> The PHY docs say it's UTMI+ compatible.
please correct me if i am wrong, but according to the datasheet [1] there should
be 2 PHYs:
Feature/Parameter | Selected value
High-Speed PHY Interfaces | 1: UTMI+
USB 1.1 Full-Speed Serial Transceiver Interface | 1: Dedicated FS
But non of them is in the BCM2835 devicetree and i don't know if there is any
PHY driver
we could use. Also there is no OTG clock decribed for dwc2.
Btw the USB_GAHBCFG register is modified for BCM2835 following p. 204 in the
datasheet. I don't know
if it's important for this issue.
[1] -
https://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Thanks
Stefan
>
> >> 4. Which version of the controller is being used in these cases?
> >
> > @John: The BCM2835 has version 2.80a
>
> Yeah, that looks right.
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
> On 19.03.2016, at 03:17, Eric Anholt wrote: > > Stefan Wahren writes: > >> Hi Eric, >> hi Martin, >> >>> John Youn hat am 16. März 2016 um 19:28 >>> geschrieben: >>> >>> >>> On 3/10/2016 11:14 AM, John Youn wrote: On 3/9/2016 11:06 AM, Doug Anderson wrote: > > John: it's pretty clear that there's something taking almost exactly > 10ms on my system and almost exactly 50ms on Stefan's system. Is > there some register we could poll to see when this process is done? > ...or can we look at the dwc2 revision number / feature register and > detect how long to delay? > Maybe this difference is related to overclocking settings in the firmware? >>> >>> 1. What is the AHB Clock frequency? Is the AHB Clock gated during >>> Reset? > > Low confidence here as I'm tracing lines across a ton of modules, but it > looks like it comes from the USB AXI clock in peri_image, which is a > gate on the normal 250Mhz APB clock, but nothing should be touching that > gate register as part of USB reset as far as I know. > Isn’t it possible that this clock (probably BCM2835_CLOCK_VPU) is changed by the firmware due to overclocking settings in /boot/config.txt? Martin
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
Hi,
On Wed, Mar 16, 2016 at 11:28 AM, John Youn wrote:
> On 3/10/2016 11:14 AM, John Youn wrote:
>> On 3/9/2016 11:06 AM, Doug Anderson wrote:
>>> Stefan,
>>>
>>> On Wed, Mar 9, 2016 at 11:01 AM, Stefan Wahren
>>> wrote:
> Doug Anderson hat am 7. März 2016 um 22:30
> geschrieben:
>
>
> Stefan,
>
> On Mon, Mar 7, 2016 at 10:40 AM, Stefan Wahren
> wrote:
>> Hi Doug,
>>
>>> Douglas Anderson hat am 4. März 2016 um 19:23
>>> geschrieben:
>>>
>>>
>>> This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
>>> bcm2835") now that we've found the root cause. See the change
>>> titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
>>
>> adding a delay of 10 ms after a core reset might be a idea, but applying
>> both
>> patches breaks USB support on RPi :-(
>>
>> I'm getting the wrong register values ...
>
> Ugh. :(
>
> Just out of curiosity, if you loop and time long it takes for the
> registers to get to the right state after reset, what do you get?
> AKA, pick:
>
> https://chromium-review.googlesource.com/331260
>
> ...and let me know what it prints out.
On my Raspberry Pi B i get the following:
[2.084411] dwc2 2098.usb: mapped PA 2098 to VA cc88
[2.084461] dwc2 2098.usb: cannot get otg clock
[2.084549] dwc2 2098.usb: registering common handler for irq33
[2.084713] dwc2 2098.usb: Configuration mismatch. dr_mode forced
to host
[2.153965] dwc2 2098.usb: Waited 49996 us, 0x00201000 =>
0x01001000,
0x => 0x02002000
[2.174930] dwc2 2098.usb: Forcing mode to host
So i changed the delay in patch #1 to msleep(50) and then both patches
work like
a charm.
>>>
>>> Great news! :-)
>>>
>>> John: it's pretty clear that there's something taking almost exactly
>>> 10ms on my system and almost exactly 50ms on Stefan's system. Is
>>> there some register we could poll to see when this process is done?
>>> ...or can we look at the dwc2 revision number / feature register and
>>> detect how long to delay?
>>>
>>
>> Hi Doug,
>>
>> I'll have to ask around to see if anyone knows about this. And I'll
>> run some tests on the platforms I have available to me as well.
>>
>
> There's still nothing definitive on our end as to why this is
> happening. Also I don't think there is any other way to poll the
> reset.
One thing I noticed is that the delay was only needed on my OTG port
(not my host-only port). ...I also noticed that while waiting the
HPTXFSIZ was temporarily 0x while I was delaying. That seems
to match Stephan.
I wonder if perhaps the delay has to do with how long it took to
detect that it needed to go into host mode?
Ah, interesting. It looks as if "GOTGCTL" changes during this time
too. To summarize:
HOST-only (ff54.usb): needs no delay:
GNPTXFSIZ: 0x04000400
HPTXFSIZ: 0x02000800
GOTGCTL: 0x002d
OTG (ff58): needs 10ms delay. Before delay:
GNPTXFSIZ: 0x00100400
HPTXFSIZ: 0x
GOTGCTL: 0x0001
After delay:
GNPTXFSIZ: 0x04000400
HPTXFSIZ: 0x02000800
GOTGCTL: 0x002c
Could we loop until either BSesVld or ASesVld is set? Don't know much
about OTG, but seems like that might be something sane?
> Our hardware engineers asked for some more information to look
> into it further. Doug, Stefan, Caesar, and anyone else with a related
> platform, do you know the answers to the following:
>
> 1. What is the AHB Clock frequency? Is the AHB Clock gated during
> Reset?
According to commit 20bde643434d ("usb: dwc2: reduce dwc2 driver probe
time"), our AHB clock is 150MHz. I'm nearly certain it is not gated.
> 2. Also is the PHY clock stopped during the reset or is the PHY PLL
> lock times high in the order of ms?
I don't think so.
> 3. In these cases, is the PHY actually an FS Transceiver and not a
> UTMI/ULPI PHY?
I don't think so. Should be answered by debug info spew below...
> 4. Which version of the controller is being used in these cases?
There are two controllers in my case and they behave differently. OTG
takes 10ms and the host-only 0ms.
Here is debug info:
[1.752005] dwc2 ff54.usb: Core Release: 3.10a (snpsid=4f54310a)
[1.758350] dwc2 ff54.usb: hwcfg1=
[1.762807] dwc2 ff54.usb: hwcfg2=228fc856
[1.767245] dwc2 ff54.usb: hwcfg3=03c0c068
[1.771693] dwc2 ff54.usb: hwcfg4=c8004030
[1.776149] dwc2 ff54.usb: grxfsiz=0400
[1.780687] dwc2 ff54.usb: gnptxfsiz=04000400
[1.785402] dwc2 ff54.usb: hptxfsiz=02000800
[1.790024] dwc2 ff54.usb: Detected values from hardware:
[1.795781] dwc2 ff54.usb: op_mode=6
[1.799872] dwc2 ff54.usb: arch=2
[1.817620] dwc2 ff54.usb: dma_desc_enable=1
[1.955925] dwc2 ff54.usb: power_optimized=1
[2.022862] dwc2 ff54
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
Stefan Wahren writes:
> Hi Eric,
> hi Martin,
>
>> John Youn hat am 16. März 2016 um 19:28 geschrieben:
>>
>>
>> On 3/10/2016 11:14 AM, John Youn wrote:
>> > On 3/9/2016 11:06 AM, Doug Anderson wrote:
>> >> Stefan,
>> >>
>> >> On Wed, Mar 9, 2016 at 11:01 AM, Stefan Wahren
>> >> wrote:
>> >>>
>> Doug Anderson hat am 7. März 2016 um 22:30
>> geschrieben:
>>
>>
>> Stefan,
>>
>> On Mon, Mar 7, 2016 at 10:40 AM, Stefan Wahren
>> wrote:
>> > Hi Doug,
>> >
>> >> Douglas Anderson hat am 4. März 2016 um 19:23
>> >> geschrieben:
>> >>
>> >>
>> >> This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
>> >> bcm2835") now that we've found the root cause. See the change
>> >> titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
>> >
>> > adding a delay of 10 ms after a core reset might be a idea, but
>> > applying
>> > both
>> > patches breaks USB support on RPi :-(
>> >
>> > I'm getting the wrong register values ...
>>
>> Ugh. :(
>>
>> Just out of curiosity, if you loop and time long it takes for the
>> registers to get to the right state after reset, what do you get?
>> AKA, pick:
>>
>> https://chromium-review.googlesource.com/331260
>>
>> ...and let me know what it prints out.
>> >>>
>> >>> On my Raspberry Pi B i get the following:
>> >>>
>> >>> [ 2.084411] dwc2 2098.usb: mapped PA 2098 to VA cc88
>> >>> [ 2.084461] dwc2 2098.usb: cannot get otg clock
>> >>> [ 2.084549] dwc2 2098.usb: registering common handler for irq33
>> >>> [ 2.084713] dwc2 2098.usb: Configuration mismatch. dr_mode forced to
>> >>> host
>> >>> [ 2.153965] dwc2 2098.usb: Waited 49996 us, 0x00201000 => 0x01001000,
>> >>> 0x => 0x02002000
>> >>> [ 2.174930] dwc2 2098.usb: Forcing mode to host
>> >>>
>> >>> So i changed the delay in patch #1 to msleep(50) and then both patches
>> >>> work like
>> >>> a charm.
>> >>
>> >> Great news! :-)
>> >>
>> >> John: it's pretty clear that there's something taking almost exactly
>> >> 10ms on my system and almost exactly 50ms on Stefan's system. Is
>> >> there some register we could poll to see when this process is done?
>> >> ...or can we look at the dwc2 revision number / feature register and
>> >> detect how long to delay?
>> >>
>> >
>> > Hi Doug,
>> >
>> > I'll have to ask around to see if anyone knows about this. And I'll
>> > run some tests on the platforms I have available to me as well.
>> >
>>
>> There's still nothing definitive on our end as to why this is
>> happening. Also I don't think there is any other way to poll the
>> reset. Our hardware engineers asked for some more information to look
>> into it further. Doug, Stefan, Caesar, and anyone else with a related
>> platform, do you know the answers to the following:
>>
>> 1. What is the AHB Clock frequency? Is the AHB Clock gated during
>> Reset?
Low confidence here as I'm tracing lines across a ton of modules, but it
looks like it comes from the USB AXI clock in peri_image, which is a
gate on the normal 250Mhz APB clock, but nothing should be touching that
gate register as part of USB reset as far as I know.
>> 2. Also is the PHY clock stopped during the reset or is the PHY PLL
>> lock times high in the order of ms?
PHY PLL lock times should be about 40 us, and reset needs to be high for
40us. I haven't traced where GRSTCTL_CSFTRST (the reset I assume you're
talking about here) goes, so I can't say if it's an input to PHY reset.
>> 3. In these cases, is the PHY actually an FS Transceiver and not a
>> UTMI/ULPI PHY?
The PHY docs say it's UTMI+ compatible.
>> 4. Which version of the controller is being used in these cases?
>
> @John: The BCM2835 has version 2.80a
Yeah, that looks right.
signature.asc
Description: PGP signature
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
Hi Eric,
hi Martin,
> John Youn hat am 16. März 2016 um 19:28 geschrieben:
>
>
> On 3/10/2016 11:14 AM, John Youn wrote:
> > On 3/9/2016 11:06 AM, Doug Anderson wrote:
> >> Stefan,
> >>
> >> On Wed, Mar 9, 2016 at 11:01 AM, Stefan Wahren
> >> wrote:
> >>>
> Doug Anderson hat am 7. März 2016 um 22:30
> geschrieben:
>
>
> Stefan,
>
> On Mon, Mar 7, 2016 at 10:40 AM, Stefan Wahren
> wrote:
> > Hi Doug,
> >
> >> Douglas Anderson hat am 4. März 2016 um 19:23
> >> geschrieben:
> >>
> >>
> >> This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
> >> bcm2835") now that we've found the root cause. See the change
> >> titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
> >
> > adding a delay of 10 ms after a core reset might be a idea, but applying
> > both
> > patches breaks USB support on RPi :-(
> >
> > I'm getting the wrong register values ...
>
> Ugh. :(
>
> Just out of curiosity, if you loop and time long it takes for the
> registers to get to the right state after reset, what do you get?
> AKA, pick:
>
> https://chromium-review.googlesource.com/331260
>
> ...and let me know what it prints out.
> >>>
> >>> On my Raspberry Pi B i get the following:
> >>>
> >>> [ 2.084411] dwc2 2098.usb: mapped PA 2098 to VA cc88
> >>> [ 2.084461] dwc2 2098.usb: cannot get otg clock
> >>> [ 2.084549] dwc2 2098.usb: registering common handler for irq33
> >>> [ 2.084713] dwc2 2098.usb: Configuration mismatch. dr_mode forced to
> >>> host
> >>> [ 2.153965] dwc2 2098.usb: Waited 49996 us, 0x00201000 => 0x01001000,
> >>> 0x => 0x02002000
> >>> [ 2.174930] dwc2 2098.usb: Forcing mode to host
> >>>
> >>> So i changed the delay in patch #1 to msleep(50) and then both patches
> >>> work like
> >>> a charm.
> >>
> >> Great news! :-)
> >>
> >> John: it's pretty clear that there's something taking almost exactly
> >> 10ms on my system and almost exactly 50ms on Stefan's system. Is
> >> there some register we could poll to see when this process is done?
> >> ...or can we look at the dwc2 revision number / feature register and
> >> detect how long to delay?
> >>
> >
> > Hi Doug,
> >
> > I'll have to ask around to see if anyone knows about this. And I'll
> > run some tests on the platforms I have available to me as well.
> >
>
> There's still nothing definitive on our end as to why this is
> happening. Also I don't think there is any other way to poll the
> reset. Our hardware engineers asked for some more information to look
> into it further. Doug, Stefan, Caesar, and anyone else with a related
> platform, do you know the answers to the following:
>
> 1. What is the AHB Clock frequency? Is the AHB Clock gated during
> Reset?
>
> 2. Also is the PHY clock stopped during the reset or is the PHY PLL
> lock times high in the order of ms?
>
> 3. In these cases, is the PHY actually an FS Transceiver and not a
> UTMI/ULPI PHY?
are you able to answer these questions 1 - 3 for BCM2835? I don't want to say
something wrong here.
>
> 4. Which version of the controller is being used in these cases?
@John: The BCM2835 has version 2.80a
Regards
Stefan
>
> Regards,
> John
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
On 3/9/2016 11:06 AM, Doug Anderson wrote:
> Stefan,
>
> On Wed, Mar 9, 2016 at 11:01 AM, Stefan Wahren wrote:
>>
>>> Doug Anderson hat am 7. März 2016 um 22:30
>>> geschrieben:
>>>
>>>
>>> Stefan,
>>>
>>> On Mon, Mar 7, 2016 at 10:40 AM, Stefan Wahren
>>> wrote:
Hi Doug,
> Douglas Anderson hat am 4. März 2016 um 19:23
> geschrieben:
>
>
> This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
> bcm2835") now that we've found the root cause. See the change
> titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
adding a delay of 10 ms after a core reset might be a idea, but applying
both
patches breaks USB support on RPi :-(
I'm getting the wrong register values ...
>>>
>>> Ugh. :(
>>>
>>> Just out of curiosity, if you loop and time long it takes for the
>>> registers to get to the right state after reset, what do you get?
>>> AKA, pick:
>>>
>>> https://chromium-review.googlesource.com/331260
>>>
>>> ...and let me know what it prints out.
>>
>> On my Raspberry Pi B i get the following:
>>
>> [2.084411] dwc2 2098.usb: mapped PA 2098 to VA cc88
>> [2.084461] dwc2 2098.usb: cannot get otg clock
>> [2.084549] dwc2 2098.usb: registering common handler for irq33
>> [2.084713] dwc2 2098.usb: Configuration mismatch. dr_mode forced to
>> host
>> [2.153965] dwc2 2098.usb: Waited 49996 us, 0x00201000 => 0x01001000,
>> 0x => 0x02002000
>> [2.174930] dwc2 2098.usb: Forcing mode to host
>>
>> So i changed the delay in patch #1 to msleep(50) and then both patches work
>> like
>> a charm.
>
> Great news! :-)
>
> John: it's pretty clear that there's something taking almost exactly
> 10ms on my system and almost exactly 50ms on Stefan's system. Is
> there some register we could poll to see when this process is done?
> ...or can we look at the dwc2 revision number / feature register and
> detect how long to delay?
>
Hi Doug,
I'll have to ask around to see if anyone knows about this. And I'll
run some tests on the platforms I have available to me as well.
Regards,
John
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
Stefan,
On Wed, Mar 9, 2016 at 11:01 AM, Stefan Wahren wrote:
>
>> Doug Anderson hat am 7. März 2016 um 22:30
>> geschrieben:
>>
>>
>> Stefan,
>>
>> On Mon, Mar 7, 2016 at 10:40 AM, Stefan Wahren
>> wrote:
>> > Hi Doug,
>> >
>> >> Douglas Anderson hat am 4. März 2016 um 19:23
>> >> geschrieben:
>> >>
>> >>
>> >> This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
>> >> bcm2835") now that we've found the root cause. See the change
>> >> titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
>> >
>> > adding a delay of 10 ms after a core reset might be a idea, but applying
>> > both
>> > patches breaks USB support on RPi :-(
>> >
>> > I'm getting the wrong register values ...
>>
>> Ugh. :(
>>
>> Just out of curiosity, if you loop and time long it takes for the
>> registers to get to the right state after reset, what do you get?
>> AKA, pick:
>>
>> https://chromium-review.googlesource.com/331260
>>
>> ...and let me know what it prints out.
>
> On my Raspberry Pi B i get the following:
>
> [2.084411] dwc2 2098.usb: mapped PA 2098 to VA cc88
> [2.084461] dwc2 2098.usb: cannot get otg clock
> [2.084549] dwc2 2098.usb: registering common handler for irq33
> [2.084713] dwc2 2098.usb: Configuration mismatch. dr_mode forced to
> host
> [2.153965] dwc2 2098.usb: Waited 49996 us, 0x00201000 => 0x01001000,
> 0x => 0x02002000
> [2.174930] dwc2 2098.usb: Forcing mode to host
>
> So i changed the delay in patch #1 to msleep(50) and then both patches work
> like
> a charm.
Great news! :-)
John: it's pretty clear that there's something taking almost exactly
10ms on my system and almost exactly 50ms on Stefan's system. Is
there some register we could poll to see when this process is done?
...or can we look at the dwc2 revision number / feature register and
detect how long to delay?
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
> Doug Anderson hat am 7. März 2016 um 22:30
> geschrieben:
>
>
> Stefan,
>
> On Mon, Mar 7, 2016 at 10:40 AM, Stefan Wahren wrote:
> > Hi Doug,
> >
> >> Douglas Anderson hat am 4. März 2016 um 19:23
> >> geschrieben:
> >>
> >>
> >> This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
> >> bcm2835") now that we've found the root cause. See the change
> >> titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
> >
> > adding a delay of 10 ms after a core reset might be a idea, but applying
> > both
> > patches breaks USB support on RPi :-(
> >
> > I'm getting the wrong register values ...
>
> Ugh. :(
>
> Just out of curiosity, if you loop and time long it takes for the
> registers to get to the right state after reset, what do you get?
> AKA, pick:
>
> https://chromium-review.googlesource.com/331260
>
> ...and let me know what it prints out.
On my Raspberry Pi B i get the following:
[2.084411] dwc2 2098.usb: mapped PA 2098 to VA cc88
[2.084461] dwc2 2098.usb: cannot get otg clock
[2.084549] dwc2 2098.usb: registering common handler for irq33
[2.084713] dwc2 2098.usb: Configuration mismatch. dr_mode forced to host
[2.153965] dwc2 2098.usb: Waited 49996 us, 0x00201000 => 0x01001000,
0x => 0x02002000
[2.174930] dwc2 2098.usb: Forcing mode to host
So i changed the delay in patch #1 to msleep(50) and then both patches work like
a charm.
Stefan
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
Hi Doug,
> Doug Anderson hat am 7. März 2016 um 22:30
> geschrieben:
>
>
> Stefan,
>
> On Mon, Mar 7, 2016 at 10:40 AM, Stefan Wahren wrote:
> > Hi Doug,
> >
> >> Douglas Anderson hat am 4. März 2016 um 19:23
> >> geschrieben:
> >>
> >>
> >> This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
> >> bcm2835") now that we've found the root cause. See the change
> >> titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
> >
> > adding a delay of 10 ms after a core reset might be a idea, but applying
> > both
> > patches breaks USB support on RPi :-(
> >
> > I'm getting the wrong register values ...
>
> Ugh. :(
>
> Just out of curiosity, if you loop and time long it takes for the
> registers to get to the right state after reset, what do you get?
> AKA, pick:
>
> https://chromium-review.googlesource.com/331260
>
> ...and let me know what it prints out. On my system I see:
>
> [ 1.990743] dwc2 ff54.usb: Waited 31 us, 0x04000400 =>
> 0x04000400, 0x02000800 => 0x02000800
> [ 2.119677] dwc2 ff58.usb: Waited 9997 us, 0x00100400 =>
> 0x04000400, 0x => 0x02000800
sure, but this will take some time (weekend).
>
> I believe the difference in behavior is because of the two different
> types of USB controllers (one is OTG and the other is host only).
>
>
> -Doug
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
Stefan,
On Mon, Mar 7, 2016 at 10:40 AM, Stefan Wahren wrote:
> Hi Doug,
>
>> Douglas Anderson hat am 4. März 2016 um 19:23
>> geschrieben:
>>
>>
>> This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
>> bcm2835") now that we've found the root cause. See the change
>> titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
>
> adding a delay of 10 ms after a core reset might be a idea, but applying both
> patches breaks USB support on RPi :-(
>
> I'm getting the wrong register values ...
Ugh. :(
Just out of curiosity, if you loop and time long it takes for the
registers to get to the right state after reset, what do you get?
AKA, pick:
https://chromium-review.googlesource.com/331260
...and let me know what it prints out. On my system I see:
[1.990743] dwc2 ff54.usb: Waited 31 us, 0x04000400 =>
0x04000400, 0x02000800 => 0x02000800
[2.119677] dwc2 ff58.usb: Waited 9997 us, 0x00100400 =>
0x04000400, 0x => 0x02000800
I believe the difference in behavior is because of the two different
types of USB controllers (one is OTG and the other is host only).
-Doug
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
Hi Doug,
> Douglas Anderson hat am 4. März 2016 um 19:23
> geschrieben:
>
>
> This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
> bcm2835") now that we've found the root cause. See the change
> titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
adding a delay of 10 ms after a core reset might be a idea, but applying both
patches breaks USB support on RPi :-(
I'm getting the wrong register values ...
Stefan
Re: [RFT PATCH 2/2] Revert "usb: dwc2: Fix probe problem on bcm2835"
Am 04.03.2016 um 19:23 schrieb Douglas Anderson :
> This reverts commit 192cb07f7928 ("usb: dwc2: Fix probe problem on
> bcm2835") now that we've found the root cause. See the change
> titled ("usb: dwc2: Add a 10 ms delay to dwc2_core_reset()").
>
> Signed-off-by: Douglas Anderson
Tested-by: Michael Niewoehner
> ---
> drivers/usb/dwc2/core.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
> index 8710b2d3e770..7c4a6cf4c73a 100644
> --- a/drivers/usb/dwc2/core.c
> +++ b/drivers/usb/dwc2/core.c
> @@ -353,6 +353,12 @@ static bool dwc2_force_mode(struct dwc2_hsotg *hsotg,
> bool host)
> set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
> clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
>
> + /*
> + * If the force mode bit is already set, don't set it.
> + */
> + if ((gusbcfg & set) && !(gusbcfg & clear))
> + return false;
> +
> gusbcfg &= ~clear;
> gusbcfg |= set;
> dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
> --
> 2.7.0.rc3.207.g0ac5344
>
