Re: [linux-sunxi] Re: [PATCH v6 2/2] media: V3s: Add support for Allwinner CSI.
On Thu, Feb 01, 2018 at 11:34:43AM +, Liviu Dudau wrote: > On Thu, Feb 01, 2018 at 10:20:28AM +0100, Arnd Bergmann wrote: > > On Thu, Feb 1, 2018 at 9:32 AM, Maxime Ripard > > wrote: > > > On Wed, Jan 31, 2018 at 02:47:53PM +, Liviu Dudau wrote: > > >> On Wed, Jan 31, 2018 at 08:42:12AM +0100, Maxime Ripard wrote: > > >> > On Wed, Jan 31, 2018 at 03:08:08AM +, Liviu Dudau wrote: > > >> > > On Fri, Jan 26, 2018 at 11:00:41AM +0800, Yong wrote: > > >> > > >> Yeah, sorry, my threading of the discussion was broken and I've seen > > >> the rest of the thread after I have replied. My bad! > > >> > > >> > > > >> > In our case, the bus where the device is attached will not do the > > >> > address translations, and shouldn't. > > >> > > >> In my view, the bus is already doing address translation at physical > > >> level, AFAIU it remaps the memory to zero. > > > > > > Not really. It uses a separate bus with a different mapping for the > > > DMA accesses (and only the DMA accesses). The AXI (or AHB, I'm not > > > sure, but, well, the "registers" bus) doesn't remap anything in > > > itself, and we only describe this one usually in our DTs. > > I was actually thinking about the DMA bus (AXI bus, most likely), not the > "registers" bus (yes, usually APB or AHB). The DMA bus is the one that does > the implicit remapping for the addresses it uses, if I understood you > correctly. > > > Exactly, the DT model fundamentally assumes that each a device is > > connected to exactly one bus, so we make up a device *tree* rather > > than a non-directed mesh topology that you might see in modern > > SoCs. > > I think you are right, but we also have the registers property for a device > node > and that can be used for describing the "registers" bus. Now, it is possible > that some driver code gets confused between accessing the device registers > (which in Arm world happens through an APB or AHB bus) and the device doing > system > read/writes which usually happends through an AXI (or for very old systems, > AHB) bus. > > For the sake of making sure we are talking about the same thing and in hope > that Maxime or Yong can give a more detailed picture of this device Keep in mind that this part is heavily under-documented to us, and this is mostly information collected through testing and reading through the various vendor trees. As far as I know, a few devices (Display Engine, hardware codec, the CSI driver that spawned this discussion) are connected to the memory through a proprietary bus that does the remapping. The registers part is connected to an AHB bus. > I'll re-iterate what a lot of devices in the Arm world look like > nowadays: > > - they have a bus for accessing the "registers" of the device, for controlling > the behaviour of that device. Inside the SoC, that happens through the > APB bus and it has a separate clock. The CPU has a view of those registers > through some mapping in the address space that has been backed by the > hardware > engineers at design time and in DT we express that through the "registers" > property, > plus the "apb_clk" for most of the bindings. In DT world we express the > mapping > vis-a-vis the parent bus by using the "ranges" property. We do have that. > - they have a high speed bus for doing data transfers. Inside the SoC that > happens through an AXI or more modern CCI interconnect bus. The CPU does not > have a direct view on those transfers, but by using IOMMUs, SMMUs or simple > bus mastering capabilities it can gain knowledge of the state of the > transfers > and/or influence the target memory. Part of that bus controller allows to probe the bus bandwidth and / or set limits for the various controllers connected to it, so it seems to match that description. > In the DT world, we use the "dma-ranges" property like you say to > express the translations that happen on that bus. Right, except that the way dma-ranges is parsed at the moment is that it will look on the parent node for dma-ranges. In this case, the parent in the DT will be our AHB bus, and not all the devices connected on that AHB bus that do DMA go through that DMA bus with the different mapping. So setting it there isn't an option. > Maxime/Yong: does your device have more than one AXI bus for doing > transfers? Not as far as I know. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature
Re: [linux-sunxi] Re: [PATCH v6 2/2] media: V3s: Add support for Allwinner CSI.
On Thu, Feb 01, 2018 at 10:20:28AM +0100, Arnd Bergmann wrote: > On Thu, Feb 1, 2018 at 9:32 AM, Maxime Ripard > wrote: > > On Wed, Jan 31, 2018 at 02:47:53PM +, Liviu Dudau wrote: > >> On Wed, Jan 31, 2018 at 08:42:12AM +0100, Maxime Ripard wrote: > >> > On Wed, Jan 31, 2018 at 03:08:08AM +, Liviu Dudau wrote: > >> > > On Fri, Jan 26, 2018 at 11:00:41AM +0800, Yong wrote: > >> > >> Yeah, sorry, my threading of the discussion was broken and I've seen > >> the rest of the thread after I have replied. My bad! > >> > >> > > >> > In our case, the bus where the device is attached will not do the > >> > address translations, and shouldn't. > >> > >> In my view, the bus is already doing address translation at physical > >> level, AFAIU it remaps the memory to zero. > > > > Not really. It uses a separate bus with a different mapping for the > > DMA accesses (and only the DMA accesses). The AXI (or AHB, I'm not > > sure, but, well, the "registers" bus) doesn't remap anything in > > itself, and we only describe this one usually in our DTs. I was actually thinking about the DMA bus (AXI bus, most likely), not the "registers" bus (yes, usually APB or AHB). The DMA bus is the one that does the implicit remapping for the addresses it uses, if I understood you correctly. > > Exactly, the DT model fundamentally assumes that each a device is > connected to exactly one bus, so we make up a device *tree* rather > than a non-directed mesh topology that you might see in modern > SoCs. I think you are right, but we also have the registers property for a device node and that can be used for describing the "registers" bus. Now, it is possible that some driver code gets confused between accessing the device registers (which in Arm world happens through an APB or AHB bus) and the device doing system read/writes which usually happends through an AXI (or for very old systems, AHB) bus. For the sake of making sure we are talking about the same thing and in hope that Maxime or Yong can give a more detailed picture of this device, I'll re-iterate what a lot of devices in the Arm world look like nowadays: - they have a bus for accessing the "registers" of the device, for controlling the behaviour of that device. Inside the SoC, that happens through the APB bus and it has a separate clock. The CPU has a view of those registers through some mapping in the address space that has been backed by the hardware engineers at design time and in DT we express that through the "registers" property, plus the "apb_clk" for most of the bindings. In DT world we express the mapping vis-a-vis the parent bus by using the "ranges" property. - they have a high speed bus for doing data transfers. Inside the SoC that happens through an AXI or more modern CCI interconnect bus. The CPU does not have a direct view on those transfers, but by using IOMMUs, SMMUs or simple bus mastering capabilities it can gain knowledge of the state of the transfers and/or influence the target memory. In the DT world, we use the "dma-ranges" property like you say to express the translations that happen on that bus. Maxime/Yong: does your device have more than one AXI bus for doing transfers? > > The "dma-ranges" property was introduced when this first started > falling apart and we got devices that had a different translation > in DMA direction compared to control direction (i.e. the "ranges" > property), but that still assumed that every device on a given bus > had the same view of DMA space. > > With just "dma-ranges", we could easy deal with a topology where > each DMA master on an AXI bus sees main memory at address > zero but the CPU sees the same memory at a high address while > seeing the MMIO ranges at a low address. > > What we cannot represent is multiple masters on the same > AXI bus that use a different translation. Making up arbitrary > intermediate buses would get this to work, but would likely > cause other problems in the future when we do something > else that relies on having a correct representation of the > hierarchy of all the AXI/AHB/APB buses in the system, such > as doing per-bus bandwidth allocation for child devices or > anything else that requires configuring the bus bridge itself. Agree we cannot express multiple masters on the same AXI bus having different translations. Maybe we need to try to make things look more like PCI where the child busses can have their own view of the world as long as they don't try to communicate upwards to their parents or sideways to sibling busses? > > >> What you (we?) need is a simple bus driver that registers the > >> correct virt_to_bus()/bus_to_virt() hooks for the device that do > >> this translation at the DMA API level as well. > > > > Like I said, this only impact DMA transfers, and not the registers > > accesses. We have other devices sitting on the same bus that do not > > perform DMA accesses through that special memory bus and will not have > > that mapping ch
Re: [linux-sunxi] Re: [PATCH v6 2/2] media: V3s: Add support for Allwinner CSI.
On Thu, Feb 1, 2018 at 9:32 AM, Maxime Ripard wrote: > On Wed, Jan 31, 2018 at 02:47:53PM +, Liviu Dudau wrote: >> On Wed, Jan 31, 2018 at 08:42:12AM +0100, Maxime Ripard wrote: >> > On Wed, Jan 31, 2018 at 03:08:08AM +, Liviu Dudau wrote: >> > > On Fri, Jan 26, 2018 at 11:00:41AM +0800, Yong wrote: >> >> Yeah, sorry, my threading of the discussion was broken and I've seen >> the rest of the thread after I have replied. My bad! >> >> > >> > In our case, the bus where the device is attached will not do the >> > address translations, and shouldn't. >> >> In my view, the bus is already doing address translation at physical >> level, AFAIU it remaps the memory to zero. > > Not really. It uses a separate bus with a different mapping for the > DMA accesses (and only the DMA accesses). The AXI (or AHB, I'm not > sure, but, well, the "registers" bus) doesn't remap anything in > itself, and we only describe this one usually in our DTs. Exactly, the DT model fundamentally assumes that each a device is connected to exactly one bus, so we make up a device *tree* rather than a non-directed mesh topology that you might see in modern SoCs. The "dma-ranges" property was introduced when this first started falling apart and we got devices that had a different translation in DMA direction compared to control direction (i.e. the "ranges" property), but that still assumed that every device on a given bus had the same view of DMA space. With just "dma-ranges", we could easy deal with a topology where each DMA master on an AXI bus sees main memory at address zero but the CPU sees the same memory at a high address while seeing the MMIO ranges at a low address. What we cannot represent is multiple masters on the same AXI bus that use a different translation. Making up arbitrary intermediate buses would get this to work, but would likely cause other problems in the future when we do something else that relies on having a correct representation of the hierarchy of all the AXI/AHB/APB buses in the system, such as doing per-bus bandwidth allocation for child devices or anything else that requires configuring the bus bridge itself. >> What you (we?) need is a simple bus driver that registers the >> correct virt_to_bus()/bus_to_virt() hooks for the device that do >> this translation at the DMA API level as well. > > Like I said, this only impact DMA transfers, and not the registers > accesses. We have other devices sitting on the same bus that do not > perform DMA accesses through that special memory bus and will not have > that mapping changed. virt_to_bus()/bus_to_virt() don't actually exist on modern platforms any more, but when they did, they were only about dma access, not mmio access, so they would correspond to what we do with 'dma-ranges' rather than 'ranges'. Arnd
Re: [linux-sunxi] Re: [PATCH v6 2/2] media: V3s: Add support for Allwinner CSI.
On Wed, Jan 31, 2018 at 02:47:53PM +, Liviu Dudau wrote: > On Wed, Jan 31, 2018 at 08:42:12AM +0100, Maxime Ripard wrote: > > On Wed, Jan 31, 2018 at 03:08:08AM +, Liviu Dudau wrote: > > > On Fri, Jan 26, 2018 at 11:00:41AM +0800, Yong wrote: > > > > Hi Maxime, > > > > > > > > On Fri, 26 Jan 2018 09:46:58 +0800 > > > > Yong wrote: > > > > > > > > > Hi Maxime, > > > > > > > > > > Do you have any experience in solving this problem? > > > > > It seems the PHYS_OFFSET maybe undeclared when the ARCH is not arm. > > > > > > > > Got it. > > > > Should I add 'depends on ARM' in Kconfig? > > > > > > No, I don't think you should do that, you should fix the code. > > > > > > The dma_addr_t addr that you've got is ideally coming from > > > dma_alloc_coherent(), > > > in which case the addr is already "suitable" for use by the device > > > (because the > > > bus where the device is attached to does all the address translations). > > > > Like we're discussing in that other part of the thread with Thierry > > and Arnd, things are slightly more complicated than that :) > > Yeah, sorry, my threading of the discussion was broken and I've seen > the rest of the thread after I have replied. My bad! > > > > > In our case, the bus where the device is attached will not do the > > address translations, and shouldn't. > > In my view, the bus is already doing address translation at physical > level, AFAIU it remaps the memory to zero. Not really. It uses a separate bus with a different mapping for the DMA accesses (and only the DMA accesses). The AXI (or AHB, I'm not sure, but, well, the "registers" bus) doesn't remap anything in itself, and we only describe this one usually in our DTs. > What you (we?) need is a simple bus driver that registers the > correct virt_to_bus()/bus_to_virt() hooks for the device that do > this translation at the DMA API level as well. Like I said, this only impact DMA transfers, and not the registers accesses. We have other devices sitting on the same bus that do not perform DMA accesses through that special memory bus and will not have that mapping changed. > > > If you apply PHYS_OFFSET forcefully to it you might get unexpected > > > results. > > > > Out of curiosity, what would be these unexpected results? > > If in the future (or a parallel world setup) the device is sitting > behind an IOMMU, the addr value might well be smaller than > PHYS_OFFSET and you will under-wrap, possibly starting to hit kernel > physical addresses (or anything sitting at the top of the physical > memory). > > From my time playing with IOMMUs and PCI domains, I've learned to > treat the dma_addr_t as a cookie value and never try to do > arithmetics with it. I've never worked with PCI or IOMMU, so I tend to overlook them, but yeah, you're right :) Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature
Re: [linux-sunxi] Re: [PATCH v6 2/2] media: V3s: Add support for Allwinner CSI.
On Wed, Jan 31, 2018 at 08:42:12AM +0100, Maxime Ripard wrote: > Hi Liviu, Hi Maxime, > > On Wed, Jan 31, 2018 at 03:08:08AM +, Liviu Dudau wrote: > > On Fri, Jan 26, 2018 at 11:00:41AM +0800, Yong wrote: > > > Hi Maxime, > > > > > > On Fri, 26 Jan 2018 09:46:58 +0800 > > > Yong wrote: > > > > > > > Hi Maxime, > > > > > > > > Do you have any experience in solving this problem? > > > > It seems the PHYS_OFFSET maybe undeclared when the ARCH is not arm. > > > > > > Got it. > > > Should I add 'depends on ARM' in Kconfig? > > > > No, I don't think you should do that, you should fix the code. > > > > The dma_addr_t addr that you've got is ideally coming from > > dma_alloc_coherent(), > > in which case the addr is already "suitable" for use by the device (because > > the > > bus where the device is attached to does all the address translations). > > Like we're discussing in that other part of the thread with Thierry > and Arnd, things are slightly more complicated than that :) Yeah, sorry, my threading of the discussion was broken and I've seen the rest of the thread after I have replied. My bad! > > In our case, the bus where the device is attached will not do the > address translations, and shouldn't. In my view, the bus is already doing address translation at physical level, AFAIU it remaps the memory to zero. What you (we?) need is a simple bus driver that registers the correct virt_to_bus()/bus_to_virt() hooks for the device that do this translation at the DMA API level as well. > > > If you apply PHYS_OFFSET forcefully to it you might get unexpected > > results. > > Out of curiosity, what would be these unexpected results? If in the future (or a parallel world setup) the device is sitting behind an IOMMU, the addr value might well be smaller than PHYS_OFFSET and you will under-wrap, possibly starting to hit kernel physical addresses (or anything sitting at the top of the physical memory). >From my time playing with IOMMUs and PCI domains, I've learned to treat the >dma_addr_t as a cookie value and never try to do arithmetics with it. Best regards, Liviu > > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com > > -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to linux-sunxi+unsubscr...@googlegroups.com. > For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH v6 2/2] media: V3s: Add support for Allwinner CSI.
Hi Liviu, On Wed, Jan 31, 2018 at 03:08:08AM +, Liviu Dudau wrote: > On Fri, Jan 26, 2018 at 11:00:41AM +0800, Yong wrote: > > Hi Maxime, > > > > On Fri, 26 Jan 2018 09:46:58 +0800 > > Yong wrote: > > > > > Hi Maxime, > > > > > > Do you have any experience in solving this problem? > > > It seems the PHYS_OFFSET maybe undeclared when the ARCH is not arm. > > > > Got it. > > Should I add 'depends on ARM' in Kconfig? > > No, I don't think you should do that, you should fix the code. > > The dma_addr_t addr that you've got is ideally coming from > dma_alloc_coherent(), > in which case the addr is already "suitable" for use by the device (because > the > bus where the device is attached to does all the address translations). Like we're discussing in that other part of the thread with Thierry and Arnd, things are slightly more complicated than that :) In our case, the bus where the device is attached will not do the address translations, and shouldn't. > If you apply PHYS_OFFSET forcefully to it you might get unexpected > results. Out of curiosity, what would be these unexpected results? Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature
Re: [linux-sunxi] Re: [PATCH v6 2/2] media: V3s: Add support for Allwinner CSI.
On Wed, Jan 31, 2018 at 11:08 AM, Liviu Dudau wrote:
> On Fri, Jan 26, 2018 at 11:00:41AM +0800, Yong wrote:
>> Hi Maxime,
>>
>> On Fri, 26 Jan 2018 09:46:58 +0800
>> Yong wrote:
>>
>> > Hi Maxime,
>> >
>> > Do you have any experience in solving this problem?
>> > It seems the PHYS_OFFSET maybe undeclared when the ARCH is not arm.
>>
>> Got it.
>> Should I add 'depends on ARM' in Kconfig?
>
> No, I don't think you should do that, you should fix the code.
>
> The dma_addr_t addr that you've got is ideally coming from
> dma_alloc_coherent(),
> in which case the addr is already "suitable" for use by the device (because
> the
> bus where the device is attached to does all the address translations). If you
> apply PHYS_OFFSET forcefully to it you might get unexpected results.
As explained in the thread, the dma_addr_t address is based on the kernel
and processor's viewpoint, which has DRAM at an offset. This particular
peripheral (and some others, such as display and video decoder) on Allwinner
platforms do DMA on the separate memory bus directly, which does _not_
have that memory offset. This is specific to our hardware. And also mentioned
is that there is no sensible representation in the device tree that would
allow the DMA API to do proper address translation.
Just throwing it out there, maybe we could do a dummy IOMMU that does the
simple translation of (addr - PHYS_OFFSET)? Still I'm not sure if the device
tree representation would be sane.
ChenYu
>>
>> >
>> > On Fri, 26 Jan 2018 08:04:18 +0800
>> > kbuild test robot wrote:
>> >
>> > > Hi Yong,
>> > >
>> > > I love your patch! Yet something to improve:
>> > >
>> > > [auto build test ERROR on linuxtv-media/master]
>> > > [also build test ERROR on v4.15-rc9 next-20180119]
>> > > [if your patch is applied to the wrong git tree, please drop us a note
>> > > to help improve the system]
>> > >
>> > > url:
>> > > https://github.com/0day-ci/linux/commits/Yong-Deng/dt-bindings-media-Add-Allwinner-V3s-Camera-Sensor-Interface-CSI/20180126-054511
>> > > base: git://linuxtv.org/media_tree.git master
>> > > config: i386-allmodconfig (attached as .config)
>> > > compiler: gcc-7 (Debian 7.2.0-12) 7.2.1 20171025
>> > > reproduce:
>> > > # save the attached .config to linux build tree
>> > > make ARCH=i386
>> > >
>> > > All errors (new ones prefixed by >>):
>> > >
>> > >drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c: In function
>> > > 'sun6i_csi_update_buf_addr':
>> > > >> drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c:567:31: error:
>> > > >> 'PHYS_OFFSET' undeclared (first use in this function); did you mean
>> > > >> 'PAGE_OFFSET'?
>> > > dma_addr_t bus_addr = addr - PHYS_OFFSET;
>> > > ^~~
>> > > PAGE_OFFSET
>> > >drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c:567:31: note: each
>> > > undeclared identifier is reported only once for each function it appears
>> > > in
>> > >
>> > > vim +567 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
>> > >
>> > >562
>> > >563void sun6i_csi_update_buf_addr(struct sun6i_csi *csi,
>> > > dma_addr_t addr)
>> > >564{
>> > >565struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
>> > >566/* transform physical address to bus address */
>> > > > 567dma_addr_t bus_addr = addr - PHYS_OFFSET;
>> > >568
>> > >569regmap_write(sdev->regmap, CSI_CH_F0_BUFA_REG,
>> > >570 (bus_addr + sdev->planar_offset[0]) >> 2);
>> > >571if (sdev->planar_offset[1] != -1)
>> > >572regmap_write(sdev->regmap, CSI_CH_F1_BUFA_REG,
>> > >573 (bus_addr +
>> > > sdev->planar_offset[1]) >> 2);
>> > >574if (sdev->planar_offset[2] != -1)
>> > >575regmap_write(sdev->regmap, CSI_CH_F2_BUFA_REG,
>> > >576 (bus_addr +
>> > > sdev->planar_offset[2]) >> 2);
>> > >577}
>> > >578
>> > >
>> > > ---
>> > > 0-DAY kernel test infrastructureOpen Source Technology
>> > > Center
>> > > https://lists.01.org/pipermail/kbuild-all Intel
>> > > Corporation
>> >
>> >
>> > Thanks,
>> > Yong
>>
>>
>> Thanks,
>> Yong
>>
>> --
>> You received this message because you are subscribed to the Google Groups
>> "linux-sunxi" group.
>> To unsubscribe from this group and stop receiving emails from it, send an
>> email to linux-sunxi+unsubscr...@googlegroups.com.
>> For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH v6 2/2] media: V3s: Add support for Allwinner CSI.
On Fri, Jan 26, 2018 at 11:00:41AM +0800, Yong wrote:
> Hi Maxime,
>
> On Fri, 26 Jan 2018 09:46:58 +0800
> Yong wrote:
>
> > Hi Maxime,
> >
> > Do you have any experience in solving this problem?
> > It seems the PHYS_OFFSET maybe undeclared when the ARCH is not arm.
>
> Got it.
> Should I add 'depends on ARM' in Kconfig?
No, I don't think you should do that, you should fix the code.
The dma_addr_t addr that you've got is ideally coming from dma_alloc_coherent(),
in which case the addr is already "suitable" for use by the device (because the
bus where the device is attached to does all the address translations). If you
apply PHYS_OFFSET forcefully to it you might get unexpected results.
Best regards,
Liviu
>
> >
> > On Fri, 26 Jan 2018 08:04:18 +0800
> > kbuild test robot wrote:
> >
> > > Hi Yong,
> > >
> > > I love your patch! Yet something to improve:
> > >
> > > [auto build test ERROR on linuxtv-media/master]
> > > [also build test ERROR on v4.15-rc9 next-20180119]
> > > [if your patch is applied to the wrong git tree, please drop us a note to
> > > help improve the system]
> > >
> > > url:
> > > https://github.com/0day-ci/linux/commits/Yong-Deng/dt-bindings-media-Add-Allwinner-V3s-Camera-Sensor-Interface-CSI/20180126-054511
> > > base: git://linuxtv.org/media_tree.git master
> > > config: i386-allmodconfig (attached as .config)
> > > compiler: gcc-7 (Debian 7.2.0-12) 7.2.1 20171025
> > > reproduce:
> > > # save the attached .config to linux build tree
> > > make ARCH=i386
> > >
> > > All errors (new ones prefixed by >>):
> > >
> > >drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c: In function
> > > 'sun6i_csi_update_buf_addr':
> > > >> drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c:567:31: error:
> > > >> 'PHYS_OFFSET' undeclared (first use in this function); did you mean
> > > >> 'PAGE_OFFSET'?
> > > dma_addr_t bus_addr = addr - PHYS_OFFSET;
> > > ^~~
> > > PAGE_OFFSET
> > >drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c:567:31: note: each
> > > undeclared identifier is reported only once for each function it appears
> > > in
> > >
> > > vim +567 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > >
> > >562
> > >563void sun6i_csi_update_buf_addr(struct sun6i_csi *csi,
> > > dma_addr_t addr)
> > >564{
> > >565struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
> > >566/* transform physical address to bus address */
> > > > 567dma_addr_t bus_addr = addr - PHYS_OFFSET;
> > >568
> > >569regmap_write(sdev->regmap, CSI_CH_F0_BUFA_REG,
> > >570 (bus_addr + sdev->planar_offset[0]) >> 2);
> > >571if (sdev->planar_offset[1] != -1)
> > >572regmap_write(sdev->regmap, CSI_CH_F1_BUFA_REG,
> > >573 (bus_addr +
> > > sdev->planar_offset[1]) >> 2);
> > >574if (sdev->planar_offset[2] != -1)
> > >575regmap_write(sdev->regmap, CSI_CH_F2_BUFA_REG,
> > >576 (bus_addr +
> > > sdev->planar_offset[2]) >> 2);
> > >577}
> > >578
> > >
> > > ---
> > > 0-DAY kernel test infrastructureOpen Source Technology
> > > Center
> > > https://lists.01.org/pipermail/kbuild-all Intel
> > > Corporation
> >
> >
> > Thanks,
> > Yong
>
>
> Thanks,
> Yong
>
> --
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Re: [linux-sunxi] Re: [PATCH v6 2/2] media: V3s: Add support for Allwinner CSI.
Hi, On Sun, Jan 28, 2018 at 10:19:03AM +0800, Yong wrote: > Hi Maxime, > > On Fri, 26 Jan 2018 09:10:00 +0100 > Maxime Ripard wrote: > > > On Fri, Jan 26, 2018 at 11:00:41AM +0800, Yong wrote: > > > Hi Maxime, > > > > > > On Fri, 26 Jan 2018 09:46:58 +0800 > > > Yong wrote: > > > > > > > Hi Maxime, > > > > > > > > Do you have any experience in solving this problem? > > > > It seems the PHYS_OFFSET maybe undeclared when the ARCH is not arm. > > > > > > Got it. > > > Should I add 'depends on ARM' in Kconfig? > > > > Yes, or even better a depends on MACH_SUNXI :) > > Do you mean ARCH_SUNXI? Yeah, sorry :) > ARCH_SUNXI is alreay there. In the early version, my Kconfig is like this: > > depends on ARCH_SUNXI > > But Hans suggest me to change this to: > > depends on ARCH_SUNXI || COMPILE_TEST > > to allow this driver to be compiled on e.g. Intel for compile testing. > > Should we get rid of COMPILE_TEST? Yes, it cannot be compiled as is on anything but ARM and a few architectures. Or maybe something like || (COMPILE_TEST && ARM) if that makes sense? Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature
Re: [linux-sunxi] Re: [PATCH v6 2/2] media: V3s: Add support for Allwinner CSI.
Hi Maxime, On Fri, 26 Jan 2018 09:10:00 +0100 Maxime Ripard wrote: > On Fri, Jan 26, 2018 at 11:00:41AM +0800, Yong wrote: > > Hi Maxime, > > > > On Fri, 26 Jan 2018 09:46:58 +0800 > > Yong wrote: > > > > > Hi Maxime, > > > > > > Do you have any experience in solving this problem? > > > It seems the PHYS_OFFSET maybe undeclared when the ARCH is not arm. > > > > Got it. > > Should I add 'depends on ARM' in Kconfig? > > Yes, or even better a depends on MACH_SUNXI :) Do you mean ARCH_SUNXI? ARCH_SUNXI is alreay there. In the early version, my Kconfig is like this: depends on ARCH_SUNXI But Hans suggest me to change this to: depends on ARCH_SUNXI || COMPILE_TEST to allow this driver to be compiled on e.g. Intel for compile testing. Should we get rid of COMPILE_TEST? Yong
