Re: [tip:x86/urgent] x86/mm/pat: Adjust default caching mode translation tables
Ingo,
Please drop this change as I explained below.
http://marc.info/?l=linux-kernel=143751782107284=2
Thanks,
-Toshi
On Tue, 2015-07-21 at 02:38 -0700, tip-bot for Jan Beulich wrote:
> Commit-ID: ca1fec58bc6a90be96a59b4769e951156846c6ca
> Gitweb:
> http://git.kernel.org/tip/ca1fec58bc6a90be96a59b4769e951156846c6ca
> Author: Jan Beulich
> AuthorDate: Mon, 20 Jul 2015 08:46:14 +0100
> Committer: Ingo Molnar
> CommitDate: Tue, 21 Jul 2015 08:23:06 +0200
>
> x86/mm/pat: Adjust default caching mode translation tables
>
> Make WT really mean WT (rather than UC).
>
> I can't see why commit 9cd25aac1f ("x86/mm/pat: Emulate PAT when
> it is disabled") didn't make this to match its changes to
> pat_init().
>
> Signed-off-by: Jan Beulich
> Cc: Andy Lutomirski
> Cc: Borislav Petkov
> Cc: Linus Torvalds
> Cc: Peter Zijlstra
> Cc: Thomas Gleixner
> Cc: Toshi Kani
> Link:
> http://lkml.kernel.org/r/55acc366027800092...@mail.emea.novell.com
> Signed-off-by: Ingo Molnar
> ---
> arch/x86/mm/init.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
> index 8533b46..7a45322 100644
> --- a/arch/x86/mm/init.c
> +++ b/arch/x86/mm/init.c
> @@ -43,18 +43,18 @@ uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] =
> {
> [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD,
> [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
> [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD,
> - [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
> + [_PAGE_CACHE_MODE_WT ] = _PAGE_PWT | 0,
> [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD,
> };
> EXPORT_SYMBOL(__cachemode2pte_tbl);
>
> uint8_t __pte2cachemode_tbl[8] = {
> [__pte2cm_idx( 0| 0 | 0)] =
> _PAGE_CACHE_MODE_WB,
> - [__pte2cm_idx(_PAGE_PWT | 0 | 0)] =
> _PAGE_CACHE_MODE_UC_MINUS,
> + [__pte2cm_idx(_PAGE_PWT | 0 | 0)] =
> _PAGE_CACHE_MODE_WT,
> [__pte2cm_idx( 0| _PAGE_PCD | 0)] =
> _PAGE_CACHE_MODE_UC_MINUS,
> [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0)] =
> _PAGE_CACHE_MODE_UC,
> [__pte2cm_idx( 0| 0 | _PAGE_PAT)] =
> _PAGE_CACHE_MODE_WB,
> - [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] =
> _PAGE_CACHE_MODE_UC_MINUS,
> + [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] =
> _PAGE_CACHE_MODE_WT,
> [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] =
> _PAGE_CACHE_MODE_UC_MINUS,
> [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] =
> _PAGE_CACHE_MODE_UC,
> };
--
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Re: [tip:x86/urgent] x86/mm/pat: Adjust default caching mode translation tables
Ingo,
Please drop this change as I explained below.
http://marc.info/?l=linux-kernelm=143751782107284w=2
Thanks,
-Toshi
On Tue, 2015-07-21 at 02:38 -0700, tip-bot for Jan Beulich wrote:
Commit-ID: ca1fec58bc6a90be96a59b4769e951156846c6ca
Gitweb:
http://git.kernel.org/tip/ca1fec58bc6a90be96a59b4769e951156846c6ca
Author: Jan Beulich jbeul...@suse.com
AuthorDate: Mon, 20 Jul 2015 08:46:14 +0100
Committer: Ingo Molnar mi...@kernel.org
CommitDate: Tue, 21 Jul 2015 08:23:06 +0200
x86/mm/pat: Adjust default caching mode translation tables
Make WT really mean WT (rather than UC).
I can't see why commit 9cd25aac1f (x86/mm/pat: Emulate PAT when
it is disabled) didn't make this to match its changes to
pat_init().
Signed-off-by: Jan Beulich jbeul...@suse.com
Cc: Andy Lutomirski l...@amacapital.net
Cc: Borislav Petkov b...@suse.de
Cc: Linus Torvalds torva...@linux-foundation.org
Cc: Peter Zijlstra pet...@infradead.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Toshi Kani toshi.k...@hp.com
Link:
http://lkml.kernel.org/r/55acc366027800092...@mail.emea.novell.com
Signed-off-by: Ingo Molnar mi...@kernel.org
---
arch/x86/mm/init.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 8533b46..7a45322 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -43,18 +43,18 @@ uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] =
{
[_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD,
[_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
[_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD,
- [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
+ [_PAGE_CACHE_MODE_WT ] = _PAGE_PWT | 0,
[_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD,
};
EXPORT_SYMBOL(__cachemode2pte_tbl);
uint8_t __pte2cachemode_tbl[8] = {
[__pte2cm_idx( 0| 0 | 0)] =
_PAGE_CACHE_MODE_WB,
- [__pte2cm_idx(_PAGE_PWT | 0 | 0)] =
_PAGE_CACHE_MODE_UC_MINUS,
+ [__pte2cm_idx(_PAGE_PWT | 0 | 0)] =
_PAGE_CACHE_MODE_WT,
[__pte2cm_idx( 0| _PAGE_PCD | 0)] =
_PAGE_CACHE_MODE_UC_MINUS,
[__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0)] =
_PAGE_CACHE_MODE_UC,
[__pte2cm_idx( 0| 0 | _PAGE_PAT)] =
_PAGE_CACHE_MODE_WB,
- [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] =
_PAGE_CACHE_MODE_UC_MINUS,
+ [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] =
_PAGE_CACHE_MODE_WT,
[__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] =
_PAGE_CACHE_MODE_UC_MINUS,
[__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] =
_PAGE_CACHE_MODE_UC,
};
--
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