Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
On Thursday, 14 of February 2008, Alexey Dobriyan wrote: > On Wed, Feb 13, 2008 at 11:52:46PM +0100, Rafael J. Wysocki wrote: > > On Monday, 4 of February 2008, Alexey Dobriyan wrote: > > > Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka > > > "PCI: Fix bus resource assignment on 32 bits with 64b resources" > > > renders one tg3-equipped box networkless here. > > > > Has it been fixed already or is it still happening with the current > > mainline? > > It's fine now. See 20651af9ac60fd6e31360688ad44861a7d05256a aka > "x86: fix mttr trimming". OK, thanks. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
On Wed, 2008-02-13 at 23:52 +0100, Rafael J. Wysocki wrote: > On Monday, 4 of February 2008, Alexey Dobriyan wrote: > > Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka > > "PCI: Fix bus resource assignment on 32 bits with 64b resources" > > renders one tg3-equipped box networkless here. > > Has it been fixed already or is it still happening with the current mainline? Alexey said it got fixed by some other change, could have been a BIOS issue of some sort ? Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
On Wed, Feb 13, 2008 at 11:52:46PM +0100, Rafael J. Wysocki wrote: > On Monday, 4 of February 2008, Alexey Dobriyan wrote: > > Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka > > "PCI: Fix bus resource assignment on 32 bits with 64b resources" > > renders one tg3-equipped box networkless here. > > Has it been fixed already or is it still happening with the current mainline? It's fine now. See 20651af9ac60fd6e31360688ad44861a7d05256a aka "x86: fix mttr trimming". -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
On Monday, 4 of February 2008, Alexey Dobriyan wrote: > Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka > "PCI: Fix bus resource assignment on 32 bits with 64b resources" > renders one tg3-equipped box networkless here. Has it been fixed already or is it still happening with the current mainline? Rafael > tg3.c:v3.87 (December 20, 2007) > tg3: (:02:05.0) phy probe failed, err -19 > tg3: Problem fetching invariants of chip, aborting. > tg3: (:02:05.1) phy probe failed, err -19 > tg3: Problem fetching invariants of chip, aborting. > > It's 32-bit CONFIG_RESOURCES_64BIT=y box. > > Not sure what you need this, but below is some lspci -vvvxxx output: > > > 00:06.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07) > (prog-if 00 [Normal decode]) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- > Stepping- SERR+ FastB2B- > Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- > SERR-Latency: 64 > Bus: primary=00, secondary=03, subordinate=03, sec-latency=64 > I/O behind bridge: a000-bfff > Memory behind bridge: 8000-817f > Prefetchable memory behind bridge: 8180-818f > Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=medium >TAbort- >BridgeCtl: Parity+ SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B- > Capabilities: [c0] HyperTransport: Slave or Primary Interface > !!! Possibly incomplete decoding > Command: BaseUnitID=6 UnitCnt=4 MastHost- DefDir- > Link Control 0: CFlE- CST- CFE- Link Config 0: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit > Link Control 1: CFlE- CST- CFE- Link Config 1: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit > Revision ID: 1.02 > Capabilities: [f0] HyperTransport: Interrupt Discovery and Configuration > 00: 22 10 60 74 17 01 30 02 07 00 04 06 00 40 01 00 > 10: 00 00 00 00 00 00 00 00 00 03 03 40 a0 b0 00 02 > 20: 00 80 70 81 80 81 80 81 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 0b 00 > 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 08 f0 86 00 20 00 00 00 d0 00 00 00 22 00 01 00 > d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 0d 00 0f 00 0d 00 11 00 13 00 17 00 00 00 00 00 > f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 > > 00:07.3 Bridge: Advanced Micro Devices [AMD] AMD-8111 ACPI (rev 05) > Subsystem: Super Micro Computer Inc Unknown device 0811 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- > Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- > SERR- 00: 22 10 6b 74 00 00 80 02 05 00 80 06 00 40 00 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 08 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: 80 b1 09 bc 00 00 00 00 20 04 50 00 00 00 00 03 > 50: 01 00 00 00 0f 00 00 00 01 50 00 00 00 00 00 00 > 60: 00 00 80 06 13 00 00 00 00 00 00 00 00 00 00 00 > 70: 06 29 4b 55 0c 00 00 00 00 00 00 00 d9 15 11 08 > 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 31 57 46 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 00:0a.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev > 13) (prog-if 00 [Normal decode]) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- > Stepping- SERR+ FastB2B- > Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- > SERR-Latency: 64 > Bus: primary=00, secondary=02, subordinate=02, sec-latency=64 > I/O behind bridge: 9000-9fff > Memory behind bridge: 8190-819f > Prefetchable memory behind bridge: 000181a0-000181af > Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- >BridgeCtl: Parity+ SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- > Capabilities: [a0] PCI-X bridge device > Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=100MHz > Status: Dev=00:0a.0 64bit+ 133MHz+ SCD- USC- SCO- SRD- > Upstream: Capacity=14 CommitmentLimit=65535 > Downstream: Capacity=2 CommitmentLimit=65535
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
On Monday, 4 of February 2008, Alexey Dobriyan wrote: Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka PCI: Fix bus resource assignment on 32 bits with 64b resources renders one tg3-equipped box networkless here. Has it been fixed already or is it still happening with the current mainline? Rafael tg3.c:v3.87 (December 20, 2007) tg3: (:02:05.0) phy probe failed, err -19 tg3: Problem fetching invariants of chip, aborting. tg3: (:02:05.1) phy probe failed, err -19 tg3: Problem fetching invariants of chip, aborting. It's 32-bit CONFIG_RESOURCES_64BIT=y box. Not sure what you need this, but below is some lspci -vvvxxx output: 00:06.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- Latency: 64 Bus: primary=00, secondary=03, subordinate=03, sec-latency=64 I/O behind bridge: a000-bfff Memory behind bridge: 8000-817f Prefetchable memory behind bridge: 8180-818f Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- BridgeCtl: Parity+ SERR+ NoISA- VGA+ MAbort- Reset- FastB2B- Capabilities: [c0] HyperTransport: Slave or Primary Interface !!! Possibly incomplete decoding Command: BaseUnitID=6 UnitCnt=4 MastHost- DefDir- Link Control 0: CFlE- CST- CFE- LkFail- Init+ EOC- TXO- CRCErr=0 Link Config 0: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit Link Control 1: CFlE- CST- CFE- LkFail+ Init- EOC+ TXO+ CRCErr=0 Link Config 1: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit Revision ID: 1.02 Capabilities: [f0] HyperTransport: Interrupt Discovery and Configuration 00: 22 10 60 74 17 01 30 02 07 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 40 a0 b0 00 02 20: 00 80 70 81 80 81 80 81 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 0b 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 08 f0 86 00 20 00 00 00 d0 00 00 00 22 00 01 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 0d 00 0f 00 0d 00 11 00 13 00 17 00 00 00 00 00 f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00:07.3 Bridge: Advanced Micro Devices [AMD] AMD-8111 ACPI (rev 05) Subsystem: Super Micro Computer Inc Unknown device 0811 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- 00: 22 10 6b 74 00 00 80 02 05 00 80 06 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 08 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 80 b1 09 bc 00 00 00 00 20 04 50 00 00 00 00 03 50: 01 00 00 00 0f 00 00 00 01 50 00 00 00 00 00 00 60: 00 00 80 06 13 00 00 00 00 00 00 00 00 00 00 00 70: 06 29 4b 55 0c 00 00 00 00 00 00 00 d9 15 11 08 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 31 57 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 13) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- Latency: 64 Bus: primary=00, secondary=02, subordinate=02, sec-latency=64 I/O behind bridge: 9000-9fff Memory behind bridge: 8190-819f Prefetchable memory behind bridge: 000181a0-000181af Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium TAbort- TAbort- MAbort+ SERR- PERR- BridgeCtl: Parity+ SERR- NoISA+ VGA- MAbort- Reset- FastB2B- Capabilities: [a0] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=100MHz Status: Dev=00:0a.0 64bit+ 133MHz+ SCD- USC- SCO- SRD- Upstream:
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
On Thursday, 14 of February 2008, Alexey Dobriyan wrote: On Wed, Feb 13, 2008 at 11:52:46PM +0100, Rafael J. Wysocki wrote: On Monday, 4 of February 2008, Alexey Dobriyan wrote: Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka PCI: Fix bus resource assignment on 32 bits with 64b resources renders one tg3-equipped box networkless here. Has it been fixed already or is it still happening with the current mainline? It's fine now. See 20651af9ac60fd6e31360688ad44861a7d05256a aka x86: fix mttr trimming. OK, thanks. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
On Wed, 2008-02-13 at 23:52 +0100, Rafael J. Wysocki wrote: On Monday, 4 of February 2008, Alexey Dobriyan wrote: Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka PCI: Fix bus resource assignment on 32 bits with 64b resources renders one tg3-equipped box networkless here. Has it been fixed already or is it still happening with the current mainline? Alexey said it got fixed by some other change, could have been a BIOS issue of some sort ? Cheers, Ben. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
On Wed, Feb 13, 2008 at 11:52:46PM +0100, Rafael J. Wysocki wrote: On Monday, 4 of February 2008, Alexey Dobriyan wrote: Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka PCI: Fix bus resource assignment on 32 bits with 64b resources renders one tg3-equipped box networkless here. Has it been fixed already or is it still happening with the current mainline? It's fine now. See 20651af9ac60fd6e31360688ad44861a7d05256a aka x86: fix mttr trimming. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
On Thu, Feb 07, 2008 at 08:15:26AM +1100, Benjamin Herrenschmidt wrote: > > > > > BTW, "[PATCH] x86_32: fix regression caused by trim ram according to mtrr > > on system with 4G more RAM" > > http://marc.info/?l=linux-kernel=120229095121673=2 > > fixes this box too and I have back all 4G of RAM as a bonus. :-) > > You mean you no longer have a problem or does your tg3 issue still > stand ? tg3 is fine now, thanks everyone. :) -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
On Thu, Feb 07, 2008 at 08:15:26AM +1100, Benjamin Herrenschmidt wrote: BTW, [PATCH] x86_32: fix regression caused by trim ram according to mtrr on system with 4G more RAM http://marc.info/?l=linux-kernelm=120229095121673w=2 fixes this box too and I have back all 4G of RAM as a bonus. :-) You mean you no longer have a problem or does your tg3 issue still stand ? tg3 is fine now, thanks everyone. :) -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
> > BTW, "[PATCH] x86_32: fix regression caused by trim ram according to mtrr on > system with 4G more RAM" > http://marc.info/?l=linux-kernel=120229095121673=2 > fixes this box too and I have back all 4G of RAM as a bonus. :-) You mean you no longer have a problem or does your tg3 issue still stand ? Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
On Feb 6, 2008 2:05 AM, Alexey Dobriyan <[EMAIL PROTECTED]> wrote: > > On Wed, Feb 06, 2008 at 07:49:52AM +1100, Benjamin Herrenschmidt wrote: > > > > > so x86_64 will work well? > > > > > > the problem is that BIOS does not assign one resource for you tg3. and > > > kernel pcibios_assign_to_unassign (?) try > > > to assign resource to your card. > > > > But the kernel shouldn't try to assign a resource in the 64 bits space > > to a card behind a bridge... at least not a non-prefetchable resource > > since those can't be forwarded (P2P bridges only define a 32 bits window > > for non-prefetchable resources). > > > > So it does look to me like the kernel may be doing something wrong. I > > haven't had a chance to look at the logs in details yet (just woke up). > > > > > revert the patch happen to work, you only have 2g less RAM (?), so > > > 0x800 still can be used. > > > > > > sometime you could get hang if your MB have two HT chains. ...because > > > BIOS already allocate two io range for the two chain. > > > and kernel may assign resource from the range1 belong to HT1 to device > > > under HT0. > > > solution: need pci root bios to provide _CRS to replace... > > > and i have one patch but it only take care of 64 bit kernel for this case. > > > > > > > > > easy solution for you: try to get one updated BIOS. > > BTW, "[PATCH] x86_32: fix regression caused by trim ram according to mtrr on > system with 4G more RAM" > http://marc.info/?l=linux-kernel=120229095121673=2 > fixes this box too and I have back all 4G of RAM as a bonus. :-) so you have 4g ram, and with hw memhole enabled? BIOS should have Tom2 set, and WB set .. you must have rev C or Rev E instead of rev F? can you post the /proc/mtrrs and boot message? YH -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
On Wed, Feb 06, 2008 at 07:49:52AM +1100, Benjamin Herrenschmidt wrote: > > > so x86_64 will work well? > > > > the problem is that BIOS does not assign one resource for you tg3. and > > kernel pcibios_assign_to_unassign (?) try > > to assign resource to your card. > > But the kernel shouldn't try to assign a resource in the 64 bits space > to a card behind a bridge... at least not a non-prefetchable resource > since those can't be forwarded (P2P bridges only define a 32 bits window > for non-prefetchable resources). > > So it does look to me like the kernel may be doing something wrong. I > haven't had a chance to look at the logs in details yet (just woke up). > > > revert the patch happen to work, you only have 2g less RAM (?), so > > 0x800 still can be used. > > > > sometime you could get hang if your MB have two HT chains. ...because > > BIOS already allocate two io range for the two chain. > > and kernel may assign resource from the range1 belong to HT1 to device > > under HT0. > > solution: need pci root bios to provide _CRS to replace... > > and i have one patch but it only take care of 64 bit kernel for this case. > > > > > > easy solution for you: try to get one updated BIOS. BTW, "[PATCH] x86_32: fix regression caused by trim ram according to mtrr on system with 4G more RAM" http://marc.info/?l=linux-kernel=120229095121673=2 fixes this box too and I have back all 4G of RAM as a bonus. :-) -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
On Wed, Feb 06, 2008 at 07:49:52AM +1100, Benjamin Herrenschmidt wrote: so x86_64 will work well? the problem is that BIOS does not assign one resource for you tg3. and kernel pcibios_assign_to_unassign (?) try to assign resource to your card. But the kernel shouldn't try to assign a resource in the 64 bits space to a card behind a bridge... at least not a non-prefetchable resource since those can't be forwarded (P2P bridges only define a 32 bits window for non-prefetchable resources). So it does look to me like the kernel may be doing something wrong. I haven't had a chance to look at the logs in details yet (just woke up). revert the patch happen to work, you only have 2g less RAM (?), so 0x800 still can be used. sometime you could get hang if your MB have two HT chains. ...because BIOS already allocate two io range for the two chain. and kernel may assign resource from the range1 belong to HT1 to device under HT0. solution: need pci root bios to provide _CRS to replace... and i have one patch but it only take care of 64 bit kernel for this case. easy solution for you: try to get one updated BIOS. BTW, [PATCH] x86_32: fix regression caused by trim ram according to mtrr on system with 4G more RAM http://marc.info/?l=linux-kernelm=120229095121673w=2 fixes this box too and I have back all 4G of RAM as a bonus. :-) -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
On Feb 6, 2008 2:05 AM, Alexey Dobriyan [EMAIL PROTECTED] wrote: On Wed, Feb 06, 2008 at 07:49:52AM +1100, Benjamin Herrenschmidt wrote: so x86_64 will work well? the problem is that BIOS does not assign one resource for you tg3. and kernel pcibios_assign_to_unassign (?) try to assign resource to your card. But the kernel shouldn't try to assign a resource in the 64 bits space to a card behind a bridge... at least not a non-prefetchable resource since those can't be forwarded (P2P bridges only define a 32 bits window for non-prefetchable resources). So it does look to me like the kernel may be doing something wrong. I haven't had a chance to look at the logs in details yet (just woke up). revert the patch happen to work, you only have 2g less RAM (?), so 0x800 still can be used. sometime you could get hang if your MB have two HT chains. ...because BIOS already allocate two io range for the two chain. and kernel may assign resource from the range1 belong to HT1 to device under HT0. solution: need pci root bios to provide _CRS to replace... and i have one patch but it only take care of 64 bit kernel for this case. easy solution for you: try to get one updated BIOS. BTW, [PATCH] x86_32: fix regression caused by trim ram according to mtrr on system with 4G more RAM http://marc.info/?l=linux-kernelm=120229095121673w=2 fixes this box too and I have back all 4G of RAM as a bonus. :-) so you have 4g ram, and with hw memhole enabled? BIOS should have Tom2 set, and WB set .. you must have rev C or Rev E instead of rev F? can you post the /proc/mtrrs and boot message? YH -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
BTW, [PATCH] x86_32: fix regression caused by trim ram according to mtrr on system with 4G more RAM http://marc.info/?l=linux-kernelm=120229095121673w=2 fixes this box too and I have back all 4G of RAM as a bonus. :-) You mean you no longer have a problem or does your tg3 issue still stand ? Ben. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
Looks like your attachment got currupted for some reason (got here as a corrupted bzip2 file that was encoded as plain text). Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
> so x86_64 will work well? > > the problem is that BIOS does not assign one resource for you tg3. and > kernel pcibios_assign_to_unassign (?) try > to assign resource to your card. But the kernel shouldn't try to assign a resource in the 64 bits space to a card behind a bridge... at least not a non-prefetchable resource since those can't be forwarded (P2P bridges only define a 32 bits window for non-prefetchable resources). So it does look to me like the kernel may be doing something wrong. I haven't had a chance to look at the logs in details yet (just woke up). > revert the patch happen to work, you only have 2g less RAM (?), so > 0x800 still can be used. > > sometime you could get hang if your MB have two HT chains. ...because > BIOS already allocate two io range for the two chain. > and kernel may assign resource from the range1 belong to HT1 to device > under HT0. > solution: need pci root bios to provide _CRS to replace... > and i have one patch but it only take care of 64 bit kernel for this case. > > > easy solution for you: try to get one updated BIOS. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
On Feb 5, 2008 1:17 AM, Alexey Dobriyan <[EMAIL PROTECTED]> wrote: > On Tue, Feb 05, 2008 at 08:54:33AM +1100, Benjamin Herrenschmidt wrote: > > > > On Mon, 2008-02-04 at 18:12 +0300, Alexey Dobriyan wrote: > > > Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka > > > "PCI: Fix bus resource assignment on 32 bits with 64b resources" > > > renders one tg3-equipped box networkless here. > > > > > > tg3.c:v3.87 (December 20, 2007) > > > tg3: (:02:05.0) phy probe failed, err -19 > > > tg3: Problem fetching invariants of chip, aborting. > > > tg3: (:02:05.1) phy probe failed, err -19 > > > tg3: Problem fetching invariants of chip, aborting. > > > > > > It's 32-bit CONFIG_RESOURCES_64BIT=y box. > > > > > > Not sure what you need this, but below is some lspci -vvvxxx output: > > > > Interesting. It looks like the BAR of the tg3 has a spurrious 0x1 > > bit set to it. Can you send me a full dmesg, if possible enabling DEBUG > > in the pci code (there's some places to turn DEBUG on in drivers/pci/*) > > OK, attached data collected on 2.6.24-9ef9dc69d4167276c04590d67ee55de8380bc1ad > with CONFIG_PCI_DEBUG=y with and without your patch: > (-000 means vanilla, -001 means with reverted patch) > > -rw-r--r-- 1 ad ad 25261 2008-02-05 12:08 tg3-000.dmesg > -rw-r--r-- 1 ad ad 1112 2008-02-05 12:08 tg3-000.iomem > -rw-r--r-- 1 ad ad 37785 2008-02-05 12:08 tg3-000.lspci > -rw-r--r-- 1 ad ad 25495 2008-02-05 12:08 tg3-001.dmesg > -rw-r--r-- 1 ad ad 1172 2008-02-05 12:08 tg3-001.iomem > -rw-r--r-- 1 ad ad 37933 2008-02-05 12:08 tg3-001.lspci > > dmesg is full of such chunks: > - got res [18000:180ff] bus [18000:180ff] flags 200 for BAR > 0 of :03:04.0 > + got res [18000:180ff] bus [8000:80ff] flags 200 for BAR 0 > of :03:04.0 > > which is definitely not difference in formatting. > so x86_64 will work well? the problem is that BIOS does not assign one resource for you tg3. and kernel pcibios_assign_to_unassign (?) try to assign resource to your card. revert the patch happen to work, you only have 2g less RAM (?), so 0x800 still can be used. sometime you could get hang if your MB have two HT chains. ...because BIOS already allocate two io range for the two chain. and kernel may assign resource from the range1 belong to HT1 to device under HT0. solution: need pci root bios to provide _CRS to replace... and i have one patch but it only take care of 64 bit kernel for this case. easy solution for you: try to get one updated BIOS. YH -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
On Feb 5, 2008 1:17 AM, Alexey Dobriyan [EMAIL PROTECTED] wrote: On Tue, Feb 05, 2008 at 08:54:33AM +1100, Benjamin Herrenschmidt wrote: On Mon, 2008-02-04 at 18:12 +0300, Alexey Dobriyan wrote: Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka PCI: Fix bus resource assignment on 32 bits with 64b resources renders one tg3-equipped box networkless here. tg3.c:v3.87 (December 20, 2007) tg3: (:02:05.0) phy probe failed, err -19 tg3: Problem fetching invariants of chip, aborting. tg3: (:02:05.1) phy probe failed, err -19 tg3: Problem fetching invariants of chip, aborting. It's 32-bit CONFIG_RESOURCES_64BIT=y box. Not sure what you need this, but below is some lspci -vvvxxx output: Interesting. It looks like the BAR of the tg3 has a spurrious 0x1 bit set to it. Can you send me a full dmesg, if possible enabling DEBUG in the pci code (there's some places to turn DEBUG on in drivers/pci/*) OK, attached data collected on 2.6.24-9ef9dc69d4167276c04590d67ee55de8380bc1ad with CONFIG_PCI_DEBUG=y with and without your patch: (-000 means vanilla, -001 means with reverted patch) -rw-r--r-- 1 ad ad 25261 2008-02-05 12:08 tg3-000.dmesg -rw-r--r-- 1 ad ad 1112 2008-02-05 12:08 tg3-000.iomem -rw-r--r-- 1 ad ad 37785 2008-02-05 12:08 tg3-000.lspci -rw-r--r-- 1 ad ad 25495 2008-02-05 12:08 tg3-001.dmesg -rw-r--r-- 1 ad ad 1172 2008-02-05 12:08 tg3-001.iomem -rw-r--r-- 1 ad ad 37933 2008-02-05 12:08 tg3-001.lspci dmesg is full of such chunks: - got res [18000:180ff] bus [18000:180ff] flags 200 for BAR 0 of :03:04.0 + got res [18000:180ff] bus [8000:80ff] flags 200 for BAR 0 of :03:04.0 which is definitely not difference in formatting. so x86_64 will work well? the problem is that BIOS does not assign one resource for you tg3. and kernel pcibios_assign_to_unassign (?) try to assign resource to your card. revert the patch happen to work, you only have 2g less RAM (?), so 0x800 still can be used. sometime you could get hang if your MB have two HT chains. ...because BIOS already allocate two io range for the two chain. and kernel may assign resource from the range1 belong to HT1 to device under HT0. solution: need pci root bios to provide _CRS to replace... and i have one patch but it only take care of 64 bit kernel for this case. easy solution for you: try to get one updated BIOS. YH -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
so x86_64 will work well? the problem is that BIOS does not assign one resource for you tg3. and kernel pcibios_assign_to_unassign (?) try to assign resource to your card. But the kernel shouldn't try to assign a resource in the 64 bits space to a card behind a bridge... at least not a non-prefetchable resource since those can't be forwarded (P2P bridges only define a 32 bits window for non-prefetchable resources). So it does look to me like the kernel may be doing something wrong. I haven't had a chance to look at the logs in details yet (just woke up). revert the patch happen to work, you only have 2g less RAM (?), so 0x800 still can be used. sometime you could get hang if your MB have two HT chains. ...because BIOS already allocate two io range for the two chain. and kernel may assign resource from the range1 belong to HT1 to device under HT0. solution: need pci root bios to provide _CRS to replace... and i have one patch but it only take care of 64 bit kernel for this case. easy solution for you: try to get one updated BIOS. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
Looks like your attachment got currupted for some reason (got here as a corrupted bzip2 file that was encoded as plain text). Ben. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
And I could also use the lspci output without the patch. Thanks, Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
Oh and send me the output of /proc/iomem as well. Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
On Mon, 2008-02-04 at 18:12 +0300, Alexey Dobriyan wrote: > Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka > "PCI: Fix bus resource assignment on 32 bits with 64b resources" > renders one tg3-equipped box networkless here. > > tg3.c:v3.87 (December 20, 2007) > tg3: (:02:05.0) phy probe failed, err -19 > tg3: Problem fetching invariants of chip, aborting. > tg3: (:02:05.1) phy probe failed, err -19 > tg3: Problem fetching invariants of chip, aborting. > > It's 32-bit CONFIG_RESOURCES_64BIT=y box. > > Not sure what you need this, but below is some lspci -vvvxxx output: Interesting. It looks like the BAR of the tg3 has a spurrious 0x1 bit set to it. Can you send me a full dmesg, if possible enabling DEBUG in the pci code (there's some places to turn DEBUG on in drivers/pci/*) Ben. > 00:06.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07) > (prog-if 00 [Normal decode]) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- > Stepping- SERR+ FastB2B- > Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- > SERR-Latency: 64 > Bus: primary=00, secondary=03, subordinate=03, sec-latency=64 > I/O behind bridge: a000-bfff > Memory behind bridge: 8000-817f > Prefetchable memory behind bridge: 8180-818f > Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=medium >TAbort- >BridgeCtl: Parity+ SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B- > Capabilities: [c0] HyperTransport: Slave or Primary Interface > !!! Possibly incomplete decoding > Command: BaseUnitID=6 UnitCnt=4 MastHost- DefDir- > Link Control 0: CFlE- CST- CFE- Link Config 0: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit > Link Control 1: CFlE- CST- CFE- Link Config 1: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit > Revision ID: 1.02 > Capabilities: [f0] HyperTransport: Interrupt Discovery and Configuration > 00: 22 10 60 74 17 01 30 02 07 00 04 06 00 40 01 00 > 10: 00 00 00 00 00 00 00 00 00 03 03 40 a0 b0 00 02 > 20: 00 80 70 81 80 81 80 81 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 0b 00 > 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 08 f0 86 00 20 00 00 00 d0 00 00 00 22 00 01 00 > d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 0d 00 0f 00 0d 00 11 00 13 00 17 00 00 00 00 00 > f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 > > 00:07.3 Bridge: Advanced Micro Devices [AMD] AMD-8111 ACPI (rev 05) > Subsystem: Super Micro Computer Inc Unknown device 0811 > Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- > Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- > SERR- 00: 22 10 6b 74 00 00 80 02 05 00 80 06 00 40 00 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 08 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: 80 b1 09 bc 00 00 00 00 20 04 50 00 00 00 00 03 > 50: 01 00 00 00 0f 00 00 00 01 50 00 00 00 00 00 00 > 60: 00 00 80 06 13 00 00 00 00 00 00 00 00 00 00 00 > 70: 06 29 4b 55 0c 00 00 00 00 00 00 00 d9 15 11 08 > 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 31 57 46 00 00 00 00 00 00 00 00 00 00 00 00 00 > > 00:0a.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev > 13) (prog-if 00 [Normal decode]) > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- > Stepping- SERR+ FastB2B- > Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- > SERR-Latency: 64 > Bus: primary=00, secondary=02, subordinate=02, sec-latency=64 > I/O behind bridge: 9000-9fff > Memory behind bridge: 8190-819f > Prefetchable memory behind bridge: 000181a0-000181af > Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- >BridgeCtl: Parity+ SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- > Capabilities: [a0] PCI-X bridge device > Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=100MHz > Status: Dev=00:0a.0 64bit+ 133MHz+
tg3 broken after "PCI: Fix bus resource assignment on 32 bits with 64b resources"
Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka "PCI: Fix bus resource assignment on 32 bits with 64b resources" renders one tg3-equipped box networkless here. tg3.c:v3.87 (December 20, 2007) tg3: (:02:05.0) phy probe failed, err -19 tg3: Problem fetching invariants of chip, aborting. tg3: (:02:05.1) phy probe failed, err -19 tg3: Problem fetching invariants of chip, aborting. It's 32-bit CONFIG_RESOURCES_64BIT=y box. Not sure what you need this, but below is some lspci -vvvxxx output: 00:06.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- Reset- FastB2B- Capabilities: [c0] HyperTransport: Slave or Primary Interface !!! Possibly incomplete decoding Command: BaseUnitID=6 UnitCnt=4 MastHost- DefDir- Link Control 0: CFlE- CST- CFE- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- Capabilities: [a0] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=100MHz Status: Dev=00:0a.0 64bit+ 133MHz+ SCD- USC- SCO- SRD- Upstream: Capacity=14 CommitmentLimit=65535 Downstream: Capacity=2 CommitmentLimit=65535 Capabilities: [b8] HyperTransport: Interrupt Discovery and Configuration Capabilities: [c0] HyperTransport: Slave or Primary Interface !!! Possibly incomplete decoding Command: BaseUnitID=10 UnitCnt=2 MastHost- DefDir- Link Control 0: CFlE- CST- CFE- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka PCI: Fix bus resource assignment on 32 bits with 64b resources renders one tg3-equipped box networkless here. tg3.c:v3.87 (December 20, 2007) tg3: (:02:05.0) phy probe failed, err -19 tg3: Problem fetching invariants of chip, aborting. tg3: (:02:05.1) phy probe failed, err -19 tg3: Problem fetching invariants of chip, aborting. It's 32-bit CONFIG_RESOURCES_64BIT=y box. Not sure what you need this, but below is some lspci -vvvxxx output: 00:06.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- Latency: 64 Bus: primary=00, secondary=03, subordinate=03, sec-latency=64 I/O behind bridge: a000-bfff Memory behind bridge: 8000-817f Prefetchable memory behind bridge: 8180-818f Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- BridgeCtl: Parity+ SERR+ NoISA- VGA+ MAbort- Reset- FastB2B- Capabilities: [c0] HyperTransport: Slave or Primary Interface !!! Possibly incomplete decoding Command: BaseUnitID=6 UnitCnt=4 MastHost- DefDir- Link Control 0: CFlE- CST- CFE- LkFail- Init+ EOC- TXO- CRCErr=0 Link Config 0: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit Link Control 1: CFlE- CST- CFE- LkFail+ Init- EOC+ TXO+ CRCErr=0 Link Config 1: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit Revision ID: 1.02 Capabilities: [f0] HyperTransport: Interrupt Discovery and Configuration 00: 22 10 60 74 17 01 30 02 07 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 40 a0 b0 00 02 20: 00 80 70 81 80 81 80 81 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 0b 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 08 f0 86 00 20 00 00 00 d0 00 00 00 22 00 01 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 0d 00 0f 00 0d 00 11 00 13 00 17 00 00 00 00 00 f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00:07.3 Bridge: Advanced Micro Devices [AMD] AMD-8111 ACPI (rev 05) Subsystem: Super Micro Computer Inc Unknown device 0811 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- 00: 22 10 6b 74 00 00 80 02 05 00 80 06 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 08 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 80 b1 09 bc 00 00 00 00 20 04 50 00 00 00 00 03 50: 01 00 00 00 0f 00 00 00 01 50 00 00 00 00 00 00 60: 00 00 80 06 13 00 00 00 00 00 00 00 00 00 00 00 70: 06 29 4b 55 0c 00 00 00 00 00 00 00 d9 15 11 08 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 31 57 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 13) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- Latency: 64 Bus: primary=00, secondary=02, subordinate=02, sec-latency=64 I/O behind bridge: 9000-9fff Memory behind bridge: 8190-819f Prefetchable memory behind bridge: 000181a0-000181af Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium TAbort- TAbort- MAbort+ SERR- PERR- BridgeCtl: Parity+ SERR- NoISA+ VGA- MAbort- Reset- FastB2B- Capabilities: [a0] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=100MHz Status: Dev=00:0a.0 64bit+ 133MHz+ SCD- USC- SCO- SRD- Upstream: Capacity=14 CommitmentLimit=65535 Downstream: Capacity=2 CommitmentLimit=65535 Capabilities: [b8] HyperTransport: Interrupt Discovery and
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
On Mon, 2008-02-04 at 18:12 +0300, Alexey Dobriyan wrote: Commit c40a22e0ce5eb400f27449e59e43d021bee58b8d aka PCI: Fix bus resource assignment on 32 bits with 64b resources renders one tg3-equipped box networkless here. tg3.c:v3.87 (December 20, 2007) tg3: (:02:05.0) phy probe failed, err -19 tg3: Problem fetching invariants of chip, aborting. tg3: (:02:05.1) phy probe failed, err -19 tg3: Problem fetching invariants of chip, aborting. It's 32-bit CONFIG_RESOURCES_64BIT=y box. Not sure what you need this, but below is some lspci -vvvxxx output: Interesting. It looks like the BAR of the tg3 has a spurrious 0x1 bit set to it. Can you send me a full dmesg, if possible enabling DEBUG in the pci code (there's some places to turn DEBUG on in drivers/pci/*) Ben. 00:06.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- Latency: 64 Bus: primary=00, secondary=03, subordinate=03, sec-latency=64 I/O behind bridge: a000-bfff Memory behind bridge: 8000-817f Prefetchable memory behind bridge: 8180-818f Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- BridgeCtl: Parity+ SERR+ NoISA- VGA+ MAbort- Reset- FastB2B- Capabilities: [c0] HyperTransport: Slave or Primary Interface !!! Possibly incomplete decoding Command: BaseUnitID=6 UnitCnt=4 MastHost- DefDir- Link Control 0: CFlE- CST- CFE- LkFail- Init+ EOC- TXO- CRCErr=0 Link Config 0: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit Link Control 1: CFlE- CST- CFE- LkFail+ Init- EOC+ TXO+ CRCErr=0 Link Config 1: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit Revision ID: 1.02 Capabilities: [f0] HyperTransport: Interrupt Discovery and Configuration 00: 22 10 60 74 17 01 30 02 07 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 40 a0 b0 00 02 20: 00 80 70 81 80 81 80 81 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 0b 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 08 f0 86 00 20 00 00 00 d0 00 00 00 22 00 01 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 0d 00 0f 00 0d 00 11 00 13 00 17 00 00 00 00 00 f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00:07.3 Bridge: Advanced Micro Devices [AMD] AMD-8111 ACPI (rev 05) Subsystem: Super Micro Computer Inc Unknown device 0811 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- 00: 22 10 6b 74 00 00 80 02 05 00 80 06 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 08 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 80 b1 09 bc 00 00 00 00 20 04 50 00 00 00 00 03 50: 01 00 00 00 0f 00 00 00 01 50 00 00 00 00 00 00 60: 00 00 80 06 13 00 00 00 00 00 00 00 00 00 00 00 70: 06 29 4b 55 0c 00 00 00 00 00 00 00 d9 15 11 08 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 31 57 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 13) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- Latency: 64 Bus: primary=00, secondary=02, subordinate=02, sec-latency=64 I/O behind bridge: 9000-9fff Memory behind bridge: 8190-819f Prefetchable memory behind bridge: 000181a0-000181af Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium TAbort- TAbort- MAbort+ SERR- PERR- BridgeCtl: Parity+ SERR- NoISA+ VGA- MAbort- Reset- FastB2B- Capabilities: [a0] PCI-X bridge device Secondary Status:
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
And I could also use the lspci output without the patch. Thanks, Ben. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: tg3 broken after PCI: Fix bus resource assignment on 32 bits with 64b resources
Oh and send me the output of /proc/iomem as well. Cheers, Ben. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
