[PATCH] usb: dwc3: gadget: Avoid race between dwc3 interrupt handler and irq thread handler
On some platfroms(like x86 platform), when one core is running the USB gadget
irq thread handler by dwc3_thread_interrupt(), meanwhile another core also can
respond other interrupts from dwc3 controller and modify the event buffer by
dwc3_interrupt() function, that will cause getting the wrong event count in
irq thread handler to make the USB function abnormal.
We should add spin_lock/unlock() in dwc3_check_event_buf() to avoid this race.
Signed-off-by: Baolin Wang
---
drivers/usb/dwc3/gadget.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 6785595..1a1e1f4 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2894,10 +2894,13 @@ static irqreturn_t dwc3_check_event_buf(struct
dwc3_event_buffer *evt)
return IRQ_HANDLED;
}
+ spin_lock(&dwc->lock);
count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
count &= DWC3_GEVNTCOUNT_MASK;
- if (!count)
+ if (!count) {
+ spin_unlock(&dwc->lock);
return IRQ_NONE;
+ }
evt->count = count;
evt->flags |= DWC3_EVENT_PENDING;
@@ -2914,6 +2917,7 @@ static irqreturn_t dwc3_check_event_buf(struct
dwc3_event_buffer *evt)
memcpy(evt->cache, evt->buf, count - amount);
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
+ spin_unlock(&dwc->lock);
return IRQ_WAKE_THREAD;
}
--
1.7.9.5
drivers/built-in.o:undefined reference to `sys_fillrect'
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 7ce7d89f48834cefece7804d38fc5d85382edf77 commit: 8992da44c6805d53b920fe538992eae4afd6f22e auxdisplay: ht16k33: Driver for LED controller date: 7 weeks ago config: i386-randconfig-b0-12261424 (attached as .config) compiler: gcc-5 (Debian 5.4.1-2) 5.4.1 20160904 reproduce: git checkout 8992da44c6805d53b920fe538992eae4afd6f22e # save the attached .config to linux build tree make ARCH=i386 All errors (new ones prefixed by >>): drivers/built-in.o:(.data+0x19c4c): undefined reference to `fb_sys_read' drivers/built-in.o:(.data+0x19c50): undefined reference to `fb_sys_write' >> drivers/built-in.o:(.data+0x19c6c): undefined reference to `sys_fillrect' >> drivers/built-in.o:(.data+0x19c70): undefined reference to `sys_copyarea' >> drivers/built-in.o:(.data+0x19c74): undefined reference to `sys_imageblit' --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip
Re: [RFC PATCH 4.10 0/6] Switch BPF's digest to SHA256
Andy Lutomirski wrote: > Since there are plenty of uses for the new-in-4.10 BPF digest feature > that would be problematic if malicious users could produce collisions, > the BPF digest should be collision-resistant. SHA-1 is no longer > considered collision-resistant, so switch it to SHA-256. > > The actual switchover is trivial. Most of this series consists of > cleanups to the SHA256 code to make it usable as a standalone library > (since BPF should not depend on crypto). > > The cleaned up library is much more user-friendly than the SHA-1 code, > so this also significantly tidies up the BPF digest code. > > This is intended for 4.10. If this series misses 4.10 and nothing > takes its place, then we'll have an unpleasant ABI stability > situation. Can you please explain why BPF needs to be able to use SHA directly rather than through the crypto API? Thanks, -- Email: Herbert Xu Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
Re: Linux 4.10-rc1
Hi Linus,
On 2016/12/26 8:41, Linus Torvalds wrote:
> It's Christmas Day, and it's two weeks since the merge window opened.
> Thus, the merge window is now closed.
>
> I did a few final pulls today, but I also rejected a couple of pulls
> that came in late in the window and looked dodgy. You know who you
> are.
>
> On the whole, this wasn't all that big a release - nothing like 4.9.
> Although it wasn't tiny either. I think 4.7 was smaller. 4.8 might
> have been too. It's xmas day, and right now I can't be arsed to
> actually do the statistics I'd normally do.
>
> Everything looks pretty normal, although we had an unusual amount of
> tree-wide final cleanups in the last days of the merge window. But the
> general statistics look fairly common: a bit over half is drivers,
> maybe slightly less arch updates than normal, and a fair amount of
> documentation updates due to the sphinx conversion. And then the usual
> misc noise all over, although the perf tooling updates do stand out.
>
> The shortlog is much too big, as it always is during the merge window,
> so as usual you just get the merge-log.
Kejian and I got massive compile error when cross-compile the kernel for ARM64,
such as
./include/asm-generic/atomic-long.h:23: Error: unknown mnemonic `typedef' --
`typedef atomic64_t atomic_long_t'
./include/asm-generic/atomic-long.h:44: Error: unknown mnemonic `static' --
`static inline long atomic_long_read(const
atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
./include/asm-generic/atomic-long.h:44: Error: unknown mnemonic `return' --
`return (long)READ_ONCE((v)->counter)'
./include/asm-generic/atomic-long.h:44: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/atomic-long.h:45: Error: unknown mnemonic `static' --
`static inline long atomic_long_read_acquire(const
atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
./include/asm-generic/atomic-long.h:45: Error: unknown mnemonic `return' --
`return (long)smp_load_acquire(&(v)->counter)'
./include/asm-generic/atomic-long.h:45: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/atomic-long.h:56: Error: unknown mnemonic `static' --
`static inline void atomic_long_set(atomic_long_t*l,long
i){atomic64_t*v=(atomic64_t*)l'
./include/asm-generic/atomic-long.h:56: Error: unknown mnemonic `write_once' --
`write_once(((v)->counter), (i))'
./include/asm-generic/atomic-long.h:56: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/atomic-long.h:57: Error: unknown mnemonic `static' --
`static inline void atomic_long_set_release(atomic_long_t*l,long
i){atomic64_t*v=(atomic64_t*)l'
./include/asm-generic/atomic-long.h:57: Error: unknown mnemonic
`smp_store_release' -- `smp_store_release(&(v)->counter, (i))'
./include/asm-generic/atomic-long.h:57: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/atomic-long.h:69: Error: unknown mnemonic `static' --
`static inline long atomic_long_add_return(long
i,atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
./include/asm-generic/atomic-long.h:69: Error: unknown mnemonic `return' --
`return (long)atomic64_add_return(i,v)'
./include/asm-generic/atomic-long.h:69: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/atomic-long.h:70: Error: unknown mnemonic `static' --
`static inline long atomic_long_add_return_relaxed(long
i,atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
./include/asm-generic/atomic-long.h:70: Error: unknown mnemonic `return' --
`return (long)atomic64_add_return_relaxed(i,v)'
./include/asm-generic/atomic-long.h:70: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/atomic-long.h:71: Error: unknown mnemonic `static' --
`static inline long atomic_long_add_return_acquire(long
i,atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
./include/asm-generic/atomic-long.h:71: Error: unknown mnemonic `return' --
`return (long)atomic64_add_return_acquire(i,v)'
./include/asm-generic/atomic-long.h:71: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/atomic-long.h:72: Error: unknown mnemonic `static' --
`static inline long atomic_long_add_return_release(long
i,atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
./include/asm-generic/atomic-long.h:72: Error: unknown mnemonic `return' --
`return (long)atomic64_add_return_release(i,v)'
./include/asm-generic/atomic-long.h:72: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/atomic-long.h:73: Error: unknown mnemonic `static' --
`static inline long atomic_long_sub_return(long
i,atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
./include/asm-generic/atomic-long.h:73: Error: unknown mnemonic `return' --
`return (long)atomic64_sub_return(i,v)'
./include/asm-generic/atomic-long.h:73: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/atomic-long.h:74: Error: unknown mnemonic `st
[Patch V7 2/4] irqchip/qeic: merge qeic init code from platforms to a common function
The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/irq-qeic.c
For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);".
qe_ic_cascade_muxed_mpic was used for boards has the same interrupt
number for low interrupt and high interrupt, qe_ic_init has checked
if "low interrupt == high interrupt"
Signed-off-by: Zhao Qiang
---
Changes for v2:
- modify subject and commit msg
- add check for qeic by type
Changes for v3:
- na
Changes for v4:
- na
Changes for v5:
- na
Changes for v6:
- rebase
Changes for v7:
- na
arch/powerpc/platforms/83xx/misc.c| 15 ---
arch/powerpc/platforms/85xx/corenet_generic.c | 9 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 14 --
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 16
arch/powerpc/platforms/85xx/twr_p102x.c | 14 --
drivers/irqchip/irq-qeic.c| 16
6 files changed, 16 insertions(+), 68 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/misc.c
b/arch/powerpc/platforms/83xx/misc.c
index d75c981..c09a135 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -93,24 +93,9 @@ void __init mpc83xx_ipic_init_IRQ(void)
}
#ifdef CONFIG_QUICC_ENGINE
-void __init mpc83xx_qe_init_IRQ(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
- qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
- of_node_put(np);
-}
-
void __init mpc83xx_ipic_and_qe_init_IRQ(void)
{
mpc83xx_ipic_init_IRQ();
- mpc83xx_qe_init_IRQ();
}
#endif /* CONFIG_QUICC_ENGINE */
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index 1179115..1d96c3f 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -41,8 +41,6 @@ void __init corenet_gen_pic_init(void)
unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
MPIC_NO_RESET;
- struct device_node *np;
-
if (ppc_md.get_irq == mpic_get_coreint_irq)
flags |= MPIC_ENABLE_COREINT;
@@ -50,13 +48,6 @@ void __init corenet_gen_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
- }
}
/*
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index d7e440e..06f34a9 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -283,20 +283,6 @@ static void __init mpc85xx_mds_qeic_init(void)
of_node_put(np);
return;
}
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
-
- if (machine_is(p1021_mds))
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- else
- qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
- of_node_put(np);
}
#else
static void __init mpc85xx_mds_qe_init(void) { }
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 1006950..000d385 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -48,10 +48,6 @@ void __init mpc85xx_rdb_pic_init(void)
{
struct mpic *mpic;
-#ifdef CONFIG_QUICC_ENGINE
- struct device_node *np;
-#endif
-
if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) {
mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
MPIC_BIG_ENDIAN |
@@ -66,18 +62,6 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
-
- } else
- pr_err("%s: Could not find qe-ic node\n", __func__);
-#endif
-
}
/*
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c
b/arch/powerpc/platforms/85xx/twr_p102x.c
index 360f625..6be9b33 100644
--- a/ar
[Patch V7 3/4] irqchip/qeic: merge qeic_of_init into qe_ic_init
qeic_of_init just get device_node of qeic from dtb and call qe_ic_init,
pass the device_node to qe_ic_init.
So merge qeic_of_init into qe_ic_init to get the qeic node in
qe_ic_init.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- modify subject and commit msg
- return 0 and add put node when return in qe_ic_init
Changes for v3:
- na
Changes for v4:
- na
Changes for v5:
- na
Changes for v6:
- rebase
Changes for v6:
- na
drivers/irqchip/irq-qeic.c | 91 +-
include/soc/fsl/qe/qe_ic.h | 7
2 files changed, 50 insertions(+), 48 deletions(-)
diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c
index 1463731..4f49d4b 100644
--- a/drivers/irqchip/irq-qeic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -406,27 +406,38 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-void __init qe_ic_init(struct device_node *node, unsigned int flags,
- void (*low_handler)(struct irq_desc *desc),
- void (*high_handler)(struct irq_desc *desc))
+static int __init qe_ic_init(unsigned int flags)
{
+ struct device_node *node;
struct qe_ic *qe_ic;
struct resource res;
- u32 temp = 0, ret, high_active = 0;
+ u32 temp = 0, high_active = 0;
+ int ret = 0;
+
+ node = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+ if (!node) {
+ node = of_find_node_by_type(NULL, "qeic");
+ if (!node)
+ return -ENODEV;
+ }
ret = of_address_to_resource(node, 0, &res);
- if (ret)
- return;
+ if (ret) {
+ ret = -ENODEV;
+ goto err_put_node;
+ }
qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
- if (qe_ic == NULL)
- return;
+ if (qe_ic == NULL) {
+ ret = -ENOMEM;
+ goto err_put_node;
+ }
qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
&qe_ic_host_ops, qe_ic);
if (qe_ic->irqhost == NULL) {
- kfree(qe_ic);
- return;
+ ret = -ENOMEM;
+ goto err_free_qe_ic;
}
qe_ic->regs = ioremap(res.start, resource_size(&res));
@@ -437,9 +448,9 @@ void __init qe_ic_init(struct device_node *node, unsigned
int flags,
qe_ic->virq_low = irq_of_parse_and_map(node, 1);
if (qe_ic->virq_low == NO_IRQ) {
- printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
- kfree(qe_ic);
- return;
+ pr_err("Failed to map QE_IC low IRQ\n");
+ ret = -ENOMEM;
+ goto err_domain_remove;
}
/* default priority scheme is grouped. If spread mode is*/
@@ -466,13 +477,24 @@ void __init qe_ic_init(struct device_node *node, unsigned
int flags,
qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
irq_set_handler_data(qe_ic->virq_low, qe_ic);
- irq_set_chained_handler(qe_ic->virq_low, low_handler);
+ irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
if (qe_ic->virq_high != NO_IRQ &&
qe_ic->virq_high != qe_ic->virq_low) {
irq_set_handler_data(qe_ic->virq_high, qe_ic);
- irq_set_chained_handler(qe_ic->virq_high, high_handler);
+ irq_set_chained_handler(qe_ic->virq_high,
+ qe_ic_cascade_high_mpic);
}
+ of_node_put(node);
+ return 0;
+
+err_domain_remove:
+ irq_domain_remove(qe_ic->irqhost);
+err_free_qe_ic:
+ kfree(qe_ic);
+err_put_node:
+ of_node_put(node);
+ return ret;
}
void qe_ic_set_highest_priority(unsigned int virq, int high)
@@ -579,39 +601,26 @@ static struct device device_qe_ic = {
.bus = &qe_ic_subsys,
};
-static int __init init_qe_ic_sysfs(void)
+static int __init init_qe_ic(void)
{
- int rc;
+ int ret;
- printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
+ ret = qe_ic_init(0);
+ if (ret)
+ return ret;
- rc = subsys_system_register(&qe_ic_subsys, NULL);
- if (rc) {
- printk(KERN_ERR "Failed registering qe_ic sys class\n");
+ ret = subsys_system_register(&qe_ic_subsys, NULL);
+ if (ret) {
+ pr_err("Failed registering qe_ic sys class\n");
return -ENODEV;
}
- rc = device_register(&device_qe_ic);
- if (rc) {
- printk(KERN_ERR "Failed registering qe_ic sys device\n");
+ ret = device_register(&device_qe_ic);
+ if (ret) {
+ pr_err("Failed registering qe_ic sys device\n");
return -ENODEV;
}
- return 0;
-}
-
-static int __init qeic_of_init(void)
-{
- struct devi
[Patch V7 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
move the driver from drivers/soc/fsl/qe to drivers/irqchip,
merge qe_ic.h and qe_ic.c into irq-qeic.c.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- modify the subject and commit msg
Changes for v3:
- merge .h file to .c, rename it with irq-qeic.c
Changes for v4:
- modify comments
Changes for v5:
- disable rename detection
Changes for v6:
- rebase
Changes for v7:
- na
drivers/irqchip/Makefile| 1 +
drivers/irqchip/irq-qeic.c | 601
drivers/soc/fsl/qe/Makefile | 2 +-
drivers/soc/fsl/qe/qe_ic.c | 512 -
drivers/soc/fsl/qe/qe_ic.h | 103
5 files changed, 603 insertions(+), 616 deletions(-)
create mode 100644 drivers/irqchip/irq-qeic.c
delete mode 100644 drivers/soc/fsl/qe/qe_ic.c
delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 4c203b6..face608 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
+obj-$(CONFIG_QUICC_ENGINE) += irq-qeic.o
diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c
new file mode 100644
index 000..48ceded
--- /dev/null
+++ b/drivers/irqchip/irq-qeic.c
@@ -0,0 +1,601 @@
+/*
+ * drivers/irqchip/irq-qeic.c
+ *
+ * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Li Yang
+ * Based on code from Shlomi Gridish
+ *
+ * QUICC ENGINE Interrupt Controller
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define NR_QE_IC_INTS 64
+
+/* QE IC registers offset */
+#define QEIC_CICR 0x00
+#define QEIC_CIVEC 0x04
+#define QEIC_CRIPNR0x08
+#define QEIC_CIPNR 0x0c
+#define QEIC_CIPXCC0x10
+#define QEIC_CIPYCC0x14
+#define QEIC_CIPWCC0x18
+#define QEIC_CIPZCC0x1c
+#define QEIC_CIMR 0x20
+#define QEIC_CRIMR 0x24
+#define QEIC_CICNR 0x28
+#define QEIC_CIPRTA0x30
+#define QEIC_CIPRTB0x34
+#define QEIC_CRICR 0x3c
+#define QEIC_CHIVEC0x60
+
+/* Interrupt priority registers */
+#define CIPCC_SHIFT_PRI0 29
+#define CIPCC_SHIFT_PRI1 26
+#define CIPCC_SHIFT_PRI2 23
+#define CIPCC_SHIFT_PRI3 20
+#define CIPCC_SHIFT_PRI4 13
+#define CIPCC_SHIFT_PRI5 10
+#define CIPCC_SHIFT_PRI6 7
+#define CIPCC_SHIFT_PRI7 4
+
+/* CICR priority modes */
+#define CICR_GWCC 0x0004
+#define CICR_GXCC 0x0002
+#define CICR_GYCC 0x0001
+#define CICR_GZCC 0x0008
+#define CICR_GRTA 0x0020
+#define CICR_GRTB 0x0040
+#define CICR_HPIT_SHIFT8
+#define CICR_HPIT_MASK 0x0300
+#define CICR_HP_SHIFT 24
+#define CICR_HP_MASK 0x3f00
+
+/* CICNR */
+#define CICNR_WCC1T_SHIFT 20
+#define CICNR_ZCC1T_SHIFT 28
+#define CICNR_YCC1T_SHIFT 12
+#define CICNR_XCC1T_SHIFT 4
+
+/* CRICR */
+#define CRICR_RTA1T_SHIFT 20
+#define CRICR_RTB1T_SHIFT 28
+
+/* Signal indicator */
+#define SIGNAL_MASK3
+#define SIGNAL_HIGH2
+#define SIGNAL_LOW 0
+
+struct qe_ic {
+ /* Control registers offset */
+ volatile u32 __iomem *regs;
+
+ /* The remapper for this QEIC */
+ struct irq_domain *irqhost;
+
+ /* The "linux" controller struct */
+ struct irq_chip hc_irq;
+
+ /* VIRQ numbers of QE high/low irqs */
+ unsigned int virq_high;
+ unsigned int virq_low;
+};
+
+/*
+ * QE interrupt controller internal structure
+ */
+struct qe_ic_info {
+ /* location of this source at the QIMR register. */
+ u32 mask;
+
+ /* Mask register offset */
+ u32 mask_reg;
+
+ /*
+* for grouped interrupts sources - the interrupt
+* code as appears at the group priority register
+*/
+ u8 pri_code;
+
+ /* Group priority register offset */
+ u32 pri_reg;
+};
+
+static DEFINE_RAW_SPINLOCK(qe_ic_lock);
+
+static struct qe_ic_info qe_ic_info[] = {
+ [1] = {
+ .mask = 0x8000,
+ .mask_reg = QEIC_CIMR,
+ .pri_code = 0,
+
lkml.org issues
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Re: [PATCH v5 00/14] ACPI platform MSI support and its example mbigen
Hi Hanjun: This patch set works fine on my Hisilicon D05 board. Feel free to add Tested-by: Majun 在 2016/12/22 13:35, Hanjun Guo 写道: > From: Hanjun Guo > > v4 -> v5: > - Add mbigen support back with tested on with Agustin's patchset, > and it's a good example of how ACPI platform MSI works > - rebased on top of lastest Linus tree (commit 52bce91 splice: > reinstate SIGPIPE/EPIPE handling) > > v3 -> v4: > - Drop mbi-gen patches to just submit platform msi support because > will rebase mbi-gen patches on top of Agustin's patchset, and > discusion > is going there. > - Add a patch to support device topology such as NC(named componant, > paltform device) > ->SMMU->ITS which suggested by Lorenzo; > - rebased on top of Lorenzo's v9 of ACPI IORT ARM SMMU support; > - rebased on top of 4.9-rc7 > > v2 -> v3: > - Drop RFC tag > - Rebase against v4.9-rc2 and Lorenzo's v6 of ACPI IORT ARM SMMU > support [1] > - Add 3 cleanup patches (patch 1, 2, 3) > - Drop arch_init call patch from last version > - Introduce a callback for platform device to set msi domain > - Introduce a new API to get paltform device's domain instead of > reusing the PCI one in previous version > - Add a patch to rework iort_node_get_id() > > [1]: http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1251993.html > > v1 -> v2: > - Fix the bug of if multi Interrupt() resoures in single _PRS, > we need to calculate all the irq numbers (I missed it in previous > version); > - Rebased on Marc's irq/irqchip-4.9 branch and Lorenzo's v5 > SMMU patches (also Robin's SMMu patches) > - Add patch irqchip: mbigen: promote mbigen init. > > With platform msi support landed in the kernel, and the introduction > of IORT for GICv3 ITS (PCI MSI) and SMMU, the framework for platform msi > is ready, this patch set add few patches to enable the ACPI platform > msi support. > > For platform device connecting to ITS on arm platform, we have IORT > table with the named componant node to describe the mappings of paltform > device and ITS, so we can retrieve the dev id and find its parent > irqdomain (ITS) from IORT table (simlar with the ACPI ITS support). > > The fisrt 3 patches are cleanups; > > Patch 4,5 are refactoring its_pmsi_prepare() for both DT and ACPI > then retrieve the dev id from iort; > > Patch 6,7 to create platform msi domain to ACPI case which scanned > the MADT table; > > Patch 8,9,10,11 to setup the msi domain for platform device based > on IORT table. > > Patch 12,13,14 convert dt based mbigen driver to support ACPI. > > Teasted on Hisilicon D03/D05. > > Happy holidays! > > Thanks > Hanjun > > Hanjun Guo (12): > ACPI: ARM64: IORT: minor cleanup for iort_match_node_callback() > irqchip: gic-v3-its: keep the head file include in alphabetic order > ACPI: ARM64: IORT: add missing comment for iort_dev_find_its_id() > irqchip: gicv3-its: platform-msi: refactor its_pmsi_prepare() > ACPI: platform-msi: retrieve dev id from IORT > irqchip: gicv3-its: platform-msi: refactor its_pmsi_init() to prepare > for ACPI > irqchip: gicv3-its: platform-msi: scan MADT to create platform msi > domain > ACPI: ARM64: IORT: rework iort_node_get_id() > ACPI: platform: setup MSI domain for ACPI based platform device > ACPI: ARM64: IORT: rework iort_node_get_id() for NC->SMMU->ITS case > msi: platform: make platform_msi_create_device_domain() ACPI aware > irqchip: mbigen: Add ACPI support > > Kefeng Wang (2): > irqchip: mbigen: drop module owner > irqchip: mbigen: introduce mbigen_of_create_domain() > > drivers/acpi/acpi_platform.c | 11 ++ > drivers/acpi/arm64/iort.c | 138 > -- > drivers/base/platform-msi.c | 3 +- > drivers/base/platform.c | 3 + > drivers/irqchip/irq-gic-v3-its-platform-msi.c | 106 +++- > drivers/irqchip/irq-gic-v3-its.c | 3 +- > drivers/irqchip/irq-mbigen.c | 109 > include/linux/acpi_iort.h | 11 ++ > include/linux/platform_device.h | 3 + > 9 files changed, 309 insertions(+), 78 deletions(-) >
[Patch V7 4/4] irqchip/qeic: remove PPCisms for QEIC
QEIC was supported on PowerPC, and dependent on PPC,
Now it is supported on other platforms, so remove PPCisms.
Signed-off-by: Zhao Qiang
---
Changes for v6:
- new added
Changes for v7:
- fix warning
drivers/irqchip/irq-qeic.c | 34 --
include/soc/fsl/qe/qe_ic.h | 12 ++--
2 files changed, 26 insertions(+), 20 deletions(-)
diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c
index 4f49d4b..957ea5b 100644
--- a/drivers/irqchip/irq-qeic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -18,7 +18,10 @@
#include
#include
#include
+#include
#include
+#include
+#include
#include
#include
#include
@@ -88,7 +91,7 @@
struct qe_ic {
/* Control registers offset */
- volatile u32 __iomem *regs;
+ u32 __iomem *regs;
/* The remapper for this QEIC */
struct irq_domain *irqhost;
@@ -264,15 +267,15 @@ static struct qe_ic_info qe_ic_info[] = {
},
};
-static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
+static inline u32 qe_ic_read(__be32 __iomem * base, unsigned int reg)
{
- return in_be32(base + (reg >> 2));
+ return ioread32be(base + (reg >> 2));
}
-static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int
reg,
+static inline void qe_ic_write(__be32 __iomem * base, unsigned int reg,
u32 value)
{
- out_be32(base + (reg >> 2), value);
+ iowrite32be(value, base + (reg >> 2));
}
static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
@@ -374,7 +377,7 @@ static const struct irq_domain_ops qe_ic_host_ops = {
.xlate = irq_domain_xlate_onetwocell,
};
-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+/* Return an interrupt vector or 0 if no interrupt is pending. */
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{
int irq;
@@ -385,12 +388,12 @@ unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
if (irq == 0)
- return NO_IRQ;
+ return 0;
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+/* Return an interrupt vector or 0 if no interrupt is pending. */
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
{
int irq;
@@ -401,7 +404,7 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
if (irq == 0)
- return NO_IRQ;
+ return 0;
return irq_linear_revmap(qe_ic->irqhost, irq);
}
@@ -447,7 +450,7 @@ static int __init qe_ic_init(unsigned int flags)
qe_ic->virq_high = irq_of_parse_and_map(node, 0);
qe_ic->virq_low = irq_of_parse_and_map(node, 1);
- if (qe_ic->virq_low == NO_IRQ) {
+ if (qe_ic->virq_low == 0) {
pr_err("Failed to map QE_IC low IRQ\n");
ret = -ENOMEM;
goto err_domain_remove;
@@ -479,7 +482,7 @@ static int __init qe_ic_init(unsigned int flags)
irq_set_handler_data(qe_ic->virq_low, qe_ic);
irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
- if (qe_ic->virq_high != NO_IRQ &&
+ if (qe_ic->virq_high != 0 &&
qe_ic->virq_high != qe_ic->virq_low) {
irq_set_handler_data(qe_ic->virq_high, qe_ic);
irq_set_chained_handler(qe_ic->virq_high,
@@ -500,7 +503,8 @@ err_put_node:
void qe_ic_set_highest_priority(unsigned int virq, int high)
{
struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
+ struct irq_data *irq_data = irq_get_irq_data(virq);
+ irq_hw_number_t src = WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
u32 temp = 0;
temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
@@ -518,7 +522,8 @@ void qe_ic_set_highest_priority(unsigned int virq, int high)
int qe_ic_set_priority(unsigned int virq, unsigned int priority)
{
struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
+ struct irq_data *irq_data = irq_get_irq_data(virq);
+ irq_hw_number_t src = WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
u32 temp;
if (priority > 8 || priority == 0)
@@ -548,7 +553,8 @@ int qe_ic_set_priority(unsigned int virq, unsigned int
priority)
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
{
struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
+ struct irq_data *irq_data = irq_get_irq_data(virq);
+ irq_hw_number_t src = WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
u32 temp, control_reg = QEIC_CICNR, shift = 0;
if (priority > 2 || priority == 0)
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index 6113699..863cfec 100644
--- a/in
Re: [PATCH v5 13/14] irqchip: mbigen: introduce mbigen_of_create_domain()
Hi hanjun：
在 2016/12/22 13:35, Hanjun Guo 写道:
> From: Kefeng Wang
>
> Introduce mbigen_of_create_domain() to consolidate OF related
> code and prepare for ACPI later, no funtional change.
>
> Signed-off-by: Kefeng Wang
> Signed-off-by: Hanjun Guo
> Cc: Marc Zyngier
> Cc: Thomas Gleixner
> Cc: Ma Jun
> ---
> drivers/irqchip/irq-mbigen.c | 42 +++---
> 1 file changed, 27 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
> index c01ab41..4e11da5 100644
> --- a/drivers/irqchip/irq-mbigen.c
> +++ b/drivers/irqchip/irq-mbigen.c
> @@ -236,27 +236,15 @@ static int mbigen_irq_domain_alloc(struct irq_domain
> *domain,
> .free = irq_domain_free_irqs_common,
> };
>
> -static int mbigen_device_probe(struct platform_device *pdev)
> +static int mbigen_of_create_domain(struct platform_device *pdev,
> +struct mbigen_device *mgn_chip)
> {
> - struct mbigen_device *mgn_chip;
> + struct device *parent;
> struct platform_device *child;
> struct irq_domain *domain;
> struct device_node *np;
> - struct device *parent;
> - struct resource *res;
> u32 num_pins;
>
> - mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
> - if (!mgn_chip)
> - return -ENOMEM;
> -
> - mgn_chip->pdev = pdev;
> -
> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - mgn_chip->base = devm_ioremap_resource(&pdev->dev, res);
> - if (IS_ERR(mgn_chip->base))
> - return PTR_ERR(mgn_chip->base);
> -
> for_each_child_of_node(pdev->dev.of_node, np) {
> if (!of_property_read_bool(np, "interrupt-controller"))
> continue;
> @@ -280,6 +268,30 @@ static int mbigen_device_probe(struct platform_device
> *pdev)
> return -ENOMEM;
> }
>
> + return 0;
> +}
> +
> +static int mbigen_device_probe(struct platform_device *pdev)
> +{
> + struct mbigen_device *mgn_chip;
> + struct resource *res;
> + int err;
> +
> + mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
> + if (!mgn_chip)
> + return -ENOMEM;
> +
> + mgn_chip->pdev = pdev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + mgn_chip->base = devm_ioremap(&pdev->dev, res->start,
> resource_size(res));
> + if (IS_ERR(mgn_chip->base))
> + return PTR_ERR(mgn_chip->base);
> +
> + err = mbigen_of_create_domain(pdev, mgn_chip);
> + if (err)
> + return err;
> +
> platform_set_drvdata(pdev, mgn_chip);
> return 0;
> }
>
Reviewed-by: MaJun
Re: [PATCH v5 12/14] irqchip: mbigen: drop module owner
Hi hanjun：
在 2016/12/22 13:35, Hanjun Guo 写道:
> From: Kefeng Wang
>
> Module owner will be set by driver core, so drop it.
>
> Signed-off-by: Kefeng Wang
> Signed-off-by: Hanjun Guo
> Cc: Marc Zyngier
> Cc: Thomas Gleixner
> Cc: Ma Jun
> ---
> drivers/irqchip/irq-mbigen.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
> index 03b79b0..c01ab41 100644
> --- a/drivers/irqchip/irq-mbigen.c
> +++ b/drivers/irqchip/irq-mbigen.c
> @@ -293,7 +293,6 @@ static int mbigen_device_probe(struct platform_device
> *pdev)
> static struct platform_driver mbigen_platform_driver = {
> .driver = {
> .name = "Hisilicon MBIGEN-V2",
> - .owner = THIS_MODULE,
> .of_match_table = mbigen_of_match,
> },
> .probe = mbigen_device_probe,
>
Reviewed-by: MaJun
Re: [PATCH v5 14/14] irqchip: mbigen: Add ACPI support
Hi hanjun：
在 2016/12/22 13:35, Hanjun Guo 写道:
> From: Hanjun Guo
>
> With the preparation of platform msi support and interrupt producer
> in DSDT, we can add mbigen ACPI support now.
>
> We are using _PRS methd to indicate number of irq pins instead
> of num_pins in DT to avoid _DSD usage in this case.
>
> For mbi-gen,
> Device(MBI0) {
> Name(_HID, "HISI0152")
> Name(_UID, Zero)
> Name(_CRS, ResourceTemplate() {
> Memory32Fixed(ReadWrite, 0xa008, 0x1)
> })
>
> Name (_PRS, ResourceTemplate() {
> Interrupt(ResourceProducer,...) {12,14,}
> })
> }
>
> For devices,
>
>Device(COM0) {
> Name(_HID, "ACPIIDxx")
> Name(_UID, Zero)
> Name(_CRS, ResourceTemplate() {
> Memory32Fixed(ReadWrite, 0xb003, 0x1)
>Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12}
> })
> }
>
> With the helpe of platform msi and interrupt producer, then devices
> will get the virq from mbi-gen's irqdomain.
>
> Signed-off-by: Hanjun Guo
> Cc: Marc Zyngier
> Cc: Thomas Gleixner
> Cc: Ma Jun
> ---
> drivers/irqchip/irq-mbigen.c | 70
> ++--
> 1 file changed, 67 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
> index 4e11da5..17d35fa 100644
> --- a/drivers/irqchip/irq-mbigen.c
> +++ b/drivers/irqchip/irq-mbigen.c
> @@ -16,6 +16,7 @@
> * along with this program. If not, see
Re: [PATCH] PCI: exynos: refactor exynos pcie driver
Hi Pankaj,
On 12/23/2016 07:56 PM, Pankaj Dubey wrote:
> From: Niyas Ahmed S T
>
> Currently Exynos PCIe driver is only supported for Exynos5440 SoC.
> This patch does refactoring of Exynos PCIe driver to extend support
> for other Exynos SoC.
>
> Following are the main changes done via this patch:
> 1) It adds separate structs for memory, clock resources.
> 2) It add exynos_pcie_ops struct which will allow us to support the
> differences in resources in different Exynos SoC.
It's nice to me for reusing this file.
but after considering too many times, i decided not to use this file.
I'm not sure what block base is..actually this pci-exynos.c is really black-box.
(No one maintains this file, even Samsung didn't care.)
Who is using this?
If Someone can share the information about exynos5440, i can refactor
everything.
Otherwise, there are two solution..
One is "adding the new pci-exynos.c" likes pci-exynos5433.c
Other is "refactor this file" under assuming the each register's usage.
I want to use the PHY generic Framework for EXYNOS PCIe.
If you or other guys really want to use the pci-exynos.c for other exynos,
I will rework with PHY generic framework. Then i will resend the my patches as
V2.
One more thing..Does anyone know what the usage of block base is?
Can i use that register as "syscon"?
Best Regards,
Jaehoon Chung
>
> No functional change intended.
>
> Signed-off-by: Niyas Ahmed S T
> Signed-off-by: Pankaj Dubey
> ---
> This patch set is prepared on top of Krzysztof's for-next and
> PCIe driver cleanup patch [1] by Jaehoon Chung.
>
> [1]: https://lkml.org/lkml/2016/12/19/44
>
>
> drivers/pci/host/pci-exynos.c | 346
> ++
> 1 file changed, 217 insertions(+), 129 deletions(-)
>
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index 33562cf..2dc54f7 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -17,6 +17,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -28,16 +29,6 @@
>
> #define to_exynos_pcie(x)container_of(x, struct exynos_pcie, pp)
>
> -struct exynos_pcie {
> - struct pcie_portpp;
> - void __iomem*elbi_base; /* DT 0th resource */
> - void __iomem*phy_base; /* DT 1st resource */
> - void __iomem*block_base;/* DT 2nd resource */
> - int reset_gpio;
> - struct clk *clk;
> - struct clk *bus_clk;
> -};
> -
> /* PCIe ELBI registers */
> #define PCIE_IRQ_PULSE 0x000
> #define IRQ_INTA_ASSERT BIT(0)
> @@ -102,6 +93,122 @@ struct exynos_pcie {
> #define PCIE_PHY_TRSV3_PD_TSVBIT(7)
> #define PCIE_PHY_TRSV3_LVCC 0x31c
>
> +struct exynos_pcie_mem_res {
> + void __iomem *elbi_base; /* DT 0th resource: PCIE CTRL */
> + void __iomem *phy_base; /* DT 1st resource: PHY CTRL */
> + void __iomem *block_base; /* DT 2nd resource: PHY ADDITIONAL CTRL */
> +};
> +
> +struct exynos_pcie_clk_res {
> + struct clk *clk;
> + struct clk *bus_clk;
> +};
> +
> +struct exynos_pcie {
> + struct pcie_portpp;
> + struct exynos_pcie_mem_res *mem_res;
> + struct exynos_pcie_clk_res *clk_res;
> + const struct exynos_pcie_ops*ops;
> + int reset_gpio;
> +};
> +
> +struct exynos_pcie_ops {
> + int (*get_mem_resources)(struct platform_device *pdev,
> + struct exynos_pcie *ep);
> + int (*get_clk_resources)(struct exynos_pcie *ep);
> + int (*init_clk_resources)(struct exynos_pcie *ep);
> + void (*deinit_clk_resources)(struct exynos_pcie *ep);
> +};
> +
> +static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
> + struct exynos_pcie *ep)
> +{
> + struct resource *res;
> + struct device *dev = ep->pp.dev;
> +
> + ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
> + if (!ep->mem_res)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + ep->mem_res->elbi_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(ep->mem_res->elbi_base))
> + return PTR_ERR(ep->mem_res->elbi_base);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(ep->mem_res->phy_base))
> + return PTR_ERR(ep->mem_res->phy_base);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> + ep->mem_res->block_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(ep->mem_res->block_base))
> + return PTR_ERR(ep->mem_res->block_base);
> +
> + return 0;
> +}
> +
> +static int exynos5440_pcie_get_clk_resources(struct exynos_pcie *ep)
> +{
> + struct dev
Re: [patch] mm, thp: always direct reclaim for MADV_HUGEPAGE even when deferred
On Fri 23-12-16 14:46:43, David Rientjes wrote: [...] > You want defrag=madvise to start doing background compaction for > everybody, which was never done before for existing users of > defrag=madvise? That might be possible, I don't really care, I just think > it's riskier because there are existing users of defrag=madvise who are > opting in to new behavior because of the kernel change. This patch > changes defrag=defer because it's the new option and people setting the > mode know what they are getting. But my primary argument is that if you tweak "defer" value behavior then you lose the only "stall free yet allow background compaction" option. That option is really important. You seem to think that it is the application which is under the control. And I am not all that surprised because you are under control of the whole userspace in your deployments. But there are others where the administrator is not under the control of what application asks for yet he is responsible for the overal "experience" if you will. Long stalls during the page faults are often seen as bugs and users might not really care whether the application writer really wanted THP or not... [...] > This is obviously fine for Kirill, and I have users who remap their .text > segment and do madvise(MADV_DONTNEED) because they really want hugepages > when they are exec'd, so I'd kindly ask you to consider the real-world use > cases that require background compaction to make hugepages available for > everybody but allow apps to opt-in to take the expense of compaction on > themselves rather than your own theory of what users want. I definitely _agree_ that this is a very important usecase! I am just trying to think long term and a more sophisticated background compaction is something that we definitely lack and _want_ longterm. There are more high order users than THP. I believe we really want to teach kcompactd to maintain configurable amount of highorder pages. If there is really a need for an immediate solution^Wworkaround then I think that tweaking the madvise option should be reasonably safe. Admins are really prepared for stalls because they are explicitly opting in for madvise behavior and they will get a background compaction on top. This is a new behavior but I do not see how it would be harmful. If an excessive compaction is a problem then THP can be reduced to madvise only vmas. But, I really _do_ care about having a stall free option which is not a complete disable of the background compaction for THP. diff --git a/mm/huge_memory.c b/mm/huge_memory.c index f3c2040edbb1..3679c47faef4 100644 --- a/mm/huge_memory.c +++ b/mm/huge_memory.c @@ -622,8 +622,8 @@ static inline gfp_t alloc_hugepage_direct_gfpmask(struct vm_area_struct *vma) bool vma_madvised = !!(vma->vm_flags & VM_HUGEPAGE); if (test_bit(TRANSPARENT_HUGEPAGE_DEFRAG_REQ_MADV_FLAG, - &transparent_hugepage_flags) && vma_madvised) - return GFP_TRANSHUGE; + &transparent_hugepage_flags)) + return (vma_madvise) ? GFP_TRANSHUGE : GFP_TRANSHUGE_LIGHT | __GFP_KSWAPD_RECLAIM; else if (test_bit(TRANSPARENT_HUGEPAGE_DEFRAG_KSWAPD_FLAG, &transparent_hugepage_flags)) return GFP_TRANSHUGE_LIGHT | __GFP_KSWAPD_RECLAIM; -- Michal Hocko SUSE Labs
Re: [PATCH] PCI: exynos: refactor exynos pcie driver
On 12/26/2016 06:02 PM, Jaehoon Chung wrote:
> Hi Pankaj,
>
> On 12/23/2016 07:56 PM, Pankaj Dubey wrote:
>> From: Niyas Ahmed S T
>>
>> Currently Exynos PCIe driver is only supported for Exynos5440 SoC.
>> This patch does refactoring of Exynos PCIe driver to extend support
>> for other Exynos SoC.
>>
>> Following are the main changes done via this patch:
>> 1) It adds separate structs for memory, clock resources.
>> 2) It add exynos_pcie_ops struct which will allow us to support the
>> differences in resources in different Exynos SoC.
>
> It's nice to me for reusing this file.
> but after considering too many times, i decided not to use this file.
>
> I'm not sure what block base is..actually this pci-exynos.c is really
> black-box.
> (No one maintains this file, even Samsung didn't care.)
> Who is using this?
> If Someone can share the information about exynos5440, i can refactor
> everything.
> Otherwise, there are two solution..
>
> One is "adding the new pci-exynos.c" likes pci-exynos5433.c
> Other is "refactor this file" under assuming the each register's usage.
>
> I want to use the PHY generic Framework for EXYNOS PCIe.
>
> If you or other guys really want to use the pci-exynos.c for other exynos,
> I will rework with PHY generic framework. Then i will resend the my patches
> as V2.
>
> One more thing..Does anyone know what the usage of block base is?
> Can i use that register as "syscon"?
One more..I sent the patches for RFC. Plz, check them. :)
https://lkml.org/lkml/2016/12/26/6
Best Regards,
Jaehoon Chung
>
> Best Regards,
> Jaehoon Chung
>
>>
>> No functional change intended.
>>
>> Signed-off-by: Niyas Ahmed S T
>> Signed-off-by: Pankaj Dubey
>> ---
>> This patch set is prepared on top of Krzysztof's for-next and
>> PCIe driver cleanup patch [1] by Jaehoon Chung.
>>
>> [1]: https://lkml.org/lkml/2016/12/19/44
>>
>>
>> drivers/pci/host/pci-exynos.c | 346
>> ++
>> 1 file changed, 217 insertions(+), 129 deletions(-)
>>
>> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
>> index 33562cf..2dc54f7 100644
>> --- a/drivers/pci/host/pci-exynos.c
>> +++ b/drivers/pci/host/pci-exynos.c
>> @@ -17,6 +17,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -28,16 +29,6 @@
>>
>> #define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp)
>>
>> -struct exynos_pcie {
>> -struct pcie_portpp;
>> -void __iomem*elbi_base; /* DT 0th resource */
>> -void __iomem*phy_base; /* DT 1st resource */
>> -void __iomem*block_base;/* DT 2nd resource */
>> -int reset_gpio;
>> -struct clk *clk;
>> -struct clk *bus_clk;
>> -};
>> -
>> /* PCIe ELBI registers */
>> #define PCIE_IRQ_PULSE 0x000
>> #define IRQ_INTA_ASSERT BIT(0)
>> @@ -102,6 +93,122 @@ struct exynos_pcie {
>> #define PCIE_PHY_TRSV3_PD_TSV BIT(7)
>> #define PCIE_PHY_TRSV3_LVCC 0x31c
>>
>> +struct exynos_pcie_mem_res {
>> +void __iomem *elbi_base; /* DT 0th resource: PCIE CTRL */
>> +void __iomem *phy_base; /* DT 1st resource: PHY CTRL */
>> +void __iomem *block_base; /* DT 2nd resource: PHY ADDITIONAL CTRL */
>> +};
>> +
>> +struct exynos_pcie_clk_res {
>> +struct clk *clk;
>> +struct clk *bus_clk;
>> +};
>> +
>> +struct exynos_pcie {
>> +struct pcie_portpp;
>> +struct exynos_pcie_mem_res *mem_res;
>> +struct exynos_pcie_clk_res *clk_res;
>> +const struct exynos_pcie_ops*ops;
>> +int reset_gpio;
>> +};
>> +
>> +struct exynos_pcie_ops {
>> +int (*get_mem_resources)(struct platform_device *pdev,
>> +struct exynos_pcie *ep);
>> +int (*get_clk_resources)(struct exynos_pcie *ep);
>> +int (*init_clk_resources)(struct exynos_pcie *ep);
>> +void (*deinit_clk_resources)(struct exynos_pcie *ep);
>> +};
>> +
>> +static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
>> +struct exynos_pcie *ep)
>> +{
>> +struct resource *res;
>> +struct device *dev = ep->pp.dev;
>> +
>> +ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
>> +if (!ep->mem_res)
>> +return -ENOMEM;
>> +
>> +res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +ep->mem_res->elbi_base = devm_ioremap_resource(dev, res);
>> +if (IS_ERR(ep->mem_res->elbi_base))
>> +return PTR_ERR(ep->mem_res->elbi_base);
>> +
>> +res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> +ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
>> +if (IS_ERR(ep->mem_res->phy_base))
>> +return PTR_ERR(ep->mem_res->phy_base);
>> +
>> +res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>> +
Re: Linux 4.10-rc1
On 2016/12/26 16:38, Hanjun Guo wrote:
> Hi Linus,
>
> On 2016/12/26 8:41, Linus Torvalds wrote:
>> It's Christmas Day, and it's two weeks since the merge window opened.
>> Thus, the merge window is now closed.
>>
>> I did a few final pulls today, but I also rejected a couple of pulls
>> that came in late in the window and looked dodgy. You know who you
>> are.
>>
>> On the whole, this wasn't all that big a release - nothing like 4.9.
>> Although it wasn't tiny either. I think 4.7 was smaller. 4.8 might
>> have been too. It's xmas day, and right now I can't be arsed to
>> actually do the statistics I'd normally do.
>>
>> Everything looks pretty normal, although we had an unusual amount of
>> tree-wide final cleanups in the last days of the merge window. But the
>> general statistics look fairly common: a bit over half is drivers,
>> maybe slightly less arch updates than normal, and a fair amount of
>> documentation updates due to the sphinx conversion. And then the usual
>> misc noise all over, although the perf tooling updates do stand out.
>>
>> The shortlog is much too big, as it always is during the merge window,
>> so as usual you just get the merge-log.
>
> Kejian and I got massive compile error when cross-compile the kernel for
> ARM64, such as
>
> ./include/asm-generic/atomic-long.h:23: Error: unknown mnemonic `typedef' --
> `typedef atomic64_t atomic_long_t'
> ./include/asm-generic/atomic-long.h:44: Error: unknown mnemonic `static' --
> `static inline long atomic_long_read(const
> atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
> ./include/asm-generic/atomic-long.h:44: Error: unknown mnemonic `return' --
> `return (long)READ_ONCE((v)->counter)'
> ./include/asm-generic/atomic-long.h:44: Error: junk at end of line, first
> unrecognized character is `}'
> ./include/asm-generic/atomic-long.h:45: Error: unknown mnemonic `static' --
> `static inline long atomic_long_read_acquire(const
> atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
> ./include/asm-generic/atomic-long.h:45: Error: unknown mnemonic `return' --
> `return (long)smp_load_acquire(&(v)->counter)'
> ./include/asm-generic/atomic-long.h:45: Error: junk at end of line, first
> unrecognized character is `}'
> ./include/asm-generic/atomic-long.h:56: Error: unknown mnemonic `static' --
> `static inline void atomic_long_set(atomic_long_t*l,long
> i){atomic64_t*v=(atomic64_t*)l'
> ./include/asm-generic/atomic-long.h:56: Error: unknown mnemonic `write_once'
> -- `write_once(((v)->counter), (i))'
> ./include/asm-generic/atomic-long.h:56: Error: junk at end of line, first
> unrecognized character is `}'
> ./include/asm-generic/atomic-long.h:57: Error: unknown mnemonic `static' --
> `static inline void atomic_long_set_release(atomic_long_t*l,long
> i){atomic64_t*v=(atomic64_t*)l'
> ./include/asm-generic/atomic-long.h:57: Error: unknown mnemonic
> `smp_store_release' -- `smp_store_release(&(v)->counter, (i))'
> ./include/asm-generic/atomic-long.h:57: Error: junk at end of line, first
> unrecognized character is `}'
> ./include/asm-generic/atomic-long.h:69: Error: unknown mnemonic `static' --
> `static inline long atomic_long_add_return(long
> i,atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
> ./include/asm-generic/atomic-long.h:69: Error: unknown mnemonic `return' --
> `return (long)atomic64_add_return(i,v)'
> ./include/asm-generic/atomic-long.h:69: Error: junk at end of line, first
> unrecognized character is `}'
> ./include/asm-generic/atomic-long.h:70: Error: unknown mnemonic `static' --
> `static inline long atomic_long_add_return_relaxed(long
> i,atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
> ./include/asm-generic/atomic-long.h:70: Error: unknown mnemonic `return' --
> `return (long)atomic64_add_return_relaxed(i,v)'
> ./include/asm-generic/atomic-long.h:70: Error: junk at end of line, first
> unrecognized character is `}'
> ./include/asm-generic/atomic-long.h:71: Error: unknown mnemonic `static' --
> `static inline long atomic_long_add_return_acquire(long
> i,atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
> ./include/asm-generic/atomic-long.h:71: Error: unknown mnemonic `return' --
> `return (long)atomic64_add_return_acquire(i,v)'
> ./include/asm-generic/atomic-long.h:71: Error: junk at end of line, first
> unrecognized character is `}'
> ./include/asm-generic/atomic-long.h:72: Error: unknown mnemonic `static' --
> `static inline long atomic_long_add_return_release(long
> i,atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
> ./include/asm-generic/atomic-long.h:72: Error: unknown mnemonic `return' --
> `return (long)atomic64_add_return_release(i,v)'
> ./include/asm-generic/atomic-long.h:72: Error: junk at end of line, first
> unrecognized character is `}'
> ./include/asm-generic/atomic-long.h:73: Error: unknown mnemonic `static' --
> `static inline long atomic_long_sub_return(long
> i,atomic_long_t*l){atomic64_t*v=(atomic64_t*)l'
> ./include/asm-generic/atomic-long.h:73: Error: unknown mnemonic `return' --
> `return (l
Re: [HMM v14 05/16] mm/ZONE_DEVICE/unaddressable: add support for un-addressable device memory
On 12/09/2016 02:07 AM, Jerome Glisse wrote: >> On 12/08/2016 08:39 AM, Jerome Glisse wrote: > >> On 12/08/2016 08:39 AM, Jérôme Glisse wrote: >>> > >>> > > Architecture that wish to support un-addressable device >>> > >>> > > memory should >>> > >>> > > make >>> > >>> > > sure to never populate the kernel linar mapping for the >>> > >>> > > physical >>> > >>> > > range. > > >> > > > >> > Does the platform somehow provide a range of physical addresses > > >> > for this > > >> > unaddressable area? How do we know no memory will be hot-added in > > >> > a > > >> > range we're using for unaddressable device memory, for instance? >>> > > That's what one of the big issue. No platform does not reserve any >>> > > range so >>> > > there is a possibility that some memory get hotpluged and assign this >>> > > range. >>> > > >>> > > I pushed the range decision to higher level (ie it is the device driver >>> > > that >>> > > pick one) so right now for device driver using HMM (NVidia close driver >>> > > as >>> > > we don't have nouveau ready for that yet) it goes from the highest >>> > > physical >>> > > address and scan down until finding an empty range big enough. >> > >> > I don't think you should be stealing physical address space for things >> > that don't and can't have physical addresses. Delegating this to >> > individual device drivers and hoping that they all get it right seems >> > like a recipe for disaster. > Well i expected device driver to use hmm_devmem_add() which does not take > physical address but use the above logic to pick one. > >> > >> > Maybe worth adding to the changelog: >> > >> >This feature potentially breaks memory hotplug unless every >> >driver using it magically predicts the future addresses of >> >where memory will be hotplugged. > I will add debug printk to memory hotplug in case it fails because of some > un-addressable resource. If you really dislike memory hotplug being broken > then i can go down the way of allowing to hotplug memory above the max > physical memory limit. This require more changes but i believe this is > doable for some of the memory model (sparsemem and sparsemem extreme). Did not get that. Hotplug memory request will come within the max physical memory limit as they are real RAM. The address range also would have been specified. How it can be added beyond the physical limit irrespective of which we memory model we use.
Re: Linux 4.10-rc1
On Mon, Dec 26, 2016 at 04:38:13PM +0800, Hanjun Guo wrote: > ./include/asm-generic/atomic-long.h:23: Error: unknown mnemonic `typedef' -- > `typedef atomic64_t atomic_long_t' *blink* OK, I see what has happened here - it's "arm64: Factor out PAN enabling/disabling into separate uaccess_* macros" that went in during this window, adding an include of asm/uaccess.h into several assembler files. AFAICS, the easiest way to deal with that is to separate for-asm parts of uaccess.h into a new header and use _that_ from *.S, as in (completely untested) diff below. Seeing that there's basically no overlap between the __ASSEMBLY__ and normal parts of arm64 uaccess.h, that would seem to be a fairly obvious solution... Objections? diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h new file mode 100644 index ..df411f3e083c --- /dev/null +++ b/arch/arm64/include/asm/asm-uaccess.h @@ -0,0 +1,65 @@ +#ifndef __ASM_ASM_UACCESS_H +#define __ASM_ASM_UACCESS_H + +#include +#include +#include +#include + +/* + * User access enabling/disabling macros. + */ +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + .macro __uaccess_ttbr0_disable, tmp1 + mrs \tmp1, ttbr1_el1// swapper_pg_dir + add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir + msr ttbr0_el1, \tmp1// set reserved TTBR0_EL1 + isb + .endm + + .macro __uaccess_ttbr0_enable, tmp1 + get_thread_info \tmp1 + ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 + msr ttbr0_el1, \tmp1// set the non-PAN TTBR0_EL1 + isb + .endm + + .macro uaccess_ttbr0_disable, tmp1 +alternative_if_not ARM64_HAS_PAN + __uaccess_ttbr0_disable \tmp1 +alternative_else_nop_endif + .endm + + .macro uaccess_ttbr0_enable, tmp1, tmp2 +alternative_if_not ARM64_HAS_PAN + save_and_disable_irq \tmp2 // avoid preemption + __uaccess_ttbr0_enable \tmp1 + restore_irq \tmp2 +alternative_else_nop_endif + .endm +#else + .macro uaccess_ttbr0_disable, tmp1 + .endm + + .macro uaccess_ttbr0_enable, tmp1, tmp2 + .endm +#endif + +/* + * These macros are no-ops when UAO is present. + */ + .macro uaccess_disable_not_uao, tmp1 + uaccess_ttbr0_disable \tmp1 +alternative_if ARM64_ALT_PAN_NOT_UAO + SET_PSTATE_PAN(1) +alternative_else_nop_endif + .endm + + .macro uaccess_enable_not_uao, tmp1, tmp2 + uaccess_ttbr0_enable \tmp1, \tmp2 +alternative_if ARM64_ALT_PAN_NOT_UAO + SET_PSTATE_PAN(0) +alternative_else_nop_endif + .endm + +#endif diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index d26750ca6e06..46da3ea638bb 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -22,8 +22,6 @@ #include #include -#ifndef __ASSEMBLY__ - /* * User space memory access functions */ @@ -424,66 +422,4 @@ extern long strncpy_from_user(char *dest, const char __user *src, long count); extern __must_check long strlen_user(const char __user *str); extern __must_check long strnlen_user(const char __user *str, long n); -#else /* __ASSEMBLY__ */ - -#include - -/* - * User access enabling/disabling macros. - */ -#ifdef CONFIG_ARM64_SW_TTBR0_PAN - .macro __uaccess_ttbr0_disable, tmp1 - mrs \tmp1, ttbr1_el1// swapper_pg_dir - add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir - msr ttbr0_el1, \tmp1// set reserved TTBR0_EL1 - isb - .endm - - .macro __uaccess_ttbr0_enable, tmp1 - get_thread_info \tmp1 - ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 - msr ttbr0_el1, \tmp1// set the non-PAN TTBR0_EL1 - isb - .endm - - .macro uaccess_ttbr0_disable, tmp1 -alternative_if_not ARM64_HAS_PAN - __uaccess_ttbr0_disable \tmp1 -alternative_else_nop_endif - .endm - - .macro uaccess_ttbr0_enable, tmp1, tmp2 -alternative_if_not ARM64_HAS_PAN - save_and_disable_irq \tmp2 // avoid preemption - __uaccess_ttbr0_enable \tmp1 - restore_irq \tmp2 -alternative_else_nop_endif - .endm -#else - .macro uaccess_ttbr0_disable, tmp1 - .endm - - .macro uaccess_ttbr0_enable, tmp1, tmp2 - .endm -#endif - -/* - * These macros are no-ops when UAO is present. - */ - .macro uaccess_disable_not_uao, tmp1 - uaccess_ttbr0_disable \tmp1 -alternative_if ARM64_ALT_PAN_NOT_UAO - SET_PSTATE_PAN(1) -alternative_else_nop_endif - .endm - - .macro uaccess_enable_not_uao, tmp1, tmp2 - uaccess_ttbr0_enable \tmp1, \tmp2 -alternative_if ARM64_ALT_PAN_NOT_UAO - SET_PSTATE_PAN(0) -alternative_else_nop_endif - .endm - -#endif /* __ASSEMBLY__ */ -
Re: Linux 4.10-rc1
On Mon, Dec 26, 2016 at 05:05:37PM +0800, Kefeng Wang wrote: > It looks like we need revert the changes from assembly files. Better yet, split the damn thing in two and include the asm-only part. > diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S > diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S Missed those two... OK, how about this? arm64: don't pull uaccess.h into *.S Split asm-only parts of arm64 uaccess.h into a new header and use that from *.S. Signed-off-by: Al Viro diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h new file mode 100644 index ..df411f3e083c --- /dev/null +++ b/arch/arm64/include/asm/asm-uaccess.h @@ -0,0 +1,65 @@ +#ifndef __ASM_ASM_UACCESS_H +#define __ASM_ASM_UACCESS_H + +#include +#include +#include +#include + +/* + * User access enabling/disabling macros. + */ +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + .macro __uaccess_ttbr0_disable, tmp1 + mrs \tmp1, ttbr1_el1// swapper_pg_dir + add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir + msr ttbr0_el1, \tmp1// set reserved TTBR0_EL1 + isb + .endm + + .macro __uaccess_ttbr0_enable, tmp1 + get_thread_info \tmp1 + ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 + msr ttbr0_el1, \tmp1// set the non-PAN TTBR0_EL1 + isb + .endm + + .macro uaccess_ttbr0_disable, tmp1 +alternative_if_not ARM64_HAS_PAN + __uaccess_ttbr0_disable \tmp1 +alternative_else_nop_endif + .endm + + .macro uaccess_ttbr0_enable, tmp1, tmp2 +alternative_if_not ARM64_HAS_PAN + save_and_disable_irq \tmp2 // avoid preemption + __uaccess_ttbr0_enable \tmp1 + restore_irq \tmp2 +alternative_else_nop_endif + .endm +#else + .macro uaccess_ttbr0_disable, tmp1 + .endm + + .macro uaccess_ttbr0_enable, tmp1, tmp2 + .endm +#endif + +/* + * These macros are no-ops when UAO is present. + */ + .macro uaccess_disable_not_uao, tmp1 + uaccess_ttbr0_disable \tmp1 +alternative_if ARM64_ALT_PAN_NOT_UAO + SET_PSTATE_PAN(1) +alternative_else_nop_endif + .endm + + .macro uaccess_enable_not_uao, tmp1, tmp2 + uaccess_ttbr0_enable \tmp1, \tmp2 +alternative_if ARM64_ALT_PAN_NOT_UAO + SET_PSTATE_PAN(0) +alternative_else_nop_endif + .endm + +#endif diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index d26750ca6e06..46da3ea638bb 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -22,8 +22,6 @@ #include #include -#ifndef __ASSEMBLY__ - /* * User space memory access functions */ @@ -424,66 +422,4 @@ extern long strncpy_from_user(char *dest, const char __user *src, long count); extern __must_check long strlen_user(const char __user *str); extern __must_check long strnlen_user(const char __user *str, long n); -#else /* __ASSEMBLY__ */ - -#include - -/* - * User access enabling/disabling macros. - */ -#ifdef CONFIG_ARM64_SW_TTBR0_PAN - .macro __uaccess_ttbr0_disable, tmp1 - mrs \tmp1, ttbr1_el1// swapper_pg_dir - add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir - msr ttbr0_el1, \tmp1// set reserved TTBR0_EL1 - isb - .endm - - .macro __uaccess_ttbr0_enable, tmp1 - get_thread_info \tmp1 - ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 - msr ttbr0_el1, \tmp1// set the non-PAN TTBR0_EL1 - isb - .endm - - .macro uaccess_ttbr0_disable, tmp1 -alternative_if_not ARM64_HAS_PAN - __uaccess_ttbr0_disable \tmp1 -alternative_else_nop_endif - .endm - - .macro uaccess_ttbr0_enable, tmp1, tmp2 -alternative_if_not ARM64_HAS_PAN - save_and_disable_irq \tmp2 // avoid preemption - __uaccess_ttbr0_enable \tmp1 - restore_irq \tmp2 -alternative_else_nop_endif - .endm -#else - .macro uaccess_ttbr0_disable, tmp1 - .endm - - .macro uaccess_ttbr0_enable, tmp1, tmp2 - .endm -#endif - -/* - * These macros are no-ops when UAO is present. - */ - .macro uaccess_disable_not_uao, tmp1 - uaccess_ttbr0_disable \tmp1 -alternative_if ARM64_ALT_PAN_NOT_UAO - SET_PSTATE_PAN(1) -alternative_else_nop_endif - .endm - - .macro uaccess_enable_not_uao, tmp1, tmp2 - uaccess_ttbr0_enable \tmp1, \tmp2 -alternative_if ARM64_ALT_PAN_NOT_UAO - SET_PSTATE_PAN(0) -alternative_else_nop_endif - .endm - -#endif /* __ASSEMBLY__ */ - #endif /* __ASM_UACCESS_H */ diff --git a/arch/arm64/lib/clear_user.S b/arch/arm64/lib/clear_user.S index add4a1334085..e88fb99c1561 100644 --- a/arch/arm64/lib/clear_user.S +++ b/arch/arm64/lib/clear_user.S @@ -17,7
[PATCH] ceph: cleanup ACCESS_ONCE -> READ_ONCE
This removes the uses of ACCESS_ONCE in favor of READ_ONCE
Signed-off-by: Seraphime Kirkovski
---
fs/ceph/addr.c | 4 ++--
fs/ceph/caps.c | 2 +-
fs/ceph/dir.c| 2 +-
fs/ceph/inode.c | 2 +-
fs/ceph/mds_client.c | 10 +-
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/fs/ceph/addr.c b/fs/ceph/addr.c
index 9cd0c0e..e61bc3f 100644
--- a/fs/ceph/addr.c
+++ b/fs/ceph/addr.c
@@ -771,7 +771,7 @@ static int ceph_writepages_start(struct address_space
*mapping,
wbc->sync_mode == WB_SYNC_NONE ? "NONE" :
(wbc->sync_mode == WB_SYNC_ALL ? "ALL" : "HOLD"));
- if (ACCESS_ONCE(fsc->mount_state) == CEPH_MOUNT_SHUTDOWN) {
+ if (READ_ONCE(fsc->mount_state) == CEPH_MOUNT_SHUTDOWN) {
if (ci->i_wrbuffer_ref > 0) {
pr_warn_ratelimited(
"writepage_start %p %lld forced umount\n",
@@ -1194,7 +1194,7 @@ static int ceph_update_writeable_page(struct file *file,
int r;
struct ceph_snap_context *snapc, *oldest;
- if (ACCESS_ONCE(fsc->mount_state) == CEPH_MOUNT_SHUTDOWN) {
+ if (READ_ONCE(fsc->mount_state) == CEPH_MOUNT_SHUTDOWN) {
dout(" page %p forced umount\n", page);
unlock_page(page);
return -EIO;
diff --git a/fs/ceph/caps.c b/fs/ceph/caps.c
index baea866..193ba82 100644
--- a/fs/ceph/caps.c
+++ b/fs/ceph/caps.c
@@ -2477,7 +2477,7 @@ static int try_get_cap_refs(struct ceph_inode_info *ci,
int need, int want,
if (ci->i_ceph_flags & CEPH_I_CAP_DROPPED) {
int mds_wanted;
- if (ACCESS_ONCE(mdsc->fsc->mount_state) ==
+ if (READ_ONCE(mdsc->fsc->mount_state) ==
CEPH_MOUNT_SHUTDOWN) {
dout("get_cap_refs %p forced umount\n", inode);
*err = -EIO;
diff --git a/fs/ceph/dir.c b/fs/ceph/dir.c
index d7a9369..cd99b26 100644
--- a/fs/ceph/dir.c
+++ b/fs/ceph/dir.c
@@ -1194,7 +1194,7 @@ static int ceph_d_revalidate(struct dentry *dentry,
unsigned int flags)
struct inode *dir;
if (flags & LOOKUP_RCU) {
- parent = ACCESS_ONCE(dentry->d_parent);
+ parent = READ_ONCE(dentry->d_parent);
dir = d_inode_rcu(parent);
if (!dir)
return -ECHILD;
diff --git a/fs/ceph/inode.c b/fs/ceph/inode.c
index 398e532..1476f54 100644
--- a/fs/ceph/inode.c
+++ b/fs/ceph/inode.c
@@ -1719,7 +1719,7 @@ static void ceph_invalidate_work(struct work_struct *work)
mutex_lock(&ci->i_truncate_mutex);
- if (ACCESS_ONCE(fsc->mount_state) == CEPH_MOUNT_SHUTDOWN) {
+ if (READ_ONCE(fsc->mount_state) == CEPH_MOUNT_SHUTDOWN) {
pr_warn_ratelimited("invalidate_pages %p %lld forced umount\n",
inode, ceph_ino(inode));
mapping_set_error(inode->i_mapping, -EIO);
diff --git a/fs/ceph/mds_client.c b/fs/ceph/mds_client.c
index 4f49253..df90794 100644
--- a/fs/ceph/mds_client.c
+++ b/fs/ceph/mds_client.c
@@ -1145,7 +1145,7 @@ static int remove_session_caps_cb(struct inode *inode,
struct ceph_cap *cap,
ci->i_ceph_flags |= CEPH_I_CAP_DROPPED;
if (ci->i_wrbuffer_ref > 0 &&
- ACCESS_ONCE(fsc->mount_state) == CEPH_MOUNT_SHUTDOWN)
+ READ_ONCE(fsc->mount_state) == CEPH_MOUNT_SHUTDOWN)
invalidate = true;
while (!list_empty(&ci->i_cap_flush_list)) {
@@ -2095,12 +2095,12 @@ static int __do_request(struct ceph_mds_client *mdsc,
err = -EIO;
goto finish;
}
- if (ACCESS_ONCE(mdsc->fsc->mount_state) == CEPH_MOUNT_SHUTDOWN) {
+ if (READ_ONCE(mdsc->fsc->mount_state) == CEPH_MOUNT_SHUTDOWN) {
dout("do_request forced umount\n");
err = -EIO;
goto finish;
}
- if (ACCESS_ONCE(mdsc->fsc->mount_state) == CEPH_MOUNT_MOUNTING) {
+ if (READ_ONCE(mdsc->fsc->mount_state) == CEPH_MOUNT_MOUNTING) {
if (mdsc->mdsmap_err) {
err = mdsc->mdsmap_err;
dout("do_request mdsmap err %d\n", err);
@@ -3550,7 +3550,7 @@ void ceph_mdsc_sync(struct ceph_mds_client *mdsc)
{
u64 want_tid, want_flush;
- if (ACCESS_ONCE(mdsc->fsc->mount_state) == CEPH_MOUNT_SHUTDOWN)
+ if (READ_ONCE(mdsc->fsc->mount_state) == CEPH_MOUNT_SHUTDOWN)
return;
dout("sync\n");
@@ -3581,7 +3581,7 @@ void ceph_mdsc_sync(struct ceph_mds_client *mdsc)
*/
static bool done_closing_sessions(struct ceph_mds_client *mdsc, int skipped)
{
- if (ACCESS_ONCE(mdsc->fsc->mount_state) == CEPH_MOUNT_SHUTDOWN)
+ if (READ_ONCE(mdsc->fsc->mount_state) == CEPH_MOUNT_SHUTDOWN)
return true;
return atomic_rea
Re: [PATCH v5 00/14] ACPI platform MSI support and its example mbigen
Hi: 在 2016/12/26 16:57, majun (Euler7) 写道: > Hi Hanjun: > This patch set works fine on my Hisilicon D05 board. > Feel free to add Based on the Patch 1/3, 2/3 of [PATCH V9 0/3] irqchip: qcom: Add IRQ combiner driver from Agustin Vega-Frias https://lwn.net/Articles/709222/ > Tested-by: Majun > > 在 2016/12/22 13:35, Hanjun Guo 写道: >> From: Hanjun Guo >> >> v4 -> v5: >> - Add mbigen support back with tested on with Agustin's patchset, >>and it's a good example of how ACPI platform MSI works >> - rebased on top of lastest Linus tree (commit 52bce91 splice: >> reinstate SIGPIPE/EPIPE handling) >> >> v3 -> v4: >> - Drop mbi-gen patches to just submit platform msi support because >> will rebase mbi-gen patches on top of Agustin's patchset, and >> discusion >> is going there. >> - Add a patch to support device topology such as NC(named componant, >> paltform device) >> ->SMMU->ITS which suggested by Lorenzo; >> - rebased on top of Lorenzo's v9 of ACPI IORT ARM SMMU support; >> - rebased on top of 4.9-rc7 >> >> v2 -> v3: >> - Drop RFC tag >> - Rebase against v4.9-rc2 and Lorenzo's v6 of ACPI IORT ARM SMMU >> support [1] >> - Add 3 cleanup patches (patch 1, 2, 3) >> - Drop arch_init call patch from last version >> - Introduce a callback for platform device to set msi domain >> - Introduce a new API to get paltform device's domain instead of >> reusing the PCI one in previous version >> - Add a patch to rework iort_node_get_id() >> >> [1]: http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1251993.html >> >> v1 -> v2: >> - Fix the bug of if multi Interrupt() resoures in single _PRS, >> we need to calculate all the irq numbers (I missed it in previous >> version); >> - Rebased on Marc's irq/irqchip-4.9 branch and Lorenzo's v5 >> SMMU patches (also Robin's SMMu patches) >> - Add patch irqchip: mbigen: promote mbigen init. >> >> With platform msi support landed in the kernel, and the introduction >> of IORT for GICv3 ITS (PCI MSI) and SMMU, the framework for platform msi >> is ready, this patch set add few patches to enable the ACPI platform >> msi support. >> >> For platform device connecting to ITS on arm platform, we have IORT >> table with the named componant node to describe the mappings of paltform >> device and ITS, so we can retrieve the dev id and find its parent >> irqdomain (ITS) from IORT table (simlar with the ACPI ITS support). >> >> The fisrt 3 patches are cleanups; >> >> Patch 4,5 are refactoring its_pmsi_prepare() for both DT and ACPI >> then retrieve the dev id from iort; >> >> Patch 6,7 to create platform msi domain to ACPI case which scanned >> the MADT table; >> >> Patch 8,9,10,11 to setup the msi domain for platform device based >> on IORT table. >> >> Patch 12,13,14 convert dt based mbigen driver to support ACPI. >> >> Teasted on Hisilicon D03/D05. >> >> Happy holidays! >> >> Thanks >> Hanjun >> >> Hanjun Guo (12): >> ACPI: ARM64: IORT: minor cleanup for iort_match_node_callback() >> irqchip: gic-v3-its: keep the head file include in alphabetic order >> ACPI: ARM64: IORT: add missing comment for iort_dev_find_its_id() >> irqchip: gicv3-its: platform-msi: refactor its_pmsi_prepare() >> ACPI: platform-msi: retrieve dev id from IORT >> irqchip: gicv3-its: platform-msi: refactor its_pmsi_init() to prepare >> for ACPI >> irqchip: gicv3-its: platform-msi: scan MADT to create platform msi >> domain >> ACPI: ARM64: IORT: rework iort_node_get_id() >> ACPI: platform: setup MSI domain for ACPI based platform device >> ACPI: ARM64: IORT: rework iort_node_get_id() for NC->SMMU->ITS case >> msi: platform: make platform_msi_create_device_domain() ACPI aware >> irqchip: mbigen: Add ACPI support >> >> Kefeng Wang (2): >> irqchip: mbigen: drop module owner >> irqchip: mbigen: introduce mbigen_of_create_domain() >> >> drivers/acpi/acpi_platform.c | 11 ++ >> drivers/acpi/arm64/iort.c | 138 >> -- >> drivers/base/platform-msi.c | 3 +- >> drivers/base/platform.c | 3 + >> drivers/irqchip/irq-gic-v3-its-platform-msi.c | 106 +++- >> drivers/irqchip/irq-gic-v3-its.c | 3 +- >> drivers/irqchip/irq-mbigen.c | 109 >> include/linux/acpi_iort.h | 11 ++ >> include/linux/platform_device.h | 3 + >> 9 files changed, 309 insertions(+), 78 deletions(-) >> > > > . >
coresight: Problem caused by resetting enable_sink
Hi Mathieu,
I meet problems caused by your commit d52c9750f150 ('coresight:
reset "enable_sink" flag when need be'). Not only the one I
posted in the previous patch.
My use case is a simple 'perf record -e cs_etm// ls'. It works
properly before this commit, and failed when allocating aux buffer
after your commit. I can't fully understand your code, but the
problem I meet seems caused by inappropriately reseting sink.
My device is connected like this (use two etfs):
Core0--+
Core1--+-- funnel0 --> etf0
Core2--|
Core3--+
Core0--+
Core1--+-- funnel1 --> etf1
Core2--|
Core3--+
Before running perf, two etfs are activated using sysfs
enable_sink interface.
During etm_setup_aux, coresight_get_enabled_sink() finds
etf0 for core0, and automatically deactivates it.
For core1, coresight_get_enabled_sink() returns etf1.
However, etf1 is not on the link of core1, so following
coresight_build_path() fails.
I guess your commit is based on the assumption that all
sinks are in the patch for each cores. Like this:
Core0--+
Core1--+-- funnel0 --> etf0 ++
Core2--| |+--- etr
Core3--+ ||
+ replicator +
Core0--+ ||
Core1--+-- funnel1 --> etf1 +++--- etb
Core2--|
Core3--+
But it is not true, at least for some hisilicon board.
I have to revert your patch to make CoreSight on my board
work. Please reconsider this patch, or please give some
suggestion if you think I misunderstood your patch.
Thank you.
[RESEND 2/2] arm64: dts: Add dts files for Hisilicon Hi3660 SoC
Add initial dtsi file to support Hisilicon Hi3660 SoC with
support of Octal core CPUs in two clusters(4 * A53 & 4 * A73).
Also add dts file to support HiKey960 development board which
based on Hi3660 SoC.
The output console is earlycon "earlycon=pl011,0xfdf05000".
And the con_init uart5 with a fixed clock, which already
configured at bootloader.
When clock is available, the uart5 will be modified.
Tested on HiKey960 Board.
Signed-off-by: Chen Feng
---
arch/arm64/boot/dts/hisilicon/Makefile| 1 +
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 34 +
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 156 ++
3 files changed, 191 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile
b/arch/arm64/boot/dts/hisilicon/Makefile
index d5f43a0..b633b5d 100644
--- a/arch/arm64/boot/dts/hisilicon/Makefile
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -1,4 +1,5 @@
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
+dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
new file mode 100644
index 000..3d7aead
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -0,0 +1,34 @@
+/*
+ * dts file for Hisilicon HiKey960 Development Board
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "hi3660.dtsi"
+
+/ {
+ model = "HiKey960";
+ compatible = "hisilicon,hi3660";
+
+ aliases {
+ serial5 = &uart5; /* console UART */
+ };
+
+ chosen {
+ stdout-path = "serial5:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0040 0x0 0xBFE0>;
+ };
+
+ soc {
+ uart5: uart@fdf05000 {
+ status = "ok";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
new file mode 100644
index 000..7f9805c
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -0,0 +1,156 @@
+/*
+ * dts file for Hisilicon Hi3660 SoC
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ */
+
+#include
+
+/ {
+ compatible = "hisilicon,hi3660";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+
+ cpu4: cpu@100 {
+
[RESEND 1/2] document: dt: add binding for Hi3660 SoC
Add binding for hisilicon Hi3660 SoC and HiKey960 Board. Signed-off-by: Chen Feng --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 3f81575..7cf2847 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -8,6 +8,10 @@ Hi6220 SoC Required root node properties: - compatible = "hisilicon,hi6220"; +Hi3660 SoC +Required root node properties: + - compatible = "hisilicon,hi3660"; + HiKey Board Required root node properties: - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; -- 1.9.1
Re: Linux 4.10-rc1
On 2016/12/26 17:18, Al Viro wrote:
> On Mon, Dec 26, 2016 at 05:05:37PM +0800, Kefeng Wang wrote:
>> It looks like we need revert the changes from assembly files.
> Better yet, split the damn thing in two and include the asm-only part.
>
>> diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
>> diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S
> Missed those two... OK, how about this?
It happens some where else,
./include/asm-generic/rwsem.h:48: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/rwsem.h:49: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/rwsem.h:50: Error: unknown mnemonic `return' -- `return 0'
./include/asm-generic/rwsem.h:51: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/rwsem.h:56: Error: unknown mnemonic `static' -- `static
inline void __down_write(struct rw_semaphore*sem)'
./include/asm-generic/rwsem.h:57: Error: junk at end of line, first
unrecognized character is `{'
./include/asm-generic/rwsem.h:58: Error: unknown mnemonic `long' -- `long tmp'
./include/asm-generic/rwsem.h:60: Error: junk at end of line, first
unrecognized character is `('
./include/asm-generic/rwsem.h:61: Error: junk at end of line, first
unrecognized character is `('
./include/asm-generic/rwsem.h:62: Error: unknown mnemonic `if' -- `if
(unlikely(tmp!=((-0xL-1)+0x0001L)))'
./include/asm-generic/rwsem.h:63: Error: unknown mnemonic
`rwsem_down_write_failed' -- `rwsem_down_write_failed(sem)'
./include/asm-generic/rwsem.h:64: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/rwsem.h:66: Error: unknown mnemonic `static' -- `static
inline int __down_write_killable(struct rw_semaphore*sem)'
./include/asm-generic/rwsem.h:67: Error: junk at end of line, first
unrecognized character is `{'
./include/asm-generic/rwsem.h:68: Error: unknown mnemonic `long' -- `long tmp'
./include/asm-generic/rwsem.h:70: Error: junk at end of line, first
unrecognized character is `('
./include/asm-generic/rwsem.h:71: Error: junk at end of line, first
unrecognized character is `('
./include/asm-generic/rwsem.h:72: Error: unknown mnemonic `if' -- `if
(unlikely(tmp!=((-0xL-1)+0x0001L)))'
./include/asm-generic/rwsem.h:73: Error: unknown mnemonic `if' -- `if
(IS_ERR(rwsem_down_write_failed_killable(sem)))'
./include/asm-generic/rwsem.h:74: Error: unknown mnemonic `return' -- `return
-4'
./include/asm-generic/rwsem.h:75: Error: unknown mnemonic `return' -- `return 0'
./include/asm-generic/rwsem.h:76: Error: junk at end of line, first
unrecognized character is `}'
./include/asm-generic/rwsem.h:78: Error: unknown mnemonic `static' -- `static
inline int __down_write_trylock(struct rw_semaphore*sem)'
./include/asm-generic/rwsem.h:79: Error: junk at end of line, first
unrecognized character is `{'
./include/linux/highuid.h:34: Error: unknown mnemonic `extern' -- `extern int
overflowuid'
./include/linux/highuid.h:35: Error: unknown mnemonic `extern' -- `extern int
overflowgid'
./include/linux/highuid.h:37: Error: unknown mnemonic `extern' -- `extern void
__bad_uid(void)'
./include/linux/uidgid.h:21: Error: unknown mnemonic `uid_t' -- `uid_t val'
./include/linux/uidgid.h:22: Error: junk at end of line, first unrecognized
character is `}'
./include/linux/uidgid.h:25: Error: unknown mnemonic `typedef' -- `typedef
struct{'
./include/linux/uidgid.h:26: Error: unknown mnemonic `gid_t' -- `gid_t val'
./include/linux/uidgid.h:27: Error: junk at end of line, first unrecognized
character is `}'
./include/uapi/linux/sysctl.h:34: Error: unknown mnemonic `struct' -- `struct
__sysctl_args{'
./include/uapi/linux/sysctl.h:35: Error: unknown mnemonic `int' -- `int
__user*name'
./include/uapi/linux/sysctl.h:36: Error: unknown mnemonic `int' -- `int nlen'
./include/uapi/linux/sysctl.h:37: Error: unknown mnemonic `void' -- `void
__user*oldval'
Thanks
Hanjun
>
> arm64: don't pull uaccess.h into *.S
>
> Split asm-only parts of arm64 uaccess.h into a new header and use that
> from *.S.
>
> Signed-off-by: Al Viro
>
> diff --git a/arch/arm64/include/asm/asm-uaccess.h
> b/arch/arm64/include/asm/asm-uaccess.h
> new file mode 100644
> index ..df411f3e083c
> --- /dev/null
> +++ b/arch/arm64/include/asm/asm-uaccess.h
> @@ -0,0 +1,65 @@
> +#ifndef __ASM_ASM_UACCESS_H
> +#define __ASM_ASM_UACCESS_H
> +
> +#include
> +#include
> +#include
> +#include
> +
> +/*
> + * User access enabling/disabling macros.
> + */
> +#ifdef CONFIG_ARM64_SW_TTBR0_PAN
> + .macro __uaccess_ttbr0_disable, tmp1
> + mrs \tmp1, ttbr1_el1// swapper_pg_dir
> + add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of
> swapper_pg_dir
> + msr ttbr0_el1, \tmp1// set reserved TTBR0_EL1
> + isb
> + .endm
> +
> + .macro __uaccess_ttbr0_enable, tmp1
> + get_thread_info \tmp1
> +
Re: Linux 4.10-rc1
On 2016/12/26 17:18, Al Viro wrote: > On Mon, Dec 26, 2016 at 05:05:37PM +0800, Kefeng Wang wrote: >> It looks like we need revert the changes from assembly files. I tested Kefeng's patch and works. more comments below. > Better yet, split the damn thing in two and include the asm-only part. split will cause other places for building errors, because there is no -#ifndef __ASSEMBLY__ in the file. > >> diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S >> diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S > Missed those two... OK, how about this? > > arm64: don't pull uaccess.h into *.S > > Split asm-only parts of arm64 uaccess.h into a new header and use that > from *.S. > > Signed-off-by: Al Viro > > diff --git a/arch/arm64/include/asm/asm-uaccess.h > b/arch/arm64/include/asm/asm-uaccess.h > new file mode 100644 > index ..df411f3e083c > --- /dev/null > +++ b/arch/arm64/include/asm/asm-uaccess.h > @@ -0,0 +1,65 @@ > +#ifndef __ASM_ASM_UACCESS_H > +#define __ASM_ASM_UACCESS_H > + > +#include > +#include > +#include > +#include > + > +/* > + * User access enabling/disabling macros. > + */ > +#ifdef CONFIG_ARM64_SW_TTBR0_PAN > + .macro __uaccess_ttbr0_disable, tmp1 > + mrs \tmp1, ttbr1_el1// swapper_pg_dir > + add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of > swapper_pg_dir > + msr ttbr0_el1, \tmp1// set reserved TTBR0_EL1 > + isb > + .endm > + > + .macro __uaccess_ttbr0_enable, tmp1 > + get_thread_info \tmp1 > + ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 > + msr ttbr0_el1, \tmp1// set the non-PAN TTBR0_EL1 > + isb > + .endm > + > + .macro uaccess_ttbr0_disable, tmp1 > +alternative_if_not ARM64_HAS_PAN > + __uaccess_ttbr0_disable \tmp1 > +alternative_else_nop_endif > + .endm > + > + .macro uaccess_ttbr0_enable, tmp1, tmp2 > +alternative_if_not ARM64_HAS_PAN > + save_and_disable_irq \tmp2 // avoid preemption > + __uaccess_ttbr0_enable \tmp1 > + restore_irq \tmp2 > +alternative_else_nop_endif > + .endm > +#else > + .macro uaccess_ttbr0_disable, tmp1 > + .endm > + > + .macro uaccess_ttbr0_enable, tmp1, tmp2 > + .endm > +#endif > + > +/* > + * These macros are no-ops when UAO is present. > + */ > + .macro uaccess_disable_not_uao, tmp1 > + uaccess_ttbr0_disable \tmp1 > +alternative_if ARM64_ALT_PAN_NOT_UAO > + SET_PSTATE_PAN(1) > +alternative_else_nop_endif > + .endm > + > + .macro uaccess_enable_not_uao, tmp1, tmp2 > + uaccess_ttbr0_enable \tmp1, \tmp2 > +alternative_if ARM64_ALT_PAN_NOT_UAO > + SET_PSTATE_PAN(0) > +alternative_else_nop_endif > + .endm > + > +#endif > diff --git a/arch/arm64/include/asm/uaccess.h > b/arch/arm64/include/asm/uaccess.h > index d26750ca6e06..46da3ea638bb 100644 > --- a/arch/arm64/include/asm/uaccess.h > +++ b/arch/arm64/include/asm/uaccess.h > @@ -22,8 +22,6 @@ > #include > #include > > -#ifndef __ASSEMBLY__ > - > /* > * User space memory access functions > */ > @@ -424,66 +422,4 @@ extern long strncpy_from_user(char *dest, const char > __user *src, long count); > extern __must_check long strlen_user(const char __user *str); > extern __must_check long strnlen_user(const char __user *str, long n); > > -#else/* __ASSEMBLY__ */ > - > -#include > - > -/* > - * User access enabling/disabling macros. > - */ > -#ifdef CONFIG_ARM64_SW_TTBR0_PAN > - .macro __uaccess_ttbr0_disable, tmp1 > - mrs \tmp1, ttbr1_el1// swapper_pg_dir > - add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of > swapper_pg_dir > - msr ttbr0_el1, \tmp1// set reserved TTBR0_EL1 > - isb > - .endm > - > - .macro __uaccess_ttbr0_enable, tmp1 > - get_thread_info \tmp1 > - ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 > - msr ttbr0_el1, \tmp1// set the non-PAN TTBR0_EL1 > - isb > - .endm > - > - .macro uaccess_ttbr0_disable, tmp1 > -alternative_if_not ARM64_HAS_PAN > - __uaccess_ttbr0_disable \tmp1 > -alternative_else_nop_endif > - .endm > - > - .macro uaccess_ttbr0_enable, tmp1, tmp2 > -alternative_if_not ARM64_HAS_PAN > - save_and_disable_irq \tmp2 // avoid preemption > - __uaccess_ttbr0_enable \tmp1 > - restore_irq \tmp2 > -alternative_else_nop_endif > - .endm > -#else > - .macro uaccess_ttbr0_disable, tmp1 > - .endm > - > - .macro uaccess_ttbr0_enable, tmp1, tmp2 > - .endm > -#endif > - > -/* > - * These macros are no-ops when UAO is present. > - */ > - .macro uaccess_disable_not_uao, tmp1 > - uaccess_ttbr0_disable \tmp1 > -alternative_if ARM64_ALT_PAN_NOT_UAO > - SET_PSTATE_PAN(1) > -alternative_else_nop_endif > - .endm > - > - .macro uaccess_enable_not_uao, tmp
Re: [PATCH] PCI: exynos: refactor exynos pcie driver
Hello Jaehoon
On 12/26/2016 02:32 PM, Jaehoon Chung wrote:
Hi Pankaj,
On 12/23/2016 07:56 PM, Pankaj Dubey wrote:
From: Niyas Ahmed S T
Currently Exynos PCIe driver is only supported for Exynos5440 SoC.
This patch does refactoring of Exynos PCIe driver to extend support
for other Exynos SoC.
Following are the main changes done via this patch:
1) It adds separate structs for memory, clock resources.
2) It add exynos_pcie_ops struct which will allow us to support the
differences in resources in different Exynos SoC.
It's nice to me for reusing this file.
but after considering too many times, i decided not to use this file.
I'm not sure what block base is..actually this pci-exynos.c is really black-box.
(No one maintains this file, even Samsung didn't care.)
Who is using this?
If Someone can share the information about exynos5440, i can refactor
everything.
Otherwise, there are two solution..
One is "adding the new pci-exynos.c" likes pci-exynos5433.c
Other is "refactor this file" under assuming the each register's usage.
Its alway good to reuse code as far as possible.
I am yet to see the details of 5440, but since people are now going to
support more Exynos variants, in my opinion, instead of adding
pci-exynos5433.c, you can rename current pci-exynos.c to something like
pci-exynos5440.c (only in case its too much changes needed to support
5433/exynos7) and lets have a common pci-exynos.c where we can add
exynos7/5433 and others SoCs, AFAIK at least exynos7 and 5433 has
similar pci controller.
I want to use the PHY generic Framework for EXYNOS PCIe.
I don't think you have an option here, you should use generic PHY APIs,
otherwise phy drive should go to drivers/misc.
Other thoughts are welcome.
If you or other guys really want to use the pci-exynos.c for other exynos,
I will rework with PHY generic framework. Then i will resend the my patches as
V2.
One more thing..Does anyone know what the usage of block base is?
Can i use that register as "syscon"?
Best Regards,
Jaehoon Chung
No functional change intended.
Signed-off-by: Niyas Ahmed S T
Signed-off-by: Pankaj Dubey
---
This patch set is prepared on top of Krzysztof's for-next and
PCIe driver cleanup patch [1] by Jaehoon Chung.
[1]: https://lkml.org/lkml/2016/12/19/44
drivers/pci/host/pci-exynos.c | 346 ++
1 file changed, 217 insertions(+), 129 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 33562cf..2dc54f7 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -28,16 +29,6 @@
#define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp)
-struct exynos_pcie {
- struct pcie_portpp;
- void __iomem*elbi_base; /* DT 0th resource */
- void __iomem*phy_base; /* DT 1st resource */
- void __iomem*block_base;/* DT 2nd resource */
- int reset_gpio;
- struct clk *clk;
- struct clk *bus_clk;
-};
-
/* PCIe ELBI registers */
#define PCIE_IRQ_PULSE0x000
#define IRQ_INTA_ASSERT BIT(0)
@@ -102,6 +93,122 @@ struct exynos_pcie {
#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
#define PCIE_PHY_TRSV3_LVCC 0x31c
+struct exynos_pcie_mem_res {
+ void __iomem *elbi_base; /* DT 0th resource: PCIE CTRL */
+ void __iomem *phy_base; /* DT 1st resource: PHY CTRL */
+ void __iomem *block_base; /* DT 2nd resource: PHY ADDITIONAL CTRL */
+};
+
+struct exynos_pcie_clk_res {
+ struct clk *clk;
+ struct clk *bus_clk;
+};
+
+struct exynos_pcie {
+ struct pcie_portpp;
+ struct exynos_pcie_mem_res *mem_res;
+ struct exynos_pcie_clk_res *clk_res;
+ const struct exynos_pcie_ops*ops;
+ int reset_gpio;
+};
+
+struct exynos_pcie_ops {
+ int (*get_mem_resources)(struct platform_device *pdev,
+ struct exynos_pcie *ep);
+ int (*get_clk_resources)(struct exynos_pcie *ep);
+ int (*init_clk_resources)(struct exynos_pcie *ep);
+ void (*deinit_clk_resources)(struct exynos_pcie *ep);
+};
+
+static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
+ struct exynos_pcie *ep)
+{
+ struct resource *res;
+ struct device *dev = ep->pp.dev;
+
+ ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
+ if (!ep->mem_res)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ep->mem_res->elbi_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(ep->mem_res->elbi_base))
+ return PTR_ERR(ep->mem_res->elbi_base);
+
+ res
[PATCH] perf/x86/amd/ibs: Fix typo after cleanup state names in cpu/hotplug
Fix a small typo after cleanup state names in cpu/hotplug.
The new convention is 'subsys/xxx/yyy:state' where "state" here is called
"starting" not "STARTING".
Fixes: 73c1b41e63f0 ("cpu/hotplug: Cleanup state names")
CC: Thomas Gleixner
CC: Ingo Molnar
CC: "H. Peter Anvin"
CC: x...@kernel.org
CC: Peter Zijlstra
CC: Borislav Petkov
CC: Paul Gortmaker
CC: linux-kernel@vger.kernel.org
Signed-off-by: Sedat Dilek
---
arch/x86/events/amd/ibs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index 05612a2529c8..496e60391fac 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -1010,7 +1010,7 @@ static __init int amd_ibs_init(void)
* all online cpus.
*/
cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
- "perf/x86/amd/ibs:STARTING",
+ "perf/x86/amd/ibs:starting",
x86_pmu_amd_ibs_starting_cpu,
x86_pmu_amd_ibs_dying_cpu);
--
2.11.0
[PATCH] arm64: Do not include linux/uaccess.h from assembler files
Including linux/uaccess.h from assembler files in arm64 builds results
in the following build errors.
In file included from arm64/include/asm/asm-offsets.h:1:0,
from arch/arm64/include/asm/assembler.h:26,
from arch/arm64/include/asm/alternative.h:68,
from arch/arm64/kernel/entry.S
include/linux/sched/prio.h: Assembler messages:
include/linux/sched/prio.h:47: Error:
unknown mnemonic `static' --
`static inline long nice_to_rlimit(long nice)'
build/include/linux/sched/prio.h:48: Error:
junk at end of line, first unrecognized character is `{'
[and many more]
If asm/uaccess.h is not included, many of the affected files fail to build
with errors such as the following.
arch/arm64/lib/copy_to_user.S: Assembler messages:
arch/arm64/lib/copy_to_user.S:66: Error:
unknown mnemonic `uaccess_enable_not_uao' --
`uaccess_enable_not_uao x3,x4'
arch/arm64/lib/copy_template.S:71: Error:
unknown mnemonic `uao_user_alternative' --
`uao_user_alternative 9998f,strb,st trb,tmp1w,dst,#1'
Either drop the include if unnecessary or, if needed, replace with
asm/uaccess.h.
Fixes: 7c0f6ba682b9 ("Replace with globally")
Cc: Linus Torvalds
Cc: Al Viro
Signed-off-by: Guenter Roeck
---
arch/arm64/kernel/entry.S | 1 -
arch/arm64/lib/clear_user.S | 2 +-
arch/arm64/lib/copy_from_user.S | 2 +-
arch/arm64/lib/copy_in_user.S | 2 +-
arch/arm64/lib/copy_to_user.S | 2 +-
arch/arm64/mm/cache.S | 2 +-
arch/arm64/xen/hypercall.S | 2 +-
7 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index a7504f40d7ee..fb93f8c25ff0 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -31,7 +31,6 @@
#include
#include
#include
-#include
#include
/*
diff --git a/arch/arm64/lib/clear_user.S b/arch/arm64/lib/clear_user.S
index add4a1334085..d7150e30438a 100644
--- a/arch/arm64/lib/clear_user.S
+++ b/arch/arm64/lib/clear_user.S
@@ -17,7 +17,7 @@
*/
#include
-#include
+#include
.text
diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_user.S
index fd6cd05593f9..cfe13396085b 100644
--- a/arch/arm64/lib/copy_from_user.S
+++ b/arch/arm64/lib/copy_from_user.S
@@ -17,7 +17,7 @@
#include
#include
-#include
+#include
/*
* Copy from user space to a kernel buffer (alignment handled by the hardware)
diff --git a/arch/arm64/lib/copy_in_user.S b/arch/arm64/lib/copy_in_user.S
index d828540ded6f..718b1c4e2f85 100644
--- a/arch/arm64/lib/copy_in_user.S
+++ b/arch/arm64/lib/copy_in_user.S
@@ -19,7 +19,7 @@
#include
#include
-#include
+#include
/*
* Copy from user space to user space (alignment handled by the hardware)
diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S
index 3e6ae2663b82..e99e31c9acac 100644
--- a/arch/arm64/lib/copy_to_user.S
+++ b/arch/arm64/lib/copy_to_user.S
@@ -17,7 +17,7 @@
#include
#include
-#include
+#include
/*
* Copy to user space from a kernel buffer (alignment handled by the hardware)
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 17f422a4dc55..da9576932322 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -23,7 +23,7 @@
#include
#include
#include
-#include
+#include
/*
* flush_icache_range(start,end)
diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S
index 47cf3f9d89ff..b41aff25426d 100644
--- a/arch/arm64/xen/hypercall.S
+++ b/arch/arm64/xen/hypercall.S
@@ -49,7 +49,7 @@
#include
#include
-#include
+#include
#include
--
2.7.4
Re: [PATCH] drivers: watchdog: pika_wdt: add __ro_after_init to ident
On 12/25/2016 12:00 AM, Bhumika Goyal wrote:
The object ident of type watchdog_info structure is not
modified after getting initialized by pikawdt_init. Apart from getting
referenced in init it is also passed as an argument to the function
copy_to_user but this argument is of type const void *. Therefore add
__ro_after_init to its declaration.
Signed-off-by: Bhumika Goyal
Reviewed-by: Guenter Roeck
---
drivers/watchdog/pika_wdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/pika_wdt.c b/drivers/watchdog/pika_wdt.c
index 0cdfee2..e35cf5e 100644
--- a/drivers/watchdog/pika_wdt.c
+++ b/drivers/watchdog/pika_wdt.c
@@ -54,7 +54,7 @@
struct timer_list timer;/* The timer that pings the watchdog */
} pikawdt_private;
-static struct watchdog_info ident = {
+static struct watchdog_info ident __ro_after_init = {
.identity = DRV_NAME,
.options= WDIOF_CARDRESET |
WDIOF_SETTIMEOUT |
Re: [RFC PATCH v2 3/4] hwmon: adc128d818: Trivial code style fixup
On 12/23/2016 02:12 PM, Alexander Koch wrote: Replace sysfs symbolic file permissions, e.g. 'S_IRUGO', by octal permissions. This fixes checkpatch.pl warnings. Signed-off-by: Alexander Koch Please do not bother with those warnings and ignore checkpatch. We are in the process of doing an automated conversion. Thanks, Guenter --- drivers/hwmon/adc128d818.c | 99 ++ 1 file changed, 39 insertions(+), 60 deletions(-) diff --git a/drivers/hwmon/adc128d818.c b/drivers/hwmon/adc128d818.c index 8667f454ea11..cbb3bc5e5229 100644 --- a/drivers/hwmon/adc128d818.c +++ b/drivers/hwmon/adc128d818.c @@ -242,69 +242,48 @@ static ssize_t adc128_show_alarm(struct device *dev, return sprintf(buf, "%u\n", !!(alarms & mask)); } -static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, - adc128_show_in, NULL, 0, 0); -static SENSOR_DEVICE_ATTR_2(in0_min, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 0, 1); -static SENSOR_DEVICE_ATTR_2(in0_max, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 0, 2); - -static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, - adc128_show_in, NULL, 1, 0); -static SENSOR_DEVICE_ATTR_2(in1_min, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 1, 1); -static SENSOR_DEVICE_ATTR_2(in1_max, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 1, 2); - -static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, - adc128_show_in, NULL, 2, 0); -static SENSOR_DEVICE_ATTR_2(in2_min, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 2, 1); -static SENSOR_DEVICE_ATTR_2(in2_max, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 2, 2); - -static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, - adc128_show_in, NULL, 3, 0); -static SENSOR_DEVICE_ATTR_2(in3_min, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 3, 1); -static SENSOR_DEVICE_ATTR_2(in3_max, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 3, 2); - -static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, - adc128_show_in, NULL, 4, 0); -static SENSOR_DEVICE_ATTR_2(in4_min, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 4, 1); -static SENSOR_DEVICE_ATTR_2(in4_max, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 4, 2); - -static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, - adc128_show_in, NULL, 5, 0); -static SENSOR_DEVICE_ATTR_2(in5_min, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 5, 1); -static SENSOR_DEVICE_ATTR_2(in5_max, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 5, 2); - -static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, - adc128_show_in, NULL, 6, 0); -static SENSOR_DEVICE_ATTR_2(in6_min, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 6, 1); -static SENSOR_DEVICE_ATTR_2(in6_max, S_IWUSR | S_IRUGO, - adc128_show_in, adc128_set_in, 6, 2); - -static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, adc128_show_temp, NULL, 0); -static SENSOR_DEVICE_ATTR(temp1_max, S_IWUSR | S_IRUGO, +static SENSOR_DEVICE_ATTR_2(in0_input, 0444, adc128_show_in, NULL, 0, 0); +static SENSOR_DEVICE_ATTR_2(in0_min, 0644, adc128_show_in, adc128_set_in, 0, 1); +static SENSOR_DEVICE_ATTR_2(in0_max, 0644, adc128_show_in, adc128_set_in, 0, 2); + +static SENSOR_DEVICE_ATTR_2(in1_input, 0444, adc128_show_in, NULL, 1, 0); +static SENSOR_DEVICE_ATTR_2(in1_min, 0644, adc128_show_in, adc128_set_in, 1, 1); +static SENSOR_DEVICE_ATTR_2(in1_max, 0644, adc128_show_in, adc128_set_in, 1, 2); + +static SENSOR_DEVICE_ATTR_2(in2_input, 0444, adc128_show_in, NULL, 2, 0); +static SENSOR_DEVICE_ATTR_2(in2_min, 0644, adc128_show_in, adc128_set_in, 2, 1); +static SENSOR_DEVICE_ATTR_2(in2_max, 0644, adc128_show_in, adc128_set_in, 2, 2); + +static SENSOR_DEVICE_ATTR_2(in3_input, 0444, adc128_show_in, NULL, 3, 0); +static SENSOR_DEVICE_ATTR_2(in3_min, 0644, adc128_show_in, adc128_set_in, 3, 1); +static SENSOR_DEVICE_ATTR_2(in3_max, 0644, adc128_show_in, adc128_set_in, 3, 2); + +static SENSOR_DEVICE_ATTR_2(in4_input, 0444, adc128_show_in, NULL, 4, 0); +static SENSOR_DEVICE_ATTR_2(in4_min, 0644, adc128_show_in, adc128_set_in, 4, 1); +static SENSOR_DEVICE_ATTR_2(in4_max, 0644, adc128_show_in, adc128_set_in, 4, 2); + +static SENSOR_DEVICE_ATTR_2(in5_input, 0444, adc128_show_in, NULL, 5, 0); +static SENSOR_DEVICE_ATTR_2(in5_min, 0644, adc128_show_in, adc128_set_in, 5, 1); +static SENSOR_DEVICE_ATTR_2(in5_max, 0644, adc128_show_in, adc128_set_in, 5, 2); + +static SENSOR_DEVICE_ATTR_2(in6_input, 0444, adc128_show_in, NULL, 6, 0); +static SENSOR_DEVICE_ATTR_2(in6_min, 0644, adc128_show_in, adc128_set_in
Re: Bug 4.9 and memorymanagement
[CCing linux-mm] On Sun 25-12-16 21:52:52, Klaus Ethgen wrote: > Hello, > > The last days I compiled version 4.9 for my i386 laptop. (Lenovo x61s) Do you have memory cgroups enabled in runtime (aka does the same happen with cgroup_disable=memory)? > First, everything seems to be sane but after some sleep and awake > (suspend to ram) cycles I seen some really weird behaviour ending in OOM > or even complete freeze of the laptop. > > What I was able to see is that it went to swap even if there is plenty > of memory left. The OOMs was also with many memory left. Could you paste those OOM reports from the kernel log? > Once I also catched kswapd0 with running insane with 100% CPU > utilization. > > I first had in mind the CONFIG_SLAB_FREELIST_RANDOM setting and disabled > it. This didn't made the problem to go away but it helped a little. > Nevertheless, further OOM or other strange behaviour happened. > > I went back to 4.8.15 now with the same config from 4.9 and everything > gets back to normal. > > So it seems for me that there are some really strange memory leaks in > 4.9. The biggest problem is, that I do not know how to reproduce it > reliable. The only what I know is that it happened after several > suspends. (Not necessarily the first.) > > Am I the only one seeing that behavior or do anybody have an idea what > could went wrong? no there were some reports recently and 32b with memory cgroups are broken since 4.8 when the zone LRU's were moved to nodes. >x > For the reference I put the .configs of the two compilings as attachment > to this mail. > > Please keep me in CC as I am not subscribed to LKML. > > Regards >Klaus -- Michal Hocko SUSE Labs
Re: [GIT pull] smp/hotplug: Removal of notifiers
On 2016.12.26 at 08:45 +0100, Markus Trippelsdorf wrote: > On 2016.12.25 at 14:39 +0100, Thomas Gleixner wrote: > > Linus, > > > > please pull the latest smp-urgent-for-linus git tree from: > > > >git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git > > smp-urgent-for-linus > > > > Thomas Gleixner (11): > > cpu/hotplug: Prevent overwriting of callbacks > > The following commit: > > commit dc280d93623927570da279e99393879dbbab39e7 > Author: Thomas Gleixner > Date: Wed Dec 21 20:19:49 2016 +0100 > > cpu/hotplug: Prevent overwriting of callbacks > > results in an early OOPs during boot on my AMD machine. > I haven't wrote down the entire backtrace, but basically things start to > go wrong in mce_threshold_create_device() from > arch/x86/kernel/cpu/mcheck/mce_amd.c. > > # CONFIG_HOTPLUG_CPU is not set > > Reverting the commit "fixes" the issue for me. CCing Sebastian and Borislav. -- Markus
Re: [PATCH v3 2/4] dt-bindings: add bindings for rk3328 clock controller
Hi Elaine,
Am Montag, 26. Dezember 2016, 11:45:28 CET schrieb Elaine Zhang:
> Add devicetree bindings for Rockchip cru which found on
> Rockchip SoCs.
>
> Signed-off-by: Elaine Zhang
> ---
> .../bindings/clock/rockchip,rk3328-cru.txt | 57
> ++ 1 file changed, 57 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
> b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt new file
> mode 100644
> index ..20053494d49f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
> @@ -0,0 +1,57 @@
> +* Rockchip RK3328 Clock and Reset Unit
> +
> +The RK3328 clock controller generates and supplies clock to various
> +controllers within the SoC and also implements a reset controller for SoC
> +peripherals.
> +
> +Required Properties:
> +
> +- compatible: should be "rockchip,rk3328-cru"
> +- reg: physical base address of the controller and length of memory mapped
> + region.
> +- #clock-cells: should be 1.
> +- #reset-cells: should be 1.
> +
> +Optional Properties:
> +
> +- rockchip,grf: phandle to the syscon managing the "general register files"
> + If missing pll rates are not changeable, due to the missing pll lock
> status. +
> +Each clock is assigned an identifier and client nodes can use this
> identifier +to specify the clock which they consume. All available clocks
> are defined as +preprocessor macros in the dt-bindings/clock/rk3328-cru.h
> headers and can be +used in device tree sources. Similar macros exist for
> the reset sources in +these files.
> +
> +External clocks:
> +
> +There are several clocks that are generated outside the SoC. It is expected
> +that they are defined using standard clock bindings with following
> +clock-output-names:
> + - "xin24m" - crystal input - required,
> + - "clkin_i2s" - external I2S clock - optional,
> + - "gmac_clkin" - external GMAC clock - optional
> + - "phy_50m_out" - output clock of the pll in the mac phy
> +
> +Example: Clock controller node:
> +
> + cru: clock-controller@ff44 {
> + compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
Rob suggested dropping the "rockchip,cru" and "syscon" properties from the
example and I definitly agree with that.
Otherwise look ok to me.
Heiko
Re: [PATCH v3 4/4] clk: rockchip: add new pll-type for rk3328
Am Montag, 26. Dezember 2016, 11:45:30 CET schrieb Elaine Zhang:
> The rk3328's pll and clock are similar with rk3036's,
> it different with pll_mode_mask, the rk3328 soc
> pll mode only one bit(rk3036 soc have two bits)
> so these should be independent and separate from
> the series of rk3328s.
>
> Changes in v3:
> fix up the pll type pll_rk3328 description and use
>
> Signed-off-by: Elaine Zhang
> ---
pll-specific code looks good now, but please make this patch before the clock
controller in the series and move the
@@ -130,6 +152,7 @@
enum rockchip_pll_type {
pll_rk3036,
pll_rk3066,
+ pll_rk3328,
pll_rk3399,
};
from patch3 into this one.
Thanks
Heiko
PS: I will have some comments for the clock controller patch, but it's xmas,
so that may take bit still.
RE: [PATCH] adc: add adc driver for Hisilicon BVT SOCs
Hi Jonathan,
Thanks very much for your reply , it get me great courage to continue this
upstreaming .
we will make a careful analysis of your suggestion and update a new patch after
a few days.
Best regards
/Allen
/-/
From: Jonathan Cameron [mailto:ji...@jic23.retrosnub.co.uk]
Sent: 24 December 2016 19:46
To: liurenzhong; ji...@kernel.org; knaac...@gmx.de; l...@metafoo.de;
pme...@pmeerw.net; robh...@kernel.org; mark.rutl...@arm.com
Cc: akinobu.m...@gmail.com; ludovic.desroc...@atmel.com; k...@kernel.org;
vilhelm.g...@gmail.com; ksenija.stanoje...@gmail.com; zhiyong@mediatek.com;
daniel.bal...@intel.com; leonard.cres...@intel.com; ray@broadcom.com;
raveendra.padasal...@broadcom.com; mranos...@gmail.com; amsfiel...@gmail.com;
linux-...@vger.kernel.org; devicet...@vger.kernel.org;
linux-kernel@vger.kernel.org; Xuejiancheng; Lixu (kevin)
Subject: Re: [PATCH] adc: add adc driver for Hisilicon BVT SOCs
On 24 December 2016 01:54:57 GMT+00:00, Allen Liu
wrote:
>Add ADC driver for the ADC controller found on HiSilicon BVT SOCs, like
>Hi3516CV300, etc.
>The ADC controller is primarily in charge of detecting voltage.
>
>Reviewed-by: Jiancheng Xue
>Signed-off-by: Allen Liu
Reading on phone so may not be that thorough!
Looks pretty good. The device abstraction makes it slightly more complicated
than it needs to be. If you aren't going to follow up quickly with other
device support please drop the abstraction. It can be easily readded when
needed.
Various little things inline.
Thanks
Jonathan
>---
> .../devicetree/bindings/iio/adc/hibvt-lsadc.txt| 26 ++
> drivers/iio/adc/Kconfig| 10 +
> drivers/iio/adc/Makefile | 1 +
>drivers/iio/adc/hibvt_lsadc.c | 344
>+
> 4 files changed, 381 insertions(+)
>create mode 100644
>Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
> create mode 100644 drivers/iio/adc/hibvt_lsadc.c
>
>diff --git a/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
>b/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
>new file mode 100644
>index 000..63de46e
>--- /dev/null
>+++ b/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
>@@ -0,0 +1,26 @@
>+Hisilicon BVT Low Speed (LS) A/D Converter bindings
>+
>+Required properties:
>+- compatible: should be "hisilicon,-lsadc"
>+ - "hisilicon,hibvt-lsadc": for hi3516cv300
>+
>+- reg: physical base address of the controller and length of memory
>mapped
>+ region.
>+- interrupts: The interrupt number to the cpu. The interrupt specifier
>format
>+ depends on the interrupt controller.
A cross reference to the interrupt bindings doc always good to add.
>+- #io-channel-cells: Should be 1, see ../iio-bindings.txt
>+
>+Optional properties:
>+- resets: Must contain an entry for each entry in reset-names if need
>support
>+this option. See ../reset/reset.txt for details.
>+- reset-names: Must include the name "saradc-apb".
>+
>+Example:
>+ lsadc: hibvt-lsadc@120e {
>+ compatible = "hisilicon,hibvt-lsadc";
>+ reg = <0x120e 0x1000>;
>+ interrupts = <19>;
>+ resets = <&crg 0x7c 3>;
>+ reset-names = "lsadc-crg";
Doesn't contain saradc-apb which docs say it must...
>+ status = "disabled";
Not documented...
>+ };
>diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index
>99c0514..0443f51 100644
>--- a/drivers/iio/adc/Kconfig
>+++ b/drivers/iio/adc/Kconfig
>@@ -225,6 +225,16 @@ config HI8435
> This driver can also be built as a module. If so, the module will be
> called hi8435.
>
>+config HIBVT_LSADC
>+ tristate "HIBVT LSADC driver"
>+ depends on ARCH_HISI || COMPILE_TEST
>+ help
>+Say yes here to build support for the LSADC found in SoCs from
>+hisilicon BVT chip.
>+
>+To compile this driver as a module, choose M here: the
>+module will be called hibvt_lsadc.
>+
> config INA2XX_ADC
> tristate "Texas Instruments INA2xx Power Monitors IIO driver"
> depends on I2C && !SENSORS_INA2XX
>diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index
>7a40c04..6554d92 100644
>--- a/drivers/iio/adc/Makefile
>+++ b/drivers/iio/adc/Makefile
>@@ -23,6 +23,7 @@ obj-$(CONFIG_DA9150_GPADC) += da9150-gpadc.o
> obj-$(CONFIG_EXYNOS_ADC) += exynos_adc.o
> obj-$(CONFIG_FSL_MX25_ADC) += fsl-imx25-gcq.o
> obj-$(CONFIG_HI8435) += hi8435.o
>+obj-$(CONFIG_HIBVT_LSADC) += hibvt_lsadc.o
> obj-$(CONFIG_IMX7D_ADC) += imx7d_adc.o
> obj-$(CONFIG_INA2XX_ADC) += ina2xx-adc.o
> obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o diff --git
>a/drivers/iio/adc/hibvt_lsadc.c b/drivers/iio/adc/hibvt_lsadc.c new
>file mode 100644 index 000..a20afe8
>--- /dev/null
>+++ b/drivers/iio/adc/hibvt_lsadc.c
>@@ -0,0 +1,344 @@
>+/*
>+ * Hisilicon BVT Low Speed (LS) A/D Conve
[PATCH] rtc: armada38x: add __ro_after_init to armada38x_rtc_ops
The object armada38x_rtc_ops of type rtc_class_ops structure is not
modified after getting initialized by armada38x_rtc_probe. Apart from
getting referenced in init it is also passed as an argument to the function
devm_rtc_device_register but this argument is of type const struct
rtc_class_ops *. Therefore add __ro_after_init to its declaration.
Signed-off-by: Bhumika Goyal
---
drivers/rtc/rtc-armada38x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-armada38x.c b/drivers/rtc/rtc-armada38x.c
index 9a3f2a6..7883c7f 100644
--- a/drivers/rtc/rtc-armada38x.c
+++ b/drivers/rtc/rtc-armada38x.c
@@ -202,7 +202,7 @@ static irqreturn_t armada38x_rtc_alarm_irq(int irq, void
*data)
return IRQ_HANDLED;
}
-static struct rtc_class_ops armada38x_rtc_ops = {
+static struct rtc_class_ops armada38x_rtc_ops __ro_after_init = {
.read_time = armada38x_rtc_read_time,
.set_time = armada38x_rtc_set_time,
.read_alarm = armada38x_rtc_read_alarm,
--
1.9.1
Re: [PATCH] mm/page_alloc: Wait for oom_lock before retrying.
Cc Greg, Jiri,
On (12/26/16 19:54), Tetsuo Handa wrote:
[..]
>
> (3) I got below warning. (Though not reproducible.)
> If fb_flashcursor() called console_trylock(), console_may_schedule is set
> to 1?
hmmm... it takes an atomic/spin `printing_lock' lock in vt_console_print(),
then call console_conditional_schedule() from lf(), being under spin_lock.
`console_may_schedule' in console_conditional_schedule() still keeps the
value from console_trylock(), which was ok (console_may_schedule permits
rescheduling). but preemption got changed under console_trylock(), by
that spin_lock.
console_trylock() used to always forbid rescheduling; but it got changed
like a yaer ago.
the other thing is... do we really need to console_conditional_schedule()
from fbcon_*()? console_unlock() does cond_resched() after every line it
prints. wouldn't that be enough?
so may be we can drop some of console_conditional_schedule()
call sites in fbcon. or update console_conditional_schedule()
function to always return the current preemption value, not the
one we saw in console_trylock().
(not tested)
---
kernel/printk/printk.c | 35 ---
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index 8b2696420abb..ad4a02cf9f15 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -2075,6 +2075,24 @@ static int console_cpu_notify(unsigned int cpu)
return 0;
}
+static int get_console_may_schedule(void)
+{
+ /*
+* When PREEMPT_COUNT disabled we can't reliably detect if it's
+* safe to schedule (e.g. calling printk while holding a spin_lock),
+* because preempt_disable()/preempt_enable() are just barriers there
+* and preempt_count() is always 0.
+*
+* RCU read sections have a separate preemption counter when
+* PREEMPT_RCU enabled thus we must take extra care and check
+* rcu_preempt_depth(), otherwise RCU read sections modify
+* preempt_count().
+*/
+ return !oops_in_progress &&
+ preemptible() &&
+ !rcu_preempt_depth();
+}
+
/**
* console_lock - lock the console system for exclusive use.
*
@@ -2112,20 +2130,7 @@ int console_trylock(void)
return 0;
}
console_locked = 1;
- /*
-* When PREEMPT_COUNT disabled we can't reliably detect if it's
-* safe to schedule (e.g. calling printk while holding a spin_lock),
-* because preempt_disable()/preempt_enable() are just barriers there
-* and preempt_count() is always 0.
-*
-* RCU read sections have a separate preemption counter when
-* PREEMPT_RCU enabled thus we must take extra care and check
-* rcu_preempt_depth(), otherwise RCU read sections modify
-* preempt_count().
-*/
- console_may_schedule = !oops_in_progress &&
- preemptible() &&
- !rcu_preempt_depth();
+ console_may_schedule = get_console_may_schedule();
return 1;
}
EXPORT_SYMBOL(console_trylock);
@@ -2316,7 +2321,7 @@ EXPORT_SYMBOL(console_unlock);
*/
void __sched console_conditional_schedule(void)
{
- if (console_may_schedule)
+ if (get_console_may_schedule())
cond_resched();
}
EXPORT_SYMBOL(console_conditional_schedule);
---
-ss
>
> [ OK [ 255.862188] audit: type=1131 audit(1482733112.662:148): pid=1 uid=0
> auid=4294967295 ses=4294967295 msg='unit=systemd-tmpfiles-setup-dev
> comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=?
> res=success'
> ] Stopped Create Static Device Nodes in /dev.
>
> [ 255.871468] BUG: sleeping function called from invalid context at
> kernel/printk/printk.c:2325
> [ 255.871469] in_atomic(): 1, irqs_disabled(): 1, pid: 10079, name: plymouthd
> [ 255.871469] 6 locks held by plymouthd/10079:
> [ 255.871470] #0: (&tty->ldisc_sem){.+}, at: []
> ldsem_down_read+0x32/0x40
> [ 255.871472] #1: (&tty->atomic_write_lock){+.+.+.}, at:
> [] tty_write_lock+0x19/0x50
> [ 255.871474] #2: (&tty->termios_rwsem){..}, at: []
> n_tty_write+0x99/0x470
> [ 255.871475] #3: (&ldata->output_lock){+.+...}, at: []
> n_tty_write+0x130/0x470
> [ 255.871477] #4: (console_lock){+.+.+.}, at: []
> console_unlock+0x33e/0x6b0
> [ 255.871479] #5: (printing_lock){..}, at: []
> vt_console_print+0x75/0x3d0
> [ 255.871481] irq event stamp: 15244
> [ 255.871481] hardirqs last enabled at (15243): []
> __down_trylock_console_sem+0x91/0xa0
> [ 255.871482] hardirqs last disabled at (15244): []
> console_unlock+0x74/0x6b0
> [ 255.871482] softirqs last enabled at (14968): []
> __do_softirq+0x344/0x580
> [ 255.871482] softirqs last disabled at (14963): []
> irq_exit+0xe3/0x120
> [ 255.871483] CPU: 0 PID: 10079 Comm: plymouthd Not tainted
> 4.9.0-next-20161224+ #12
Re: [RFC PATCH 4/6] PCI: exynos5433: Add new exynos pci host controller for Exynos5433
Hello Jaehoon,
Às 5:20 AM de 12/26/2016, Jaehoon Chung escreveu:
> Exynos5433 supports the PCIe.
> This patch adds new pci-exynos5433.c file for Exynos ARM64.
>
> Signed-off-by: Jaehoon Chung
> ---
> drivers/pci/host/Kconfig | 9 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pci-exynos5433.c | 338
> ++
> 3 files changed, 348 insertions(+)
> create mode 100644 drivers/pci/host/pci-exynos5433.c
>
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index d7e7c0a..3d77d0b 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -60,6 +60,15 @@ config PCI_EXYNOS
> select PCIEPORTBUS
> select PCIE_DW
>
> +config PCI_EXYNOS5433
> + bool "Samsung Exynos5433 PCIe controller"
> + depends on ARCH_EXYNOS && ARM64
> + depends on PCI_MSI_IRQ_DOMAIN
> + select PCIEPORTBUS
> + select PCIE_DW
> + help
> + If you want support for Exynos5433 PCIe host controller, say Y.
> +
> config PCI_IMX6
> bool "Freescale i.MX6 PCIe controller"
> depends on SOC_IMX6Q
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index 084cb49..2168de2 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -2,6 +2,7 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
> obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
> obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
> obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> +obj-$(CONFIG_PCI_EXYNOS5433) += pci-exynos5433.o
> obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
> obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o
> obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
> diff --git a/drivers/pci/host/pci-exynos5433.c
> b/drivers/pci/host/pci-exynos5433.c
> new file mode 100644
> index 000..ff254ca
> --- /dev/null
> +++ b/drivers/pci/host/pci-exynos5433.c
> @@ -0,0 +1,338 @@
> +/*
> + * PCIe host controller driver for Samsung EXYNOS5433 SoCs
> + *
> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
> + *
> https://urldefense.proofpoint.com/v2/url?u=http-3A__www.samsung.com&d=DgIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=s2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=fUwnZks1U2AwaOxMkLdSnE700sfQXpB3WAg_EJw7NaE&s=IwRYD8maTuXG57Q0qlAmFNh3_TSfUTE27xq8p13FFKI&e=
>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "pcie-designware.h"
> +
> +#define to_exynos_pcie(x)container_of(x, struct exynos_pcie, pp)
> +
> +/* Pcie structure for Exynos specific data */
> +struct exynos_pcie {
> + void __iomem*elbi_base;
> + struct clk *clk;
> + struct clk *bus_clk;
> + struct pcie_portpp;
> + struct phy *phy;
> +};
> +
> +/* PCIe ELBI registers */
> +#define PCIE_IRQ_PULSE 0x000
> +#define IRQ_INTA_ASSERT BIT(0)
> +#define IRQ_INTB_ASSERT BIT(2)
> +#define IRQ_INTC_ASSERT BIT(4)
> +#define IRQ_INTD_ASSERT BIT(6)
> +#define IRQ_INTX_ASSERT (IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | \
> + IRQ_INTC_ASSERT | IRQ_INTD_ASSERT)
> +#define PCIE_IRQ_EN_PULSE0x00c
> +#define PCIE_IRQ_EN_LEVEL0x010
> +#define PCIE_SW_WAKE 0x018
> +#define PCIE_BUS_EN BIT(1)
> +#define PCIE_APP_LTSSM_ENABLE0x02c
> +#define PCIE_ELBI_LTSSM_ENABLE 0x1
> +#define PCIE_ELBI_DEBUG_L0x074
> +#define PCIE_ELBI_XMLH_LINK_UP BIT(4)
> +#define PCIE_ELBI_SLV_AWMISC 0x11c
> +#define PCIE_ELBI_SLV_ARMISC 0x120
> +#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
> +
> +/* DBI register */
> +#define PCIE_MISC_CONTROL_1_OFF 0x8BC
> +#define DBI_RO_WR_EN BIT(0)
> +
> +static inline void exynos_pcie_writel(void __iomem *base, u32 val, u32
> offset)
> +{
> + writel(val, base + offset);
> +}
> +
> +static inline u32 exynos_pcie_readl(void __iomem *base, u32 offset)
> +{
> + return readl(base + offset);
> +}
> +
> +static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
> +{
> + u32 val;
> +
> + val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
> + val &= ~IRQ_INTX_ASSERT;
> + exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
> +}
> +
> +static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
> +{
> + exynos_pcie_writel(ep->elbi_base, IRQ_INTX_ASSERT, PCIE_IRQ_EN_PULSE);
> +
> + /* Clear PCIE_IRQ_EN_LEVEL register */
> + exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL);
> +}
> +
> +static irqreturn
linux-next: stats (Was: Linux 4.10-rc1)
Hi All, On Sun, 25 Dec 2016 16:41:46 -0800 Linus Torvalds wrote: > > It's Christmas Day, and it's two weeks since the merge window opened. > Thus, the merge window is now closed. As usual, the executive friendly graph is at http://neuling.org/linux-next-size.html :-) (No merge commits counted, next-20161212 was the first linux-next after the merge window opened.) Commits in v4.10-rc1 (relative to v4.9): 11455 Commits in next-20161212: 10625 Commits with the same SHA1: 9927 Commits with the same patch_id: 437 (1) Commits with the same subject line: 25 (1) (1) not counting those in the lines above. So commits in -rc1 that were in next-20161212: 10389 90% Some breakdown of the list of extra commits (relative to next-20161212) in -rc1: Top ten first word of commit summary: 153 ib 64 drm 46 x86 38 i40iw 34 net 33 s390 33 input 30 ubifs 27 perf 26 btrfs Top ten authors: 32 t...@linutronix.de 27 rich...@nod.at 26 bart.vanass...@sandisk.com 22 henry.oro...@intel.com 20 l...@kernel.org 19 je...@suse.com 18 m...@redhat.com 18 idryo...@gmail.com 15 trond.mykleb...@primarydata.com 13 vinod.k...@intel.com Top ten commiters: 225 dledf...@redhat.com 115 da...@davemloft.net 63 t...@linutronix.de 34 torva...@linux-foundation.org 34 m...@redhat.com 33 schwidef...@de.ibm.com 33 a...@redhat.com 32 idryo...@gmail.com 32 dmitry.torok...@gmail.com 31 rich...@nod.at There are also 236 commits in next-20161212 that didn't make it into v4.10-rc1. Top ten first word of commit summary: 24 arm 21 rcu 9 keys 9 coresight 9 btrfs 8 vfs 8 torture 8 thermal 6 mm 6 bf609 Top ten authors: 24 paul...@linux.vnet.ibm.com 15 mszer...@redhat.com 14 a...@linux-foundation.org 11 o...@lixom.net 11 dhowe...@redhat.com 10 v...@zeniv.linux.org.uk 8 wangxg.f...@cn.fujitsu.com 6 vitalyw...@gmail.com 6 colin.k...@canonical.com 5 sonic.zh...@analog.com Some of Andrew's patches are fixes for other patches in his tree (and have been merged into those). Top ten commiters: 39 s...@canb.auug.org.au 36 paul...@linux.vnet.ibm.com 16 steven@ubuntu-virtualbox.(none) 15 mszer...@redhat.com 13 o...@lixom.net 11 dhowe...@redhat.com 10 v...@zeniv.linux.org.uk 10 edubez...@gmail.com 9 mathieu.poir...@linaro.org 9 dste...@suse.com Those commits by me are from the quilt series (mainly Andrew's mmotm tree). Turns out that steven@ubuntu-virtualbox.(none) is Steven Miao and all those commits are old stuff left over in the blackfin tree since March, 2016 - it would be nice if they were cleaned up. -- Cheers, Stephen Rothwell
Re: [lkp-developer] [mm, memcg] d18e2b2aca: WARNING:at_mm/memcontrol.c:#mem_cgroup_update_lru_size
On Mon 26-12-16 06:25:56, kernel test robot wrote:
>
> FYI, we noticed the following commit:
>
> commit: d18e2b2aca0396849f588241e134787a829c707d ("mm, memcg: fix (Re: OOM:
> Better, but still there on)")
> url:
> https://github.com/0day-ci/linux/commits/Michal-Hocko/mm-memcg-fix-Re-OOM-Better-but-still-there-on/20161223-225057
> base: git://git.cmpxchg.org/linux-mmotm.git master
>
> in testcase: boot
>
> on test machine: qemu-system-i386 -enable-kvm -m 360M
>
> caused below changes:
>
>
> ++++
> || c7d85b880b |
> d18e2b2aca |
> ++++
> | boot_successes | 8 | 0
> |
> | boot_failures | 0 | 2
> |
> | WARNING:at_mm/memcontrol.c:#mem_cgroup_update_lru_size | 0 | 2
> |
> | kernel_BUG_at_mm/memcontrol.c | 0 | 2
> |
> | invalid_opcode:#[##]DEBUG_PAGEALLOC| 0 | 2
> |
> | Kernel_panic-not_syncing:Fatal_exception | 0 | 2
> |
> ++++
>
>
>
> [ 95.226364] init: tty6 main process (990) killed by TERM signal
> [ 95.314020] init: plymouth-upstart-bridge main process (1039) terminated
> with status 1
> [ 97.588568] [ cut here ]
> [ 97.594364] WARNING: CPU: 0 PID: 1055 at mm/memcontrol.c:1032
> mem_cgroup_update_lru_size+0xdd/0x12b
> [ 97.606654] mem_cgroup_update_lru_size(40297f00, 0, -1): lru_size 1 but
> empty
> [ 97.615140] Modules linked in:
> [ 97.618834] CPU: 0 PID: 1055 Comm: killall5 Not tainted
> 4.9.0-mm1-00095-gd18e2b2 #82
> [ 97.628008] Call Trace:
> [ 97.631025] dump_stack+0x16/0x18
> [ 97.635107] __warn+0xaf/0xc6
> [ 97.638729] ? mem_cgroup_update_lru_size+0xdd/0x12b
Do you have the full backtrace?
--
Michal Hocko
SUSE Labs
[RFC PATCH] ext4: increase the protection of drop nlink and ext4 inode destroy
Because of the disk and hardware issue, the ext4 filesystem have
many errors, the inode->i_nlink of ext4 becomes zero abnormally
but the dentry is still positive, it will cause memory corruption
after the following process:
1) Due to the inode->i_nlink is 0, this inode will be added into
the orhpan list,
2) ext4_rename() cover this inode, and drop_nlink() will reverse
the inode->i_nlink to 0x,
3) iput() add this inode to LRU,
4) evict() will call destroy_inode() to destroy this inode but
skip removing it from the orphan list,
5) after this, the inode's memory address space will be used by
other module, when the ext4 filesystem change the orphan list, it will
trample other module's data and then may cause oops.
Although we cannot avoid hardware and disk errors, we can control the
softwore error in the ext4 module, do not affect other modules and
increase the difficulty of locating problems.
This patch avoid inode->i_nlink reverse and remove the inode form the
orphan list when destroy it if the list is not empty.
Signed-off-by: yi zhang
---
fs/ext4/super.c | 1 +
fs/inode.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/fs/ext4/super.c b/fs/ext4/super.c
index 52b0530..617327e 100644
--- a/fs/ext4/super.c
+++ b/fs/ext4/super.c
@@ -975,6 +975,7 @@ static void ext4_destroy_inode(struct inode *inode)
EXT4_I(inode), sizeof(struct ext4_inode_info),
true);
dump_stack();
+ ext4_orphan_del(NULL, inode);
}
call_rcu(&inode->i_rcu, ext4_i_callback);
}
diff --git a/fs/inode.c b/fs/inode.c
index 88110fd..079d383 100644
--- a/fs/inode.c
+++ b/fs/inode.c
@@ -279,7 +279,10 @@ static void destroy_inode(struct inode *inode)
*/
void drop_nlink(struct inode *inode)
{
- WARN_ON(inode->i_nlink == 0);
+ if (WARN(inode->i_nlink == 0, "inode %lu nlink"
+ " is already 0", inode->i_ino))
+ return;
+
inode->__i_nlink--;
if (!inode->i_nlink)
atomic_long_inc(&inode->i_sb->s_remove_count);
--
2.5.0
Re: [RFC PATCH] mm, memcg: fix (Re: OOM: Better, but still there on)
On Fri 23-12-16 23:26:00, Nils Holland wrote:
> On Fri, Dec 23, 2016 at 03:47:39PM +0100, Michal Hocko wrote:
> >
> > Nils, even though this is still highly experimental, could you give it a
> > try please?
>
> Yes, no problem! So I kept the very first patch you sent but had to
> revert the latest version of the debugging patch (the one in
> which you added the "mm_vmscan_inactive_list_is_low" event) because
> otherwise the patch you just sent wouldn't apply. Then I rebooted with
> memory cgroups enabled again, and the first thing that strikes the eye
> is that I get this during boot:
>
> [1.568174] [ cut here ]
> [1.568327] WARNING: CPU: 0 PID: 1 at mm/memcontrol.c:1032
> mem_cgroup_update_lru_size+0x118/0x130
> [1.568543] mem_cgroup_update_lru_size(f4406400, 2, 1): lru_size 0 but not
> empty
Ohh, I can see what is wrong! a) there is a bug in the accounting in
my patch (I double account) and b) the detection for the empty list
cannot work after my change because per node zone will not match per
zone statistics. The updated patch is below. So I hope my brain already
works after it's been mostly off last few days...
---
>From 397adf46917b2d9493180354a7b0182aee280a8b Mon Sep 17 00:00:00 2001
From: Michal Hocko
Date: Fri, 23 Dec 2016 15:11:54 +0100
Subject: [PATCH] mm, memcg: fix the active list aging for lowmem requests when
memcg is enabled
Nils Holland has reported unexpected OOM killer invocations with 32b
kernel starting with 4.8 kernels
kworker/u4:5 invoked oom-killer:
gfp_mask=0x2400840(GFP_NOFS|__GFP_NOFAIL), nodemask=0, order=0, oom_score_adj=0
kworker/u4:5 cpuset=/ mems_allowed=0
CPU: 1 PID: 2603 Comm: kworker/u4:5 Not tainted 4.9.0-gentoo #2
[...]
Mem-Info:
active_anon:58685 inactive_anon:90 isolated_anon:0
active_file:274324 inactive_file:281962 isolated_file:0
unevictable:0 dirty:649 writeback:0 unstable:0
slab_reclaimable:40662 slab_unreclaimable:17754
mapped:7382 shmem:202 pagetables:351 bounce:0
free:206736 free_pcp:332 free_cma:0
Node 0 active_anon:234740kB inactive_anon:360kB active_file:1097296kB
inactive_file:1127848kB unevictable:0kB isolated(anon):0kB isolated(file):0kB
mapped:29528kB dirty:2596kB writeback:0kB shmem:0kB shmem_thp: 0kB
shmem_pmdmapped: 184320kB anon_thp: 808kB writeback_tmp:0kB unstable:0kB
pages_scanned:0 all_unreclaimable? no
DMA free:3952kB min:788kB low:984kB high:1180kB active_anon:0kB
inactive_anon:0kB active_file:7316kB inactive_file:0kB unevictable:0kB
writepending:96kB present:15992kB managed:15916kB mlocked:0kB
slab_reclaimable:3200kB slab_unreclaimable:1408kB kernel_stack:0kB
pagetables:0kB bounce:0kB free_pcp:0kB local_pcp:0kB free_cma:0kB
lowmem_reserve[]: 0 813 3474 3474
Normal free:41332kB min:41368kB low:51708kB high:62048kB
active_anon:0kB inactive_anon:0kB active_file:532748kB inactive_file:44kB
unevictable:0kB writepending:24kB present:897016kB managed:836248kB mlocked:0kB
slab_reclaimable:159448kB slab_unreclaimable:69608kB kernel_stack:1112kB
pagetables:1404kB bounce:0kB free_pcp:528kB local_pcp:340kB free_cma:0kB
lowmem_reserve[]: 0 0 21292 21292
HighMem free:781660kB min:512kB low:34356kB high:68200kB
active_anon:234740kB inactive_anon:360kB active_file:557232kB
inactive_file:1127804kB unevictable:0kB writepending:2592kB present:2725384kB
managed:2725384kB mlocked:0kB slab_reclaimable:0kB slab_unreclaimable:0kB
kernel_stack:0kB pagetables:0kB bounce:0kB free_pcp:800kB local_pcp:608kB
free_cma:0kB
the oom killer is clearly pre-mature because there there is still a
lot of page cache in the zone Normal which should satisfy this lowmem
request. Further debugging has shown that the reclaim cannot make any
forward progress because the page cache is hidden in the active list
which doesn't get rotated because inactive_list_is_low is not memcg
aware.
It simply subtracts per-zone highmem counters from the respective
memcg's lru sizes which doesn't make any sense. We can simply end up
always seeing the resulting active and inactive counts 0 and return
false. This issue is not limited to 32b kernels but in practice the
effect on systems without CONFIG_HIGHMEM would be much harder to notice
because we do not invoke the OOM killer for allocations requests
targeting < ZONE_NORMAL.
Fix the issue by tracking per zone lru page counts in mem_cgroup_per_node
and subtract per-memcg highmem counts when memcg is enabled. Introduce
helper lruvec_zone_lru_size which redirects to either zone counters or
mem_cgroup_get_zone_lru_size when appropriate.
We are loosing empty LRU but non-zero lru size detection introduced by
ca707239e8a7 ("mm: update_lru_size warn and reset bad lru_size") because
of the inherent zone vs. node discrepancy.
Fixes: f8d1a31163fc ("mm: consider whether to decivate based on eligible zones
inactive ratio")
Cc: stable # 4.8+
Reported-by: Nils Holla
Re: [lkp-developer] [mm, memcg] d18e2b2aca: WARNING:at_mm/memcontrol.c:#mem_cgroup_update_lru_size
On Mon 26-12-16 13:26:51, Michal Hocko wrote: > On Mon 26-12-16 06:25:56, kernel test robot wrote: [...] > > [ 95.226364] init: tty6 main process (990) killed by TERM signal > > [ 95.314020] init: plymouth-upstart-bridge main process (1039) terminated > > with status 1 > > [ 97.588568] [ cut here ] > > [ 97.594364] WARNING: CPU: 0 PID: 1055 at mm/memcontrol.c:1032 > > mem_cgroup_update_lru_size+0xdd/0x12b > > [ 97.606654] mem_cgroup_update_lru_size(40297f00, 0, -1): lru_size 1 but > > empty > > [ 97.615140] Modules linked in: > > [ 97.618834] CPU: 0 PID: 1055 Comm: killall5 Not tainted > > 4.9.0-mm1-00095-gd18e2b2 #82 > > [ 97.628008] Call Trace: > > [ 97.631025] dump_stack+0x16/0x18 > > [ 97.635107] __warn+0xaf/0xc6 > > [ 97.638729] ? mem_cgroup_update_lru_size+0xdd/0x12b > > Do you have the full backtrace? It's not needed. I found the bug in my patch and it should be fixed by the updated patch http://lkml.kernel.org/r/20161226124839.gb20...@dhcp22.suse.cz -- Michal Hocko SUSE Labs
Re: PROBLEM: Kernel BUG with raid5 soft + Xen + DRBD - invalid opcode
Hi guys, I've tested the same set-up except with a RAID 1 Soft Array, in this case I get no issue at all. It's definitely a raid 5 problem. As requested, I've tested re-creating the RAID 5 array (just to be sure), issue remains the same, even with metadata 0.90 or metadata 1.2. Thanks, Le 23/12/2016 19:25, MasterPrenium a écrit : Hello Guys, I've having some trouble on a new system I'm setting up. I'm getting a kernel BUG message, seems to be related with the use of Xen (when I boot the system _without_ Xen, I don't get any crash). Here is configuration : - 3x Hard Drives running on RAID 5 Software raid created by mdadm - On top of it, DRBD for replication over another node (Active/passive cluster) - On top of it, a BTRFS FileSystem with a few subvolumes - On top of it, XEN VMs running. The BUG is happening when I'm making "huge" I/O (20MB/s with a rsync for example) on the RAID5 stack. I've to reset system to make it work again. Reproducible : ALWAYS (making the i/o, it crash in 2-5mins). Also reproducible on another system with the same hardware. Kernel versions impacted (at least): kernel-4.4.26, kernel-4.8.15, kernel-4.9.0 Here dmesg errors : [ 937.123220] [ cut here ] [ 937.127549] kernel BUG at drivers/md/raid5.c:527! [ 937.131891] invalid opcode: [#1] SMP [ 937.136216] Modules linked in: x86_pkg_temp_thermal coretemp crc32c_intel aesni_intel aes_x86_64 ablk_helper mei_me mei mpt3sas [ 937.145665] CPU: 2 PID: 9704 Comm: kworker/u16:8 Not tainted 4.9.0-gentoo #2 [ 937.150293] Hardware name: Supermicro Super Server/X10SDV-4C-7TP4F, BIOS 1.0b 11/21/2016 [ 937.155531] Workqueue: drbd0_submit do_submit [ 937.160506] task: 88026b0b2940 task.stack: c9000a66c000 [ 937.164115] RIP: e030:[] [] raid5_get_active_stripe+0x5e1/0x670 [ 937.169584] RSP: e02b:c9000a66fa58 EFLAGS: 00010086 [ 937.175070] RAX: RBX: 880249d5 RCX: 8802648bb5d0 [ 937.180640] RDX: RSI: 0001 RDI: 880249d5 [ 937.185505] RBP: c9000a66faf0 R08: 8801f4813288 R09: [ 937.190631] R10: 0288 R11: R12: [ 937.196030] R13: 1e773e88 R14: 880249d5 R15: 8802648bb400 [ 937.202011] FS: () GS:880270c8() knlGS:880270c8 [ 937.206628] CS: e033 DS: ES: CR0: 80050033 [ 937.212372] CR2: 7f68a101b520 CR3: 000257875000 CR4: 00042660 [ 937.217538] Stack: [ 937.223361] 8802648bb400 880269550b40 000166cf3800 [ 937.229103] 1e773e88 8802648bb5d0 0001 [ 937.233707] 8802648bb40c 0001 c9000a66faf0 880047cba958 [ 937.239736] Call Trace: [ 937.244406] [] raid5_make_request+0x17d/0xdf0 [ 937.250345] [] ? wake_up_atomic_t+0x30/0x30 [ 937.256173] [] md_make_request+0xe3/0x220 [ 937.261031] [] generic_make_request+0xcb/0x1a0 [ 937.265615] [] drbd_send_and_submit+0x497/0x1310 [ 937.271605] [] ? wake_up_atomic_t+0x30/0x30 [ 937.276726] [] send_and_submit_pending+0x6a/0x90 [ 937.282292] [] do_submit+0x463/0x550 [ 937.288333] [] ? wake_up_atomic_t+0x30/0x30 [ 937.293205] [] process_one_work+0x170/0x420 [ 937.298982] [] worker_thread+0x123/0x500 [ 937.304154] [] ? process_one_work+0x420/0x420 [ 937.310314] [] ? process_one_work+0x420/0x420 [ 937.316013] [] kthread+0xc5/0xe0 [ 937.320918] [] ? __switch_to+0x355/0x7a0 [ 937.327029] [] ? kthread_park+0x60/0x60 [ 937.331994] [] ret_from_fork+0x25/0x30 [ 937.338068] Code: 85 d0 fb ff ff f0 41 80 8f 98 02 00 00 04 e9 c2 fb ff ff f3 90 41 8b 47 70 a8 01 75 f6 89 45 a4 e9 e2 fd ff ff 0f 0b 0f 0b 0f 0b <0f> 0b 49 89 d6 e9 e1 fa ff ff 49 8b 82 e8 01 00 00 4d 8b 8a e0 [ 937.349579] RIP [] raid5_get_active_stripe+0x5e1/0x670 [ 937.355290] RSP [ 937.386587] ---[ end trace b870be01f61065a5 ]--- [ 941.931453] BUG: unable to handle kernel NULL pointer dereference at (null) [ 941.937139] IP: [] __wake_up_common+0x26/0x80 [ 941.943106] PGD 252dde067 [ 941.943219] PUD 252ee7067 [ 941.950107] PMD 0 [ 941.956080] Oops: [#2] SMP [ 941.961919] Modules linked in: x86_pkg_temp_thermal coretemp crc32c_intel aesni_intel aes_x86_64 ablk_helper mei_me mei mpt3sas [ 941.974933] CPU: 2 PID: 9704 Comm: kworker/u16:8 Tainted: G D 4.9.0-gentoo #2 [ 941.982080] Hardware name: Supermicro Super Server/X10SDV-4C-7TP4F, BIOS 1.0b 11/21/2016 [ 941.989296] task: 88026b0b2940 task.stack: c9000a66c000 [ 941.996831] RIP: e030:[] [] __wake_up_common+0x26/0x80 [ 942.004391] RSP: e02b:c9000a66fe50 EFLAGS: 00010086 [ 942.011818] RAX: 0200 RBX: c9000a66ff18 RCX: [ 942.019290] RDX: RSI: 0003 RDI: c9000a66ff18 [ 942.026779] RBP: c9000a66fe88 R08: R09: 00
[PATCH 1/2] scsi: qla2xxx: silent -Wformat-security warning
qla24xx_enable_msix() calls scnprintf() with a non-literal format string. This makes clang report -Wformat-security warnings when compiling this function: drivers/scsi/qla2xxx/qla_isr.c:3083:7: error: format string is not a string literal (potentially insecure) [-Werror,-Wformat-security] msix_entries[i].name); ^~~~ drivers/scsi/qla2xxx/qla_isr.c:3083:7: note: treat the string as an argument to avoid this msix_entries[i].name); ^ "%s", drivers/scsi/qla2xxx/qla_isr.c:3119:7: error: format string is not a string literal (potentially insecure) [-Werror,-Wformat-security] msix_entries[QLA_ATIO_VECTOR].name); ^~ drivers/scsi/qla2xxx/qla_isr.c:3119:7: note: treat the string as an argument to avoid this msix_entries[QLA_ATIO_VECTOR].name); ^ "%s", Even though msix_entries[...].name are initialized as literal strings with no % character and are never modified, introduce a "%s" format parameter in order to silent this -Wformat-security warning and make clang able to detect at compile time real bugs related to string formatting. Signed-off-by: Nicolas Iooss --- drivers/scsi/qla2xxx/qla_isr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c index 5093ca9b02ec..474b415217df 100644 --- a/drivers/scsi/qla2xxx/qla_isr.c +++ b/drivers/scsi/qla2xxx/qla_isr.c @@ -3080,7 +3080,7 @@ qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp) qentry->handle = rsp; rsp->msix = qentry; scnprintf(qentry->name, sizeof(qentry->name), - msix_entries[i].name); + "%s", msix_entries[i].name); if (IS_P3P_TYPE(ha)) ret = request_irq(qentry->vector, qla82xx_msix_entries[i].handler, @@ -3116,7 +3116,7 @@ qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp) rsp->msix = qentry; qentry->handle = rsp; scnprintf(qentry->name, sizeof(qentry->name), - msix_entries[QLA_ATIO_VECTOR].name); + "%s", msix_entries[QLA_ATIO_VECTOR].name); qentry->in_use = 1; ret = request_irq(qentry->vector, msix_entries[QLA_ATIO_VECTOR].handler, -- 2.11.0
[PATCH 2/2] scsi: qla2xxx: make msix_entries const
msix_entries and qla82xx_msix_entries arrays are never modified in
drivers/scsi/qla2xxx/qla_isr.c. Move their contents to read-only data.
Signed-off-by: Nicolas Iooss
---
drivers/scsi/qla2xxx/qla_isr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c
index 474b415217df..b9c113e47346 100644
--- a/drivers/scsi/qla2xxx/qla_isr.c
+++ b/drivers/scsi/qla2xxx/qla_isr.c
@@ -3003,14 +3003,14 @@ struct qla_init_msix_entry {
irq_handler_t handler;
};
-static struct qla_init_msix_entry msix_entries[] = {
+static const struct qla_init_msix_entry msix_entries[] = {
{ "qla2xxx (default)", qla24xx_msix_default },
{ "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
{ "qla2xxx (atio_q)", qla83xx_msix_atio_q },
{ "qla2xxx (qpair_multiq)", qla2xxx_msix_rsp_q },
};
-static struct qla_init_msix_entry qla82xx_msix_entries[] = {
+static const struct qla_init_msix_entry qla82xx_msix_entries[] = {
{ "qla2xxx (default)", qla82xx_msix_default },
{ "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
};
@@ -3284,7 +3284,7 @@ qla2x00_free_irqs(scsi_qla_host_t *vha)
int qla25xx_request_irq(struct qla_hw_data *ha, struct qla_qpair *qpair,
struct qla_msix_entry *msix, int vector_type)
{
- struct qla_init_msix_entry *intr = &msix_entries[vector_type];
+ const struct qla_init_msix_entry *intr = &msix_entries[vector_type];
scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
int ret;
--
2.11.0
[PATCH 1/1] [media] v4l: rcar_fdp1: use %4.4s to format a 4-byte string
Using %4s to format f->fmt.pix_mp.pixelformat in fdp1_try_fmt() and fdp1_s_fmt() may lead to more characters being printed (when the byte following field pixelformat is not zero). Add ".4" to the format specifier to limit the number of printed characters to four. The resulting format specifier "%4.4s" is also used by other media drivers to print pixelformat value. Signed-off-by: Nicolas Iooss --- drivers/media/platform/rcar_fdp1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/rcar_fdp1.c b/drivers/media/platform/rcar_fdp1.c index 674cc1309b43..42f25d241edd 100644 --- a/drivers/media/platform/rcar_fdp1.c +++ b/drivers/media/platform/rcar_fdp1.c @@ -1596,7 +1596,7 @@ static int fdp1_try_fmt(struct file *file, void *priv, struct v4l2_format *f) else fdp1_try_fmt_capture(ctx, NULL, &f->fmt.pix_mp); - dprintk(ctx->fdp1, "Try %s format: %4s (0x%08x) %ux%u field %u\n", + dprintk(ctx->fdp1, "Try %s format: %4.4s (0x%08x) %ux%u field %u\n", V4L2_TYPE_IS_OUTPUT(f->type) ? "output" : "capture", (char *)&f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.field); @@ -1671,7 +1671,7 @@ static int fdp1_s_fmt(struct file *file, void *priv, struct v4l2_format *f) fdp1_set_format(ctx, &f->fmt.pix_mp, f->type); - dprintk(ctx->fdp1, "Set %s format: %4s (0x%08x) %ux%u field %u\n", + dprintk(ctx->fdp1, "Set %s format: %4.4s (0x%08x) %ux%u field %u\n", V4L2_TYPE_IS_OUTPUT(f->type) ? "output" : "capture", (char *)&f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.field); -- 2.11.0
[PATCH] drivers: watchdog: constify watchdog_info structures
Declare watchdog_info structures as const as they are only stored in the
info field of watchdog_device structures. This field is of type const
struct watchdog_info *, so watchdog_info structures having this property
can be declared const too.
Done using Coccinelle:
@r1 disable optional_qualifier@
identifier i;
position p;
@@
static struct watchdog_info i@p={...};
@ok@
identifier r1.i;
position p;
struct watchdog_device obj;
@@
obj.info=&i@p;
@bad@
position p!={r1.p,ok.p};
identifier r1.i;
@@
i@p
@depends on !bad disable optional_qualifier@
identifier r1.i;
@@
+const
struct watchdog_info i;
Size details:
textdata bss dec hex filename
1882 249 02131 853 drivers/watchdog/bcm7038_wdt.o
1938 193 02131 853 drivers/watchdog/bcm7038_wdt.o
1673 720 82401 961 drivers/watchdog/bcm_kona_wdt.o
1729 656 82393 959 drivers/watchdog/bcm_kona_wdt.o
2370 760 83138 c42 drivers/watchdog/cadence_wdt.o
2434 704 83146 c4a drivers/watchdog/cadence_wdt.o
1448 248 01696 6a0 drivers/watchdog/da9052_wdt.o
1512 192 01704 6a8 drivers/watchdog/da9052_wdt.o
1077 249 01326 52e drivers/watchdog/da9055_wdt.o
1141 193 01334 536 drivers/watchdog/da9055_wdt.o
1416 544 121972 7b4 drivers/watchdog/digicolor_wdt.o
1480 480 121972 7b4 drivers/watchdog/digicolor_wdt.o
2653 249 42906 b5a drivers/watchdog/imgpdc_wdt.o
2717 193 42914 b62 drivers/watchdog/imgpdc_wdt.o
2923 257 43184 c70 drivers/watchdog/kempld_wdt.o
2987 201 43192 c78 drivers/watchdog/kempld_wdt.o
2469 249 202738 ab2 drivers/watchdog/lpc18xx_wdt.o
2533 193 202746 aba drivers/watchdog/lpc18xx_wdt.o
1119 249 41372 55c drivers/watchdog/rn5t618_wdt.o
1183 193 41380 564 drivers/watchdog/rn5t618_wdt.o
1218 528 81754 6da drivers/watchdog/softdog.o
1282 464 81754 6da drivers/watchdog/softdog.o
2934 249 243207 c87 drivers/watchdog/w83627hf_wdt.o
2998 185 243207 c87 drivers/watchdog/w83627hf_wdt.o
Signed-off-by: Bhumika Goyal
---
drivers/watchdog/bcm7038_wdt.c | 2 +-
drivers/watchdog/bcm_kona_wdt.c | 2 +-
drivers/watchdog/cadence_wdt.c | 2 +-
drivers/watchdog/da9052_wdt.c| 2 +-
drivers/watchdog/da9055_wdt.c| 2 +-
drivers/watchdog/digicolor_wdt.c | 2 +-
drivers/watchdog/imgpdc_wdt.c| 2 +-
drivers/watchdog/kempld_wdt.c| 2 +-
drivers/watchdog/lpc18xx_wdt.c | 2 +-
drivers/watchdog/rn5t618_wdt.c | 2 +-
drivers/watchdog/sbsa_gwdt.c | 2 +-
drivers/watchdog/w83627hf_wdt.c | 2 +-
12 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/watchdog/bcm7038_wdt.c b/drivers/watchdog/bcm7038_wdt.c
index e238df4..37c6a49 100644
--- a/drivers/watchdog/bcm7038_wdt.c
+++ b/drivers/watchdog/bcm7038_wdt.c
@@ -101,7 +101,7 @@ static unsigned int bcm7038_wdt_get_timeleft(struct
watchdog_device *wdog)
return time_left / wdt->rate;
}
-static struct watchdog_info bcm7038_wdt_info = {
+static const struct watchdog_info bcm7038_wdt_info = {
.identity = "Broadcom BCM7038 Watchdog Timer",
.options= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE
diff --git a/drivers/watchdog/bcm_kona_wdt.c b/drivers/watchdog/bcm_kona_wdt.c
index e0c9842..76b0080 100644
--- a/drivers/watchdog/bcm_kona_wdt.c
+++ b/drivers/watchdog/bcm_kona_wdt.c
@@ -274,7 +274,7 @@ static int bcm_kona_wdt_stop(struct watchdog_device *wdog)
.get_timeleft = bcm_kona_wdt_get_timeleft,
};
-static struct watchdog_info bcm_kona_wdt_info = {
+static const struct watchdog_info bcm_kona_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.identity = "Broadcom Kona Watchdog Timer",
diff --git a/drivers/watchdog/cadence_wdt.c b/drivers/watchdog/cadence_wdt.c
index 98acef7..8d61e8b 100644
--- a/drivers/watchdog/cadence_wdt.c
+++ b/drivers/watchdog/cadence_wdt.c
@@ -262,7 +262,7 @@ static irqreturn_t cdns_wdt_irq_handler(int irq, void
*dev_id)
* Info structure used to indicate the features supported by the device
* to the upper layers. This is defined in watchdog.h header file.
*/
-static struct watchdog_info cdns_wdt_info = {
+static const struct watchdog_info cdns_wdt_info = {
.identity = "cdns_wdt watchdog",
.options= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
diff --git a/drivers/watchdog/da9052_wdt.c b/drivers/watchdog/da9052_wdt.c
index 2fc19a3..d86a57e 100644
--- a/drivers/watchdog/da9052_wdt.c
+++ b/drivers/watchdog/da9052_wdt.c
@@
Re: [PATCH 0/4] PCI: exynos: cleans the minor things
On Tuesday, December 20, 2016 12:36 PM, Bartlomiej Zolnierkiewicz wrote: > > Hi, > > On Monday, December 19, 2016 05:16:10 PM Jaehoon Chung wrote: > > Current pci-exnoys.c is used for only EXYNOS5440. > > Even if there is no use-case, just cleans the codes for maintaining. > > > > In future, I will upstream for Exynso5433(TM2). > > Before sending patches for exynos5433, i want to reuse the some codse in > pic-exynos.c. > > This patch is for perparing it. > > > > My Final goal is to apply the pcie-exynos5433 into v4.11. > > > > Jaehoon Chung (4): > > PCI: exynos: replace to one register accessor from each accessors > > PCI: exynos: Remove the unnecessary variables > > PCI: exynos: Use the bitops API to operate the bit shifting > > PCI: exynos: remove the duplicated codes > > > > drivers/pci/host/pci-exynos.c | 260 +++ > --- > > 1 file changed, 116 insertions(+), 144 deletions(-) > > Reviewed-by: Bartlomiej Zolnierkiewicz Acked-by: Jingoo Han Best regards, Jingoo Han > > Best regards, > -- > Bartlomiej Zolnierkiewicz > Samsung R&D Institute Poland > Samsung Electronics
[PATCH 1/1] drm/i915/gvt: verify functions types in new_mmio_info()
The current prototype of new_mmio_info() uses void* for parameters read
and write, which are functions with precise calling conventions
(argument types and return type). Write down these conventions in
new_mmio_info() definition.
This has been reported by the following warnings when clang is used to
build the kernel:
drivers/gpu/drm/i915/gvt/handlers.c:124:21: error: pointer type
mismatch ('void *' and 'int (*)(struct intel_vgpu *, unsigned int,
void *, unsigned int)') [-Werror,-Wpointer-type-mismatch]
info->read = read ? read : intel_vgpu_default_mmio_read;
^
drivers/gpu/drm/i915/gvt/handlers.c:125:23: error: pointer type
mismatch ('void *' and 'int (*)(struct intel_vgpu *, unsigned int,
void *, unsigned int)') [-Werror,-Wpointer-type-mismatch]
info->write = write ? write : intel_vgpu_default_mmio_write;
^ ~ ~
This allows the compiler to detect that sbi_ctl_mmio_write() returns a
"bool" value instead of an expected "int" one. Fix this.
Signed-off-by: Nicolas Iooss
---
drivers/gpu/drm/i915/gvt/handlers.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index 522809710312..052e57124c0a 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -93,7 +93,8 @@ static void write_vreg(struct intel_vgpu *vgpu, unsigned int
offset,
static int new_mmio_info(struct intel_gvt *gvt,
u32 offset, u32 flags, u32 size,
u32 addr_mask, u32 ro_mask, u32 device,
- void *read, void *write)
+ int (*read)(struct intel_vgpu *, unsigned int, void *, unsigned
int),
+ int (*write)(struct intel_vgpu *, unsigned int, void *,
unsigned int))
{
struct intel_gvt_mmio_info *info, *p;
u32 start, end, i;
@@ -974,7 +975,7 @@ static int sbi_data_mmio_read(struct intel_vgpu *vgpu,
unsigned int offset,
return 0;
}
-static bool sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
+static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
u32 data;
--
2.11.0
RE: [RFC PATCH 4/7] HW Filter Initialization code and register access APIs
Hi Sunil,
Thanks for review. Answers inline.
Thanks,
Satha.
-Original Message-
From: Sunil Kovvuri [mailto:sunil.kovv...@gmail.com]
Sent: Wednesday, December 21, 2016 4:36 AM
To: Koteshwar Rao, Satha
Cc: LKML; Goutham, Sunil; Robert Richter; David S. Miller; Daney, David;
Vatsavayi, Raghu; Chickles, Derek; Romanov, Philip; Linux Netdev List; LAKML
Subject: Re: [RFC PATCH 4/7] HW Filter Initialization code and register access
APIs
On Wed, Dec 21, 2016 at 2:16 PM, Satha Koteswara Rao
wrote:
> ---
> drivers/net/ethernet/cavium/thunder/pf_reg.c | 660
> +++
> 1 file changed, 660 insertions(+)
> create mode 100644 drivers/net/ethernet/cavium/thunder/pf_reg.c
>
> diff --git a/drivers/net/ethernet/cavium/thunder/pf_reg.c
> b/drivers/net/ethernet/cavium/thunder/pf_reg.c
Sunil>>
From the file name 'pf_reg.c', what is PF here ?
TNS is not a SRIOV device right ?
SATHA>>> PF stands for acted Physical Function. PF referred in file name
confuses common usage of NIC PF, planning to change file name in next version
Yes this block does not support SRIOV
> new file mode 100644
> index 000..1f95c7f
> --- /dev/null
> +++ b/drivers/net/ethernet/cavium/thunder/pf_reg.c
> @@ -0,0 +1,660 @@
> +/*
> + * Copyright (C) 2015 Cavium, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> +modify it
> + * under the terms of version 2 of the GNU General Public License
> + * as published by the Free Software Foundation.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "pf_globals.h"
> +#include "pf_locals.h"
> +#include "tbl_access.h"
> +#include "linux/lz4.h"
> +
> +struct tns_table_s tbl_info[TNS_MAX_TABLE];
> +
> +#define TNS_TDMA_SST_ACC_CMD_ADDR 0x84200270ull
> +
> +#define BAR0_START 0x8420
> +#define BAR0_END 0x8420
> +#define BAR0_SIZE (64 * 1024)
> +#define BAR2_START 0x84204000
> +#define BAR2_END 0x84207FFF
> +#define BAR2_SIZE (1024 * 1024 * 1024)
> +
> +#define NODE1_BAR0_START 0x9420
> +#define NODE1_BAR0_END 0x9420
> +#define NODE1_BAR0_SIZE (64 * 1024)
> +#define NODE1_BAR2_START 0x94204000
> +#define NODE1_BAR2_END 0x94207FFF
> +#define NODE1_BAR2_SIZE (1024 * 1024 * 1024)
Sunil>> This is absurd, why are you using hardcoded HW addresses,
why not use TNS device's PCI BARs.
SATHA>>> Due to various considerations TNS is not treated as PCI device by our
driver (probably will be even disabled as such later in the FW), HW addresses
mentioned was register base address as per HRM.
Macro name with BAR_X confuses, will change this in my next revision.
> +/* Allow a max of 4 chunks for the Indirect Read/Write */ #define
> +MAX_SIZE (64 * 4) #define CHUNK_SIZE (64)
> +/* To protect register access */
> +spinlock_t pf_reg_lock;
> +
> +u64 iomem0;
> +u64 iomem2;
> +u8 tns_enabled;
> +u64 node1_iomem0;
> +u64 node1_iomem2;
> +u8 node1_tns;
> +int n1_tns;
Sunil>> A simple structure would have nice instead of so many global variables.
SATHA>>> Good suggestion, will do this in next version
> +
> +int tns_write_register_indirect(int node_id, u64 address, u8 size,
> + u8 *kern_buffer) {
> + union tns_tdma_sst_acc_cmd acccmd;
> + union tns_tdma_sst_acc_stat_t accstat;
> + union tns_acc_data data;
> + int i, j, w = 0;
> + int cnt = 0;
> + u32 *dataw = NULL;
> + int temp = 0;
> + int k = 0;
> + int chunks = 0;
> + u64 acccmd_address;
> + u64 lmem2 = 0, lmem0 = 0;
> +
> + if (size == 0 || !kern_buffer) {
> + filter_dbg(FERR, "%s data size cannot be zero\n", __func__);
> + return TNS_ERROR_INVALID_ARG;
> + }
> + if (size > MAX_SIZE) {
> + filter_dbg(FERR, "%s Max allowed size exceeded\n", __func__);
> + return TNS_ERROR_DATA_TOO_LARGE;
> + }
> + if (node_id) {
> + lmem0 = node1_iomem0;
> + lmem2 = node1_iomem2;
> + } else {
> + lmem0 = iomem0;
> + lmem2 = iomem2;
> + }
> +
> + chunks = ((size + (CHUNK_SIZE - 1)) / CHUNK_SIZE);
> + acccmd_address = (address & 0x);
> + spin_lock_bh(&pf_reg_lock);
> +
> + for (k = 0; k < chunks; k++) {
Sunil>> Why not use some proper variable names, instead of i,j,k,w,
temp e.t.c e.t.c
SATHA>>> Will do this in next version
> + /* Should never happen */
> + if (size < 0) {
> + filter_dbg(FERR, "%s size mismatch [CHUNK %d]\n",
> + __func__, k);
> + break;
> + }
> + temp = (size > CHUNK_SIZE) ? CHUNK_SIZE : size;
> + dataw = (u32 *)(kern_bu
RE: [RFC PATCH 5/7] Multiple VF's grouped together under single physical port called PF group PF Group maintainance API's
Thanks for suggestion. Will clean up code in next revision
Thanks,
Satha
-Original Message-
From: Sunil Kovvuri [mailto:sunil.kovv...@gmail.com]
Sent: Wednesday, December 21, 2016 4:44 AM
To: Koteshwar Rao, Satha
Cc: LKML; Goutham, Sunil; Robert Richter; David S. Miller; Daney, David;
Vatsavayi, Raghu; Chickles, Derek; Romanov, Philip; Linux Netdev List; LAKML
Subject: Re: [RFC PATCH 5/7] Multiple VF's grouped together under single
physical port called PF group PF Group maintainance API's
On Wed, Dec 21, 2016 at 2:16 PM, Satha Koteswara Rao
wrote:
> +struct tns_global_st {
> + u64 magic;
> + char version[16];
> + u64 reg_cnt;
> + struct table_static_s tbl_info[TNS_MAX_TABLE]; };
> +
> +#define PF_COUNT 3
> +#define PF_1 0
> +#define PF_2 64
> +#define PF_3 96
> +#define PF_END 128
Some comments please ... what is 0, 64, 96 ??
You can read PCI_SRIOV_TOTAL_VF from PCI config space instead of defining
PF_END with 128.
RE: [RFC PATCH 1/7] PF driver modified to enable HW filter support, changes works in backward compatibility mode Enable required things in Makefile Enable LZ4 dependecy inside config file
Responses inline
Thanks,
Satha
-Original Message-
From: Sunil Kovvuri [mailto:sunil.kovv...@gmail.com]
Sent: Wednesday, December 21, 2016 5:05 AM
To: Koteshwar Rao, Satha
Cc: LKML; Goutham, Sunil; Robert Richter; David S. Miller; Daney, David;
Vatsavayi, Raghu; Chickles, Derek; Romanov, Philip; Linux Netdev List; LAKML
Subject: Re: [RFC PATCH 1/7] PF driver modified to enable HW filter support,
changes works in backward compatibility mode Enable required things in Makefile
Enable LZ4 dependecy inside config file
>
> #define NIC_MAX_RSS_HASH_BITS 8
> #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
> +#define NIC_TNS_RSS_IDR_TBL_SIZE 5
So you want to use only 5 queues per VF when TNS is enabled, is it ??
There are 4096 RSS indices in total, for each VF you can use max 32.
I guess you wanted to set no of hash bits to 5 instead of table size.
SATHA>>> We enabled 8 queues for VF. Yes Macro name misleads it has to be hash
bits, will change this in next version
> #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */
>
> struct nicvf_rss_info {
> @@ -255,74 +258,6 @@ struct nicvf_drv_stats {
> struct u64_stats_sync syncp;
> };
>
> -struct nicvf {
> - struct nicvf*pnicvf;
> - struct net_device *netdev;
> - struct pci_dev *pdev;
> - void __iomem*reg_base;
Didn't get why you moved this structure to the end of file.
Looks like an unnecessary modification.
SATHA>>> Previously we have some dependency, we look into this, and address in
next verison
> +static unsigned int num_vfs;
> +module_param(num_vfs, uint, 0644);
> +MODULE_PARM_DESC(num_vfs, "Non zero positive value, specifies number
> +of VF's per physical port");
So what if driver is built-in instead of module, I can't use TNS is it ?
SATHA>>> Still you can enable this special features by passing boot argument
"nicpf.num_vfs=X"
>
> +/* Set RBDR Backpressure (RBDR_BP) and CQ backpressure (CQ_BP) of
> +vnic queues
> + * to 129 each
Why 129 ??
RBDR minimum size is 8K buffers, why you want to assert BP when still ~4K
buffers are available. Isn't 4K a huge number to start asserting backpressure ?
SATHA>>> As CQ count was 4K entries, I used same BP value for both, will
address this in next version
RE: [RFC PATCH 0/7] ThunderX Embedded switch support
Hi Sunil, In RFC cover letter we explained the feature details, files organized based on their supporting functionality, let me know if you are interested in any specific details Thanks, Satha -Original Message- From: Sunil Kovvuri [mailto:sunil.kovv...@gmail.com] Sent: Wednesday, December 21, 2016 4:03 AM To: Koteshwar Rao, Satha Cc: LKML; Goutham, Sunil; Robert Richter; David S. Miller; Daney, David; Vatsavayi, Raghu; Chickles, Derek; Romanov, Philip; Linux Netdev List; LAKML Subject: Re: [RFC PATCH 0/7] ThunderX Embedded switch support It would be easier for anyone to review if you prepare patches based on features rather than based on modifications to files. Thanks, Sunil.
Re: Linux 4.10-rc1
On Mon, Dec 26, 2016 at 05:45:10PM +0800, Hanjun Guo wrote: > On 2016/12/26 17:18, Al Viro wrote: > > On Mon, Dec 26, 2016 at 05:05:37PM +0800, Kefeng Wang wrote: > >> It looks like we need revert the changes from assembly files. > > I tested Kefeng's patch and works. more comments below. > > > Better yet, split the damn thing in two and include the asm-only part. > > split will cause other places for building errors, because there is no > > -#ifndef __ASSEMBLY__ Huh? It's included only from assembler files, so what would use the other parts?
RE: [RFC PATCH 3/7] Enable pause frame support
Thanks Sunil, will fix this in next version
Thanks,
Satha
From: Goutham, Sunil
Sent: Wednesday, December 21, 2016 1:20 AM
To: Koteshwar Rao, Satha; linux-kernel@vger.kernel.org
Cc: r...@kernel.org; da...@davemloft.net; Daney, David; Vatsavayi, Raghu;
Chickles, Derek; Romanov, Philip; net...@vger.kernel.org;
linux-arm-ker...@lists.infradead.org
Subject: Re: [RFC PATCH 3/7] Enable pause frame support
>>+#define BGX_SMUX_CBFC_CTL 0x20218
These macros are already defined.
if you check 'net-next ' branch pause frame support has already been
added. You should send patch on top it if you have further changes
to the existing.
Thanks,
Sunil.
From: Koteshwar Rao, Satha
Sent: Wednesday, December 21, 2016 2:16 PM
To: linux-kernel@vger.kernel.org
Cc: Goutham, Sunil; r...@kernel.org; da...@davemloft.net; Daney, David;
Vatsavayi, Raghu; Chickles, Derek; Koteshwar Rao, Satha; Romanov, Philip;
net...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
Subject: [RFC PATCH 3/7] Enable pause frame support
---
drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 25 +++
drivers/net/ethernet/cavium/thunder/thunder_bgx.h | 7 +++
2 files changed, 32 insertions(+)
diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
index 050e21f..92d7e04 100644
--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
+++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
@@ -121,6 +121,31 @@ static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg,
u64 mask, bool zero)
return 1;
}
+void enable_pause_frames(int node, int bgx_idx, int lmac)
+{
+ u64 reg_value = 0;
+ struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
+
+ reg_value = bgx_reg_read(bgx, lmac, BGX_SMUX_TX_CTL);
+ /* Enable BGX()_SMU()_TX_CTL */
+ if (!(reg_value & L2P_BP_CONV))
+ bgx_reg_write(bgx, lmac, BGX_SMUX_TX_CTL,
+ (reg_value | (L2P_BP_CONV)));
+
+ reg_value = bgx_reg_read(bgx, lmac, BGX_SMUX_HG2_CTL);
+ /* Clear if BGX()_SMU()_HG2_CONTROL[HG2TX_EN] is set */
+ if (reg_value & SMUX_HG2_CTL_HG2TX_EN)
+ bgx_reg_write(bgx, lmac, BGX_SMUX_HG2_CTL,
+ (reg_value & (~SMUX_HG2_CTL_HG2TX_EN)));
+
+ reg_value = bgx_reg_read(bgx, lmac, BGX_SMUX_CBFC_CTL);
+ /* Clear if BGX()_SMU()_CBFC_CTL[TX_EN] is set */
+ if (reg_value & CBFC_CTL_TX_EN)
+ bgx_reg_write(bgx, lmac, BGX_SMUX_CBFC_CTL,
+ (reg_value & (~CBFC_CTL_TX_EN)));
+}
+EXPORT_SYMBOL(enable_pause_frames);
+
/* Return number of BGX present in HW */
unsigned bgx_get_map(int node)
{
diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h
b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h
index 01cc7c8..5b57bd1 100644
--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h
+++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h
@@ -131,6 +131,11 @@
#define BGX_SMUX_TX_CTL 0x20178
#define SMU_TX_CTL_DIC_EN BIT_ULL(0)
#define SMU_TX_CTL_UNI_EN BIT_ULL(1)
+#define L2P_BP_CONV BIT_ULL(7)
+#define BGX_SMUX_CBFC_CTL 0x20218
+#define CBFC_CTL_TX_EN BIT_ULL(1)
+#define BGX_SMUX_HG2_CTL 0x20210
+#define SMUX_HG2_CTL_HG2TX_EN BIT_ULL(18)
#define SMU_TX_CTL_LNK_STATUS (3ull << 4)
#define BGX_SMUX_TX_THRESH 0x20180
#define BGX_SMUX_CTL 0x20200
@@ -212,6 +217,8 @@ void bgx_lmac_internal_loopback(int node, int bgx_idx,
u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx);
u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx);
+void enable_pause_frames(int node, int bgx_idx, int lmac);
+
#define BGX_RX_STATS_COUNT 11
#define BGX_TX_STATS_COUNT 18
--
1.8.3.1
Re: [linux-sunxi] [PATCH 1/2] drivers: pinctrl: add driver for Allwinner H5 SoC
Hi,
On 23/12/16 12:50, Icenowy Zheng wrote:
> Based on the Allwinner H5 datasheet and the pinctrl driver of the
> backward-compatible H3 this introduces the pin multiplex assignments for
> the H5 SoC.
>
> H5 introduced some more pin functions (e.g. three more groups of TS
> pins, and one more groups of SIM pins) than H3.
More importantly you should mention the addition of the MMC2 DS pin,
since this is actually the only one we care about (I am not aware of a
driver for the SIM or TS IP blocks).
So while this patch technically looks correct, I was wondering if we
should really explore the possibility of making the whole of sunxi
pinctrl DT controlled.
I brought this up a while ago, but people weren't overly enthusiastic
about it, though their argument weren't really convincing to me[1].
So:
As this "driver" here is basically a table linking GPIO bit settings
(the actual mux value) to names and every pin we care about needs to be
enumerated in the DT anyway, why not just add something like:
allwinner,pinmux = <4>;
to each pin(group) in the DT and get rid of this "driver" file here
entirely?
Apart from saving us to dump tables for each and every SoC into the
kernel as a rather mechanical exercise, this would allow us to support
new SoCs without having to add explicit kernel support for pinctrl.
Icenowy, since you seem to have excess spare time ;-), could you imagine
to have a look what would be needed to make this happen or if there are
showstoppers preventing us from doing so without significant reworks?
>From a 10,000 feet I'd imagine that we need to add some properties for
the interrupts (number of banks?), maybe one property to set the number
of used GPIO banks (to help enumeration). Also I guess the common sunxi
pinctrl driver code needs some significant rework.
Cheers,
Andre.
[1] http://marc.info/?l=linux-arm-kernel&m=145216133518718&w=2
>
> Signed-off-by: Icenowy Zheng
> ---
> drivers/pinctrl/sunxi/Kconfig | 4 +
> drivers/pinctrl/sunxi/Makefile| 1 +
> drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 551
> ++
> 3 files changed, 556 insertions(+)
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
>
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index bff1ffc6f01e..e9c47e8b2ee0 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -76,4 +76,8 @@ config PINCTRL_SUN50I_A64
> bool
> select PINCTRL_SUNXI
>
> +config PINCTRL_SUN50I_H5
> + bool
> + select PINCTRL_SUNXI
> +
> endif
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index 95f93d0561fc..bab215d25440 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -17,5 +17,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_A64)+= pinctrl-sun50i-a64.o
> obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
> obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
> obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
> +obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o
> obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
> obj-$(CONFIG_PINCTRL_SUN9I_A80_R)+= pinctrl-sun9i-a80-r.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
> b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
> new file mode 100644
> index ..98f2a6ee7634
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
> @@ -0,0 +1,551 @@
> +/*
> + * Allwinner H5 SoC pinctrl driver.
> + *
> + * Copyright (C) 2016 Icenowy Zheng
> + *
> + * Based on pinctrl-sun8i-h3.c, which is:
> + * Copyright (C) 2015 Jens Kuske
> + *
> + * Based on pinctrl-sun8i-a23.c, which is:
> + * Copyright (C) 2014 Chen-Yu Tsai
> + * Copyright (C) 2014 Maxime Ripard
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun50i_h5_pins[] = {
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> + SUNXI_FUNCTION(0x3, "jtag"), /* MS */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* RX */
> + SUNXI_FUNCTION(0x3, "jtag"), /* CK */
> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> +
Re: [PATCH] PCI: exynos: refactor exynos pcie driver
Jaehoon Chung wtote: > > Hi Pankaj, > > On 12/23/2016 07:56 PM, Pankaj Dubey wrote: > > From: Niyas Ahmed S T > > > > Currently Exynos PCIe driver is only supported for Exynos5440 SoC. > > This patch does refactoring of Exynos PCIe driver to extend support > > for other Exynos SoC. > > > > Following are the main changes done via this patch: > > 1) It adds separate structs for memory, clock resources. > > 2) It add exynos_pcie_ops struct which will allow us to support the > > differences in resources in different Exynos SoC. > > It's nice to me for reusing this file. > but after considering too many times, i decided not to use this file. > > I'm not sure what block base is..actually this pci-exynos.c is really > black-box. > (No one maintains this file, even Samsung didn't care.) > Who is using this? > If Someone can share the information about exynos5440, i can refactor > everything. > Otherwise, there are two solution.. > > One is "adding the new pci-exynos.c" likes pci-exynos5433.c As Bjorn mentioned earlier, I agree with this option. > Other is "refactor this file" under assuming the each register's usage. But, if possible, I prefer this option. I am not sure that it cannot make the code dirty. Maybe, you need to discuss with hardware design engineers. > > I want to use the PHY generic Framework for EXYNOS PCIe. > > If you or other guys really want to use the pci-exynos.c for other exynos, > I will rework with PHY generic framework. Then i will resend the my > patches as V2. When I submitted the pci-exynos.c, there was no PHY generic framework. But, currently, using PHY generic framework is mandatory, as other PCIe host driver did. I think that we should use PHY generic framework for new SoCs. > > One more thing..Does anyone know what the usage of block base is? > Can i use that register as "syscon"? 'Block' is very specific registers for 5440. Other Exynos SoCs do not use that registers. Actually, it is not the same with 'syscon'. But, you can assume 'block' as 'syscon'. Best regards, Jingoo Han > > Best Regards, > Jaehoon Chung > [.]
[PATCH tip/master] kprobes: extable: Identify kprobes' insn-slots as kernel text area
Make __kernel_text_address()/kernel_text_address() returns
true if the given address is on a kprobe's instruction slot,
which is generated by kprobes as a trampoline code.
This can help stacktraces to determine the address is on a
text area or not.
To implement this without any sleep in is_kprobe_*_slot(),
this also modify insn_cache page list as a rcu list. It may
increase processing deley (not processing time) for garbage
slot collection, because it requires to wait an additional
rcu grance period when freeing a page from the list.
However, since it is not a hot path, we may not take care of it.
Signed-off-by: Masami Hiramatsu
---
Hi Josh, could check this patch fixes your issue? It will
enable unwinder code to validate return address by using
__kernel_text_address() again.
---
include/linux/kprobes.h | 14 +
kernel/extable.c|9 +-
kernel/kprobes.c| 70 ---
3 files changed, 74 insertions(+), 19 deletions(-)
diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h
index 8f68490..400c5c1 100644
--- a/include/linux/kprobes.h
+++ b/include/linux/kprobes.h
@@ -281,6 +281,9 @@ struct kprobe_insn_cache {
extern kprobe_opcode_t *__get_insn_slot(struct kprobe_insn_cache *c);
extern void __free_insn_slot(struct kprobe_insn_cache *c,
kprobe_opcode_t *slot, int dirty);
+/* sleep-less address checking routine */
+extern bool __is_insn_slot_addr(struct kprobe_insn_cache *c,
+ unsigned long addr);
#define DEFINE_INSN_CACHE_OPS(__name) \
extern struct kprobe_insn_cache kprobe_##__name##_slots; \
@@ -294,6 +297,11 @@ static inline void free_##__name##_slot(kprobe_opcode_t
*slot, int dirty)\
{ \
__free_insn_slot(&kprobe_##__name##_slots, slot, dirty);\
} \
+ \
+static inline bool is_kprobe_##__name##_slot(unsigned long addr) \
+{ \
+ return __is_insn_slot_addr(&kprobe_##__name##_slots, addr); \
+}
DEFINE_INSN_CACHE_OPS(insn);
@@ -330,7 +338,11 @@ extern int proc_kprobes_optimization_handler(struct
ctl_table *table,
int write, void __user *buffer,
size_t *length, loff_t *ppos);
#endif
-
+#else /* CONFIG_OPTPROBES */
+static inline bool is_kprobe_optinsn_slot(unsigned long addr)
+{
+ return false;
+}
#endif /* CONFIG_OPTPROBES */
#ifdef CONFIG_KPROBES_ON_FTRACE
extern void kprobe_ftrace_handler(unsigned long ip, unsigned long parent_ip,
diff --git a/kernel/extable.c b/kernel/extable.c
index e820cce..81c9633 100644
--- a/kernel/extable.c
+++ b/kernel/extable.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
@@ -104,6 +105,8 @@ int __kernel_text_address(unsigned long addr)
return 1;
if (is_ftrace_trampoline(addr))
return 1;
+ if (is_kprobe_optinsn_slot(addr) || is_kprobe_insn_slot(addr))
+ return 1;
/*
* There might be init symbols in saved stacktraces.
* Give those symbols a chance to be printed in
@@ -123,7 +126,11 @@ int kernel_text_address(unsigned long addr)
return 1;
if (is_module_text_address(addr))
return 1;
- return is_ftrace_trampoline(addr);
+ if (is_ftrace_trampoline(addr))
+ return 1;
+ if (is_kprobe_optinsn_slot(addr) || is_kprobe_insn_slot(addr))
+ return 1;
+ return 0;
}
/*
diff --git a/kernel/kprobes.c b/kernel/kprobes.c
index d630954..1bd1c17 100644
--- a/kernel/kprobes.c
+++ b/kernel/kprobes.c
@@ -149,9 +149,11 @@ kprobe_opcode_t *__get_insn_slot(struct kprobe_insn_cache
*c)
struct kprobe_insn_page *kip;
kprobe_opcode_t *slot = NULL;
+ /* Since the slot array is not protected by rcu, we need a mutex */
mutex_lock(&c->mutex);
retry:
- list_for_each_entry(kip, &c->pages, list) {
+ rcu_read_lock();
+ list_for_each_entry_rcu(kip, &c->pages, list) {
if (kip->nused < slots_per_page(c)) {
int i;
for (i = 0; i < slots_per_page(c); i++) {
@@ -167,6 +169,7 @@ kprobe_opcode_t *__get_insn_slot(struct kprobe_insn_cache
*c)
WARN_ON(1);
}
}
+ rcu_read_unlock();
/* If there are any garbage slots, collect it and try again. */
if (c->nr_garbage && collect_garbage_slots(c) == 0)
@@ -193,13 +196,15 @@ kprobe_opcode_t *__get_insn_slot(struct kprobe_insn_cache
*c)
kip->nused = 1;
kip->ngarbage =
Re: [RFC PATCH 0/7] ThunderX Embedded switch support
On Mon, Dec 26, 2016 at 02:04:27PM +, Koteshwar Rao, Satha wrote: > Hi Sunil, > > In RFC cover letter we explained the feature details, files organized based > on their supporting functionality, let me know if you are interested in any > specific details Please don't top post. Also, please perform correct quoting of the email you are replying to. As for getting patches merged, you will find it easier to get reviews if you have lots of small patches which are obviously correct, and each has a good change log entry describing the why as well as what. Andrew
Re: Question regarding power button of Dell XPS13
26.12.2016, 00:27, "Linus Torvalds" : > On Fri, Dec 23, 2016 at 4:36 AM, Paul Menzel wrote: >> I heard that you both have a Dell XPS13. I got the “revision” 9360, and >> installed Debian Stretch/testing on it with Linux 4.8.15 and Linux 4.9-rc8. >> >> When pressing the power button the GNOME dialog, asking what to do (restart, >> power off, …) doesn’t appear. Hello, I don't think it's problem about to kernel. The problem related to GNOME . I used last time and I modified the file "gsd-media-keys-manager.c" file and added the following lines to logind.conf file: HandlePowerKey=poweroff PowerKeyIgnoreInhibited=yes This is a out of topic and XPS13 is not good, You also don't use a desktop, Suggest Openbox :) > Hmm. I don't recall ever seeing such a dialog. But I don't run Debian. > > For me it works like all power buttons on my laptops have worked > lately - it suspends the machine. > > Of course, so does just closing the lid. > > The only "bug" I've seen in this area is the design bug of the XPS13 > where there is no visible indication of the suspend state (ie the > traditional slowly pulsing LED showing that it's all nice and > suspended). But that seems to be intentional, if stupid. I think it's > the only real beef I have with the XPS13. > > Linus Regards, Ozgur
Re: lkml.org issues
26.12.2016, 10:46, "Nikita Yushchenko" : > Hi > > Is lkml.org supported? > > Currently: > > - [headers] link on top of pages does not show message headers, You can just display the header's list. > - [forward] link on top of pages is not functional - it requests text > from captcha but does not show image. where is to forward? All? > [forward] could be useful to get a list mail that one did not receive, > to be able to reply to it without doing manual black magic with > searching for message-id and forging in-reply-to headers. previously lkml hve to FAQ please contact to tux.org Regards, Ozgur
Re: Linux 4.10-rc1
On Mon, Dec 26, 2016 at 02:23:43PM +, Al Viro wrote:
> On Mon, Dec 26, 2016 at 05:45:10PM +0800, Hanjun Guo wrote:
> > On 2016/12/26 17:18, Al Viro wrote:
> > > On Mon, Dec 26, 2016 at 05:05:37PM +0800, Kefeng Wang wrote:
> > >> It looks like we need revert the changes from assembly files.
> >
> > I tested Kefeng's patch and works. more comments below.
> >
> > > Better yet, split the damn thing in two and include the asm-only part.
> >
> > split will cause other places for building errors, because there is no
> >
> > -#ifndef __ASSEMBLY__
>
> Huh? It's included only from assembler files, so what would use the other
> parts?
FWIW, my arguments for splitting it are
* asm and non-asm parts have almost no overlap - only
uaccess_{en,dis}able_not_uao (as asm macro and static inline
resp.), but that's it. It's not as if there had been arseloads of
constants shared between C and assembler, etc.
* having no asm/uaccess.h includes left allows to consolidate stuff
into linux/uaccess.h; sure, in this case the stuff getting moved there would be
under ifndef anyway, but "no includes outside of linux/uaccess.h" is easier
to verify than "no includes outside of linux/uaccess.h and arch/arm64/.../*.S"
I can live with reverting those several includes to asm/uaccess.h (all
interesting stuff is under that ifndef), but I think splitting the asm
part away would be cleaner.
PS: if that variant does cause any build errors, I would very much like to
see .config. Hanjun, could you post one that is triggering those?
[PATCH tip/master v2] kprobes: extable: Identify kprobes' insn-slots as kernel text area
Make __kernel_text_address()/kernel_text_address() returns
true if the given address is on a kprobe's instruction slot,
which is generated by kprobes as a trampoline code.
This can help stacktraces to determine the address is on a
text area or not.
To implement this without any sleep in is_kprobe_*_slot(),
this also modify insn_cache page list as a rcu list. It may
increase processing deley (not processing time) for garbage
slot collection, because it requires to wait an additional
rcu grance period when freeing a page from the list.
However, since it is not a hot path, we may not take care of it.
Signed-off-by: Masami Hiramatsu
---
V2: Fix build error when CONFIG_KPROBES=n
Hi Josh, could check this patch fixes your issue? It will
enable unwinder code to validate return address by using
__kernel_text_address() again.
---
include/linux/kprobes.h | 22 ++-
kernel/extable.c|9 +-
kernel/kprobes.c| 70 ---
3 files changed, 82 insertions(+), 19 deletions(-)
diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h
index 8f68490..f0496b0 100644
--- a/include/linux/kprobes.h
+++ b/include/linux/kprobes.h
@@ -281,6 +281,9 @@ struct kprobe_insn_cache {
extern kprobe_opcode_t *__get_insn_slot(struct kprobe_insn_cache *c);
extern void __free_insn_slot(struct kprobe_insn_cache *c,
kprobe_opcode_t *slot, int dirty);
+/* sleep-less address checking routine */
+extern bool __is_insn_slot_addr(struct kprobe_insn_cache *c,
+ unsigned long addr);
#define DEFINE_INSN_CACHE_OPS(__name) \
extern struct kprobe_insn_cache kprobe_##__name##_slots; \
@@ -294,6 +297,11 @@ static inline void free_##__name##_slot(kprobe_opcode_t
*slot, int dirty)\
{ \
__free_insn_slot(&kprobe_##__name##_slots, slot, dirty);\
} \
+ \
+static inline bool is_kprobe_##__name##_slot(unsigned long addr) \
+{ \
+ return __is_insn_slot_addr(&kprobe_##__name##_slots, addr); \
+}
DEFINE_INSN_CACHE_OPS(insn);
@@ -330,7 +338,6 @@ extern int proc_kprobes_optimization_handler(struct
ctl_table *table,
int write, void __user *buffer,
size_t *length, loff_t *ppos);
#endif
-
#endif /* CONFIG_OPTPROBES */
#ifdef CONFIG_KPROBES_ON_FTRACE
extern void kprobe_ftrace_handler(unsigned long ip, unsigned long parent_ip,
@@ -481,6 +488,19 @@ static inline int enable_jprobe(struct jprobe *jp)
return enable_kprobe(&jp->kp);
}
+#ifndef CONFIG_KPROBES
+static inline bool is_kprobe_insn_slot(unsigned long addr)
+{
+ return false;
+}
+#endif
+#ifndef CONFIG_OPTPROBES
+static inline bool is_kprobe_optinsn_slot(unsigned long addr)
+{
+ return false;
+}
+#endif
+
#ifdef CONFIG_KPROBES
/*
* Blacklist ganerating macro. Specify functions which is not probed
diff --git a/kernel/extable.c b/kernel/extable.c
index e820cce..81c9633 100644
--- a/kernel/extable.c
+++ b/kernel/extable.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
@@ -104,6 +105,8 @@ int __kernel_text_address(unsigned long addr)
return 1;
if (is_ftrace_trampoline(addr))
return 1;
+ if (is_kprobe_optinsn_slot(addr) || is_kprobe_insn_slot(addr))
+ return 1;
/*
* There might be init symbols in saved stacktraces.
* Give those symbols a chance to be printed in
@@ -123,7 +126,11 @@ int kernel_text_address(unsigned long addr)
return 1;
if (is_module_text_address(addr))
return 1;
- return is_ftrace_trampoline(addr);
+ if (is_ftrace_trampoline(addr))
+ return 1;
+ if (is_kprobe_optinsn_slot(addr) || is_kprobe_insn_slot(addr))
+ return 1;
+ return 0;
}
/*
diff --git a/kernel/kprobes.c b/kernel/kprobes.c
index d630954..1bd1c17 100644
--- a/kernel/kprobes.c
+++ b/kernel/kprobes.c
@@ -149,9 +149,11 @@ kprobe_opcode_t *__get_insn_slot(struct kprobe_insn_cache
*c)
struct kprobe_insn_page *kip;
kprobe_opcode_t *slot = NULL;
+ /* Since the slot array is not protected by rcu, we need a mutex */
mutex_lock(&c->mutex);
retry:
- list_for_each_entry(kip, &c->pages, list) {
+ rcu_read_lock();
+ list_for_each_entry_rcu(kip, &c->pages, list) {
if (kip->nused < slots_per_page(c)) {
int i;
for (i = 0; i < slots_per_page(c); i++) {
@@ -167,6 +169,7 @@ kprobe_opcode_t *__get_insn_slot(
[PATCH] PCI: acpiphp_ibm: add __ro_after_init to ibm_apci_table_attr
The object ibm_apci_table_attr of type bin_attribute structure is not
modified after getting initialized by ibm_acpiphp_init. Apart from
getting referenced in init it is also passed as an argument to the functions
sysfs_{remove/create}_bin_file but both the arguments are of type const
struct bin_attribute *. Therefore add __ro_after_init to its declaration.
Signed-off-by: Bhumika Goyal
---
drivers/pci/hotplug/acpiphp_ibm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/hotplug/acpiphp_ibm.c
b/drivers/pci/hotplug/acpiphp_ibm.c
index f6221d7..188cdfa 100644
--- a/drivers/pci/hotplug/acpiphp_ibm.c
+++ b/drivers/pci/hotplug/acpiphp_ibm.c
@@ -107,7 +107,7 @@ static acpi_status __init ibm_find_acpi_device(acpi_handle
handle,
static acpi_handle ibm_acpi_handle;
static struct notification ibm_note;
-static struct bin_attribute ibm_apci_table_attr = {
+static struct bin_attribute ibm_apci_table_attr __ro_after_init = {
.attr = {
.name = "apci_table",
.mode = S_IRUGO,
--
1.9.1
[PATCH 2/2] Style fixes
Missing braces on `if` statement; misaligned parameter.
Signed-off-by: Guillermo O. Freschi
---
drivers/staging/lustre/lustre/ldlm/ldlm_lock.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/lustre/lustre/ldlm/ldlm_lock.c
b/drivers/staging/lustre/lustre/ldlm/ldlm_lock.c
index f4cbc89b4f24..a23e7ada3891 100644
--- a/drivers/staging/lustre/lustre/ldlm/ldlm_lock.c
+++ b/drivers/staging/lustre/lustre/ldlm/ldlm_lock.c
@@ -1024,11 +1024,11 @@ void ldlm_grant_lock(struct ldlm_lock *lock, struct
list_head *work_list)
if (work_list && lock->l_completion_ast)
ldlm_add_ast_work_item(lock, NULL, work_list);
- if (res->lr_type == LDLM_PLAIN || res->lr_type == LDLM_IBITS)
+ if (res->lr_type == LDLM_PLAIN || res->lr_type == LDLM_IBITS) {
ldlm_grant_lock_with_skiplist(lock);
- else if (res->lr_type == LDLM_EXTENT)
+ } else if (res->lr_type == LDLM_EXTENT) {
ldlm_extent_add_lock(res, lock);
- else if (res->lr_type == LDLM_FLOCK) {
+ } else if (res->lr_type == LDLM_FLOCK) {
/*
* We should not add locks to granted list in the following
cases:
* - this is an UNLOCK but not a real lock;
@@ -1040,8 +1040,9 @@ void ldlm_grant_lock(struct ldlm_lock *lock, struct
list_head *work_list)
ldlm_is_test_lock(lock) || ldlm_is_flock_deadlock(lock))
return;
ldlm_resource_add_lock(res, &res->lr_granted, lock);
- } else
+ } else {
LBUG();
+ }
ldlm_pool_add(&ldlm_res_to_ns(res)->ns_pool, lock);
}
@@ -1481,7 +1482,8 @@ int ldlm_fill_lvb(struct ldlm_lock *lock, struct
req_capsule *pill,
lustre_swab_ost_lvb_v1);
else
lvb = req_capsule_server_sized_swab_get(pill,
- &RMF_DLM_LVB, size,
+
&RMF_DLM_LVB,
+ size,
lustre_swab_ost_lvb_v1);
if (unlikely(!lvb)) {
LDLM_ERROR(lock, "no LVB");
--
2.11.0
Re: [PATCH 2/6] wl1251: Use request_firmware_prefer_user() for loading NVS calibration data
Hi! > > > NVS calibration data for wl1251 are model specific. Every one > > > device with wl1251 chip has different and calibrated in factory. > > > > > > Not all wl1251 chips have own EEPROM where are calibration data > > > stored. And in that case there is no "standard" place. Every > > > device has stored them on different place (some in rootfs file, > > > some in dedicated nand partition, some in another proprietary > > > structure). > > > > > > Kernel wl1251 driver cannot support every one different storage > > > decided by device manufacture so it will use > > > request_firmware_prefer_user() call for loading NVS calibration > > > data and userspace helper will be responsible to prepare correct > > > data. > > > > Responding to this patch as it provides a lot of context to discuss. > > As you might have gathered from earlier discussions I am not a fan > > of using user-space helper. I can agree that the kernel driver, > > wl1251 in this case, should be agnostic to platform specific details > > regarding storage solutions and the firmware api should hide that. > > However, it seems your only solution is adding user-space to the mix > > and changing the api towards that. Can we solve it without > > user-space help? > > Without userspace helper it means that userspace helper code must be > integrated into kernel. > > So what is userspace helper doing? > > 1) Read MAC address from CAL > 2) Read NVS data from CAL > 3) Modify MAC address in memory NVS data (new for this patch series) > 4) Modify in memory NVS data if we in FCC country > > Checking for country is done via dbus call to either Maemo cellular > daemon or alternatively via REGDOMAIN in /etc/default/crda. I have plan > to use ofono (instead Maemo cellular daemon) too... > > Currently we are using closed Nokia proprietary CAL library. > > Steps 1) and 2) needs closed library, step 4) needs dbus call. I guess pointer to the source code implementing this would be welcome. > > But on other devices that use wl1251, but for instance have no > > userspace helper the request to userspace will fail (after 60 sec?) > > and try VFS after that. Maybe not so nice. > > Currently support for those devices is broken (like for N900) as without > proper NVS data they do not work correctly... Is it expected to work at all, perhaps with degraded performance / range? Because it seems to work for me. Thanks, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html signature.asc Description: Digital signature
[PATCH 1/2] Fixed signedness check
Was `unsigned int`, but `enum`s are signed.
Signed-off-by: Guillermo O. Freschi
---
drivers/staging/lustre/lustre/ldlm/ldlm_lock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/lustre/lustre/ldlm/ldlm_lock.c
b/drivers/staging/lustre/lustre/ldlm/ldlm_lock.c
index a4a291acb659..f4cbc89b4f24 100644
--- a/drivers/staging/lustre/lustre/ldlm/ldlm_lock.c
+++ b/drivers/staging/lustre/lustre/ldlm/ldlm_lock.c
@@ -1148,7 +1148,7 @@ static int lock_matches(struct ldlm_lock *lock, struct
lock_match_data *data)
return INTERVAL_ITER_STOP;
}
-static unsigned int itree_overlap_cb(struct interval_node *in, void *args)
+static enum interval_iter itree_overlap_cb(struct interval_node *in, void
*args)
{
struct ldlm_interval *node = to_ldlm_interval(in);
struct lock_match_data *data = args;
--
2.11.0
Re: [GIT pull] smp/hotplug: Removal of notifiers
On 2016.12.26 at 12:06 +0100, Markus Trippelsdorf wrote: > On 2016.12.26 at 08:45 +0100, Markus Trippelsdorf wrote: > > On 2016.12.25 at 14:39 +0100, Thomas Gleixner wrote: > > > Linus, > > > > > > please pull the latest smp-urgent-for-linus git tree from: > > > > > >git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git > > > smp-urgent-for-linus > > > > > > Thomas Gleixner (11): > > > cpu/hotplug: Prevent overwriting of callbacks > > > > The following commit: > > > > commit dc280d93623927570da279e99393879dbbab39e7 > > Author: Thomas Gleixner > > Date: Wed Dec 21 20:19:49 2016 +0100 > > > > cpu/hotplug: Prevent overwriting of callbacks > > > > results in an early OOPs during boot on my AMD machine. > > I haven't wrote down the entire backtrace, but basically things start to > > go wrong in mce_threshold_create_device() from > > arch/x86/kernel/cpu/mcheck/mce_amd.c. > > > > # CONFIG_HOTPLUG_CPU is not set > > > > Reverting the commit "fixes" the issue for me. > > CCing Sebastian and Borislav. BUG: unable to handle kernel NULL pointer dereference at 004c RIP: kobject_get at lib/kobject.c:594 (inlined by) kobject_add_internal at lib/kobject.c:214 ? kobj_to_dev at include/linux/device.h:968 (discriminator 1) (inlined by) get_device at drivers/base/core.c:1796 (discriminator 1) ? kobject_add at lib/kobject.c:415 ? kobject_create_and_add at lib/kobject.c:753 ? threshold_create_bank at arch/x86/kernel/cpu/mcheck/mce_amd.c:1212 (inlined by) mce_threshold_create_device at arch/x86/kernel/cpu/mcheck/mce_amd.c:1348 The comment in arch/x86/kernel/cpu/mcheck/mce_amd.c says: 1384 * mcheck_init_device should be inited before threshold_init_device to 1385 * initialize mce_device, otherwise a NULL ptr dereference will cause panic. -- Markus
Re: [PATCH 2/6] wl1251: Use request_firmware_prefer_user() for loading NVS calibration data
On Monday 26 December 2016 16:43:53 Pavel Machek wrote: > Hi! > > > > > NVS calibration data for wl1251 are model specific. Every one > > > > device with wl1251 chip has different and calibrated in > > > > factory. > > > > > > > > Not all wl1251 chips have own EEPROM where are calibration data > > > > stored. And in that case there is no "standard" place. Every > > > > device has stored them on different place (some in rootfs file, > > > > some in dedicated nand partition, some in another proprietary > > > > structure). > > > > > > > > Kernel wl1251 driver cannot support every one different storage > > > > decided by device manufacture so it will use > > > > request_firmware_prefer_user() call for loading NVS calibration > > > > data and userspace helper will be responsible to prepare > > > > correct data. > > > > > > Responding to this patch as it provides a lot of context to > > > discuss. As you might have gathered from earlier discussions I > > > am not a fan of using user-space helper. I can agree that the > > > kernel driver, wl1251 in this case, should be agnostic to > > > platform specific details regarding storage solutions and the > > > firmware api should hide that. However, it seems your only > > > solution is adding user-space to the mix and changing the api > > > towards that. Can we solve it without user-space help? > > > > Without userspace helper it means that userspace helper code must > > be integrated into kernel. > > > > So what is userspace helper doing? > > > > 1) Read MAC address from CAL > > 2) Read NVS data from CAL > > 3) Modify MAC address in memory NVS data (new for this patch > > series) 4) Modify in memory NVS data if we in FCC country > > > > Checking for country is done via dbus call to either Maemo cellular > > daemon or alternatively via REGDOMAIN in /etc/default/crda. I have > > plan to use ofono (instead Maemo cellular daemon) too... > > > > Currently we are using closed Nokia proprietary CAL library. > > > > Steps 1) and 2) needs closed library, step 4) needs dbus call. > > I guess pointer to the source code implementing this would be > welcome. Here is current code: https://github.com/community-ssu/wl1251-cal (there is implemented also Maemo netlink interface) > > > But on other devices that use wl1251, but for instance have no > > > userspace helper the request to userspace will fail (after 60 > > > sec?) and try VFS after that. Maybe not so nice. > > > > Currently support for those devices is broken (like for N900) as > > without proper NVS data they do not work correctly... > > Is it expected to work at all, perhaps with degraded performance / > range? Because it seems to work for me. Yes, some degraded performance or problems with connecting is expected. And random MAC address at every boot. Plus some regulatory problems in FCC countries. -- Pali Rohár pali.ro...@gmail.com signature.asc Description: This is a digitally signed message part.
Re: lkml.org issues
On Mon, Dec 26, 2016 at 9:46 AM, Nikita Yushchenko wrote: > Hi > > Is lkml.org supported? > > Currently: No. lkml.org is a random mailing list archive. Please contact the webmaster of it. See lkml.org -- Thanks, //richard
Re: [PATCH v3 1/3] ARM: dts: imx6: Add Savageboard common file
On Thu, Dec 8, 2016 at 11:04 PM, Milo Kim wrote: > * Memory > memblock for DDR3 1GB > > * Regulator > 3.3V for panel and backlight. > > * Display > Enable HDMI and LVDS panel. Savageboard supports AVIC TM097TDH02 panel > which is compatible with Hannstar HSD100PXN1, so reuse it. > > * Clock > The commit d28be499c45e6 is applied to support LVDS and HDMI output > simultaneously. > > * Pinmux > eMMC, ethernet, HDMI, I2C, power button, PWM, SD card and UART. > > * Others > Enable ethernet, UART1 debug, USB host, USDHC3 for microSD card and > USDHC4 for built-in eMMC storage. > > Signed-off-by: Milo Kim Reviewed-by: Fabio Estevam
Re: [PATCH v2 3/3] ARM: dts: imx6: Support Savageboard quad
On Tue, Dec 6, 2016 at 5:08 AM, Milo Kim wrote: > Use common board file and support SATA interface additionally. > > Signed-off-by: Milo Kim Reviewed-by: Fabio Estevam
Re: [PATCH 2/6] wl1251: Use request_firmware_prefer_user() for loading NVS calibration data
On Sun 2016-12-25 21:15:40, Arend Van Spriel wrote: > On 24-12-2016 17:52, Pali Rohár wrote: > > NVS calibration data for wl1251 are model specific. Every one device with > > wl1251 chip has different and calibrated in factory. > > > > Not all wl1251 chips have own EEPROM where are calibration data stored. And > > in that case there is no "standard" place. Every device has stored them on > > different place (some in rootfs file, some in dedicated nand partition, > > some in another proprietary structure). > > > > Kernel wl1251 driver cannot support every one different storage decided by > > device manufacture so it will use request_firmware_prefer_user() call for > > loading NVS calibration data and userspace helper will be responsible to > > prepare correct data. > > Responding to this patch as it provides a lot of context to discuss. As > you might have gathered from earlier discussions I am not a fan of using > user-space helper. I can agree that the kernel driver, wl1251 in this > case, should be agnostic to platform specific details regarding storage > solutions and the firmware api should hide that. However, it seems your > only solution is adding user-space to the mix and changing the api > towards that. Can we solve it without user-space help? Answer is no, due to licensing. But that's wrong question to ask. Right question is "should we solve it without user-space help"? Answer is no, too. Way too complex. Yes, it would be nice if hardware was designed in such a way that getting calibration data from kernel is easy, and if you design hardware, please design it like that. But N900 is not designed like that and getting the calibration through userspace looks like only reasonable solution. Now... how exactly to do that is other question. (But this is looks very reasonable. Maybe I'd add request_firmware_with_flags(, ...int flags), but.. that's a tiny detail.). But userspace needs to be involved. Thanks, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html signature.asc Description: Digital signature
Re: [PATCH] nohz: Fix collision between tick and other hrtimers
On Sun, Dec 25, 2016 at 09:56:57PM -0500, Rik van Riel wrote: > On Sat, 2016-12-24 at 17:15 +0100, Frederic Weisbecker wrote: > > When the tick is stopped and an interrupt occurs afterward, we check > > on > > that interrupt exit if the next tick needs to be rescheduled. If it > > doesn't need any update, we don't want to do anything. > > > > In order to check if the tick needs an update, we compare it against > > the > > clockevent device deadline. Now that's a problem because the > > clockevent > > device is at a lower level than the tick itself if it is implemented > > on top of hrtimer. > > Oh, good find. That is one subtle bug. Oh yeah, it took me several month to debug that one :-) ! > > Acked-by: Rik van Riel Thanks! > > -- > All Rights Reversed.
Re: [PATCH] drivers: watchdog: constify watchdog_info structures
On 12/26/2016 05:47 AM, Bhumika Goyal wrote:
Declare watchdog_info structures as const as they are only stored in the
info field of watchdog_device structures. This field is of type const
struct watchdog_info *, so watchdog_info structures having this property
can be declared const too.
Done using Coccinelle:
@r1 disable optional_qualifier@
identifier i;
position p;
@@
static struct watchdog_info i@p={...};
@ok@
identifier r1.i;
position p;
struct watchdog_device obj;
@@
obj.info=&i@p;
@bad@
position p!={r1.p,ok.p};
identifier r1.i;
@@
i@p
@depends on !bad disable optional_qualifier@
identifier r1.i;
@@
+const
struct watchdog_info i;
Size details:
textdata bss dec hex filename
1882 249 02131 853 drivers/watchdog/bcm7038_wdt.o
1938 193 02131 853 drivers/watchdog/bcm7038_wdt.o
1673 720 82401 961 drivers/watchdog/bcm_kona_wdt.o
1729 656 82393 959 drivers/watchdog/bcm_kona_wdt.o
2370 760 83138 c42 drivers/watchdog/cadence_wdt.o
2434 704 83146 c4a drivers/watchdog/cadence_wdt.o
1448 248 01696 6a0 drivers/watchdog/da9052_wdt.o
1512 192 01704 6a8 drivers/watchdog/da9052_wdt.o
1077 249 01326 52e drivers/watchdog/da9055_wdt.o
1141 193 01334 536 drivers/watchdog/da9055_wdt.o
1416 544 121972 7b4 drivers/watchdog/digicolor_wdt.o
1480 480 121972 7b4 drivers/watchdog/digicolor_wdt.o
2653 249 42906 b5a drivers/watchdog/imgpdc_wdt.o
2717 193 42914 b62 drivers/watchdog/imgpdc_wdt.o
2923 257 43184 c70 drivers/watchdog/kempld_wdt.o
2987 201 43192 c78 drivers/watchdog/kempld_wdt.o
2469 249 202738 ab2 drivers/watchdog/lpc18xx_wdt.o
2533 193 202746 aba drivers/watchdog/lpc18xx_wdt.o
1119 249 41372 55c drivers/watchdog/rn5t618_wdt.o
1183 193 41380 564 drivers/watchdog/rn5t618_wdt.o
1218 528 81754 6da drivers/watchdog/softdog.o
1282 464 81754 6da drivers/watchdog/softdog.o
2934 249 243207 c87 drivers/watchdog/w83627hf_wdt.o
2998 185 243207 c87 drivers/watchdog/w83627hf_wdt.o
The size details are quite irrelevant for the commit log. Also, please drop
"drivers:"
from the subject line.
Guenter
Signed-off-by: Bhumika Goyal
---
drivers/watchdog/bcm7038_wdt.c | 2 +-
drivers/watchdog/bcm_kona_wdt.c | 2 +-
drivers/watchdog/cadence_wdt.c | 2 +-
drivers/watchdog/da9052_wdt.c| 2 +-
drivers/watchdog/da9055_wdt.c| 2 +-
drivers/watchdog/digicolor_wdt.c | 2 +-
drivers/watchdog/imgpdc_wdt.c| 2 +-
drivers/watchdog/kempld_wdt.c| 2 +-
drivers/watchdog/lpc18xx_wdt.c | 2 +-
drivers/watchdog/rn5t618_wdt.c | 2 +-
drivers/watchdog/sbsa_gwdt.c | 2 +-
drivers/watchdog/w83627hf_wdt.c | 2 +-
12 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/watchdog/bcm7038_wdt.c b/drivers/watchdog/bcm7038_wdt.c
index e238df4..37c6a49 100644
--- a/drivers/watchdog/bcm7038_wdt.c
+++ b/drivers/watchdog/bcm7038_wdt.c
@@ -101,7 +101,7 @@ static unsigned int bcm7038_wdt_get_timeleft(struct
watchdog_device *wdog)
return time_left / wdt->rate;
}
-static struct watchdog_info bcm7038_wdt_info = {
+static const struct watchdog_info bcm7038_wdt_info = {
.identity = "Broadcom BCM7038 Watchdog Timer",
.options= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE
diff --git a/drivers/watchdog/bcm_kona_wdt.c b/drivers/watchdog/bcm_kona_wdt.c
index e0c9842..76b0080 100644
--- a/drivers/watchdog/bcm_kona_wdt.c
+++ b/drivers/watchdog/bcm_kona_wdt.c
@@ -274,7 +274,7 @@ static int bcm_kona_wdt_stop(struct watchdog_device *wdog)
.get_timeleft = bcm_kona_wdt_get_timeleft,
};
-static struct watchdog_info bcm_kona_wdt_info = {
+static const struct watchdog_info bcm_kona_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.identity = "Broadcom Kona Watchdog Timer",
diff --git a/drivers/watchdog/cadence_wdt.c b/drivers/watchdog/cadence_wdt.c
index 98acef7..8d61e8b 100644
--- a/drivers/watchdog/cadence_wdt.c
+++ b/drivers/watchdog/cadence_wdt.c
@@ -262,7 +262,7 @@ static irqreturn_t cdns_wdt_irq_handler(int irq, void
*dev_id)
* Info structure used to indicate the features supported by the device
* to the upper layers. This is defined in watchdog.h header file.
*/
-static struct watchdog_info cdns_wdt_info = {
+static const struct watchdog_info cdns_wdt_info = {
.identity = "cdns_wdt watchdog",
.options= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
diff --git
Re: lkml.org issues
On 12/26/16 00:46, Nikita Yushchenko wrote: > Hi > > Is lkml.org supported? > Not here. Just contact Jasper Spaans directly. > Currently: > what rw said. -- ~Randy
Re: [PATCH v3 2/3] ARM: dts: imx6: Support Savageboard dual
On Thu, Dec 8, 2016 at 11:04 PM, Milo Kim wrote: > Common savageboard DT file is used for board support. > Specify this dtb file for i.MX6Q build. > > Signed-off-by: Milo Kim Reviewed-by: Fabio Estevam
[PATCH v2] watchdog: constify watchdog_info structures
Declare watchdog_info structures as const as they are only stored in the
info field of watchdog_device structures. This field is of type const
struct watchdog_info *, so watchdog_info structures having this property
can be declared const too.
Done using Coccinelle:
@r1 disable optional_qualifier@
identifier i;
position p;
@@
static struct watchdog_info i@p={...};
@ok@
identifier r1.i;
position p;
struct watchdog_device obj;
@@
obj.info=&i@p;
@bad@
position p!={r1.p,ok.p};
identifier r1.i;
@@
i@p
@depends on !bad disable optional_qualifier@
identifier r1.i;
@@
+const
struct watchdog_info i;
Signed-off-by: Bhumika Goyal
---
Changes in v2:
* Drop "drivers:" from the subject line.
* Remove the file size details.
drivers/watchdog/bcm7038_wdt.c | 2 +-
drivers/watchdog/bcm_kona_wdt.c | 2 +-
drivers/watchdog/cadence_wdt.c | 2 +-
drivers/watchdog/da9052_wdt.c| 2 +-
drivers/watchdog/da9055_wdt.c| 2 +-
drivers/watchdog/digicolor_wdt.c | 2 +-
drivers/watchdog/imgpdc_wdt.c| 2 +-
drivers/watchdog/kempld_wdt.c| 2 +-
drivers/watchdog/lpc18xx_wdt.c | 2 +-
drivers/watchdog/rn5t618_wdt.c | 2 +-
drivers/watchdog/sbsa_gwdt.c | 2 +-
drivers/watchdog/w83627hf_wdt.c | 2 +-
12 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/watchdog/bcm7038_wdt.c b/drivers/watchdog/bcm7038_wdt.c
index e238df4..37c6a49 100644
--- a/drivers/watchdog/bcm7038_wdt.c
+++ b/drivers/watchdog/bcm7038_wdt.c
@@ -101,7 +101,7 @@ static unsigned int bcm7038_wdt_get_timeleft(struct
watchdog_device *wdog)
return time_left / wdt->rate;
}
-static struct watchdog_info bcm7038_wdt_info = {
+static const struct watchdog_info bcm7038_wdt_info = {
.identity = "Broadcom BCM7038 Watchdog Timer",
.options= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE
diff --git a/drivers/watchdog/bcm_kona_wdt.c b/drivers/watchdog/bcm_kona_wdt.c
index e0c9842..76b0080 100644
--- a/drivers/watchdog/bcm_kona_wdt.c
+++ b/drivers/watchdog/bcm_kona_wdt.c
@@ -274,7 +274,7 @@ static int bcm_kona_wdt_stop(struct watchdog_device *wdog)
.get_timeleft = bcm_kona_wdt_get_timeleft,
};
-static struct watchdog_info bcm_kona_wdt_info = {
+static const struct watchdog_info bcm_kona_wdt_info = {
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
WDIOF_KEEPALIVEPING,
.identity = "Broadcom Kona Watchdog Timer",
diff --git a/drivers/watchdog/cadence_wdt.c b/drivers/watchdog/cadence_wdt.c
index 98acef7..8d61e8b 100644
--- a/drivers/watchdog/cadence_wdt.c
+++ b/drivers/watchdog/cadence_wdt.c
@@ -262,7 +262,7 @@ static irqreturn_t cdns_wdt_irq_handler(int irq, void
*dev_id)
* Info structure used to indicate the features supported by the device
* to the upper layers. This is defined in watchdog.h header file.
*/
-static struct watchdog_info cdns_wdt_info = {
+static const struct watchdog_info cdns_wdt_info = {
.identity = "cdns_wdt watchdog",
.options= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
diff --git a/drivers/watchdog/da9052_wdt.c b/drivers/watchdog/da9052_wdt.c
index 2fc19a3..d86a57e 100644
--- a/drivers/watchdog/da9052_wdt.c
+++ b/drivers/watchdog/da9052_wdt.c
@@ -140,7 +140,7 @@ static int da9052_wdt_ping(struct watchdog_device *wdt_dev)
return ret;
}
-static struct watchdog_info da9052_wdt_info = {
+static const struct watchdog_info da9052_wdt_info = {
.options= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
.identity = "DA9052 Watchdog",
};
diff --git a/drivers/watchdog/da9055_wdt.c b/drivers/watchdog/da9055_wdt.c
index 8377c43..4f30818 100644
--- a/drivers/watchdog/da9055_wdt.c
+++ b/drivers/watchdog/da9055_wdt.c
@@ -108,7 +108,7 @@ static int da9055_wdt_stop(struct watchdog_device *wdt_dev)
return da9055_wdt_set_timeout(wdt_dev, 0);
}
-static struct watchdog_info da9055_wdt_info = {
+static const struct watchdog_info da9055_wdt_info = {
.options= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
.identity = "DA9055 Watchdog",
};
diff --git a/drivers/watchdog/digicolor_wdt.c b/drivers/watchdog/digicolor_wdt.c
index 77df772..dfe7294 100644
--- a/drivers/watchdog/digicolor_wdt.c
+++ b/drivers/watchdog/digicolor_wdt.c
@@ -105,7 +105,7 @@ static unsigned int dc_wdt_get_timeleft(struct
watchdog_device *wdog)
.restart= dc_wdt_restart,
};
-static struct watchdog_info dc_wdt_info = {
+static const struct watchdog_info dc_wdt_info = {
.options= WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE
| WDIOF_KEEPALIVEPING,
.identity = "Conexant Digicolor Watchdog",
diff --git a/drivers/watchdog/imgpdc_wdt.c b/drivers/watchdog/imgpdc_wdt.c
index 516fbef..6ed39de 100644
--- a/drivers/watchdog/imgpdc_wdt.c
+++ b/drivers/watchdog/imgpdc_wdt.c
@@ -161,7 +161,7 @@ static int pdc_wdt_restart(struct watchd
Re: [PATCH tip/master v2] kprobes: extable: Identify kprobes' insn-slots as kernel text area
Hi Masami, [auto build test ERROR on tip/master] url: https://github.com/0day-ci/linux/commits/Masami-Hiramatsu/kprobes-extable-Identify-kprobes-insn-slots-as-kernel-text-area/20161226-233830 config: sparc64-defconfig (attached as .config) compiler: sparc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705 reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=sparc64 All errors (new ones prefixed by >>): kernel/built-in.o: In function `__kernel_text_address': >> (.text+0x202b0): undefined reference to `kprobe_insn_slots' kernel/built-in.o: In function `__kernel_text_address': >> (.text+0x202b8): undefined reference to `__is_insn_slot_addr' kernel/built-in.o: In function `__kernel_text_address': (.text+0x202bc): undefined reference to `kprobe_insn_slots' kernel/built-in.o: In function `kernel_text_address': (.text+0x20374): undefined reference to `kprobe_insn_slots' kernel/built-in.o: In function `kernel_text_address': (.text+0x2037c): undefined reference to `__is_insn_slot_addr' kernel/built-in.o: In function `kernel_text_address': (.text+0x20380): undefined reference to `kprobe_insn_slots' --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip
Re: [GIT pull] smp/hotplug: Removal of notifiers
On 12/26/2016 10:45 AM, Markus Trippelsdorf wrote: > On 2016.12.26 at 12:06 +0100, Markus Trippelsdorf wrote: >> On 2016.12.26 at 08:45 +0100, Markus Trippelsdorf wrote: >>> On 2016.12.25 at 14:39 +0100, Thomas Gleixner wrote: Linus, please pull the latest smp-urgent-for-linus git tree from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git smp-urgent-for-linus Thomas Gleixner (11): cpu/hotplug: Prevent overwriting of callbacks >>> The following commit: >>> >>> commit dc280d93623927570da279e99393879dbbab39e7 >>> Author: Thomas Gleixner >>> Date: Wed Dec 21 20:19:49 2016 +0100 >>> >>> cpu/hotplug: Prevent overwriting of callbacks >>> >>> results in an early OOPs during boot on my AMD machine. >>> I haven't wrote down the entire backtrace, but basically things start to >>> go wrong in mce_threshold_create_device() from >>> arch/x86/kernel/cpu/mcheck/mce_amd.c. >>> >>> # CONFIG_HOTPLUG_CPU is not set >>> >>> Reverting the commit "fixes" the issue for me. >> CCing Sebastian and Borislav. > BUG: unable to handle kernel NULL pointer dereference at 004c > > RIP: kobject_get at lib/kobject.c:594 > (inlined by) kobject_add_internal at lib/kobject.c:214 > > ? kobj_to_dev at include/linux/device.h:968 (discriminator 1) > (inlined by) get_device at drivers/base/core.c:1796 (discriminator 1) > > ? kobject_add at lib/kobject.c:415 > > ? kobject_create_and_add at lib/kobject.c:753 > > ? threshold_create_bank at arch/x86/kernel/cpu/mcheck/mce_amd.c:1212 > (inlined by) mce_threshold_create_device at > arch/x86/kernel/cpu/mcheck/mce_amd.c:1348 > > The comment in arch/x86/kernel/cpu/mcheck/mce_amd.c says: > > 1384 * mcheck_init_device should be inited before threshold_init_device to > 1385 * initialize mce_device, otherwise a NULL ptr dereference will cause > panic. My nightly test hit this as well. AMD only, Intel passed. I haven't verified whether commit that Markus implicated is the one that caused this but it's the same BUG signature (but possibly slightly different stack) [1.554351] smpboot: CPU0: AMD Engineering Sample (family: 0x10, model: 0x4, stepping: 0x1) ... [ 33.579949] BUG: unable to handle kernel NULL pointer dereference at 004c [ 33.588018] IP: kobject_get+0x11/0x80 [ 33.591787] PGD 0 [ 33.591788] [ 33.595386] Oops: [#1] SMP [ 33.598620] Modules linked in: [ 33.601765] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.10.0-rc1upstream #1 [ 33.608936] Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./To be filled by O.E.M., BIOS 080014 07/18/200 8 [ 33.620136] task: 880216eb6d40 task.stack: c9c6 [ 33.626235] RIP: 0010:kobject_get+0x11/0x80 [ 33.630543] RSP: 0018:c9c63c98 EFLAGS: 00010202 [ 33.635925] RAX: 81b6ba09 RBX: 0010 RCX: [ 33.643276] RDX: RSI: 002f RDI: 0010 [ 33.650627] RBP: c9c63ca8 R08: 0001 R09: 0025 [ 33.657978] R10: dead0200 R11: dead0100 R12: 8802164887c0 [ 33.665329] R13: R14: d538 R15: 88021694c180 [ 33.672680] FS: () GS:88021fc8() knlGS: [ 33.681015] CS: 0010 DS: ES: CR0: 80050033 [ 33.686933] CR2: 004c CR3: 01e0a000 CR4: 06e0 [ 33.694284] Call Trace: [ 33.696803] kobject_add_internal+0x40/0x2e0 [ 33.701199] ? kfree_const+0x1d/0x30 [ 33.704878] kobject_add_varg+0x38/0x60 [ 33.708829] kobject_add+0x44/0x70 [ 33.712331] kobject_create_and_add+0x3e/0x80 [ 33.716818] mce_threshold_create_device+0x128/0x380 [ 33.721931] ? __debugfs_create_file+0xe9/0x130 [ 33.726596] threshold_init_device+0x26/0x56 [ 33.730994] ? severities_debugfs_init+0x3c/0x3c [ 33.735749] ? severities_debugfs_init+0x3c/0x3c [ 33.740504] do_one_initcall+0x45/0x170 [ 33.744455] kernel_init_freeable+0x17b/0x214 [ 33.748941] ? kernel_init_freeable+0x214/0x214 [ 33.753606] ? rest_init+0x90/0x90 [ 33.757108] kernel_init+0x9/0x100 [ 33.760610] ret_from_fork+0x25/0x30 [ 33.764289] Code: 89 e5 e8 b3 a6 e5 ff c9 c3 90 55 48 89 e5 e8 a7 a6 e5 ff c9 c3 0f 1f 44 00 00 55 48 89 e5 53 48 89 fb 48 83 ec 08 48 85 ff 74 18 47 3c 01 74 1c b8 01 00 00 00 f0 0f c1 43 38 83 c0 01 83 f8 [ 33.783741] RIP: kobject_get+0x11/0x80 RSP: c9c63c98 [ 33.789570] CR2: 004c [ 33.792984] ---[ end trace 861eb820e5b8a9c8 ]--- [ 33.797737] Kernel panic - not syncing: Fatal exception [ 33.803132] Kernel Offset: disabled [ 33.806722] ---[ end Kernel panic - not syncing: Fatal exception
[RFC 3/8] KVM: arm/arm64: Add the EL1 physical timer context
Add the EL1 physical timer context.
Signed-off-by: Jintack Lim
---
include/kvm/arm_arch_timer.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
index cf84145..d21652a 100644
--- a/include/kvm/arm_arch_timer.h
+++ b/include/kvm/arm_arch_timer.h
@@ -45,6 +45,7 @@ struct arch_timer_context {
struct arch_timer_cpu {
struct arch_timer_context vtimer;
+ struct arch_timer_context ptimer;
/* Background timer used when the guest is not running */
struct hrtimer timer;
@@ -77,4 +78,5 @@ bool kvm_timer_should_fire(struct kvm_vcpu *vcpu,
void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu);
#define vcpu_vtimer(v) (&(v)->arch.timer_cpu.vtimer)
+#define vcpu_ptimer(v) (&(v)->arch.timer_cpu.ptimer)
#endif
--
1.9.1
[RFC 6/8] KVM: arm/arm64: Update the physical timer interrupt level
Now that we maintain the EL1 physical timer register states of the VM,
update the physical timer interrupt level along with the virtual one.
Note that the emulated EL1 physical timer is not mapped to any hardware
timer, so we let vgic know that.
With this commit, VMs are able to get the physical timer interrupts
while they are runnable. But they won't get interrupts once vcpus go to
sleep since we don't have code to wake vcpus up on the emulated physical
timer expiration yet.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/arm.c| 3 +-
virt/kvm/arm/arch_timer.c | 76 ++-
2 files changed, 64 insertions(+), 15 deletions(-)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 37d1623..d2dfa32 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -295,7 +295,8 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
{
- return kvm_timer_should_fire(vcpu, vcpu_vtimer(vcpu));
+ return kvm_timer_should_fire(vcpu, vcpu_vtimer(vcpu)) ||
+ kvm_timer_should_fire(vcpu, vcpu_ptimer(vcpu));
}
void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index ed80864..aa7e243 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -91,7 +91,8 @@ static void kvm_timer_inject_irq_work(struct work_struct
*work)
vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired);
vcpu->arch.timer_cpu.armed = false;
- WARN_ON(!kvm_timer_should_fire(vcpu, vcpu_vtimer(vcpu)));
+ WARN_ON(!kvm_timer_should_fire(vcpu, vcpu_vtimer(vcpu)) &&
+ !kvm_timer_should_fire(vcpu, vcpu_ptimer(vcpu)));
/*
* If the vcpu is blocked we want to wake it up so that it will see
@@ -130,6 +131,33 @@ static u64 kvm_timer_compute_delta(struct kvm_vcpu *vcpu,
return 0;
}
+static bool kvm_timer_irq_can_fire(struct arch_timer_context *timer_ctx)
+{
+ return !(timer_ctx->cnt_ctl & ARCH_TIMER_CTRL_IT_MASK) &&
+ (timer_ctx->cnt_ctl & ARCH_TIMER_CTRL_ENABLE);
+}
+
+/*
+ * Returns minimal timer expiration time in ns among guest timers.
+ * Note that it will return inf time if none of timers can fire.
+ */
+static u64 kvm_timer_min_block(struct kvm_vcpu *vcpu)
+{
+ u64 min_virt = ULLONG_MAX, min_phys = ULLONG_MAX;
+ struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
+ struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
+
+ if (kvm_timer_irq_can_fire(vtimer))
+ min_virt = kvm_timer_compute_delta(vcpu, vtimer);
+
+ if (kvm_timer_irq_can_fire(ptimer))
+ min_phys = kvm_timer_compute_delta(vcpu, ptimer);
+
+ WARN_ON((min_virt == ULLONG_MAX) && (min_phys == ULLONG_MAX));
+
+ return min(min_virt, min_phys);
+}
+
static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt)
{
struct arch_timer_cpu *timer;
@@ -144,7 +172,7 @@ static enum hrtimer_restart kvm_timer_expire(struct hrtimer
*hrt)
* PoV (NTP on the host may have forced it to expire
* early). If we should have slept longer, restart it.
*/
- ns = kvm_timer_compute_delta(vcpu, vcpu_vtimer(vcpu));
+ ns = kvm_timer_min_block(vcpu);
if (unlikely(ns)) {
hrtimer_forward_now(hrt, ns_to_ktime(ns));
return HRTIMER_RESTART;
@@ -154,12 +182,6 @@ static enum hrtimer_restart kvm_timer_expire(struct
hrtimer *hrt)
return HRTIMER_NORESTART;
}
-static bool kvm_timer_irq_can_fire(struct arch_timer_context *timer_ctx)
-{
- return !(timer_ctx->cnt_ctl & ARCH_TIMER_CTRL_IT_MASK) &&
- (timer_ctx->cnt_ctl & ARCH_TIMER_CTRL_ENABLE);
-}
-
bool kvm_timer_should_fire(struct kvm_vcpu *vcpu,
struct arch_timer_context *timer_ctx)
{
@@ -191,6 +213,21 @@ static void kvm_timer_update_mapped_irq(struct kvm_vcpu
*vcpu, bool new_level,
WARN_ON(ret);
}
+static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level,
+struct arch_timer_context *timer)
+{
+ int ret;
+
+ BUG_ON(!vgic_initialized(vcpu->kvm));
+
+ timer->irq.level = new_level;
+ trace_kvm_timer_update_irq(vcpu->vcpu_id, timer->irq.irq,
+ timer->irq.level);
+ ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, timer->irq.irq,
+ timer->irq.level);
+ WARN_ON(ret);
+}
+
/*
* Check if there was a change in the timer state (should we raise or lower
* the line level to the GIC).
@@ -198,6 +235,7 @@ static void kvm_timer_update_mapped_irq(struct kvm_vcpu
*vcpu, bool new_level,
static int kvm_timer_update_state(struct kvm_vcpu *vcpu)
{
struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
+ struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
/*
* If userspace m
[RFC 7/8] KVM: arm/arm64: Set up a background timer for the physical timer emulation
Set a background timer for the EL1 physical timer emulation while VMs are
running, so that VMs get interrupts for the physical timer in a timely
manner.
We still use just one background timer. When a VM is runnable, we use
the background timer for the physical timer emulation. When the VM is
about to be blocked, we use the background timer to wake up the vcpu at
the earliest timer expiration among timers the VM is using.
As a result, the assumption that the background timer is not armed while
VMs are running does not hold any more. So, remove BUG_ON()s and
WARN_ON()s accordingly.
Signed-off-by: Jintack Lim
---
virt/kvm/arm/arch_timer.c | 42 +++---
1 file changed, 31 insertions(+), 11 deletions(-)
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index aa7e243..be8d953 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -91,9 +91,6 @@ static void kvm_timer_inject_irq_work(struct work_struct
*work)
vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired);
vcpu->arch.timer_cpu.armed = false;
- WARN_ON(!kvm_timer_should_fire(vcpu, vcpu_vtimer(vcpu)) &&
- !kvm_timer_should_fire(vcpu, vcpu_ptimer(vcpu)));
-
/*
* If the vcpu is blocked we want to wake it up so that it will see
* the timer has expired when entering the guest.
@@ -139,7 +136,6 @@ static bool kvm_timer_irq_can_fire(struct
arch_timer_context *timer_ctx)
/*
* Returns minimal timer expiration time in ns among guest timers.
- * Note that it will return inf time if none of timers can fire.
*/
static u64 kvm_timer_min_block(struct kvm_vcpu *vcpu)
{
@@ -153,7 +149,9 @@ static u64 kvm_timer_min_block(struct kvm_vcpu *vcpu)
if (kvm_timer_irq_can_fire(ptimer))
min_phys = kvm_timer_compute_delta(vcpu, ptimer);
- WARN_ON((min_virt == ULLONG_MAX) && (min_phys == ULLONG_MAX));
+ /* If none of timers can fire, then return 0 */
+ if ((min_virt == ULLONG_MAX) && (min_phys == ULLONG_MAX))
+ return 0;
return min(min_virt, min_phys);
}
@@ -257,6 +255,26 @@ static int kvm_timer_update_state(struct kvm_vcpu *vcpu)
}
/*
+ * Schedule the background timer for the emulated timer. The background timer
+ * runs whenever vcpu is runnable and the timer is not expired.
+ */
+static void kvm_timer_emulate(struct kvm_vcpu *vcpu,
+ struct arch_timer_context *timer_ctx)
+{
+ struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+
+ if (kvm_timer_should_fire(vcpu, timer_ctx))
+ return;
+
+ if (!kvm_timer_irq_can_fire(timer_ctx))
+ return;
+
+ /* The timer has not yet expired, schedule a background timer */
+ timer_disarm(timer);
+ timer_arm(timer, kvm_timer_compute_delta(vcpu, timer_ctx));
+}
+
+/*
* Schedule the background timer before calling kvm_vcpu_block, so that this
* thread is removed from its waitqueue and made runnable when there's a timer
* interrupt to handle.
@@ -267,8 +285,6 @@ void kvm_timer_schedule(struct kvm_vcpu *vcpu)
struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
- BUG_ON(timer_is_armed(timer));
-
/*
* No need to schedule a background timer if any guest timer has
* already expired, because kvm_vcpu_block will return before putting
@@ -290,13 +306,21 @@ void kvm_timer_schedule(struct kvm_vcpu *vcpu)
* The guest timers have not yet expired, schedule a background timer.
* Pick smaller expiration time between phys and virt timer.
*/
+ timer_disarm(timer);
timer_arm(timer, kvm_timer_min_block(vcpu));
}
void kvm_timer_unschedule(struct kvm_vcpu *vcpu)
{
struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+
timer_disarm(timer);
+
+ /*
+* Now we return from the blocking. If we have any timer to emulate,
+* and it's not expired, set the background timer for it.
+*/
+ kvm_timer_emulate(vcpu, vcpu_ptimer(vcpu));
}
/**
@@ -375,10 +399,6 @@ void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
*/
void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu)
{
- struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-
- BUG_ON(timer_is_armed(timer));
-
/*
* The guest could have modified the timer registers or the timer
* could have expired, update the timer state.
--
1.9.1
Re: [PATCH tip/master v2] kprobes: extable: Identify kprobes' insn-slots as kernel text area
Hi Masami,
[auto build test ERROR on tip/master]
url:
https://github.com/0day-ci/linux/commits/Masami-Hiramatsu/kprobes-extable-Identify-kprobes-insn-slots-as-kernel-text-area/20161226-233830
config: sh-r7785rp_defconfig (attached as .config)
compiler: sh4-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
-O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=sh
All errors (new ones prefixed by >>):
kernel/built-in.o: In function `init_kernel_text':
>> kernel/extable.c:64: undefined reference to `__is_insn_slot_addr'
>> kernel/extable.c:64: undefined reference to `kprobe_insn_slots'
kernel/built-in.o: In function `kernel_text_address':
kernel/extable.c:134: undefined reference to `__is_insn_slot_addr'
kernel/extable.c:134: undefined reference to `kprobe_insn_slots'
vim +64 kernel/extable.c
^1da177e Linus Torvalds 2005-04-16 58 e =
search_module_extables(addr);
^1da177e Linus Torvalds 2005-04-16 59 return e;
^1da177e Linus Torvalds 2005-04-16 60 }
^1da177e Linus Torvalds 2005-04-16 61
4a44bac1 Ingo Molnar2009-03-19 62 static inline int
init_kernel_text(unsigned long addr)
4a44bac1 Ingo Molnar2009-03-19 63 {
4a44bac1 Ingo Molnar2009-03-19 @64 if (addr >= (unsigned
long)_sinittext &&
5ecbe3c3 Helge Deller 2013-11-28 65 addr < (unsigned
long)_einittext)
4a44bac1 Ingo Molnar2009-03-19 66 return 1;
4a44bac1 Ingo Molnar2009-03-19 67 return 0;
:: The code at line 64 was first introduced by commit
:: 4a44bac1f98223ed77e47bf3b42fcfd10cddd85f symbols, stacktrace: look up
init symbols after module symbols
:: TO: Ingo Molnar
:: CC: Ingo Molnar
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
[RFC 5/8] KVM: arm64: Add the EL1 physical timer access handler
KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle
those traps. This results in terminating VMs. Instead, set a handler for
the EL1 phys timer access, and inject an undefined exception as an
intermediate step.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 87e7e66..fd9e747 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -820,6 +820,30 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
+static bool access_cntp_tval(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ kvm_inject_undefined(vcpu);
+ return true;
+}
+
+static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ kvm_inject_undefined(vcpu);
+ return true;
+}
+
+static bool access_cntp_cval(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ kvm_inject_undefined(vcpu);
+ return true;
+}
+
/*
* Architected system registers.
* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
@@ -1029,6 +1053,16 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b011),
NULL, reset_unknown, TPIDRRO_EL0 },
+ /* CNTP_TVAL_EL0 */
+ { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b000),
+ access_cntp_tval },
+ /* CNTP_CTL_EL0 */
+ { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b001),
+ access_cntp_ctl },
+ /* CNTP_CVAL_EL0 */
+ { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b010),
+ access_cntp_cval },
+
/* PMEVCNTRn_EL0 */
PMU_PMEVCNTR_EL0(0),
PMU_PMEVCNTR_EL0(1),
--
1.9.1
[RFC 4/8] KVM: arm/arm64: Initialize the emulated EL1 physical timer
Initialize the emulated EL1 physical timer with the default irq number.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/reset.c | 9 -
arch/arm64/kvm/reset.c | 9 -
include/kvm/arm_arch_timer.h | 3 ++-
virt/kvm/arm/arch_timer.c| 12 ++--
4 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c
index 4b5e802..1da8b2d 100644
--- a/arch/arm/kvm/reset.c
+++ b/arch/arm/kvm/reset.c
@@ -37,6 +37,11 @@
.usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
};
+static const struct kvm_irq_level cortexa_ptimer_irq = {
+ { .irq = 30 },
+ .level = 1,
+};
+
static const struct kvm_irq_level cortexa_vtimer_irq = {
{ .irq = 27 },
.level = 1,
@@ -58,6 +63,7 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
{
struct kvm_regs *reset_regs;
const struct kvm_irq_level *cpu_vtimer_irq;
+ const struct kvm_irq_level *cpu_ptimer_irq;
switch (vcpu->arch.target) {
case KVM_ARM_TARGET_CORTEX_A7:
@@ -65,6 +71,7 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
reset_regs = &cortexa_regs_reset;
vcpu->arch.midr = read_cpuid_id();
cpu_vtimer_irq = &cortexa_vtimer_irq;
+ cpu_ptimer_irq = &cortexa_ptimer_irq;
break;
default:
return -ENODEV;
@@ -77,5 +84,5 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
kvm_reset_coprocs(vcpu);
/* Reset arch_timer context */
- return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
+ return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq, cpu_ptimer_irq);
}
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index 5bc4608..74322c2 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -46,6 +46,11 @@
COMPAT_PSR_I_BIT | COMPAT_PSR_F_BIT),
};
+static const struct kvm_irq_level default_ptimer_irq = {
+ .irq= 30,
+ .level = 1,
+};
+
static const struct kvm_irq_level default_vtimer_irq = {
.irq= 27,
.level = 1,
@@ -110,6 +115,7 @@ int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm,
long ext)
int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
{
const struct kvm_irq_level *cpu_vtimer_irq;
+ const struct kvm_irq_level *cpu_ptimer_irq;
const struct kvm_regs *cpu_reset;
switch (vcpu->arch.target) {
@@ -123,6 +129,7 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
}
cpu_vtimer_irq = &default_vtimer_irq;
+ cpu_ptimer_irq = &default_ptimer_irq;
break;
}
@@ -136,5 +143,5 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
kvm_pmu_vcpu_reset(vcpu);
/* Reset timer */
- return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
+ return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq, cpu_ptimer_irq);
}
diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
index d21652a..04ed9c1 100644
--- a/include/kvm/arm_arch_timer.h
+++ b/include/kvm/arm_arch_timer.h
@@ -61,7 +61,8 @@ struct arch_timer_cpu {
int kvm_timer_enable(struct kvm_vcpu *vcpu);
void kvm_timer_init(struct kvm *kvm);
int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
-const struct kvm_irq_level *irq);
+const struct kvm_irq_level *virt_irq,
+const struct kvm_irq_level *phys_irq);
void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 3bd6063..ed80864 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -339,9 +339,11 @@ void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu)
}
int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
-const struct kvm_irq_level *irq)
+const struct kvm_irq_level *virt_irq,
+const struct kvm_irq_level *phys_irq)
{
struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
+ struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
/*
* The vcpu timer irq number cannot be determined in
@@ -349,7 +351,8 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
* kvm_vcpu_set_target(). To handle this, we determine
* vcpu timer irq number when the vcpu is reset.
*/
- vtimer->irq.irq = irq->irq;
+ vtimer->irq.irq = virt_irq->irq;
+ ptimer->irq.irq = phys_irq->irq;
/*
* The bits in CNTV_CTL are architecturally reset to UNKNOWN for ARMv8
@@ -358,6 +361,7 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
* the ARMv7 architecture.
*/
vtimer->cnt_ctl = 0;
+ ptimer->cnt_ctl = 0;
kvm_timer_update_state(vcpu);
return 0;
@@ -477,11 +481,15 @@ void kvm_timer_vcpu_terminate(struct kvm_vcpu
[PATCH v2] ARM: dts: sunxi: Add num-cs for A20 spi nodes
The spi0 controller on the A20 have up to 4 CS (Chip Select) while the
others three only have 1.
Add the num-cs property to each node.
The current driver doesn't read this property but this is useful for
downstream user of DTS (FreeBSD for example).
Signed-off-by: Emmanuel Vadot
---
Changes in v2:
* Explain that driver doesn't support this but that it is useful
for downstream users of DTS.
arch/arm/boot/dts/sun7i-a20.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 94cf5a1c7172..ed21982c81cb 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -871,6 +871,7 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ num-cs = 4;
};
spi1: spi@01c06000 {
@@ -885,6 +886,7 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ num-cs = 1;
};
emac: ethernet@01c0b000 {
@@ -1037,6 +1039,7 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ num-cs = 1;
};
ahci: sata@01c18000 {
@@ -1079,6 +1082,7 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ num-cs = 1;
};
pio: pinctrl@01c20800 {
--
2.11.0
[RFC 8/8] KVM: arm/arm64: Emulate the EL1 phys timer register access
Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL.
Now the VM is able to use the EL1 physical timer.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c| 35 ---
include/kvm/arm_arch_timer.h | 3 +++
virt/kvm/arm/arch_timer.c| 4 ++--
3 files changed, 37 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index fd9e747..7cef94f 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -824,7 +824,15 @@ static bool access_cntp_tval(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
- kvm_inject_undefined(vcpu);
+ struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
+ cycle_t now = kvm_phys_timer_read();
+
+ if (p->is_write) {
+ ptimer->cnt_cval = p->regval + now;
+ kvm_timer_emulate(vcpu, ptimer);
+ } else
+ p->regval = ptimer->cnt_cval - now;
+
return true;
}
@@ -832,7 +840,21 @@ static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
- kvm_inject_undefined(vcpu);
+ struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
+
+ if (p->is_write) {
+ /* ISTATUS bit is read-only */
+ ptimer->cnt_ctl = p->regval & ~ARCH_TIMER_CTRL_IT_STAT;
+ kvm_timer_emulate(vcpu, ptimer);
+ } else {
+ cycle_t now = kvm_phys_timer_read();
+
+ p->regval = ptimer->cnt_ctl;
+ /* Set ISTATUS bit if it's expired */
+ if (ptimer->cnt_cval <= now)
+ p->regval |= ARCH_TIMER_CTRL_IT_STAT;
+ }
+
return true;
}
@@ -840,7 +862,14 @@ static bool access_cntp_cval(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
- kvm_inject_undefined(vcpu);
+ struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
+
+ if (p->is_write) {
+ ptimer->cnt_cval = p->regval;
+ kvm_timer_emulate(vcpu, ptimer);
+ } else
+ p->regval = ptimer->cnt_cval;
+
return true;
}
diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
index 04ed9c1..776579b 100644
--- a/include/kvm/arm_arch_timer.h
+++ b/include/kvm/arm_arch_timer.h
@@ -75,6 +75,9 @@ bool kvm_timer_should_fire(struct kvm_vcpu *vcpu,
struct arch_timer_context *timer_ctx);
void kvm_timer_schedule(struct kvm_vcpu *vcpu);
void kvm_timer_unschedule(struct kvm_vcpu *vcpu);
+void kvm_timer_emulate(struct kvm_vcpu *vcpu, struct arch_timer_context
*timer);
+
+cycle_t kvm_phys_timer_read(void);
void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu);
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index be8d953..7a161f8 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -39,7 +39,7 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu)
vcpu_vtimer(vcpu)->active_cleared_last = false;
}
-static cycle_t kvm_phys_timer_read(void)
+cycle_t kvm_phys_timer_read(void)
{
return timecounter->cc->read(timecounter->cc);
}
@@ -258,7 +258,7 @@ static int kvm_timer_update_state(struct kvm_vcpu *vcpu)
* Schedule the background timer for the emulated timer. The background timer
* runs whenever vcpu is runnable and the timer is not expired.
*/
-static void kvm_timer_emulate(struct kvm_vcpu *vcpu,
+void kvm_timer_emulate(struct kvm_vcpu *vcpu,
struct arch_timer_context *timer_ctx)
{
struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
--
1.9.1
[RFC 0/8] Provide the EL1 physical timer to the VM
The ARM architecture defines the EL1 physical timer and the virtual timer, and it is reasonable for an OS to expect to be able to access both. However, the current KVM implementation does not provide the EL1 physical timer to VMs but terminates VMs on access to the timer. On VHE systems, this would be as simple as allowing full access to the EL1 physical timer to VMs because the KVM host does not use the EL1 physical timer. However, on non-VHE systems, the KVM host already uses the EL1 physical timer which prevents us from granting full access of the EL1 physical timer to VMs. This patchset enables VMs to use the EL1 physical timer through trap-and-emulate. The KVM host emulates each EL1 physical timer register access and sets up the background timer accordingly. When the background timer expires, the KVM host injects EL1 physical timer interrupts to the VM. Alternatively, it's also possible to allow VMs to access the EL1 physical timer without trapping. However, this requires somehow using the EL2 physical timer for the Linux host while running the VM instead of the EL1 physical timer. Right now I just implemented trap-and-emulate because this was straightforward to do, and I leave it to future work to determine if transferring the EL1 physical timer state to the EL2 timer provides any performance benefit. This feature will be useful for any OS that wishes to access the EL1 physical timer. Nested virtualization is one of those use cases. A nested hypervisor running inside a VM would think it has full access to the hardware and naturally tries to use the EL1 physical timer as Linux would do. Other nested hypervisors may try to use the EL2 physical timer as Xen would do, but supporting the EL2 physical timer to the VM is out of scope of this patchset. This patchset will make it easy to add the EL2 timer support in the future, though. Note, Linux VMs booting in EL1 will be unaffected by this patch set and will continue to use only the virtual timer and this patch set will therefore not introduce any performance degredation as a result of trap-and-emulate. Jintack Lim (8): KVM: arm/arm64: Abstract virtual timer context into separate structure KVM: arm/arm64: Decouple kvm timer functions from virtual timer KVM: arm/arm64: Add the EL1 physical timer context KVM: arm/arm64: Initialize the emulated EL1 physical timer KVM: arm64: Add the EL1 physical timer access handler KVM: arm/arm64: Update the physical timer interrupt level KVM: arm/arm64: Set up a background timer for the physical timer emulation KVM: arm/arm64: Emulate the EL1 phys timer register access arch/arm/kvm/arm.c | 3 +- arch/arm/kvm/reset.c | 9 +- arch/arm64/kvm/reset.c | 9 +- arch/arm64/kvm/sys_regs.c| 63 + include/kvm/arm_arch_timer.h | 43 + virt/kvm/arm/arch_timer.c| 214 ++- virt/kvm/arm/hyp/timer-sr.c | 16 ++-- 7 files changed, 264 insertions(+), 93 deletions(-) -- 1.9.1
[RFC 2/8] KVM: arm/arm64: Decouple kvm timer functions from virtual timer
Now that we have a separate structure for timer context, make functions
general so that they can work on any timer context, not just the virtual
timer context. This does not change the virtual timer functionality.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/arm.c | 2 +-
include/kvm/arm_arch_timer.h | 3 +-
virt/kvm/arm/arch_timer.c| 65 +---
3 files changed, 40 insertions(+), 30 deletions(-)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 19b5f5c..37d1623 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -295,7 +295,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
{
- return kvm_timer_should_fire(vcpu);
+ return kvm_timer_should_fire(vcpu, vcpu_vtimer(vcpu));
}
void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
index 7dabe56..cf84145 100644
--- a/include/kvm/arm_arch_timer.h
+++ b/include/kvm/arm_arch_timer.h
@@ -69,7 +69,8 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
u64 kvm_arm_timer_get_reg(struct kvm_vcpu *, u64 regid);
int kvm_arm_timer_set_reg(struct kvm_vcpu *, u64 regid, u64 value);
-bool kvm_timer_should_fire(struct kvm_vcpu *vcpu);
+bool kvm_timer_should_fire(struct kvm_vcpu *vcpu,
+ struct arch_timer_context *timer_ctx);
void kvm_timer_schedule(struct kvm_vcpu *vcpu);
void kvm_timer_unschedule(struct kvm_vcpu *vcpu);
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 30a64df..3bd6063 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -91,7 +91,7 @@ static void kvm_timer_inject_irq_work(struct work_struct
*work)
vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired);
vcpu->arch.timer_cpu.armed = false;
- WARN_ON(!kvm_timer_should_fire(vcpu));
+ WARN_ON(!kvm_timer_should_fire(vcpu, vcpu_vtimer(vcpu)));
/*
* If the vcpu is blocked we want to wake it up so that it will see
@@ -100,12 +100,22 @@ static void kvm_timer_inject_irq_work(struct work_struct
*work)
kvm_vcpu_kick(vcpu);
}
-static u64 kvm_timer_compute_delta(struct kvm_vcpu *vcpu)
+static u64 kvm_timer_cntvoff(struct kvm_vcpu *vcpu,
+struct arch_timer_context *timer_ctx)
+{
+ if (timer_ctx == vcpu_vtimer(vcpu))
+ return vcpu->kvm->arch.timer.cntvoff;
+
+ return 0;
+}
+
+static u64 kvm_timer_compute_delta(struct kvm_vcpu *vcpu,
+ struct arch_timer_context *timer_ctx)
{
cycle_t cval, now;
- cval = vcpu_vtimer(vcpu)->cnt_cval;
- now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
+ cval = timer_ctx->cnt_cval;
+ now = kvm_phys_timer_read() - kvm_timer_cntvoff(vcpu, timer_ctx);
if (now < cval) {
u64 ns;
@@ -134,7 +144,7 @@ static enum hrtimer_restart kvm_timer_expire(struct hrtimer
*hrt)
* PoV (NTP on the host may have forced it to expire
* early). If we should have slept longer, restart it.
*/
- ns = kvm_timer_compute_delta(vcpu);
+ ns = kvm_timer_compute_delta(vcpu, vcpu_vtimer(vcpu));
if (unlikely(ns)) {
hrtimer_forward_now(hrt, ns_to_ktime(ns));
return HRTIMER_RESTART;
@@ -144,42 +154,40 @@ static enum hrtimer_restart kvm_timer_expire(struct
hrtimer *hrt)
return HRTIMER_NORESTART;
}
-static bool kvm_timer_irq_can_fire(struct kvm_vcpu *vcpu)
+static bool kvm_timer_irq_can_fire(struct arch_timer_context *timer_ctx)
{
- struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
-
- return !(vtimer->cnt_ctl & ARCH_TIMER_CTRL_IT_MASK) &&
- (vtimer->cnt_ctl & ARCH_TIMER_CTRL_ENABLE);
+ return !(timer_ctx->cnt_ctl & ARCH_TIMER_CTRL_IT_MASK) &&
+ (timer_ctx->cnt_ctl & ARCH_TIMER_CTRL_ENABLE);
}
-bool kvm_timer_should_fire(struct kvm_vcpu *vcpu)
+bool kvm_timer_should_fire(struct kvm_vcpu *vcpu,
+ struct arch_timer_context *timer_ctx)
{
- struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
cycle_t cval, now;
- if (!kvm_timer_irq_can_fire(vcpu))
+ if (!kvm_timer_irq_can_fire(timer_ctx))
return false;
- cval = vtimer->cnt_cval;
- now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
+ cval = timer_ctx->cnt_cval;
+ now = kvm_phys_timer_read() - kvm_timer_cntvoff(vcpu, timer_ctx);
return cval <= now;
}
-static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level)
+static void kvm_timer_update_mapped_irq(struct kvm_vcpu *vcpu, bool new_level,
+ struct arch_timer_context *timer_ctx)
{
int ret;
- struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
BUG_ON(!vgic_initialized(vcpu->kvm));
-
[RFC 1/8] KVM: arm/arm64: Abstract virtual timer context into separate structure
Abstract virtual timer context into a separate structure and change all
callers referring to timer registers, irq state and so on. No change in
functionality.
This is about to become very handy when adding the EL1 physical timer.
Signed-off-by: Jintack Lim
Acked-by: Christoffer Dall
---
include/kvm/arm_arch_timer.h | 32 +-
virt/kvm/arm/arch_timer.c| 77 ++--
virt/kvm/arm/hyp/timer-sr.c | 16 -
3 files changed, 63 insertions(+), 62 deletions(-)
diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
index dda39d8..7dabe56 100644
--- a/include/kvm/arm_arch_timer.h
+++ b/include/kvm/arm_arch_timer.h
@@ -28,15 +28,23 @@ struct arch_timer_kvm {
cycle_t cntvoff;
};
-struct arch_timer_cpu {
+struct arch_timer_context {
/* Registers: control register, timer value */
- u32 cntv_ctl; /* Saved/restored */
- cycle_t cntv_cval; /* Saved/restored */
+ u32 cnt_ctl;
+ cycle_t cnt_cval;
+
+ /* Timer IRQ */
+ struct kvm_irq_levelirq;
- /*
-* Anything that is not used directly from assembly code goes
-* here.
-*/
+ /* Active IRQ state caching */
+ boolactive_cleared_last;
+
+ /* Is the timer enabled */
+ boolenabled;
+};
+
+struct arch_timer_cpu {
+ struct arch_timer_context vtimer;
/* Background timer used when the guest is not running */
struct hrtimer timer;
@@ -46,15 +54,6 @@ struct arch_timer_cpu {
/* Background timer active */
boolarmed;
-
- /* Timer IRQ */
- struct kvm_irq_levelirq;
-
- /* Active IRQ state caching */
- boolactive_cleared_last;
-
- /* Is the timer enabled */
- boolenabled;
};
int kvm_timer_hyp_init(void);
@@ -76,4 +75,5 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu);
+#define vcpu_vtimer(v) (&(v)->arch.timer_cpu.vtimer)
#endif
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 27a1f63..30a64df 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -36,7 +36,7 @@
void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu)
{
- vcpu->arch.timer_cpu.active_cleared_last = false;
+ vcpu_vtimer(vcpu)->active_cleared_last = false;
}
static cycle_t kvm_phys_timer_read(void)
@@ -104,7 +104,7 @@ static u64 kvm_timer_compute_delta(struct kvm_vcpu *vcpu)
{
cycle_t cval, now;
- cval = vcpu->arch.timer_cpu.cntv_cval;
+ cval = vcpu_vtimer(vcpu)->cnt_cval;
now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
if (now < cval) {
@@ -146,21 +146,21 @@ static enum hrtimer_restart kvm_timer_expire(struct
hrtimer *hrt)
static bool kvm_timer_irq_can_fire(struct kvm_vcpu *vcpu)
{
- struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+ struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
- return !(timer->cntv_ctl & ARCH_TIMER_CTRL_IT_MASK) &&
- (timer->cntv_ctl & ARCH_TIMER_CTRL_ENABLE);
+ return !(vtimer->cnt_ctl & ARCH_TIMER_CTRL_IT_MASK) &&
+ (vtimer->cnt_ctl & ARCH_TIMER_CTRL_ENABLE);
}
bool kvm_timer_should_fire(struct kvm_vcpu *vcpu)
{
- struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+ struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
cycle_t cval, now;
if (!kvm_timer_irq_can_fire(vcpu))
return false;
- cval = timer->cntv_cval;
+ cval = vtimer->cnt_cval;
now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
return cval <= now;
@@ -169,17 +169,17 @@ bool kvm_timer_should_fire(struct kvm_vcpu *vcpu)
static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level)
{
int ret;
- struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+ struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
BUG_ON(!vgic_initialized(vcpu->kvm));
- timer->active_cleared_last = false;
- timer->irq.level = new_level;
- trace_kvm_timer_update_irq(vcpu->vcpu_id, timer->irq.irq,
- timer->irq.level);
+ vtimer->active_cleared_last = false;
+ vtimer->irq.level = new_level;
+ trace_kvm_timer_update_irq(vcpu->vcpu_id, vtimer->irq.irq,
+ vtimer->irq.level);
ret = kvm_vgic_inject_mapped_irq(vcpu->kvm, vcpu->vcpu_id,
-timer->irq.irq,
-timer->irq.level);
+vtimer->irq.irq,
+
Re: [RFC PATCH 4.10 1/6] crypto/sha256: Refactor the API so it can be used without shash
On 26 December 2016 at 07:57, Herbert Xu wrote: > On Sat, Dec 24, 2016 at 09:57:53AM -0800, Andy Lutomirski wrote: >> >> I actually do use incremental hashing later on. BPF currently >> vmallocs() a big temporary buffer just so it can fill it and hash it. >> I change it to hash as it goes. > > How much data is this supposed to hash on average? If it's a large > amount then perhaps using the existing crypto API would be a better > option than adding this. > This is a good point actually: you didn't explain *why* BPF shouldn't depend on the crypto API.
[PATCH] auxdisplay: fix new ht16k33 build errors
From: Randy Dunlap Fix build errors caused by selecting incorrect kconfig symbols. drivers/built-in.o:(.data+0x19cec): undefined reference to `sys_fillrect' drivers/built-in.o:(.data+0x19cf0): undefined reference to `sys_copyarea' drivers/built-in.o:(.data+0x19cf4): undefined reference to `sys_imageblit' Fixes: 31114fa95bdb (auxdisplay: ht16k33: select framebuffer helper modules) Signed-off-by: Randy Dunlap Cc: Robin van der Gracht Cc: Miguel Ojeda Sandonis Cc: Greg Kroah-Hartman Reported-by: kbuild test robot --- drivers/auxdisplay/Kconfig |6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) --- lnx-410-rc1.orig/drivers/auxdisplay/Kconfig +++ lnx-410-rc1/drivers/auxdisplay/Kconfig @@ -132,9 +132,9 @@ config HT16K33 tristate "Holtek Ht16K33 LED controller with keyscan" depends on FB && OF && I2C && INPUT select FB_SYS_FOPS - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT select INPUT_MATRIXKMAP select FB_BACKLIGHT help
[PATCH] ARM: dts: sunxi: Enable spi1 and spi2 for Olimex A20 SOM EVB
Enable the spi1 and spi2 node since the pins are exposed on the UEXT
connectors.
Signed-off-by: Emmanuel Vadot
---
arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
index 669a1c338c76..fa8c6f60552b 100644
--- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
@@ -300,12 +300,14 @@
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>,
<&spi1_cs0_pins_a>;
+ status = "okay";
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>,
<&spi2_cs0_pins_a>;
+ status = "okay";
};
&uart0 {
--
2.11.0
Re: [RFC PATCH 4.10 1/6] crypto/sha256: Refactor the API so it can be used without shash
On Mon, Dec 26, 2016 at 9:51 AM, Ard Biesheuvel wrote: > On 26 December 2016 at 07:57, Herbert Xu wrote: >> On Sat, Dec 24, 2016 at 09:57:53AM -0800, Andy Lutomirski wrote: >>> >>> I actually do use incremental hashing later on. BPF currently >>> vmallocs() a big temporary buffer just so it can fill it and hash it. >>> I change it to hash as it goes. >> >> How much data is this supposed to hash on average? If it's a large >> amount then perhaps using the existing crypto API would be a better >> option than adding this. >> > > This is a good point actually: you didn't explain *why* BPF shouldn't > depend on the crypto API. According to Daniel, the networking folks want to let embedded systems include BPF without requiring the crypto core. At some point, I'd also like to use modern hash functions for module verification. If doing so would require the crypto core to be available when modules are loaded, then the crypto core couldn't be modular. (Although it occurs to me that my patches get that wrong -- if this change happens, I need to split the code so that the library functions can be built in even if CRYPTO=m.) Daniel, would you be okay with BPF selecting CRYPTO and CRYPTO_HASH? Also, as a bikeshed thought: I could call the functions sha256_init_direct(), etc. Then there wouldn't be namespace collisions and the fact that they bypass accelerated drivers would be more obvious. --Andy
Re: [GIT pull] smp/hotplug: Removal of notifiers
On Mon, 26 Dec 2016, Boris Ostrovsky wrote: > On 12/26/2016 10:45 AM, Markus Trippelsdorf wrote: > > The comment in arch/x86/kernel/cpu/mcheck/mce_amd.c says: > > > > 1384 * mcheck_init_device should be inited before threshold_init_device to > > 1385 * initialize mce_device, otherwise a NULL ptr dereference will cause > > panic. That's not changed by this commit. > My nightly test hit this as well. AMD only, Intel passed. I haven't > verified whether commit that Markus implicated is the one that caused > this but it's the same BUG signature (but possibly slightly different stack) > > [1.554351] smpboot: CPU0: AMD Engineering Sample (family: 0x10, > model: 0x4, stepping: 0x1) > ... Is there anything interesting error message before the BUG hits? I'll try to reproduce on a AMD box tomorrow. Thanks, tglx
Re: [RFC PATCH] ext4: increase the protection of drop nlink and ext4 inode destroy
On Dec 26, 2016, at 5:34 AM, yi zhang wrote:
>
> Because of the disk and hardware issue, the ext4 filesystem have
> many errors, the inode->i_nlink of ext4 becomes zero abnormally
> but the dentry is still positive, it will cause memory corruption
> after the following process:
>
> 1) Due to the inode->i_nlink is 0, this inode will be added into
> the orhpan list,
> 2) ext4_rename() cover this inode, and drop_nlink() will reverse
> the inode->i_nlink to 0x,
> 3) iput() add this inode to LRU,
> 4) evict() will call destroy_inode() to destroy this inode but
> skip removing it from the orphan list,
> 5) after this, the inode's memory address space will be used by
> other module, when the ext4 filesystem change the orphan list, it will
> trample other module's data and then may cause oops.
>
> Although we cannot avoid hardware and disk errors, we can control the
> softwore error in the ext4 module, do not affect other modules and
> increase the difficulty of locating problems.
>
> This patch avoid inode->i_nlink reverse and remove the inode form the
(typo) s/form/from/
> orphan list when destroy it if the list is not empty.
> Signed-off-by: yi zhang
> ---
> fs/ext4/super.c | 1 +
> fs/inode.c | 5 -
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/fs/ext4/super.c b/fs/ext4/super.c
> index 52b0530..617327e 100644
> --- a/fs/ext4/super.c
> +++ b/fs/ext4/super.c
> @@ -975,6 +975,7 @@ static void ext4_destroy_inode(struct inode *inode)
> EXT4_I(inode), sizeof(struct ext4_inode_info),
> true);
> dump_stack();
> + ext4_orphan_del(NULL, inode);
> }
> call_rcu(&inode->i_rcu, ext4_i_callback);
> }
> diff --git a/fs/inode.c b/fs/inode.c
> index 88110fd..079d383 100644
> --- a/fs/inode.c
> +++ b/fs/inode.c
> @@ -279,7 +279,10 @@ static void destroy_inode(struct inode *inode)
> */
> void drop_nlink(struct inode *inode)
> {
> - WARN_ON(inode->i_nlink == 0);
> + if (WARN(inode->i_nlink == 0, "inode %lu nlink"
> + " is already 0", inode->i_ino))
(style) the string should be kept on a single line instead of being
split, especially since it can fit easily.
(defect) this needs to have a newline.
if (WARN(inode->i_nlink == 0,
"inode %lu nlink is already 0\n", inode->i_ino))
Cheers, Andreas
> + return;
> +
> inode->__i_nlink--;
> if (!inode->i_nlink)
> atomic_long_inc(&inode->i_sb->s_remove_count);
> --
> 2.5.0
>
Cheers, Andreas
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