Re: [PATCH v3 0/7] spi: add support for octo mode
Hi Yogesh On 23/10/18 3:07 PM, Yogesh Narayan Gaur wrote: > Add support for octo mode IO data transfer. > Micron flash, mt35xu512aba, supports octal mode data transfer and > NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx). > > Patch series > * Add support for octo mode flags and parsing of same in spi driver. > * Add parsing logic for spi-mem framework and m25p80.c device file. > * Add opcodes for octo I/O commands in spi-nor framework, Read and Write > proto for (1-1-8/1-8-8) mode. > Opcodes are added as per octal data IO commands required for mt35xu512aba > [1] flash. > * Add mode bit required for octo mode in nxp-fspi driver [2]. > * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2]. > You may have to rebase this series to avoid conflicts with recent spi.h changes. Also, I suggest merging patches in [1] with this series if you plan to post another version so that all bits are at one place. Regards Vignesh > Cherry pick below 2 patches (from: > https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git): > c639f871febe6667d9afce28108c634e5636c735 spi: spi-mem: Fix inverted logic > in op sanity check > db122eb8a749a1eff038f9a282c620ab16c4be1d spi: spi-mem: Add extra sanity > checks on the op param > > Tested on LX2160ARDB target with nxp-fspi driver, below are > Read performance number of 1-1-1 and 1-1-8 read protocol. > > root@lxxx:~# cat /proc/mtd > dev:size erasesize name > mtd0: 0400 1000 "spi0.0" > mtd1: 0400 1000 "spi0.1" > root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x100 0read > Copied 16777216 bytes from address 0x in flash to 0read > > real0m2.792s > user0m0.000s > sys 0m2.790s > root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x100 0read > Copied 16777216 bytes from address 0x in flash to 0read > > real0m0.441s > user0m0.000s > sys 0m0.440s > root@ls1012ardb:~# > > Flash device MTD0 configured in 1-1-1 protocol. > Flash device MTD1 configured in 1-1-8 protocol. > > [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384 > [2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=72181 > > Yogesh Gaur (7): > spi: add support for octo mode I/O data transfer > spi: spi-mem: add support for octo mode I/O data transfer > mtd: spi-nor: add opcodes for octo Read/Write commands > mtd: spi-nor: add octo read flag for flash mt35xu512aba > mtd: m25p80: add support of octo mode I/O transfer > spi: nxp-fspi: add octo mode flag bit for octal support > arm64: dts: lx2160a: update fspi node > > Changes for v3: > - Add octo mode support in spi_setup(). > - Rename all patches with 'octal' string modified as 'octo'. > Changes for v2: > - Incorporated review comments of Boris and Vignesh. > > arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 > drivers/mtd/devices/m25p80.c | 9 - > drivers/mtd/spi-nor/spi-nor.c | 15 ++- > drivers/spi/spi-mem.c | 9 - > drivers/spi/spi-nxp-fspi.c| 4 ++-- > drivers/spi/spi.c | 12 ++-- > include/linux/mtd/spi-nor.h | 8 > include/linux/spi/spi.h | 2 ++ > 8 files changed, 56 insertions(+), 7 deletions(-) > -- Regards Vignesh
Re: [PATCH] mfd: bd9571mwv: add volatile register to make DVFS work
On Wed, 03 Oct 2018, Wolfram Sang wrote:
> From: Dien Pham
>
> Because BD9571MWV_DVFS_MONIVDAC is not defined in the volatile table,
> the physical register value is not updated by regmap and DVFS doesn't
> work as expected. Fix it!
>
> Signed-off-by: Dien Pham
> [wsa: rebase, add 'Fixes', reword commit message]
> Signed-off-by: Wolfram Sang
> Fixes: d3ea21272094 ("mfd: Add ROHM BD9571MWV-M MFD PMIC driver")
> ---
>
> Grabbed from the BSP and confirmed by the datasheet. The register is RO
> and reflecting states depending on other registers.
>
> drivers/mfd/bd9571mwv.c | 1 +
> 1 file changed, 1 insertion(+)
Applied, thanks.
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
Re: [RFC PATCH 4/5] mm, memory_hotplug: print reason for the offlining failure
On Wed 07-11-18 14:04:13, Andrew Morton wrote:
> On Wed, 7 Nov 2018 11:18:29 +0100 Michal Hocko wrote:
>
> > From: Michal Hocko
> >
> > The memory offlining failure reporting is inconsistent and insufficient.
> > Some error paths simply do not report the failure to the log at all.
> > When we do report there are no details about the reason of the failure
> > and there are several of them which makes memory offlining failures
> > hard to debug.
> >
> > Make sure that the
> > memory offlining [mem %#010llx-%#010llx] failed
> > message is printed for all failures and also provide a short textual
> > reason for the failure e.g.
> >
> > [ 1984.506184] rac1 kernel: memory offlining [mem
> > 0x826-0x8267fff] failed due to signal backoff
> >
> > this tells us that the offlining has failed because of a signal pending
> > aka user intervention.
> >
> > ...
>
> Some of these messages will come out looking a bit odd.
>
> > @@ -1573,7 +1576,8 @@ static int __ref __offline_pages(unsigned long
> > start_pfn,
> >MIGRATE_MOVABLE, true);
> > if (ret) {
> > mem_hotplug_done();
> > - return ret;
> > + reason = "failed to isolate range";
>
> "memory offlining [mem ...] failed due to failed to isolate range"
>
> > + goto failed_removal
> > }
> >
> > arg.start_pfn = start_pfn;
> > @@ -1582,15 +1586,19 @@ static int __ref __offline_pages(unsigned long
> > start_pfn,
> >
> > ret = memory_notify(MEM_GOING_OFFLINE, &arg);
> > ret = notifier_to_errno(ret);
> > - if (ret)
> > - goto failed_removal;
> > + if (ret) {
> > + reason = "notifiers failure";
>
> "memory offlining [mem ...] failed due to notifiers failure"
>
> > @@ -1607,8 +1615,10 @@ static int __ref __offline_pages(unsigned long
> > start_pfn,
> > * actually in order to make hugetlbfs's object counting consistent.
> > */
> > ret = dissolve_free_huge_pages(start_pfn, end_pfn);
> > - if (ret)
> > - goto failed_removal;
> > + if (ret) {
> > + reason = "fails to disolve hugetlb pages";
>
> "memory offlining [mem ...] failed due to fails to disolve hugetlb pages"
>
>
> Fix:
>
> ---
> a/mm/memory_hotplug.c~mm-memory_hotplug-print-reason-for-the-offlining-failure-fix
> +++ a/mm/memory_hotplug.c
> @@ -1576,7 +1576,7 @@ static int __ref __offline_pages(unsigne
> MIGRATE_MOVABLE, true);
> if (ret) {
> mem_hotplug_done();
> - reason = "failed to isolate range";
> + reason = "failure to isolate range";
> goto failed_removal
> }
0day has noticed the missing ; here.
Andrew, could you pick up the follow up fix please?
commit 614212af5c20126aea1edaceb78aa586e19802cf
Author: Michal Hocko
Date: Tue Nov 13 09:01:50 2018 +0100
fold me "mm, memory_hotplug: print reason for the offlining failure"
diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
index f5f1b2a27cb3..c82193db4be6 100644
--- a/mm/memory_hotplug.c
+++ b/mm/memory_hotplug.c
@@ -1581,7 +1581,7 @@ static int __ref __offline_pages(unsigned long start_pfn,
if (ret) {
mem_hotplug_done();
reason = "failure to isolate range";
- goto failed_removal
+ goto failed_removal;
}
arg.start_pfn = start_pfn;
--
Michal Hocko
SUSE Labs
[PATCH v2] vmscan: return NODE_RECLAIM_NOSCAN in node_reclaim() when CONFIG_NUMA is n
Commit fa5e084e43eb ("vmscan: do not unconditionally treat zones that
fail zone_reclaim() as full") changed the return value of node_reclaim().
The original return value 0 means NODE_RECLAIM_SOME after this commit.
While the return value of node_reclaim() when CONFIG_NUMA is n is not
changed. This will leads to call zone_watermark_ok() again.
This patch fix the return value by adjusting to NODE_RECLAIM_NOSCAN. Since
node_reclaim() is only called in page_alloc.c, move it to mm/internal.h.
Signed-off-by: Wei Yang
---
v2: move node_reclaim() to mm/internal.h
---
include/linux/swap.h | 6 --
mm/internal.h| 10 ++
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/include/linux/swap.h b/include/linux/swap.h
index d8a07a4f171d..065988c27373 100644
--- a/include/linux/swap.h
+++ b/include/linux/swap.h
@@ -358,14 +358,8 @@ extern unsigned long vm_total_pages;
extern int node_reclaim_mode;
extern int sysctl_min_unmapped_ratio;
extern int sysctl_min_slab_ratio;
-extern int node_reclaim(struct pglist_data *, gfp_t, unsigned int);
#else
#define node_reclaim_mode 0
-static inline int node_reclaim(struct pglist_data *pgdat, gfp_t mask,
- unsigned int order)
-{
- return 0;
-}
#endif
extern int page_evictable(struct page *page);
diff --git a/mm/internal.h b/mm/internal.h
index 291eb2b6d1d8..6a57811ae47d 100644
--- a/mm/internal.h
+++ b/mm/internal.h
@@ -444,6 +444,16 @@ static inline void
mminit_validate_memmodel_limits(unsigned long *start_pfn,
#define NODE_RECLAIM_SOME 0
#define NODE_RECLAIM_SUCCESS 1
+#ifdef CONFIG_NUMA
+extern int node_reclaim(struct pglist_data *, gfp_t, unsigned int);
+#else
+static inline int node_reclaim(struct pglist_data *pgdat, gfp_t mask,
+ unsigned int order)
+{
+ return NODE_RECLAIM_NOSCAN;
+}
+#endif
+
extern int hwpoison_filter(struct page *p);
extern u32 hwpoison_filter_dev_major;
--
2.15.1
Re: [RFC PATCH 5/5] mm, memory_hotplug: be more verbose for memory offline failures
Andrew, could you pick up this one as well please? Let me know if you
prefer me to send the whole pile with all the fixes again.
> diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
> index bf214beccda3..820397e18e59 100644
> --- a/mm/memory_hotplug.c
> +++ b/mm/memory_hotplug.c
> @@ -1411,9 +1411,9 @@ do_migrate_range(unsigned long start_pfn, unsigned long
> end_pfn)
> MIGRATE_SYNC, MR_MEMORY_HOTPLUG);
> if (ret) {
> list_for_each_entry(page, &source, lru) {
> - pr_warn("migrating pfn %lx failed ",
> + pr_warn("migrating pfn %lx failed ret:%d ",
> page_to_pfn(page), ret);
> - dump_page(page, NULL);
> + dump_page(page, "migration failure");
> }
> putback_movable_pages(&source);
> }
> diff --git a/mm/page_alloc.c b/mm/page_alloc.c
> index 23267767bf98..ec2c7916dc2d 100644
> --- a/mm/page_alloc.c
> +++ b/mm/page_alloc.c
> @@ -7845,7 +7845,7 @@ bool has_unmovable_pages(struct zone *zone, struct page
> *page, int count,
> return false;
> unmovable:
> WARN_ON_ONCE(zone_idx(zone) == ZONE_MOVABLE);
> - dump_page(pfn_to_page(pfn+iter), "has_unmovable_pages");
> + dump_page(pfn_to_page(pfn+iter), "unmovable page");
> return true;
> }
>
> --
> Michal Hocko
> SUSE Labs
--
Michal Hocko
SUSE Labs
Re: [PATCH] mfd: at91-usart: Add platform dependency
On Mon, 12 Nov 2018, Jean Delvare wrote:
> It doesn't make sense to present option MFD_AT91_USART by default if
> not building an AT91 kernel, as the drivers which depend on it are
> not available.
>
> Signed-off-by: Jean Delvare
> Fixes: 7d3aa342cef7 ("mfd: at91-usart: Add MFD driver for USART")
> Cc: Radu Pirea
> Cc: Lee Jones
> ---
> As a side note, maybe it would make sense to have SPI_AT91_USART
> select MFD_AT91_USART instead of depend on it, so that
> MFD_AT91_USART could be hidden?
>
> drivers/mfd/Kconfig |1 +
> 1 file changed, 1 insertion(+)
Applied, thanks.
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
Re: [PATCH v3 0/4] Add support of STM32 hwspinlock
Hi Benjamin On 11/12/18 4:23 PM, Benjamin Gaignard wrote: This serie adds the support of the hardware semaphore block for stm32mp1 SoC. version 3: - fix clock name in properties description. - use postcore_initcall() instead of module_platform_driver() version 2: - fix comments done by Bjorn about clock naming, license terms in header, alphabetic ordering in Makefile and Kconfig and remove function - Do not push test module in this version while waiting for feedbacks about it Benjamin Gaignard (4): dt-bindings: hwlock: Document STM32 hwspinlock bindings hwspinlock: add STM32 hwspinlock device ARM: dts: stm32: Add hwspinlock node for stm32mp157 SoC ARM: dts: stm32: enable hwspinlock on stm32mp157c-ed1 DT patches applied on stm32-next. Regards Alex .../bindings/hwlock/st,stm32-hwspinlock.txt| 23 +++ arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 + arch/arm/boot/dts/stm32mp157c.dtsi | 9 ++ drivers/hwspinlock/Kconfig | 9 ++ drivers/hwspinlock/Makefile| 1 + drivers/hwspinlock/stm32_hwspinlock.c | 156 + 6 files changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt create mode 100644 drivers/hwspinlock/stm32_hwspinlock.c
RE: [PATCH V4] binder: ipc namespace support for android binder
> I have not received an answer to my questions in the last version of this > patch > set. Also it would be good if I could be Cc'ed by default. I can't hunt down > all > patches. > I do not know of any kernel entity, specifically devices, that change > namespaces > on open(). > This seems like an invitation for all kinds of security bugs. > A device node belongs to one namespace only which is attached to the > underlying kobject. Opening the device should never change that. > Please look at how mqueue or shm are doing this. They don't change > namespaces on open either. > I have to say that is one of the main reasons why I disagree with that design. > > If we must return the same context when every open in proc, we can only isolate binder with mnt namespace instead of ipc namespace, what do you think, Todd?
RE: [PATCH v4 01/10] spi: Add a driver for the Freescale/NXP QuadSPI controller
Hi, > -Original Message- > From: Frieder Schrempf [mailto:frieder.schre...@kontron.de] > Sent: Wednesday, November 7, 2018 8:13 PM > To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux- > s...@vger.kernel.org > Cc: dw...@infradead.org; computersforpe...@gmail.com; > marek.va...@gmail.com; rich...@nod.at; miquel.ray...@bootlin.com; > broo...@kernel.org; David Wolfe ; Fabio Estevam > ; Prabhakar Kushwaha > ; Yogesh Narayan Gaur > ; Han Xu ; > shawn...@kernel.org; Frieder Schrempf ; linux- > ker...@vger.kernel.org > Subject: [PATCH v4 01/10] spi: Add a driver for the Freescale/NXP QuadSPI > controller > > From: Frieder Schrempf > > This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. > It > uses the new SPI memory interface of the SPI framework to issue flash memory > operations to up to four connected flash chips (2 buses with 2 CS each). > > The controller does not support generic SPI messages. > > Signed-off-by: Frieder Schrempf > --- > drivers/spi/Kconfig| 11 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-fsl-qspi.c | 948 > 3 files changed, 960 insertions(+) > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c9..52e2298 > 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI > help > This enables Freescale i.MX LPSPI controllers in master mode. > > +config SPI_FSL_QSPI > + tristate "Freescale QSPI controller" > + depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || > COMPILE_TEST > + depends on HAS_IOMEM > + help > + This enables support for the Quad SPI controller in master mode. > + Up to four flash chips can be connected on two buses with two > + chipselects each. > + This controller does not support generic SPI messages. It only > + supports the high-level SPI memory interface. > + > config SPI_GPIO > tristate "GPIO-based bitbanging SPI Master" > depends on GPIOLIB || COMPILE_TEST > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > 3575205..833b9e7 > 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI) += spi-fsl- > dspi.o > obj-$(CONFIG_SPI_FSL_LIB)+= spi-fsl-lib.o > obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o > obj-$(CONFIG_SPI_FSL_LPSPI) += spi-fsl-lpspi.o > +obj-$(CONFIG_SPI_FSL_QSPI) += spi-fsl-qspi.o > obj-$(CONFIG_SPI_FSL_SPI)+= spi-fsl-spi.o > obj-$(CONFIG_SPI_GPIO) += spi-gpio.o > obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o > diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c new file > mode > 100644 index 000..a43cfe8 > --- /dev/null > +++ b/drivers/spi/spi-fsl-qspi.c > @@ -0,0 +1,948 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * Freescale QuadSPI driver. > + * > + * Copyright (C) 2013 Freescale Semiconductor, Inc. > + * Copyright (C) 2018 Bootlin > + * Copyright (C) 2018 exceet electronics GmbH > + * Copyright (C) 2018 Kontron Electronics GmbH > + * > + * Transition to SPI MEM interface: > + * Author: > + * Boris Brezillion > + * Frieder Schrempf > + * Yogesh Gaur > + * Suresh Gupta > + * > + * Based on the original fsl-quadspi.c spi-nor driver: > + * Author: Freescale Semiconductor, Inc. > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +/* > + * The driver only uses one single LUT entry, that is updated on > + * each call of exec_op(). Index 0 is preset at boot with a basic > + * read operation, so let's use the last entry (15). > + */ > +#define SEQID_LUT 15 > + > +/* Registers used by the driver */ > +#define QUADSPI_MCR 0x00 > +#define QUADSPI_MCR_RESERVED_MASKGENMASK(19, 16) > +#define QUADSPI_MCR_MDIS_MASKBIT(14) > +#define QUADSPI_MCR_CLR_TXF_MASK BIT(11) > +#define QUADSPI_MCR_CLR_RXF_MASK BIT(10) > +#define QUADSPI_MCR_DDR_EN_MASK BIT(7) > +#define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2) > +#define QUADSPI_MCR_SWRSTHD_MASK BIT(1) > +#define QUADSPI_MCR_SWRSTSD_MASK BIT(0) > + > +#define QUADSPI_IPCR 0x08 > +#define QUADSPI_IPCR_SEQID(x)((x) << 24) > + > +#define QUADSPI_BUF3CR 0x1c > +#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31) > +#define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8) > +#define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8) > + > +#define QUADSPI_BFGENCR 0x20 > +#define QUADSPI_BFGENCR_SEQID(x) ((x) << 12) > + > +#define QUADSPI_BUF0IND 0x30 > +#defin
Re: [RFC PATCH 06/13] m68k: Drop ARCH_USES_GETTIMEOFFSET
Hi Finn, Am 13.11.2018 um 19:15 schrieb Finn Thain: On Tue, 13 Nov 2018, Michael Schmitz wrote: (It appears that a QEMU-emulated Mac does not benefit from having a clocksource that's more accurate than the 'jiffies' clocksource, in spite of "clocksource: Switched to clocksource via1".) With the current code, kernel log timestamps have 10 ms resolution on Atari. Time resolution of times reported by initcall_debug is roughly 40 us. I'd expect that changes with falling back to jiffies only. Might be worth a try on QEMU Mac. The initcall debug output shows the same precision as my earlier tests with userland. The VIA timer only gets updated when QEMU wants to update it, which seems to be about every 9765 us. Hence, using the 'jiffies' clocksource would be effectively no regression for a virtual Mac. Running a recent kernel under ARAnyM shows 40 ns resolution so the Atari hardware emulation is a little more complete. Using that for initial tests, I can confirm that timer resolution is reduced to 10ms after patch 6, and gets restored to 40ns after applying the full series (once clocksource_init runs, that is - the first part of the boot is at 10ms resolution only, a regression compared to with use of arch_gettimeoffset). Unfortunately, I can't log in at the console with all patches applied. I immediately get the 'login timeout exceeded' message. Weird... Cheers, Michael
[PATCH 5/5] DO NOT MERGE: ARM: dts: bananapi: Add Camera support
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun7i-a20-bananapi.dts | 98 +-
1 file changed, 98 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
index 70dfc4ac0bb5..18dbff9f1ce9 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -54,6 +54,9 @@
compatible = "lemaker,bananapi", "allwinner,sun7i-a20";
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
serial0 = &uart0;
serial1 = &uart3;
serial2 = &uart7;
@@ -63,6 +66,41 @@
stdout-path = "serial0:115200n8";
};
+ reg_cam: cam {
+ compatible = "regulator-fixed";
+ regulator-name = "cam";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <®_vcc5v0>;
+ gpio = <&pio 7 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+reg_cam_avdd: cam-avdd {
+compatible = "regulator-fixed";
+regulator-name = "cam500b-avdd";
+regulator-min-microvolt = <280>;
+regulator-max-microvolt = <280>;
+vin-supply = <®_cam>;
+};
+
+reg_cam_dovdd: cam-dovdd {
+compatible = "regulator-fixed";
+regulator-name = "cam500b-dovdd";
+regulator-min-microvolt = <180>;
+regulator-max-microvolt = <180>;
+vin-supply = <®_cam>;
+};
+
+reg_cam_dvdd: cam-dvdd {
+compatible = "regulator-fixed";
+regulator-name = "cam500b-dvdd";
+regulator-min-microvolt = <150>;
+regulator-max-microvolt = <150>;
+vin-supply = <®_cam>;
+};
+
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
@@ -120,6 +158,27 @@
>;
};
+&csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi0_pins_a>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi_from_ov5640: endpoint {
+remote-endpoint = <&ov5640_to_csi>;
+bus-width = <8>;
+data-shift = <2>;
+hsync-active = <1>; /* Active high */
+vsync-active = <0>; /* Active low */
+data-active = <1>; /* Active high */
+pclk-sample = <1>; /* Rising */
+};
+ };
+};
+
&de {
status = "okay";
};
@@ -167,6 +226,39 @@
};
};
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ camera: camera@21 {
+ compatible = "ovti,ov5640";
+ reg = <0x21>;
+clocks = <&ccu CLK_CSI0>;
+clock-names = "xclk";
+ assigned-clocks = <&ccu CLK_CSI0>;
+ assigned-clock-rates = <2400>;
+
+reset-gpios = <&pio 7 14 GPIO_ACTIVE_LOW>;
+powerdown-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>;
+AVDD-supply = <®_cam_avdd>;
+DOVDD-supply = <®_cam_dovdd>;
+DVDD-supply = <®_cam_dvdd>;
+
+port {
+ov5640_to_csi: endpoint {
+remote-endpoint = <&csi_from_ov5640>;
+bus-width = <8>;
+data-shift = <2>;
+hsync-active = <1>; /* Active high */
+vsync-active = <0>; /* Active low */
+data-active = <1>; /* Active high */
+pclk-sample = <1>; /* Rising */
+};
+};
+ };
+};
+
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
@@ -252,6 +344,12 @@
"IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "",
"", "", "", "", "", "", "", "";
+ csi0_pins_a: csi_pins_a@0 {
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5",
+ "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
+ function = "csi0";
+ };
+
usb0_id_detect_pin: usb0_id_detect_pin@0 {
pins = "PH4";
function = "gpio_in";
--
git-series 0.9.1
[PATCH 4/5] ARM: dts: sun7i: Add CSI0 controller
The CSI controller embedded in the A20 can be supported by our new driver.
Let's add it to our DT.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun7i-a20.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 9c52712af241..50a9e30ee18c 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -364,6 +364,19 @@
num-cs = <1>;
};
+ csi0: csi@1c09000 {
+ compatible = "allwinner,sun7i-a20-csi",
+"allwinner,sun4i-a10-csi";
+ reg = <0x01c09000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
+<&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
+ clock-names = "ahb", "mod", "isp", "ram";
+ resets = <&ccu RST_CSI0>;
+ allwinner,csi-channels = <4>;
+ allwinner,has-isp;
+ };
+
emac: ethernet@1c0b000 {
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
--
git-series 0.9.1
Re: [PATCH] mfd: madera: Add shared data for accessory detection
On Mon, 12 Nov 2018, Richard Fitzgerald wrote: > Add variables to struct madera that will be shared by the > extcon and audio codec drivers to synchronize output state > during accessory detection. Also add a mutex to protect > the DAPM pointer. Why the odd 58 char line feeds? Not a blocker. Just looks strange. > Signed-off-by: Richard Fitzgerald > --- > drivers/mfd/madera-core.c | 3 +++ > include/linux/mfd/madera/core.h | 7 +++ > 2 files changed, 10 insertions(+) Applied, thanks. -- Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog
BUG: unable to handle kernel NULL pointer dereference in write_port
We report a bug in v4.19-rc8 (4.20-rc1 as well): kernel config: https://kt0755.github.io/etc/config-4.19-rc2.kmsan repro: https://kt0755.github.io/etc/repro.e3752.c This happens during data transition from user-supplied buffer to port (using outb) pointed by ppos. (driver/mem/char.c:640) Although there is a strict bound 65536 (driver/mem/char.c:632), user buffer copy still causes crashes within the strict bound. (In the experiment, the crash arose when loop count is beyond 0x7f ) To stop it, it probably needs a little tight bound check. I think this is a little bit related to the crash I reported before (https://lkml.org/lkml/2018/5/12/91) Crash log = BUG: unable to handle kernel NULL pointer dereference at 00af PGD 800092c1a067 P4D 800092c1a067 PUD 93a74067 PMD 0 Oops: 0002 [#1] SMP PTI CPU: 0 PID: 6651 Comm: syz-executor0 Not tainted 4.19.0-rc8+ #18 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Bochs 01/01/2011 RIP: 0010:outb arch/x86/include/asm/io.h:333 [inline] RIP: 0010:write_port+0x25b/0x420 drivers/char/mem.c:640 Code: 4c 8b 75 c8 4c 89 e7 e8 93 9f 5c fe 85 db 75 7d 48 8b 18 44 8b 22 e8 a4 de f8 fd 84 db 75 5a 48 8b 5d b0 85 db 75 5c 44 89 f0 <44> 89 66 90 49 83 c7 01 4d 89 ee 49 83 c6 01 31 c0 31 ff 45 31 e4 RSP: 0018:88009312fbf0 EFLAGS: 00010246 RAX: 21e4 RBX: RCX: 0001 RDX: c90003f89000 RSI: 011f RDI: 0120 RBP: 88009312fc98 R08: 7fff R09: 88009277fc60 R10: R11: 83772a30 R12: R13: 217f R14: 21e4 R15: 007f FS: 7f5c84a4d700() GS:88013fc0() knlGS: CS: 0010 DS: ES: CR0: 80050033 CR2: 00714fe4 CR3: 9498a000 CR4: 06f0 DR0: DR1: DR2: DR3: DR6: fffe0ff0 DR7: 0400 Call Trace: __vfs_write+0x1f4/0xa50 fs/read_write.c:485 vfs_write+0x495/0x8e0 fs/read_write.c:549 ksys_write fs/read_write.c:598 [inline] __do_sys_write fs/read_write.c:610 [inline] __se_sys_write+0x17a/0x370 fs/read_write.c:607 __x64_sys_write+0x4a/0x70 fs/read_write.c:607 do_syscall_64+0xb8/0x100 arch/x86/entry/common.c:291 entry_SYSCALL_64_after_hwframe+0x63/0xe7 RIP: 0033:0x4497b9 Code: e8 8c 9f 02 00 48 83 c4 18 c3 0f 1f 80 00 00 00 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 0f 83 9b 6b fc ff c3 66 2e 0f 1f 84 00 00 00 00 RSP: 002b:7f5c84a4cc68 EFLAGS: 0246 ORIG_RAX: 0001 RAX: ffda RBX: 7f5c84a4d6cc RCX: 004497b9 RDX: 00cc RSI: 2100 RDI: 0014 RBP: 0071bea0 R08: R09: R10: R11: 0246 R12: R13: b250 R14: 006f32f0 R15: 7f5c84a4d700 Modules linked in: Dumping ftrace buffer: (ftrace buffer empty) CR2: 00af ---[ end trace 5b28bfcf889ce399 ]--- = Crash log (reported before) = BUG: unable to handle kernel paging request at c90001eb5f90 PGD 1150c2067 P4D 1150c2067 PUD 1150c3067 PMD 10cd1e067 PTE 0 Oops: 0002 [#1] SMP KASAN PTI Dumping ftrace buffer: (ftrace buffer empty) Modules linked in: CPU: 0 PID: 2925 Comm: syz-executor7 Not tainted 4.17.0-rc3 #2 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Bochs 01/01/2011 RIP: 0010:outb arch/x86/include/asm/io.h:333 [inline] RIP: 0010:write_port+0xda/0x190 drivers/char/mem.c:640 RSP: 0018:88011095fc40 EFLAGS: 00010286 RAX: 1095feaf RBX: 2000163f RCX: 8286ca77 RDX: 0001 RSI: c90001eb6000 RDI: 880114403f58 RBP: 88011095fc78 R08: a9c6c9a0 R09: R10: 880115622813 R11: ed0022ac4503 R12: 007f R13: 000c R14: R15: 88011095feaf FS: 7f40dbe46700() GS:88011560() knlGS: CS: 0010 DS: ES: CR0: 80050033 CR2: c90001eb5f90 CR3: 0001117ca000 CR4: 06f0 DR0: DR1: DR2: DR3: DR6: fffe0ff0 DR7: 0400 Call Trace: __vfs_write+0x10d/0x610 fs/read_write.c:485 vfs_write+0x187/0x500 fs/read_write.c:549 ksys_write+0xd4/0x1a0 fs/read_write.c:598 __do_sys_write fs/read_write.c:610 [inline] __se_sys_write fs/read_write.c:607 [inline] __x64_sys_write+0x73/0xb0 fs/read_write.c:607 do_syscall_64+0xa4/0x460 arch/x86/entry/common.c:287 entry_SYSCALL_64_after_hwframe+0x49/0xbe RIP: 0033:0x4497b9 RSP: 002b:7f40dbe45c68 EFLAGS: 0246 ORIG_RAX: 0001 RAX: ffda RBX: 7f40dbe466cc RCX: 004497b9 RDX: 008c RSI: 200015c0 RD
Re: [PATCH v3 2/7] ARM: dts: at91: sama5d2: switch to new binding
clock is missing in the title of this patch. Regards Ludovic On Mon, Nov 12, 2018 at 02:31:03PM +0100, Alexandre Belloni wrote: > Switch sama5d2 boards to the new PMC clock bindings. > > Signed-off-by: Alexandre Belloni > --- > arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 12 +- > arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 2 +- > arch/arm/boot/dts/at91-sama5d2_xplained.dts | 4 +- > arch/arm/boot/dts/sama5d2.dtsi | 670 ++-- > 4 files changed, 69 insertions(+), 619 deletions(-) > > diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts > b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts > index 363a43d77424..4a258867ddf1 100644 > --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts > +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts > @@ -165,7 +165,7 @@ > dma-names = "tx", "rx"; > #address-cells = <1>; > #size-cells = <0>; > - clocks = <&flx1_clk>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_mikrobus_i2c>; > atmel,fifo-size = <16>; > @@ -211,7 +211,7 @@ > compatible = "atmel,at91sam9260-usart"; > reg = <0x200 0x200>; > interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; > - clocks = <&flx3_clk>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; > clock-names = "usart"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_flx3_default>; > @@ -223,7 +223,7 @@ > compatible = "atmel,at91rm9200-spi"; > reg = <0x400 0x200>; > interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; > - clocks = <&flx3_clk>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; > clock-names = "spi_clk"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_flx3_default>; > @@ -240,7 +240,7 @@ > compatible = "atmel,at91sam9260-usart"; > reg = <0x200 0x200>; > interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; > - clocks = <&flx4_clk>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; > clock-names = "usart"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_flx4_default>; > @@ -252,7 +252,7 @@ > compatible = "atmel,at91rm9200-spi"; > reg = <0x400 0x200>; > interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; > - clocks = <&flx4_clk>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; > clock-names = "spi_clk"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_mikrobus_spi > &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; > @@ -268,7 +268,7 @@ > dma-names = "tx", "rx"; > #address-cells = <1>; > #size-cells = <0>; > - clocks = <&flx4_clk>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_flx4_default>; > atmel,fifo-size = <16>; > diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts > b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts > index 2214bfe7aa20..ba7f3e646c26 100644 > --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts > +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts > @@ -197,7 +197,7 @@ > dma-names = "tx", "rx"; > #address-cells = <1>; > #size-cells = <0>; > - clocks = <&flx0_clk>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; > pinctrl-names = "default"; >
Re: [PATCH v4 3/6] mfd: lochnagar: Add initial binding documentation
On Thu, 08 Nov 2018, Charles Keepax wrote: > Lochnagar is an evaluation and development board for Cirrus > Logic Smart CODEC and Amp devices. It allows the connection of > most Cirrus Logic devices on mini-cards, as well as allowing > connection of various application processor systems to provide a > full evaluation platform. This driver supports the board > controller chip on the Lochnagar board. > > Signed-off-by: Charles Keepax > --- > > I have dropped Rob and Stephen's Acks from this patch on > account of the scale of the changes since v3. > > Changes since v3: > - Split the binding up into separate parts for the individual subsystems > - Added documentation for the fixed clocks that are done through DT > > Thanks, > Charles > > .../devicetree/bindings/clock/cirrus,lochnagar.txt | 89 + > .../devicetree/bindings/mfd/cirrus,lochnagar.txt | 70 ++ I think these should all be seperate patches. Code looks okay to me though. For my own reference: Acked-for-MFD-by: Lee Jones -- Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog
RE: [PATCH v4 01/10] spi: Add a driver for the Freescale/NXP QuadSPI controller
Hi, > -Original Message- > From: Yogesh Narayan Gaur > Sent: Tuesday, November 13, 2018 1:53 PM > To: 'Frieder Schrempf' ; linux- > m...@lists.infradead.org; boris.brezil...@bootlin.com; linux- > s...@vger.kernel.org > Cc: dw...@infradead.org; computersforpe...@gmail.com; > marek.va...@gmail.com; rich...@nod.at; miquel.ray...@bootlin.com; > broo...@kernel.org; David Wolfe ; Fabio Estevam > ; Prabhakar Kushwaha > ; Han Xu ; > shawn...@kernel.org; Frieder Schrempf ; linux- > ker...@vger.kernel.org > Subject: RE: [PATCH v4 01/10] spi: Add a driver for the Freescale/NXP QuadSPI > controller > > Hi, > > > -Original Message- > > From: Frieder Schrempf [mailto:frieder.schre...@kontron.de] > > Sent: Wednesday, November 7, 2018 8:13 PM > > To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux- > > s...@vger.kernel.org > > Cc: dw...@infradead.org; computersforpe...@gmail.com; > > marek.va...@gmail.com; rich...@nod.at; miquel.ray...@bootlin.com; > > broo...@kernel.org; David Wolfe ; Fabio Estevam > > ; Prabhakar Kushwaha > > ; Yogesh Narayan Gaur > > ; Han Xu ; > > shawn...@kernel.org; Frieder Schrempf ; > > linux- ker...@vger.kernel.org > > Subject: [PATCH v4 01/10] spi: Add a driver for the Freescale/NXP > > QuadSPI controller > > > > From: Frieder Schrempf > > > > This driver is derived from the SPI NOR driver at > > mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface of the > > SPI framework to issue flash memory operations to up to four connected flash > chips (2 buses with 2 CS each). > > > > The controller does not support generic SPI messages. > > > > Signed-off-by: Frieder Schrempf > > --- > > drivers/spi/Kconfig| 11 + > > drivers/spi/Makefile | 1 + > > drivers/spi/spi-fsl-qspi.c | 948 > > > > 3 files changed, 960 insertions(+) > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index > > 7d3a5c9..52e2298 > > 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI > > help > > This enables Freescale i.MX LPSPI controllers in master mode. > > > > +config SPI_FSL_QSPI > > + tristate "Freescale QSPI controller" > > + depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || > > COMPILE_TEST > > + depends on HAS_IOMEM > > + help > > + This enables support for the Quad SPI controller in master mode. > > + Up to four flash chips can be connected on two buses with two > > + chipselects each. > > + This controller does not support generic SPI messages. It only > > + supports the high-level SPI memory interface. > > + > > config SPI_GPIO > > tristate "GPIO-based bitbanging SPI Master" > > depends on GPIOLIB || COMPILE_TEST > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > > 3575205..833b9e7 > > 100644 > > --- a/drivers/spi/Makefile > > +++ b/drivers/spi/Makefile > > @@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI)+= spi-fsl- > > dspi.o > > obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o > > obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o > > obj-$(CONFIG_SPI_FSL_LPSPI)+= spi-fsl-lpspi.o > > +obj-$(CONFIG_SPI_FSL_QSPI) += spi-fsl-qspi.o > > obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o > > obj-$(CONFIG_SPI_GPIO) += spi-gpio.o > > obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o > > diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c > > new file mode > > 100644 index 000..a43cfe8 > > --- /dev/null > > +++ b/drivers/spi/spi-fsl-qspi.c > > @@ -0,0 +1,948 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > + > > +/* > > + * Freescale QuadSPI driver. > > + * > > + * Copyright (C) 2013 Freescale Semiconductor, Inc. > > + * Copyright (C) 2018 Bootlin > > + * Copyright (C) 2018 exceet electronics GmbH > > + * Copyright (C) 2018 Kontron Electronics GmbH > > + * > > + * Transition to SPI MEM interface: > > + * Author: > > + * Boris Brezillion > > + * Frieder Schrempf > > + * Yogesh Gaur > > + * Suresh Gupta > > + * > > + * Based on the original fsl-quadspi.c spi-nor driver: > > + * Author: Freescale Semiconductor, Inc. > > + * > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > +#include > > + > > +/* > > + * The driver only uses one single LUT entry, that is updated on > > + * each call of exec_op(). Index 0 is preset at boot with a basic > > + * read operation, so let's use the last entry (15). > > + */ > > +#defineSEQID_LUT 15 > > + > > +/* Registers used by the driver */ > > +#define QUADSPI_MCR0x00 > > +#define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16) > > +#def
Re: [PATCH v4 4/6] mfd: lochnagar: Add support for the Cirrus Logic Lochnagar
On Thu, 08 Nov 2018, Charles Keepax wrote: > Lochnagar is an evaluation and development board for Cirrus > Logic Smart CODEC and Amp devices. It allows the connection of > most Cirrus Logic devices on mini-cards, as well as allowing > connection of various application processor systems to provide a > full evaluation platform. This driver supports the board > controller chip on the Lochnagar board. Audio system topology, > clocking and power can all be controlled through the Lochnagar > controller chip, allowing the device under test to be used in > a variety of possible use cases. > > As the Lochnagar is a fairly complex device this MFD driver > allows the drivers for the various features to be bound > in. Initially clocking, regulator and pinctrl will be added as > these are necessary to configure the system. But in time at least > audio and voltage/current monitoring will also be added. > > Signed-off-by: Charles Keepax > --- > > Changes since v3: > - Bind in child drivers through device tree rather than using mfd_add_devices > - Remove defaults arrays for regmap > - Use a lot of ... in the regmap readable/volatile callbacks > - Explicitly include register headers, rather than relying on lochnagar.h > - Add some kernel doc > - Some minor cosmetic fixups > - Add a lockdep_assert in lochnagar_update_config > > Thanks, > Charles > > MAINTAINERS | 17 ++ > drivers/mfd/Kconfig | 8 + > drivers/mfd/Makefile| 2 + > drivers/mfd/lochnagar-i2c.c | 394 > > include/linux/mfd/lochnagar.h | 55 + > include/linux/mfd/lochnagar1_regs.h | 157 ++ > include/linux/mfd/lochnagar2_regs.h | 253 +++ > 7 files changed, 886 insertions(+) > create mode 100644 drivers/mfd/lochnagar-i2c.c > create mode 100644 include/linux/mfd/lochnagar.h > create mode 100644 include/linux/mfd/lochnagar1_regs.h > create mode 100644 include/linux/mfd/lochnagar2_regs.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index f4855974f3250..0398c8752e610 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -3567,6 +3567,23 @@ L: net...@vger.kernel.org > S: Maintained > F: drivers/net/ethernet/cirrus/ep93xx_eth.c > > +CIRRUS LOGIC LOCHNAGAR DRIVER > +M: Charles Keepax > +M: Richard Fitzgerald > +L: patc...@opensource.cirrus.com > +S: Supported > +F: drivers/clk/clk-lochnagar.c > +F: drivers/mfd/lochnagar-i2c.c > +F: drivers/pinctrl/cirrus/pinctrl-lochnagar* > +F: drivers/regulator/lochnagar-regulator.c > +F: include/dt-bindings/clk/lochnagar.h > +F: include/dt-bindings/pinctrl/lochnagar.h > +F: include/linux/mfd/lochnagar* > +F: Documentation/devicetree/bindings/mfd/cirrus,lochnagar.txt > +F: Documentation/devicetree/bindings/clock/cirrus,lochnagar.txt > +F: Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.txt > +F: Documentation/devicetree/bindings/regulator/cirrus,lochnagar.txt > + > CISCO FCOE HBA DRIVER > M: Satish Kharat > M: Sesidhar Baddela > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig > index 8c5dfdce4326c..51de2db3f6537 100644 > --- a/drivers/mfd/Kconfig > +++ b/drivers/mfd/Kconfig > @@ -1685,6 +1685,14 @@ config MFD_VX855 > VIA VX855/VX875 south bridge. You will need to enable the vx855_spi > and/or vx855_gpio drivers for this to do anything useful. > > +config MFD_LOCHNAGAR > + bool "Cirrus Logic Lochnagar Audio Development Board" > + select MFD_CORE > + select REGMAP_I2C > + depends on I2C=y && OF > + help > + Support for Cirrus Logic Lochnagar audio development board. > + > config MFD_ARIZONA > select REGMAP > select REGMAP_IRQ > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > index 12980a4ad4608..93284316d5307 100644 > --- a/drivers/mfd/Makefile > +++ b/drivers/mfd/Makefile > @@ -37,6 +37,8 @@ obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o tmio_core.o > obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o tmio_core.o > obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o tmio_core.o > > +obj-$(CONFIG_MFD_LOCHNAGAR) += lochnagar-i2c.o > + > obj-$(CONFIG_MFD_ARIZONA)+= arizona-core.o > obj-$(CONFIG_MFD_ARIZONA)+= arizona-irq.o > obj-$(CONFIG_MFD_ARIZONA_I2C)+= arizona-i2c.o > diff --git a/drivers/mfd/lochnagar-i2c.c b/drivers/mfd/lochnagar-i2c.c > new file mode 100644 > index 0..133159d7646ed > --- /dev/null > +++ b/drivers/mfd/lochnagar-i2c.c > @@ -0,0 +1,394 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Lochnagar I2C bus interface > + * > + * Copyright (c) 2012-2018 Cirrus Logic, Inc. and > + * Cirrus Logic International Semiconductor Ltd. > + * > + * Author: Charles Keepax > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#define LOCHNAGAR_BO
Re: [PATCH AUTOSEL 3.18 1/9] bfs: add sanity check at bfs_fill_super()
On Tue, 13 Nov 2018 at 05:52, Sasha Levin wrote:
> syzbot is reporting too large memory allocation at bfs_fill_super() [1].
> Since file system image is corrupted such that bfs_sb->s_start == 0,
> bfs_fill_super() is trying to allocate 8MB of continuous memory. Fix
> this by adding a sanity check on bfs_sb->s_start, __GFP_NOWARN and
> printf().
>
> [1]
> https://syzkaller.appspot.com/bug?id=16a87c236b951351374a84c8a32f40edbc034e96
Hi Sasha,
Thank you, but no, I am rejecting this patch as I have already
submitted a much more robust and accurate (stronger check) patch to
Andrew Morton a couple of days ago against 4.20-rc1.
Andrew, if you would like me to make the same patch against 4.19.1 as
well, please let me know.
Kind regards,
Tigran
>
> Link:
> http://lkml.kernel.org/r/1525862104-3407-1-git-send-email-penguin-ker...@i-love.sakura.ne.jp
> Signed-off-by: Tetsuo Handa
> Reported-by: syzbot
> Reviewed-by: Andrew Morton
> Cc: Tigran Aivazian
> Cc: Matthew Wilcox
> Signed-off-by: Andrew Morton
> Signed-off-by: Linus Torvalds
> Signed-off-by: Sasha Levin
> ---
> fs/bfs/inode.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/fs/bfs/inode.c b/fs/bfs/inode.c
> index 90bc079d9982..0ee38b284ad7 100644
> --- a/fs/bfs/inode.c
> +++ b/fs/bfs/inode.c
> @@ -349,7 +349,8 @@ static int bfs_fill_super(struct super_block *s, void
> *data, int silent)
>
> s->s_magic = BFS_MAGIC;
>
> - if (le32_to_cpu(bfs_sb->s_start) > le32_to_cpu(bfs_sb->s_end)) {
> + if (le32_to_cpu(bfs_sb->s_start) > le32_to_cpu(bfs_sb->s_end) ||
> + le32_to_cpu(bfs_sb->s_start) < BFS_BSIZE) {
> printf("Superblock is corrupted\n");
> goto out1;
> }
> @@ -358,9 +359,11 @@ static int bfs_fill_super(struct super_block *s, void
> *data, int silent)
> sizeof(struct bfs_inode)
> + BFS_ROOT_INO - 1;
> imap_len = (info->si_lasti / 8) + 1;
> - info->si_imap = kzalloc(imap_len, GFP_KERNEL);
> - if (!info->si_imap)
> + info->si_imap = kzalloc(imap_len, GFP_KERNEL | __GFP_NOWARN);
> + if (!info->si_imap) {
> + printf("Cannot allocate %u bytes\n", imap_len);
> goto out1;
> + }
> for (i = 0; i < BFS_ROOT_INO; i++)
> set_bit(i, info->si_imap);
>
> --
> 2.17.1
>
Re: [PATCH] scripts/setlocalversion: Improve -dirty check with git-status --no-optional-locks
On Tue, Nov 13, 2018 at 2:09 AM Brian Norris wrote:
>
> On Mon, Nov 12, 2018 at 10:42:26AM +0200, Alexander Kapshuk wrote:
> > An even simpler approach would be:
> >
> > {
> > git --no-optional-locks status -uno --porcelain 2>/dev/null ||
> > git diff-index --name-only HEAD
> > } | grep -qv scripts/package &&
> > printf '%s' -dirty
> >
> > Sample run:
> > cmd
> > sh: cmd: command not found
> >
> > {
> > cmd 2>/dev/null ||
> > date
> > } | grep -q 2018 &&
> > printf '%s' ok
> > ok
>
> You lose accuracy here, because now you're skipping any line that
> contains 'scripts/package', which would include, e.g., paths like
>
> tools/some/other-scripts/package
>
> Maybe if the grep expression were more like this?
>
> grep -qv '^\(.. \)\?scripts/package'
>
> I think it'd be safe enough to ignore paths that start with two
> characters and a space, like:
>
> xy scripts/package
> x/ scripts/package
>
> Brian
Thanks for your input.
I've found the following grep command, that uses extended regular
expressions, to work as required:
{
echo hello
echo scripts/package
echo '.. scripts/package'
echo tools/some/other-scripts/package
} | grep -Ev '^(.. )?scripts/package'
[Output]
hello
tools/some/other-scripts/package
If the participants of this email exchange consider the proposed
implementation as fitting the bill,
{
git --no-optional-locks status -uno --porcelain 2>/dev/null ||
git diff-index --name-only HEAD
} | grep -Eqv '^(.. )?scripts/package' &&
printf '%s' -dirty
Was the original committer of the patch proposed here,
https://lkml.org/lkml/2018/11/10/55, going to take it in, and resend it
as v2 of the patch, or did you want me to submit the patch instead?
I would be happy with either way.
Thanks.
Re: [PATCH 4.14 000/222] 4.14.81-stable review
On 11/11/2018 22:21, Greg Kroah-Hartman wrote: > This is the start of the stable review cycle for the 4.14.81 release. > There are 222 patches in this series, all will be posted as a response > to this one. If anyone has any issues with these being applied, please > let me know. > > Responses should be made by Tue Nov 13 22:15:32 UTC 2018. > Anything received after that time might be too late. All tests are passing for Tegra ... Test results for stable-v4.14: 8 builds: 8 pass, 0 fail 16 boots: 16 pass, 0 fail 14 tests: 14 pass, 0 fail Linux version: 4.14.81-rc1-g8ea9437 Boards tested: tegra124-jetson-tk1, tegra20-ventana, tegra210-p2371-2180, tegra30-cardhu-a04 Cheers Jon -- nvpublic
[PATCH] vfio/mdev: add static modifier to add_mdev_supported_type
Set add_mdev_supported_type as static since it is only used within
mdev_sysfs.c.
This fixes -Wmissing-prototypes gcc warning.
Signed-off-by: Paolo Cretaro
---
drivers/vfio/mdev/mdev_sysfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/vfio/mdev/mdev_sysfs.c b/drivers/vfio/mdev/mdev_sysfs.c
index 249472f05509..ce5dd219f2c8 100644
--- a/drivers/vfio/mdev/mdev_sysfs.c
+++ b/drivers/vfio/mdev/mdev_sysfs.c
@@ -92,8 +92,8 @@ static struct kobj_type mdev_type_ktype = {
.release = mdev_type_release,
};
-struct mdev_type *add_mdev_supported_type(struct mdev_parent *parent,
- struct attribute_group *group)
+static struct mdev_type *add_mdev_supported_type(struct mdev_parent *parent,
+struct attribute_group *group)
{
struct mdev_type *type;
int ret;
--
2.19.1
[PATCH RESEND] UAPI: move RENAME_* definitions to separated file
Discussion:
https://lore.kernel.org/lkml/20180702084622.GA15274@yury-thinkpad/
Although RENAME_* macros are exposed in kernel headers, they are not
used by glibc. That's because linux/fs.h which hosts RENAME_* is
considered unsuitable by glibc developers:
As Florian Weimer wrote:
> undefines and defines macros not mentioned in the standards
> (and it even contains a few unrelated structs), so we cannot include it
> without _GNU_SOURCE.
>
> It might be possible to include it only for _GNU_SOURCE, but there are a
> lot of things in , so that does not seem to be particularly
> advisable.
In this patch RENAME_* is removed to separated header file that
conforms standards and therefore is suitable for inclusion by glibc.
Signed-off-by: Yury Norov
---
include/uapi/linux/fs.h | 4 +---
include/uapi/linux/rename.h | 12
2 files changed, 13 insertions(+), 3 deletions(-)
create mode 100644 include/uapi/linux/rename.h
diff --git a/include/uapi/linux/fs.h b/include/uapi/linux/fs.h
index 53a22e8e0408..dbf58bbf5bad 100644
--- a/include/uapi/linux/fs.h
+++ b/include/uapi/linux/fs.h
@@ -44,9 +44,7 @@
#define SEEK_HOLE 4 /* seek to the next hole */
#define SEEK_MAX SEEK_HOLE
-#define RENAME_NOREPLACE (1 << 0)/* Don't overwrite target */
-#define RENAME_EXCHANGE(1 << 1)/* Exchange source and
dest */
-#define RENAME_WHITEOUT(1 << 2)/* Whiteout source */
+#include
struct file_clone_range {
__s64 src_fd;
diff --git a/include/uapi/linux/rename.h b/include/uapi/linux/rename.h
new file mode 100644
index ..7178f0565657
--- /dev/null
+++ b/include/uapi/linux/rename.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _UAPI_LINUX_RENAME_H
+#define _UAPI_LINUX_RENAME_H
+
+/*
+ * Definitions for rename syscall family.
+ */
+#define RENAME_NOREPLACE (1 << 0)/* Don't overwrite target */
+#define RENAME_EXCHANGE(1 << 1)/* Exchange source and
dest */
+#define RENAME_WHITEOUT(1 << 2)/* Whiteout source */
+
+#endif /* _UAPI_LINUX_RENAME_H */
--
2.17.1
[RESEND PATCH] mfd: tps6586x: Handle interrupts on suspend
From: Jonathan Hunter
The tps6586x driver creates an irqchip that is used by its various child
devices for managing interrupts. The tps6586x-rtc device is one of its
children that uses the tps6586x irqchip. When using the tps6586x-rtc as
a wake-up device from suspend, the following is seen:
PM: Syncing filesystems ... done.
Freezing user space processes ... (elapsed 0.001 seconds) done.
OOM killer disabled.
Freezing remaining freezable tasks ... (elapsed 0.000 seconds) done.
Disabling non-boot CPUs ...
Entering suspend state LP1
Enabling non-boot CPUs ...
CPU1 is up
tps6586x 3-0034: failed to read interrupt status
tps6586x 3-0034: failed to read interrupt status
The reason why the tps6586x interrupt status cannot be read is because
the tps6586x interrupt is not masked during suspend and when the
tps6586x-rtc interrupt occurs, to wake-up the device, the interrupt is
seen before the i2c controller has been resumed in order to read the
tps6586x interrupt status.
The tps6586x-rtc driver sets it's interrupt as a wake-up source during
suspend, which gets propagated to the parent tps6586x interrupt.
However, the tps6586x-rtc driver cannot disable it's interrupt during
suspend otherwise we would never be woken up and so the tps6586x must
disable it's interrupt instead.
Prevent the tps6586x interrupt handler from executing on exiting suspend
before the i2c controller has been resumed by disabling the tps6586x
interrupt on entering suspend and re-enabling it on resuming from
suspend.
Cc: sta...@vger.kernel.org
Signed-off-by: Jon Hunter
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
drivers/mfd/tps6586x.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index b89379782741..9c7925ca13cf 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -592,6 +592,29 @@ static int tps6586x_i2c_remove(struct i2c_client *client)
return 0;
}
+static int __maybe_unused tps6586x_i2c_suspend(struct device *dev)
+{
+ struct tps6586x *tps6586x = dev_get_drvdata(dev);
+
+ if (tps6586x->client->irq)
+ disable_irq(tps6586x->client->irq);
+
+ return 0;
+}
+
+static int __maybe_unused tps6586x_i2c_resume(struct device *dev)
+{
+ struct tps6586x *tps6586x = dev_get_drvdata(dev);
+
+ if (tps6586x->client->irq)
+ enable_irq(tps6586x->client->irq);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(tps6586x_pm_ops, tps6586x_i2c_suspend,
+tps6586x_i2c_resume);
+
static const struct i2c_device_id tps6586x_id_table[] = {
{ "tps6586x", 0 },
{ },
@@ -602,6 +625,7 @@ static struct i2c_driver tps6586x_driver = {
.driver = {
.name = "tps6586x",
.of_match_table = of_match_ptr(tps6586x_of_match),
+ .pm = &tps6586x_pm_ops,
},
.probe = tps6586x_i2c_probe,
.remove = tps6586x_i2c_remove,
--
2.7.4
Re: [PATCH] arm64: dts: allwinner: a64: Add mali node
Hi Jernej,
On Sun, Nov 11, 2018 at 01:18:11PM +0100, Jernej Skrabec wrote:
> A64 has Mali400 MP2 GPU. Add a node for it.
>
> Signed-off-by: Jernej Skrabec
> ---
> This node and A64 GPU binary driver was tested with Kodi on LibreELEC.
>
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 22 +++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index f3a66f888205..48cc5451d0eb 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -753,6 +753,28 @@
> #size-cells = <0>;
> };
>
> + mali: gpu@1c4 {
> + compatible = "allwinner,sun50i-a64-mali",
> + "arm,mali-400";
You should document that new compatible string. The patch looks good
otherwise, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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Re: [PATCH v3 2/7] ARM: dts: at91: sama5d2: switch to new binding
On 13/11/2018 09:27:09+0100, Ludovic Desroches wrote: > clock is missing in the title of this patch. > I fixed it up in place and pushed the at91-dt branch. Thanks! > Regards > > Ludovic > > On Mon, Nov 12, 2018 at 02:31:03PM +0100, Alexandre Belloni wrote: > > Switch sama5d2 boards to the new PMC clock bindings. > > > > Signed-off-by: Alexandre Belloni > > --- > > arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 12 +- > > arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 2 +- > > arch/arm/boot/dts/at91-sama5d2_xplained.dts | 4 +- > > arch/arm/boot/dts/sama5d2.dtsi | 670 ++-- > > 4 files changed, 69 insertions(+), 619 deletions(-) > > > > diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts > > b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts > > index 363a43d77424..4a258867ddf1 100644 > > --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts > > +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts > > @@ -165,7 +165,7 @@ > > dma-names = "tx", "rx"; > > #address-cells = <1>; > > #size-cells = <0>; > > - clocks = <&flx1_clk>; > > + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; > > pinctrl-names = "default"; > > pinctrl-0 = <&pinctrl_mikrobus_i2c>; > > atmel,fifo-size = <16>; > > @@ -211,7 +211,7 @@ > > compatible = "atmel,at91sam9260-usart"; > > reg = <0x200 0x200>; > > interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; > > - clocks = <&flx3_clk>; > > + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; > > clock-names = "usart"; > > pinctrl-names = "default"; > > pinctrl-0 = <&pinctrl_flx3_default>; > > @@ -223,7 +223,7 @@ > > compatible = "atmel,at91rm9200-spi"; > > reg = <0x400 0x200>; > > interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; > > - clocks = <&flx3_clk>; > > + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; > > clock-names = "spi_clk"; > > pinctrl-names = "default"; > > pinctrl-0 = <&pinctrl_flx3_default>; > > @@ -240,7 +240,7 @@ > > compatible = "atmel,at91sam9260-usart"; > > reg = <0x200 0x200>; > > interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; > > - clocks = <&flx4_clk>; > > + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; > > clock-names = "usart"; > > pinctrl-names = "default"; > > pinctrl-0 = <&pinctrl_flx4_default>; > > @@ -252,7 +252,7 @@ > > compatible = "atmel,at91rm9200-spi"; > > reg = <0x400 0x200>; > > interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; > > - clocks = <&flx4_clk>; > > + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; > > clock-names = "spi_clk"; > > pinctrl-names = "default"; > > pinctrl-0 = <&pinctrl_mikrobus_spi > > &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; > > @@ -268,7 +268,7 @@ > > dma-names = "tx", "rx"; > > #address-cells = <1>; > > #size-cells = <0>; > > - clocks = <&flx4_clk>; > > + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; > > pinctrl-names = "default"; > > pinctrl-0 = <&pinctrl_flx4_default>; > > atmel,fifo-size = <16>; > > diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts > > b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts > > index 2214bfe7aa20..ba7f3e646c26 100644 > > --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts > > +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts > > @@ -197,7 +197,7 @@ > > dma-names = "tx", "rx"; > > #address-cells = <1>; > > #size-cells = <0>; > > -
Re: [PATCH 4/4] nvmem: meson-efuse: add peripheral clock
On 30/10/18 10:22, Jerome Brunet wrote: Get and enable the peripheral clock required by the efuse device. The driver has been handle to work without it so far because the clock was left enabled by default but it won't be the case soon. Signed-off-by: Jerome Brunet --- drivers/nvmem/meson-efuse.c | 25 + 1 file changed, 25 insertions(+) Applied, thanks, -- Srini
Re: [PATCH 2/4] nvmem: meson-efuse: bindings: add peripheral clock
On 30/10/18 10:22, Jerome Brunet wrote: The efuse found in gx SoC requires a peripheral clock to properly operate. We have been able to work without it until now because the clock was on by default, and left on by the CCF. Soon, it will not be the case anymore, so the device needs to claim the clock it needs Signed-off-by: Jerome Brunet --- Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt | 3 +++ 1 file changed, 3 insertions(+) Applied, thanks, -- Srini
Re: [PATCH] ARM: stm32: debug: add low-level debug support
On 11/12/18 7:22 PM, Olof Johansson wrote: > On Thu, Jul 27, 2017 at 04:50:20PM +, Bich HEMON wrote: >> From: Gerald Baeza >> >> This adds low-level debug support on USART1 for STM32F4 >> and STM32F7. >> Compiled via 'CONFIG_DEBUG_LL' and 'CONFIG_EARLY_PRINTK'. >> Enabled via 'earlyprintk' in bootargs. >> >> Signed-off-by: Gerald Baeza >> Signed-off-by: Bich Hemon > > Hi, > > This had fallen between the chairs it seems. I have applied it to arm-soc > next/soc now, for 4.21 merge window. > > It ended up being patched up manually to consolidate the version in > Russell's patch tracker with this posted version, and I tweaked whitespace > a bit. Let me know if I missed something. > > > Thanks, > > -Olof > Hi Olof, Please note that this patch has to be abandoned as Ludovic BARRE pushed a new version of this change: https://patchwork.codeaurora.org/patch/400563/ You can find it in Russell's tracker here: http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8803/1 Best regards, Bich
Re: [RFC PATCH 01/13] arm: Fix mutual exclusion in arch_gettimeoffset
On Tue, Nov 13, 2018 at 02:39:00PM +1100, Finn Thain wrote:
> On Mon, 12 Nov 2018, Christoph Hellwig wrote:
>
> > On Mon, Nov 12, 2018 at 03:12:39PM +1100, Finn Thain wrote:
> > > Implementations of arch_gettimeoffset are generally not re-entrant and
> > > assume that interrupts have been disabled. Unfortunately this
> > > pre-condition got broken in v2.6.32.
> > >
> > > Fixes: 5cfc8ee0bb51 ("ARM: convert arm to arch_gettimeoffset()")
> > > Signed-off-by: Finn Thain
> >
> > This looks like a sensible fix for -stable backporting. But with m68k
> > converted over it might be time for these two arm platforms to either
> > be converted to the clocksource API or to be dropped..
> >
>
> You could remove the old arch_gettimeoffset API without dropping any
> platforms.
>
> If no-one converts a given platform to the clocksource API it would mean
> that the default 'jiffies' clocksource will get used on that platform.
>
> Clock resolution and timer precision would be degraded, but that might not
> matter.
>
> Anyway, if someone who has this hardware is willing to test a clocksource
> API conversion, they can let me know and I'll attempt that patch.
There's reasons why that's not appropriate - such as not having two
separate timers in order to supply a clocksource and separate clock
event.
Not all hardware is suited to the clocksource + clockevent idea.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
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[PATCH 2/2] arm64: dts: qcom: Add pinctrls for camera sensors
Add pinctrls required for camera sensors:
- power down signal;
- reset signal;
- camera external clock.
Signed-off-by: Todor Tomov
---
arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 64
arch/arm64/boot/dts/qcom/msm8996-pins.dtsi | 96 ++
2 files changed, 160 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 990120c..aa9a0ff 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -701,4 +701,68 @@
bias-disable;
};
};
+
+ camera_front_default: camera_front_default {
+ pinmux_pwdn {
+ function = "gpio";
+ pins = "gpio33";
+ };
+ pinconf_pwdn {
+ pins = "gpio33";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pinmux_rst {
+ function = "gpio";
+ pins = "gpio28";
+ };
+ pinconf_rst {
+ pins = "gpio28";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pinmux_mclk1 {
+ function = "cam_mclk1";
+ pins = "gpio27";
+ };
+ pinconf_mclk1 {
+ pins = "gpio27";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera_rear_default: camera_rear_default {
+ pinmux_pwdn {
+ function = "gpio";
+ pins = "gpio34";
+ };
+ pinconf_pwdn {
+ pins = "gpio34";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+pinmux_rst {
+ function = "gpio";
+ pins = "gpio35";
+ };
+ pinconf_rst {
+ pins = "gpio35";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pinmux_mclk0 {
+ function = "cam_mclk0";
+ pins = "gpio26";
+ };
+ pinconf_mclk0 {
+ pins = "gpio26";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
index d6a0a4a..8d5114d 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
@@ -519,4 +519,100 @@
bias-disable;
};
};
+
+ camera_board_default: camera_board_default {
+ mux_pwdn {
+ function = "gpio";
+ pins = "gpio98";
+ };
+ config_pwdn {
+ pins = "gpio98";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mux_rst {
+ function = "gpio";
+ pins = "gpio104";
+ };
+ config_rst {
+ pins = "gpio104";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mux_mclk1 {
+ function = "cam_mclk";
+ pins = "gpio14";
+ };
+ config_mclk1 {
+ pins = "gpio14";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera_front_default: camera_front_default {
+ mux_pwdn {
+ function = "gpio";
+ pins = "gpio133";
+ };
+ config_pwdn {
+ pins = "gpio133";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mux_rst {
+ function = "gpio";
+ pins = "gpio23";
+ };
+ config_rst {
+ pins = "gpio23";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mux_mclk2 {
+ function = "cam_mclk";
+ pins = "gpio15";
+ };
+ config_mclk2 {
+ pins = "gpio15";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera_rear_default: camera_rear_defa
[PATCH 1/2] arm64: dts: qcom: Add Camera Control Interface pinctrls
Add pinctrls required for Camera Control Interface.
Signed-off-by: Todor Tomov
---
arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 12
arch/arm64/boot/dts/qcom/msm8996-pins.dtsi | 24
2 files changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 390a2fa..990120c 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -689,4 +689,16 @@
bias-pull-up;
};
};
+
+ cci0_default: cci0_default {
+ pinmux {
+ function = "cci_i2c";
+ pins = "gpio29", "gpio30";
+ };
+ pinconf {
+ pins = "gpio29", "gpio30";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
index c5c42e9..d6a0a4a 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
@@ -495,4 +495,28 @@
bias-disable;
};
};
+
+ cci0_default: cci0_default {
+ pinmux {
+ function = "cci_i2c";
+ pins = "gpio17", "gpio18";
+ };
+ pinconf {
+ pins = "gpio17", "gpio18";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ cci1_default: cci1_default {
+ pinmux {
+ function = "cci_i2c";
+ pins = "gpio19", "gpio20";
+ };
+ pinconf {
+ pins = "gpio19", "gpio20";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
};
--
2.7.4
Re: [PATCH] ARM: stm32: debug: add low-level debug support
On Tue, Nov 13, 2018 at 09:16:16AM +, Bich HEMON wrote: > > On 11/12/18 7:22 PM, Olof Johansson wrote: > > On Thu, Jul 27, 2017 at 04:50:20PM +, Bich HEMON wrote: > >> From: Gerald Baeza > >> > >> This adds low-level debug support on USART1 for STM32F4 > >> and STM32F7. > >> Compiled via 'CONFIG_DEBUG_LL' and 'CONFIG_EARLY_PRINTK'. > >> Enabled via 'earlyprintk' in bootargs. > >> > >> Signed-off-by: Gerald Baeza > >> Signed-off-by: Bich Hemon > > > > Hi, > > > > This had fallen between the chairs it seems. I have applied it to arm-soc > > next/soc now, for 4.21 merge window. > > > > It ended up being patched up manually to consolidate the version in > > Russell's patch tracker with this posted version, and I tweaked whitespace > > a bit. Let me know if I missed something. > > > > > > Thanks, > > > > -Olof > > > > Hi Olof, > > Please note that this patch has to be abandoned as Ludovic BARRE pushed > a new version of this change: > https://patchwork.codeaurora.org/patch/400563/ > > You can find it in Russell's tracker here: > http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8803/1 And I'm not going to merge that because: 1) it's not for me to merge - it doesn't go through my tree, but through arm-soc, which Olof and Arnd manage. 2) it's not been on the mailing list as per normal submission process. Sorry. -- RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up
[PATCH][serial-next] serial-uartlite: fix null pointer dereference on pointer port
From: Colin Ian King
Pointer port is dereferenced on port->private_data when assigning pointer
pdata before port is null checked, leading to a potential null pointer
dereference. Fix this by assigning pdata after the null pointer check on
port.
Detected by CoverityScan, CID#1475434 ("Dereference before null check")
Fixes: 3b209d253e7f ("serial-uartlite: Do not use static struct uart_driver out
of probe()")
Signed-off-by: Colin Ian King
---
drivers/tty/serial/uartlite.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c
index 4a7989df5ff5..0eff33cd9f24 100644
--- a/drivers/tty/serial/uartlite.c
+++ b/drivers/tty/serial/uartlite.c
@@ -715,10 +715,12 @@ static int ulite_release(struct device *dev)
static int __maybe_unused ulite_suspend(struct device *dev)
{
struct uart_port *port = dev_get_drvdata(dev);
- struct uartlite_data *pdata = port->private_data;
- if (port)
+ if (port) {
+ struct uartlite_data *pdata = port->private_data;
+
uart_suspend_port(pdata->ulite_uart_driver, port);
+ }
return 0;
}
--
2.19.1
NACK: [PATCH][serial-next] serial-uartlite: fix null pointer dereference on pointer port
On 13/11/2018 09:38, Colin King wrote:
> From: Colin Ian King
>
> Pointer port is dereferenced on port->private_data when assigning pointer
> pdata before port is null checked, leading to a potential null pointer
> dereference. Fix this by assigning pdata after the null pointer check on
> port.
>
> Detected by CoverityScan, CID#1475434 ("Dereference before null check")
>
> Fixes: 3b209d253e7f ("serial-uartlite: Do not use static struct uart_driver
> out of probe()")
> Signed-off-by: Colin Ian King
> ---
> drivers/tty/serial/uartlite.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c
> index 4a7989df5ff5..0eff33cd9f24 100644
> --- a/drivers/tty/serial/uartlite.c
> +++ b/drivers/tty/serial/uartlite.c
> @@ -715,10 +715,12 @@ static int ulite_release(struct device *dev)
> static int __maybe_unused ulite_suspend(struct device *dev)
> {
> struct uart_port *port = dev_get_drvdata(dev);
> - struct uartlite_data *pdata = port->private_data;
>
> - if (port)
> + if (port) {
> + struct uartlite_data *pdata = port->private_data;
> +
> uart_suspend_port(pdata->ulite_uart_driver, port);
> + }
>
> return 0;
> }
>
Sorry for the noise, I sent the wrong fix. V2 coming soon.
Re: UBSAN: Undefined behaviour in mm/page_alloc.c
Andrew, could you take the patch please? This patch contains a comment
update as suggested by Tetsuo. I do not think there were any other
unresolved concerns.
>From 9ad6b1d9c07b18dd25a6af8cccbc56d1fbe6b922 Mon Sep 17 00:00:00 2001
From: Michal Hocko
Date: Fri, 9 Nov 2018 09:35:29 +0100
Subject: [PATCH] mm, page_alloc: check for max order in hot path
Konstantin has noticed that kvmalloc might trigger the following warning
[Thu Nov 1 08:43:56 2018] WARNING: CPU: 0 PID: 6676 at mm/vmstat.c:986
__fragmentation_index+0x54/0x60
[...]
[Thu Nov 1 08:43:56 2018] Call Trace:
[Thu Nov 1 08:43:56 2018] fragmentation_index+0x76/0x90
[Thu Nov 1 08:43:56 2018] compaction_suitable+0x4f/0xf0
[Thu Nov 1 08:43:56 2018] shrink_node+0x295/0x310
[Thu Nov 1 08:43:56 2018] node_reclaim+0x205/0x250
[Thu Nov 1 08:43:56 2018] get_page_from_freelist+0x649/0xad0
[Thu Nov 1 08:43:56 2018] ? get_page_from_freelist+0x2d4/0xad0
[Thu Nov 1 08:43:56 2018] ? release_sock+0x19/0x90
[Thu Nov 1 08:43:56 2018] ? do_ipv6_setsockopt.isra.5+0x10da/0x1290
[Thu Nov 1 08:43:56 2018] __alloc_pages_nodemask+0x12a/0x2a0
[Thu Nov 1 08:43:56 2018] kmalloc_large_node+0x47/0x90
[Thu Nov 1 08:43:56 2018] __kmalloc_node+0x22b/0x2e0
[Thu Nov 1 08:43:56 2018] kvmalloc_node+0x3e/0x70
[Thu Nov 1 08:43:56 2018] xt_alloc_table_info+0x3a/0x80 [x_tables]
[Thu Nov 1 08:43:56 2018] do_ip6t_set_ctl+0xcd/0x1c0 [ip6_tables]
[Thu Nov 1 08:43:56 2018] nf_setsockopt+0x44/0x60
[Thu Nov 1 08:43:56 2018] SyS_setsockopt+0x6f/0xc0
[Thu Nov 1 08:43:56 2018] do_syscall_64+0x67/0x120
[Thu Nov 1 08:43:56 2018] entry_SYSCALL_64_after_hwframe+0x3d/0xa2
the problem is that we only check for an out of bound order in the slow
path and the node reclaim might happen from the fast path already. This
is fixable by making sure that kvmalloc doesn't ever use kmalloc for
requests that are larger than KMALLOC_MAX_SIZE but this also shows that
the code is rather fragile. A recent UBSAN report just underlines that
by the following report
UBSAN: Undefined behaviour in mm/page_alloc.c:3117:19
shift exponent 51 is too large for 32-bit type 'int'
CPU: 0 PID: 6520 Comm: syz-executor1 Not tainted 4.19.0-rc2 #1
Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Bochs 01/01/2011
Call Trace:
__dump_stack lib/dump_stack.c:77 [inline]
dump_stack+0xd2/0x148 lib/dump_stack.c:113
ubsan_epilogue+0x12/0x94 lib/ubsan.c:159
__ubsan_handle_shift_out_of_bounds+0x2b6/0x30b lib/ubsan.c:425
__zone_watermark_ok+0x2c7/0x400 mm/page_alloc.c:3117
zone_watermark_fast mm/page_alloc.c:3216 [inline]
get_page_from_freelist+0xc49/0x44c0 mm/page_alloc.c:3300
__alloc_pages_nodemask+0x21e/0x640 mm/page_alloc.c:4370
alloc_pages_current+0xcc/0x210 mm/mempolicy.c:2093
alloc_pages include/linux/gfp.h:509 [inline]
__get_free_pages+0x12/0x60 mm/page_alloc.c:4414
dma_mem_alloc+0x36/0x50 arch/x86/include/asm/floppy.h:156
raw_cmd_copyin drivers/block/floppy.c:3159 [inline]
raw_cmd_ioctl drivers/block/floppy.c:3206 [inline]
fd_locked_ioctl+0xa00/0x2c10 drivers/block/floppy.c:3544
fd_ioctl+0x40/0x60 drivers/block/floppy.c:3571
__blkdev_driver_ioctl block/ioctl.c:303 [inline]
blkdev_ioctl+0xb3c/0x1a30 block/ioctl.c:601
block_ioctl+0x105/0x150 fs/block_dev.c:1883
vfs_ioctl fs/ioctl.c:46 [inline]
do_vfs_ioctl+0x1c0/0x1150 fs/ioctl.c:687
ksys_ioctl+0x9e/0xb0 fs/ioctl.c:702
__do_sys_ioctl fs/ioctl.c:709 [inline]
__se_sys_ioctl fs/ioctl.c:707 [inline]
__x64_sys_ioctl+0x7e/0xc0 fs/ioctl.c:707
do_syscall_64+0xc4/0x510 arch/x86/entry/common.c:290
entry_SYSCALL_64_after_hwframe+0x49/0xbe
Note that this is not a kvmalloc path. It is just that the fast path
really depends on having sanitzed order as well. Therefore move the
order check to the fast path.
Reported-by: Konstantin Khlebnikov
Reported-by: Kyungtae Kim
Acked-by: Vlastimil Babka
Signed-off-by: Michal Hocko
---
mm/page_alloc.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index a919ba5cb3c8..a2b68c513e22 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -4060,17 +4060,6 @@ __alloc_pages_slowpath(gfp_t gfp_mask, unsigned int
order,
unsigned int cpuset_mems_cookie;
int reserve_flags;
- /*
-* In the slowpath, we sanity check order to avoid ever trying to
-* reclaim >= MAX_ORDER areas which will never succeed. Callers may
-* be using allocators in order of preference for an area that is
-* too large.
-*/
- if (order >= MAX_ORDER) {
- WARN_ON_ONCE(!(gfp_mask & __GFP_NOWARN));
- return NULL;
- }
-
/*
* We also sanity check to catch abuse of atomic reserves being used by
* callers that are not in atomic context.
@@ -4364,6 +4353,15 @@ __alloc_pages_nodemask(gfp_t gfp_mask, unsigned int
order, int preferred_nid,
gfp_t alloc_mask; /* The gfp_t that was actually used for a
[PATCH][serial-next][V2] serial-uartlite: fix null pointer dereference on pointer port
From: Colin Ian King
Pointer port is dereferenced on port->private_data when assigning pointer
pdata before port is null checked, leading to a potential null pointer
dereference. Fix this by assigning pdata after the null pointer check on
port.
Detected by CoverityScan, CID#1475434 ("Dereference before null check")
Fixes: 3b209d253e7f ("serial-uartlite: Do not use static struct uart_driver out
of probe()")
Signed-off-by: Colin Ian King
---
drivers/tty/serial/uartlite.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c
index 4a7989df5ff5..b8b912b5a8b9 100644
--- a/drivers/tty/serial/uartlite.c
+++ b/drivers/tty/serial/uartlite.c
@@ -694,10 +694,11 @@ static int ulite_assign(struct device *dev, int id, u32
base, int irq,
static int ulite_release(struct device *dev)
{
struct uart_port *port = dev_get_drvdata(dev);
- struct uartlite_data *pdata = port->private_data;
int rc = 0;
if (port) {
+ struct uartlite_data *pdata = port->private_data;
+
rc = uart_remove_one_port(pdata->ulite_uart_driver, port);
dev_set_drvdata(dev, NULL);
port->mapbase = 0;
@@ -715,10 +716,12 @@ static int ulite_release(struct device *dev)
static int __maybe_unused ulite_suspend(struct device *dev)
{
struct uart_port *port = dev_get_drvdata(dev);
- struct uartlite_data *pdata = port->private_data;
- if (port)
+ if (port) {
+ struct uartlite_data *pdata = port->private_data;
+
uart_suspend_port(pdata->ulite_uart_driver, port);
+ }
return 0;
}
@@ -732,10 +735,12 @@ static int __maybe_unused ulite_suspend(struct device
*dev)
static int __maybe_unused ulite_resume(struct device *dev)
{
struct uart_port *port = dev_get_drvdata(dev);
- struct uartlite_data *pdata = port->private_data;
- if (port)
+ if (port) {
+ struct uartlite_data *pdata = port->private_data;
+
uart_resume_port(pdata->ulite_uart_driver, port);
+ }
return 0;
}
--
2.19.1
Re: Crash in msm serial on dragonboard with ftrace bootargs
Hi Sai, On 25/10/18 15:36, saiprakash.ran...@codeaurora.org wrote: "If I disable dma node and LS-UART0, then I don't see any crash and ftrace also works fine" And one more observation is that even without ftrace cmdline, if I use earlycon and disable dma, I face the same crash. So basically this seems to be some kind of earlycon and dma issue and not ftrace(I can be wrong). So adding Srinivas for more info on this dma node. Its Interesting that my old email conversations with SBoyd show that I have investigated this issue in early 2016! My analysis so far: This reason for such behavior is due the common iface clock (GCC_BLSP1_AHB_CLK) across multiple drivers(serial ports, bam dma and other low speed devices). The code flow in DB410C is bit different, as the uart0 is first attempted to set as console and then uart1, this ordering triggers pm state change uart_change_pm(state, UART_PM_STATE_OFF) from serial core while setting up uart0, this would go and disable all the clocks for uart0. As uart1 is not setup Yet, and earlycon is still active, any attempts by earlycon to write to registers would trigger a system reboot as the clock was just disabled by uart0 change_pm code. This can even be triggered with any drivers like spi which uses same clock I guess. Hope it helps, Either earlycon needs to reference the clocks or those clocks needs to be marked always-on (but only with earlycon). Also just for a note: apq8096-db820c.dtsi shows UART0 is disabled because bootloader does not allow access to it. Could this also be the case for db410c? No, this is not the case with DB410c. DB820c has added restrictions in TZ, I think new booloaders should have solved this issue. Thanks, srini
[PATCH 1/3] dt-bindings: pinctrl: stm32: Document hwlocks properties
Add hwlocks as optional property Signed-off-by: Benjamin Gaignard --- Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index ef4f2ff4a1aa..48df30a36b01 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -56,6 +56,7 @@ Optional properties: More details in Documentation/devicetree/bindings/gpio/gpio.txt. - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line used to select GPIOs as interrupts). + - hwlocks: reference to a phandle of a hardware spinlock provider node. Example 1: #include -- 2.15.0
[PATCH 0/3] make pin-controller use hwspinlock
This series allow to protect pin controller configuration registers with a hwspinlock to avoid conflicting accesses between processors. Benjamin Gaignard (3): dt-bindings: pinctrl: stm32: Document hwlocks properties pinctrl: stm32: protect configuration registers with a hwspinlock ARM: dts: stm32: Add hwlock for pinctrl .../bindings/pinctrl/st,stm32-pinctrl.txt | 1 + arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 1 + drivers/pinctrl/stm32/pinctrl-stm32.c | 71 +- 3 files changed, 72 insertions(+), 1 deletion(-) -- 2.15.0
[PATCH 3/3] ARM: dts: stm32: Add hwlock for pinctrl
Define a hwspinlock to be used by pin-controller
Signed-off-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index c4851271e810..2886e5a6ac27 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -14,6 +14,7 @@
ranges = <0 0x50002000 0xa400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
+ hwlocks = <&hsem 0>;
pins-are-numbered;
gpioa: gpio@50002000 {
--
2.15.0
[PATCH 2/3] pinctrl: stm32: protect configuration registers with a hwspinlock
If a hwspinlock if defined in device tree use it to protect
configuration registers.
Signed-off-by: Benjamin Gaignard
---
drivers/pinctrl/stm32/pinctrl-stm32.c | 71 ++-
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index a9bec6e6fdd1..dce9dabaf4d5 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -8,6 +8,7 @@
*/
#include
#include
+#include
#include
#include
#include
@@ -51,6 +52,8 @@
#define gpio_range_to_bank(chip) \
container_of(chip, struct stm32_gpio_bank, range)
+#define HWSPINLOCK_TIMEOUT 5 /* msec */
+
static const char * const stm32_gpio_functions[] = {
"gpio", "af0", "af1",
"af2", "af3", "af4",
@@ -91,6 +94,7 @@ struct stm32_pinctrl {
struct irq_domain *domain;
struct regmap *regmap;
struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
+ struct hwspinlock *hwlock;
};
static inline int stm32_gpio_pin(int gpio)
@@ -576,14 +580,24 @@ static int stm32_pmx_get_func_groups(struct pinctrl_dev
*pctldev,
static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
int pin, u32 mode, u32 alt)
{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
u32 val;
int alt_shift = (pin % 8) * 4;
int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
unsigned long flags;
+ int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock)
+ err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
+
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+
val = readl_relaxed(bank->base + alt_offset);
val &= ~GENMASK(alt_shift + 3, alt_shift);
val |= (alt << alt_shift);
@@ -594,6 +608,10 @@ static void stm32_pmx_set_mode(struct stm32_gpio_bank
*bank,
val |= mode << (pin * 2);
writel_relaxed(val, bank->base + STM32_GPIO_MODER);
+ if (pctl->hwlock)
+ hwspin_unlock(pctl->hwlock);
+
+unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@@ -683,17 +701,31 @@ static const struct pinmux_ops stm32_pmx_ops = {
static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
unsigned offset, u32 drive)
{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
+ int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock)
+ err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
+
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+
val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
val &= ~BIT(offset);
val |= drive << offset;
writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
+ if (pctl->hwlock)
+ hwspin_unlock(pctl->hwlock);
+
+unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@@ -719,17 +751,31 @@ static u32 stm32_pconf_get_driving(struct stm32_gpio_bank
*bank,
static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
unsigned offset, u32 speed)
{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
+ int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock)
+ err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
+
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+
val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
val &= ~GENMASK(offset * 2 + 1, offset * 2);
val |= speed << (offset * 2);
writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
+ if (pctl->hwlock)
+ hwspin_unlock(pctl->hwlock);
+
+unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@@ -755,17 +801,31 @@ static u32 stm32_pconf_get_speed(struct stm32_gpio_bank
*bank,
static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
unsigned offset, u32 bias)
{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
+ int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock)
+ err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
+
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+
Re: [resend PATCH 1/3] pwm: mediatek: drop flag 'has_clks'
Hello,
On Tue, Nov 13, 2018 at 10:08:22AM +0800, Ryder Lee wrote:
> The flag 'has_clks' and related checks are superfluous as the CCF
> subsystem does this for you.
I'd write instead:
Handle optional clocks by using NULL as clk instead of a
separate bool field in the device's platform data.
There is a semantic difference this patch introduces (i.e. if on mt2712
there are no provided clocks, the driver now successfully binds while
before it failed with -ENOENT. And for mt7628 it's the other way round).
IMHO this should be noted in the commit log, too. Otherwise it sounds as
if this patch was just an optimisation without side effects.
> ---
> drivers/pwm/pwm-mediatek.c | 20 +---
> 1 file changed, 5 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
> index eb6674c..9400c41 100644
> --- a/drivers/pwm/pwm-mediatek.c
> +++ b/drivers/pwm/pwm-mediatek.c
> @@ -57,7 +57,6 @@ enum {
> struct mtk_pwm_platform_data {
> unsigned int num_pwms;
> bool pwm45_fixup;
> - bool has_clks;
> };
>
> /**
> @@ -87,9 +86,6 @@ static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct
> pwm_device *pwm)
> struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
> int ret;
>
> - if (!pc->soc->has_clks)
> - return 0;
> -
> ret = clk_prepare_enable(pc->clks[MTK_CLK_TOP]);
> if (ret < 0)
> return ret;
> @@ -116,9 +112,6 @@ static void mtk_pwm_clk_disable(struct pwm_chip *chip,
> struct pwm_device *pwm)
> {
> struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
>
> - if (!pc->soc->has_clks)
> - return;
> -
> clk_disable_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
> clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
> clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
> @@ -246,12 +239,13 @@ static int mtk_pwm_probe(struct platform_device *pdev)
> if (IS_ERR(pc->regs))
> return PTR_ERR(pc->regs);
>
> - for (i = 0; i < data->num_pwms + 2 && pc->soc->has_clks; i++) {
> + for (i = 0; i < data->num_pwms + 2; i++) {
> pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]);
> if (IS_ERR(pc->clks[i])) {
> - dev_err(&pdev->dev, "clock: %s fail: %ld\n",
> - mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i]));
> - return PTR_ERR(pc->clks[i]);
> + if (PTR_ERR(pc->clks[i]) == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
> +
> + pc->clks[i] = NULL;
I'd prefer the following instead:
pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]);
if (IS_ERR(pc->clks[i])) {
if (PTR_ERR(pc->clks[i]) == -ENODEV) {
pc->clks[i] = NULL;
} else {
if (PTR_ERR(pc->clks[i]) == -EPROBE_DEFER)
dev_err(...);
return PTR_ERR(pc->clks[i]);
}
This way you only handle "There is no such clock" and are not ignoring
say an IO error.
I wonder if it would make sense to introduce functions like:
struct clk *clk_get_optional(struct device *dev, const char *id)
that return NULL instead of ERR_PTR(-ENODEV).
Then the above would simplify to:
pc->clks[i] = devm_clk_get_optional(&pdev->dev, mtk_pwm_clk_name[i]);
if (IS_ERR(pc->clks[i]) {
if (PTR_ERR(pc->clks[i]) == -EPROBE_DEFER)
dev_err(...);
return PTR_ERR(pc->clks[i]);
}
(added the clk people to Cc for this question).
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König|
Industrial Linux Solutions | http://www.pengutronix.de/ |
Re: [resend PATCH 3/3] dt-bindings: pwm: update bindings for MT7629 SoC
On Tue, Nov 13, 2018 at 10:08:24AM +0800, Ryder Lee wrote: > This updates bindings for MT7629 pwm controller. > > Signed-off-by: Ryder Lee > --- > Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt > b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt > index 991728c..4a2885b 100644 > --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt > +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt > @@ -6,6 +6,7 @@ Required properties: > - "mediatek,mt7622-pwm": found on mt7622 SoC. > - "mediatek,mt7623-pwm": found on mt7623 SoC. > - "mediatek,mt7628-pwm": found on mt7628 SoC. > + - "mediatek,mt7629-pwm": found on mt7629 SoC. > - reg: physical base address and length of the controller's registers. > - #pwm-cells: must be 2. See pwm.txt in this directory for a description of > the cell format. Does the mt7629 need clocks? I'd suggest to move the clocks and clock-names description to a section "Optional properties" to match what is implemented in patch 1 of this series. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König| Industrial Linux Solutions | http://www.pengutronix.de/ |
Re: [PATCH 3/3] ARM: dts: stm32: Add hwlock for pinctrl
Hi Benjamin
On 11/13/18 10:51 AM, Benjamin Gaignard wrote:
Define a hwspinlock to be used by pin-controller
Signed-off-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 1 +
1 file changed, 1 insertion(+)
In commit title please add for which SoC it is targeted. If you don't
have to send new version for driver or dt-bindings, I will do it when
I'll apply.
regards
Alex
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index c4851271e810..2886e5a6ac27 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -14,6 +14,7 @@
ranges = <0 0x50002000 0xa400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
+ hwlocks = <&hsem 0>;
pins-are-numbered;
gpioa: gpio@50002000 {
[PATCH v2 0/3] Fixes for Tegra soctherm
This series fixed some issues for Tegra soctherm Main changes from v1: 1. Acked by Thierry Reding for the patch "thermal: tegra: fix memory allocation". 2. Print out the sensor name when register failed. 2. Remove patch "thermal: tegra: fix coverity defect" Wei Ni (3): thermal: tegra: continue if sensor register fails thermal: tegra: remove unnecessary warnings thermal: tegra: fix memory allocation drivers/thermal/tegra/soctherm.c | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) -- 2.7.4
Re: [PATCH v2 05/11] Doc: DT: thermal: new irq-mode for trip point
Hi Krzysztof, Thanks for the comments. On 11/12/18 9:51 AM, Krzysztof Kozlowski wrote: > On Wed, 7 Nov 2018 at 18:10, Lukasz Luba wrote: >> > > Subject prefix: > dt-bindings: thermal: > >> Thermal trip point gets new flag in DT: irq-mode. >> Trip point may have a new explicit flag which indicate >> IRQ support when the temperature is met (so the thermal framework >> deos not need to set polling for it). >> It is useful for 'passive' cooling trip point, >> which now will not register for polling the temperature. > > You wrap lines in weird way making it more difficult to read. > I already asked about this while reviewing v1. Please fix it. > https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L633 > I will fix it in v3. >> >> Update documentation about irq-mode for trip points. >> >> Cc: Zhang Rui >> Cc: Eduardo Valentin >> Cc: Daniel Lezcano >> Cc: Rob Herring >> Cc: Mark Rutland >> Cc: devicet...@vger.kernel.org >> Signed-off-by: Lukasz Luba >> --- >> Documentation/devicetree/bindings/thermal/thermal.txt | 7 +++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/thermal/thermal.txt >> b/Documentation/devicetree/bindings/thermal/thermal.txt >> index ca14ba9..bee21e3 100644 >> --- a/Documentation/devicetree/bindings/thermal/thermal.txt >> +++ b/Documentation/devicetree/bindings/thermal/thermal.txt >> @@ -90,6 +90,10 @@ Required properties: >> "critical": Hardware not reliable. >> Type: string >> >> +- irq-mode:A flag indicating that trip rises irq, so there is no > > "rises IRQ" (it is an abbreviation). ACK > > Best regards, > Krzysztof > Regards, Lukasz
[PATCH v2 2/3] thermal: tegra: remove unnecessary warnings
Convert warnings to info as not all platforms may
have all the thresholds and sensors enabled.
Signed-off-by: Wei Ni
---
drivers/thermal/tegra/soctherm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
index a824d2e63af3..161ef242bcca 100644
--- a/drivers/thermal/tegra/soctherm.c
+++ b/drivers/thermal/tegra/soctherm.c
@@ -550,7 +550,7 @@ static int tegra_soctherm_set_hwtrips(struct device *dev,
ret = tz->ops->get_crit_temp(tz, &temperature);
if (ret) {
- dev_warn(dev, "thermtrip: %s: missing critical temperature\n",
+ dev_info(dev, "thermtrip: %s: missing critical temperature\n",
sg->name);
goto set_throttle;
}
@@ -569,7 +569,7 @@ static int tegra_soctherm_set_hwtrips(struct device *dev,
set_throttle:
ret = get_hot_temp(tz, &trip, &temperature);
if (ret) {
- dev_warn(dev, "throttrip: %s: missing hot temperature\n",
+ dev_info(dev, "throttrip: %s: missing hot temperature\n",
sg->name);
return 0;
}
@@ -600,7 +600,7 @@ static int tegra_soctherm_set_hwtrips(struct device *dev,
}
if (i == THROTTLE_SIZE)
- dev_warn(dev, "throttrip: %s: missing throttle cdev\n",
+ dev_info(dev, "throttrip: %s: missing throttle cdev\n",
sg->name);
return 0;
--
2.7.4
[PATCH v2 1/3] thermal: tegra: continue if sensor register fails
Don't bail when a sensor fails to register with the
thermal zone and allow other sensors to register.
This allows other sensors to register with thermal
framework even if one sensor fails registration.
Signed-off-by: Wei Ni
---
drivers/thermal/tegra/soctherm.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
index ed28110a3535..a824d2e63af3 100644
--- a/drivers/thermal/tegra/soctherm.c
+++ b/drivers/thermal/tegra/soctherm.c
@@ -1370,9 +1370,9 @@ static int tegra_soctherm_probe(struct platform_device
*pdev)
&tegra_of_thermal_ops);
if (IS_ERR(z)) {
err = PTR_ERR(z);
- dev_err(&pdev->dev, "failed to register sensor: %d\n",
- err);
- goto disable_clocks;
+ dev_warn(&pdev->dev, "failed to register sensor %s:
%d\n",
+soc->ttgs[i]->name, err);
+ continue;
}
zone->tz = z;
@@ -1434,6 +1434,8 @@ static int __maybe_unused soctherm_resume(struct device
*dev)
struct thermal_zone_device *tz;
tz = tegra->thermctl_tzs[soc->ttgs[i]->id];
+ if (!tz)
+ continue;
err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz);
if (err) {
dev_err(&pdev->dev,
--
2.7.4
[PATCH v2 3/3] thermal: tegra: fix memory allocation
Fix memory allocation to store the pointers to thermal_zone_device. Signed-off-by: Wei Ni Acked-by: Thierry Reding --- drivers/thermal/tegra/soctherm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c index 161ef242bcca..96ca10789f17 100644 --- a/drivers/thermal/tegra/soctherm.c +++ b/drivers/thermal/tegra/soctherm.c @@ -1339,7 +1339,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev) } tegra->thermctl_tzs = devm_kcalloc(&pdev->dev, - soc->num_ttgs, sizeof(*z), + soc->num_ttgs, sizeof(z), GFP_KERNEL); if (!tegra->thermctl_tzs) return -ENOMEM; -- 2.7.4
[PATCH v6 3/5] dt-bindings: pinctrl: Add bindings for Actions Semi S700 SoC
From: Saravanan Sekar Add pinctrl and pio bindings for Actions Semi S700 SoC. Signed-off-by: Parthiban Nallathambi Signed-off-by: Saravanan Sekar Reviewed-by: Rob Herring --- .../bindings/pinctrl/actions,s700-pinctrl.txt | 170 ++ 1 file changed, 170 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt new file mode 100644 index ..c72c09c38537 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt @@ -0,0 +1,170 @@ +Actions Semi S700 Pin Controller + +This binding describes the pin controller found in the S700 SoC. + +Required Properties: + +- compatible: Should be "actions,s700-pinctrl" +- reg: Should contain the register base address and size of + the pin controller. +- clocks: phandle of the clock feeding the pin controller +- gpio-controller: Marks the device node as a GPIO controller. +- gpio-ranges: Specifies the mapping between gpio controller and + pin-controller pins. +- #gpio-cells: Should be two. The first cell is the gpio pin number + and the second cell is used for optional parameters. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt. Shall be set to 2. The first cell + defines the interrupt number, the second encodes + the trigger flags described in + bindings/interrupt-controller/interrupts.txt +- interrupts: The interrupt outputs from the controller. There is one GPIO + interrupt per GPIO bank. The number of interrupts listed depends + on the number of GPIO banks on the SoC. The interrupts must be + ordered by bank, starting with bank 0. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +Pinmux functions are available only for the pin groups while pinconf +parameters are available for both pin groups and individual pins. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +Required Properties: + +- pins:An array of strings, each string containing the name of a pin. + These pins are used for selecting the pull control and schmitt + trigger parameters. The following are the list of pins + available: + + eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer, + eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk, + eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, + i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, + pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2, + ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp, + lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap, + lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, + lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, + lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, + dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, + sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, + sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx, + uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, + uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk, + i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1, + csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3, + sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2, +
[PATCH v6 0/5] Add Actions Semi S700 pinctrl support
This patchset adds pinctrl support for Actions Semi S700 SoC. Pinmux functions are only accessible for pin groups while pinconf parameters are available for both pin groups and individual pins. pinctrl driver is verified using the Cubieboard7. common functionalities from s900 is moved for all Actions Semi SoC's usage. Common pad control configurations are moved to SoC specific dts entry for pinctrl depends on clock driver which is still under review: https://patchwork.kernel.org/patch/10533959/ Thanks, Saravanan Parthiban Changelog in v2 - GPIO Interrupt support is added - Device tree entry for GPIO and Interrupt configured - GPIO and pinctrl define reorder, commit message findings fixed depends on owl GPIO Interrupt support https://patchwork.kernel.org/patch/10483477/ Chnagelog in v3 - Fixed 0-DAY bisectibility error Chnagelog in v4 - Fixed 0-DAY sparse warnings on static declaration Chnagelog in v5 - Rebase to mainline Chnagelog in v6 - Rebase to 4.20-rc2 mainline - Fixed nitpick findings in v5 Saravanan Sekar (5): pinctrl: actions: define constructor generic to Actions Semi SoC's pinctrl: actions: define pad control configurtion to SoC specific dt-bindings: pinctrl: Add bindings for Actions Semi S700 SoC pinctrl: actions: Add Actions Semi S700 pinctrl driver arm64: dts: actions: Add pinctrl node for Actions Semi S700 .../bindings/pinctrl/actions,s700-pinctrl.txt | 170 ++ arch/arm64/boot/dts/actions/s700.dtsi | 16 + drivers/pinctrl/actions/Kconfig |6 + drivers/pinctrl/actions/Makefile |1 + drivers/pinctrl/actions/pinctrl-owl.c | 71 +- drivers/pinctrl/actions/pinctrl-owl.h | 142 +- drivers/pinctrl/actions/pinctrl-s700.c| 1912 + drivers/pinctrl/actions/pinctrl-s900.c| 205 +- 8 files changed, 2324 insertions(+), 199 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt create mode 100644 drivers/pinctrl/actions/pinctrl-s700.c -- 2.17.2
[PATCH v6 2/5] pinctrl: actions: define pad control configurtion to SoC specific
From: Saravanan Sekar
pad control for s900 and s700 are differs in number of
pull control configuraions
s900 has 4 pull controls - high impedence, pull up, pull down, repeater
s700, s500 has 2 pull controls - pull up and pull down
so pad control configuration has to SoC specific, moved out from pinctrl
common to s900 specific.
Signed-off-by: Parthiban Nallathambi
Signed-off-by: Saravanan Sekar
---
drivers/pinctrl/actions/pinctrl-owl.c | 64 -
drivers/pinctrl/actions/pinctrl-owl.h | 13 +++--
drivers/pinctrl/actions/pinctrl-s900.c | 66 +-
3 files changed, 79 insertions(+), 64 deletions(-)
diff --git a/drivers/pinctrl/actions/pinctrl-owl.c
b/drivers/pinctrl/actions/pinctrl-owl.c
index 9d18c02f192b..cc242d6a47c3 100644
--- a/drivers/pinctrl/actions/pinctrl-owl.c
+++ b/drivers/pinctrl/actions/pinctrl-owl.c
@@ -246,60 +246,6 @@ static int owl_pad_pinconf_reg(const struct owl_padinfo
*info,
return 0;
}
-static int owl_pad_pinconf_arg2val(const struct owl_padinfo *info,
- unsigned int param,
- u32 *arg)
-{
- switch (param) {
- case PIN_CONFIG_BIAS_BUS_HOLD:
- *arg = OWL_PINCONF_PULL_HOLD;
- break;
- case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
- *arg = OWL_PINCONF_PULL_HIZ;
- break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
- *arg = OWL_PINCONF_PULL_DOWN;
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- *arg = OWL_PINCONF_PULL_UP;
- break;
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- *arg = (*arg >= 1 ? 1 : 0);
- break;
- default:
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int owl_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
- unsigned int param,
- u32 *arg)
-{
- switch (param) {
- case PIN_CONFIG_BIAS_BUS_HOLD:
- *arg = *arg == OWL_PINCONF_PULL_HOLD;
- break;
- case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
- *arg = *arg == OWL_PINCONF_PULL_HIZ;
- break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
- *arg = *arg == OWL_PINCONF_PULL_DOWN;
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- *arg = *arg == OWL_PINCONF_PULL_UP;
- break;
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- *arg = *arg == 1;
- break;
- default:
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
unsigned int pin,
unsigned long *config)
@@ -318,7 +264,10 @@ static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
arg = owl_read_field(pctrl, reg, bit, width);
- ret = owl_pad_pinconf_val2arg(info, param, &arg);
+ if (!pctrl->soc->padctl_val2arg)
+ return -ENOTSUPP;
+
+ ret = pctrl->soc->padctl_val2arg(info, param, &arg);
if (ret)
return ret;
@@ -349,7 +298,10 @@ static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
if (ret)
return ret;
- ret = owl_pad_pinconf_arg2val(info, param, &arg);
+ if (!pctrl->soc->padctl_arg2val)
+ return -ENOTSUPP;
+
+ ret = pctrl->soc->padctl_arg2val(info, param, &arg);
if (ret)
return ret;
diff --git a/drivers/pinctrl/actions/pinctrl-owl.h
b/drivers/pinctrl/actions/pinctrl-owl.h
index 31cc33d7c4a5..dae2e8363fd5 100644
--- a/drivers/pinctrl/actions/pinctrl-owl.h
+++ b/drivers/pinctrl/actions/pinctrl-owl.h
@@ -145,13 +145,6 @@
.shared_ctl_offset = _share,\
}
-enum owl_pinconf_pull {
- OWL_PINCONF_PULL_HIZ,
- OWL_PINCONF_PULL_DOWN,
- OWL_PINCONF_PULL_UP,
- OWL_PINCONF_PULL_HOLD,
-};
-
enum owl_pinconf_drv {
OWL_PINCONF_DRV_2MA,
OWL_PINCONF_DRV_4MA,
@@ -305,6 +298,12 @@ struct owl_pinctrl_soc_data {
unsigned int ngpios;
const struct owl_gpio_port *ports;
unsigned int nports;
+ int (*padctl_val2arg)(const struct owl_padinfo *padinfo,
+ unsigned int param,
+ u32 *arg);
+ int (*padctl_arg2val)(const struct owl_padinfo *info,
+ unsigned int param,
+ u32 *arg);
};
int owl_pinctrl_probe(struct platform_device *pdev,
diff --git a/drivers/pinctrl/actions/pinctrl-s900.c
b/drivers/pinctrl/actions/pinctrl-s900.c
index 0597009d8369..9492b86852e7 100644
--- a/drivers/pinctrl/actions/pinctrl-s900.c
+++ b/drivers/pinctrl/actions/pinctrl-s900.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#inc
[PATCH v6 4/5] pinctrl: actions: Add Actions Semi S700 pinctrl driver
From: Saravanan Sekar Add pinctrl and gpio driver for Actions Semi S700 SoC. The driver supports pinctrl, pinmux, pinconf, gpio and interrupt functionalities through a range of registers common to both gpio driver and pinctrl driver. Signed-off-by: Parthiban Nallathambi Signed-off-by: Saravanan Sekar --- drivers/pinctrl/actions/Kconfig|6 + drivers/pinctrl/actions/Makefile |1 + drivers/pinctrl/actions/pinctrl-owl.c |7 +- drivers/pinctrl/actions/pinctrl-s700.c | 1912 4 files changed, 1923 insertions(+), 3 deletions(-) create mode 100644 drivers/pinctrl/actions/pinctrl-s700.c diff --git a/drivers/pinctrl/actions/Kconfig b/drivers/pinctrl/actions/Kconfig index 2397cb0f6011..c7ed1d481802 100644 --- a/drivers/pinctrl/actions/Kconfig +++ b/drivers/pinctrl/actions/Kconfig @@ -9,6 +9,12 @@ config PINCTRL_OWL help Say Y here to enable Actions Semi OWL pinctrl driver +config PINCTRL_S700 + bool "Actions Semi S700 pinctrl driver" + depends on PINCTRL_OWL + help + Say Y here to enable Actions Semi S700 pinctrl driver + config PINCTRL_S900 bool "Actions Semi S900 pinctrl driver" depends on PINCTRL_OWL diff --git a/drivers/pinctrl/actions/Makefile b/drivers/pinctrl/actions/Makefile index bd232d28400f..86521ed837dd 100644 --- a/drivers/pinctrl/actions/Makefile +++ b/drivers/pinctrl/actions/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_PINCTRL_OWL) += pinctrl-owl.o +obj-$(CONFIG_PINCTRL_S700) += pinctrl-s700.o obj-$(CONFIG_PINCTRL_S900) += pinctrl-s900.o diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c index cc242d6a47c3..5dfe7188a5f8 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.c +++ b/drivers/pinctrl/actions/pinctrl-owl.c @@ -739,7 +739,7 @@ static void owl_gpio_irq_mask(struct irq_data *data) val = readl_relaxed(gpio_base + port->intc_msk); if (val == 0) owl_gpio_update_reg(gpio_base + port->intc_ctl, - OWL_GPIO_CTLR_ENABLE, false); + OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false); raw_spin_unlock_irqrestore(&pctrl->lock, flags); } @@ -763,7 +763,8 @@ static void owl_gpio_irq_unmask(struct irq_data *data) /* enable port interrupt */ value = readl_relaxed(gpio_base + port->intc_ctl); - value |= BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M); + value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M)) + << port->shared_ctl_offset * 5); writel_relaxed(value, gpio_base + port->intc_ctl); /* enable GPIO interrupt */ @@ -801,7 +802,7 @@ static void owl_gpio_irq_ack(struct irq_data *data) raw_spin_lock_irqsave(&pctrl->lock, flags); owl_gpio_update_reg(gpio_base + port->intc_ctl, - OWL_GPIO_CTLR_PENDING, true); + OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true); raw_spin_unlock_irqrestore(&pctrl->lock, flags); } diff --git a/drivers/pinctrl/actions/pinctrl-s700.c b/drivers/pinctrl/actions/pinctrl-s700.c new file mode 100644 index ..8b8121e35edb --- /dev/null +++ b/drivers/pinctrl/actions/pinctrl-s700.c @@ -0,0 +1,1912 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi Owl S700 Pinctrl driver + * + * Copyright (c) 2014 Actions Semi Inc. + * Author: David Liu + * + * Author: Pathiban Nallathambi + * Author: Saravanan Sekar + */ + +#include +#include +#include +#include +#include +#include "pinctrl-owl.h" + +/* Pinctrl registers offset */ +#define MFCTL0 (0x0040) +#define MFCTL1 (0x0044) +#define MFCTL2 (0x0048) +#define MFCTL3 (0x004C) +#define PAD_PULLCTL0 (0x0060) +#define PAD_PULLCTL1 (0x0064) +#define PAD_PULLCTL2 (0x0068) +#define PAD_ST0(0x006C) +#define PAD_ST1(0x0070) +#define PAD_CTL(0x0074) +#define PAD_DRV0 (0x0080) +#define PAD_DRV1 (0x0084) +#define PAD_DRV2 (0x0088) + +/* + * Most pins affected by the pinmux can also be GPIOs. Define these first. + * These must match how the GPIO driver names/numbers its pins. + */ +#define _GPIOA(offset) (offset) +#define _GPIOB(offset) (32 + (offset)) +#define _GPIOC(offset) (64 + (offset)) +#define _GPIOD(offset) (96 + (offset)) +#define _GPIOE(offset) (128 + (offset)) + +/* All non-GPIO pins follow */ +#define NUM_GPIOS (_GPIOE(7) + 1) +#define _PIN(offset) (NUM_GPIOS + (offset)) + +/* Ethernet MAC */ +#define ETH_TXD0 _GPIOA(14) +#define ETH_TXD1 _GPIOA(15) +#define ETH_TXD2 _GPIOE(4) +#define ETH_TXD3 _GPIOE(5) +#define
[PATCH v6 1/5] pinctrl: actions: define constructor generic to Actions Semi SoC's
From: Saravanan Sekar
Move generic defines common to the Owl family out of S900 driver.
Signed-off-by: Parthiban Nallathambi
Signed-off-by: Saravanan Sekar
---
drivers/pinctrl/actions/pinctrl-owl.h | 131 +++
drivers/pinctrl/actions/pinctrl-s900.c | 139 ++---
2 files changed, 137 insertions(+), 133 deletions(-)
diff --git a/drivers/pinctrl/actions/pinctrl-owl.h
b/drivers/pinctrl/actions/pinctrl-owl.h
index a724d1d406d4..31cc33d7c4a5 100644
--- a/drivers/pinctrl/actions/pinctrl-owl.h
+++ b/drivers/pinctrl/actions/pinctrl-owl.h
@@ -15,6 +15,136 @@
#define OWL_PINCONF_SLEW_SLOW 0
#define OWL_PINCONF_SLEW_FAST 1
+#define MUX_PG(group_name, reg, shift, width) \
+ { \
+ .name = #group_name,\
+ .pads = group_name##_pads, \
+ .npads = ARRAY_SIZE(group_name##_pads), \
+ .funcs = group_name##_funcs,\
+ .nfuncs = ARRAY_SIZE(group_name##_funcs), \
+ .mfpctl_reg = MFCTL##reg, \
+ .mfpctl_shift = shift, \
+ .mfpctl_width = width, \
+ .drv_reg = -1, \
+ .drv_shift = -1,\
+ .drv_width = -1,\
+ .sr_reg = -1, \
+ .sr_shift = -1, \
+ .sr_width = -1, \
+ }
+
+#define DRV_PG(group_name, reg, shift, width) \
+ { \
+ .name = #group_name,\
+ .pads = group_name##_pads, \
+ .npads = ARRAY_SIZE(group_name##_pads), \
+ .mfpctl_reg = -1, \
+ .mfpctl_shift = -1, \
+ .mfpctl_width = -1, \
+ .drv_reg = PAD_DRV##reg,\
+ .drv_shift = shift, \
+ .drv_width = width, \
+ .sr_reg = -1, \
+ .sr_shift = -1, \
+ .sr_width = -1, \
+ }
+
+#define SR_PG(group_name, reg, shift, width) \
+ { \
+ .name = #group_name,\
+ .pads = group_name##_pads, \
+ .npads = ARRAY_SIZE(group_name##_pads), \
+ .mfpctl_reg = -1, \
+ .mfpctl_shift = -1, \
+ .mfpctl_width = -1, \
+ .drv_reg = -1, \
+ .drv_shift = -1,\
+ .drv_width = -1,\
+ .sr_reg = PAD_SR##reg, \
+ .sr_shift = shift, \
+ .sr_width = width, \
+ }
+
+#define FUNCTION(fname)\
+ { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+/* PAD PULL UP/DOWN CONFIGURES */
+#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \
+ { \
+ .reg = PAD_PULLCTL##pull_reg, \
+ .shift = pull_sft, \
+ .width = pull_wdt, \
+ }
+
+#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \
+ struct owl_pullctl pad_name##_pullctl_conf \
+ = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
+
+#define ST_CONF(st_reg, st_sft, st_wdt)\
+ { \
+ .reg = PAD_ST##st_reg,
[PATCH v6 5/5] arm64: dts: actions: Add pinctrl node for Actions Semi S700
From: Saravanan Sekar
Add pinctrl nodes for Actions Semi S700 SoC
Signed-off-by: Parthiban Nallathambi
Signed-off-by: Saravanan Sekar
---
arch/arm64/boot/dts/actions/s700.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/actions/s700.dtsi
b/arch/arm64/boot/dts/actions/s700.dtsi
index 192c7b39c8c1..dceadb945da3 100644
--- a/arch/arm64/boot/dts/actions/s700.dtsi
+++ b/arch/arm64/boot/dts/actions/s700.dtsi
@@ -186,5 +186,21 @@
interrupts = ;
interrupt-names = "timer1";
};
+
+ pinctrl: pinctrl@e01b {
+ compatible = "actions,s700-pinctrl";
+ reg = <0x0 0xe01b 0x0 0x1000>;
+ clocks = <&cmu CLK_GPIO>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 136>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = ,
+,
+,
+,
+;
+ };
};
};
--
2.17.2
Re: [PATCH] vfio/mdev: add static modifier to add_mdev_supported_type
On Tue, 13 Nov 2018 09:45:43 +0100
Paolo Cretaro wrote:
> Set add_mdev_supported_type as static since it is only used within
> mdev_sysfs.c.
> This fixes -Wmissing-prototypes gcc warning.
>
> Signed-off-by: Paolo Cretaro
> ---
> drivers/vfio/mdev/mdev_sysfs.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/vfio/mdev/mdev_sysfs.c b/drivers/vfio/mdev/mdev_sysfs.c
> index 249472f05509..ce5dd219f2c8 100644
> --- a/drivers/vfio/mdev/mdev_sysfs.c
> +++ b/drivers/vfio/mdev/mdev_sysfs.c
> @@ -92,8 +92,8 @@ static struct kobj_type mdev_type_ktype = {
> .release = mdev_type_release,
> };
>
> -struct mdev_type *add_mdev_supported_type(struct mdev_parent *parent,
> - struct attribute_group *group)
> +static struct mdev_type *add_mdev_supported_type(struct mdev_parent *parent,
> + struct attribute_group *group)
> {
> struct mdev_type *type;
> int ret;
Reviewed-by: Cornelia Huck
Re: [PATCH] x86/irq: Fix -Wmissing-prototypes warning for init_IRQ()
On Tue, Nov 13, 2018 at 09:56:29AM +0800, Yi Wang wrote: > We get a warning when building kernel with W=1: > arch/x86/kernel/irqinit.c:79:13: warning: no previous prototype for > ‘init_IRQ’ [-Wmissing-prototypes] > void __init init_IRQ(void) > ^ > > Add the missing declaration in head file to fix this. > > Signed-off-by: Yi Wang > --- > arch/x86/include/asm/irq.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h > index 2395bb7..399a9c5 100644 > --- a/arch/x86/include/asm/irq.h > +++ b/arch/x86/include/asm/irq.h > @@ -41,6 +41,8 @@ static inline int irq_canonicalize(int irq) > > extern void init_ISA_irqs(void); > > +extern void __init init_IRQ(void); > + > #ifdef CONFIG_X86_LOCAL_APIC > void arch_trigger_cpumask_backtrace(const struct cpumask *mask, > bool exclude_self); > -- I'm not sure we should do one patch per warning - that's too granulary. What I did earlier was this: make allmodconfig make W=1 arch/x86/kernel/apic/ and then looked at all those -Wmissing-prototypes warnings. Once I've fixed them, I commit the result as a x86/apic: Fix -Wmissing-prototypes warnings and this way it is more or less per subsystem or folder or whatever, which still keeps the amount of patches sane for further handling. Now, I did some fixes here so I'd suggest you do all your patches ontop of tip/master after merging this branch into it: https://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git/log/?h=tip-ras-core I'll push it into tip the next days. Thx. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.
Re: [PATCH] ARM: stm32: debug: add low-level debug support
On 11/13/18 10:24 AM, Russell King - ARM Linux wrote: > On Tue, Nov 13, 2018 at 09:16:16AM +, Bich HEMON wrote: >> >> On 11/12/18 7:22 PM, Olof Johansson wrote: >>> On Thu, Jul 27, 2017 at 04:50:20PM +, Bich HEMON wrote: From: Gerald Baeza This adds low-level debug support on USART1 for STM32F4 and STM32F7. Compiled via 'CONFIG_DEBUG_LL' and 'CONFIG_EARLY_PRINTK'. Enabled via 'earlyprintk' in bootargs. Signed-off-by: Gerald Baeza Signed-off-by: Bich Hemon >>> >>> Hi, >>> >>> This had fallen between the chairs it seems. I have applied it to arm-soc >>> next/soc now, for 4.21 merge window. >>> >>> It ended up being patched up manually to consolidate the version in >>> Russell's patch tracker with this posted version, and I tweaked whitespace >>> a bit. Let me know if I missed something. >>> >>> >>> Thanks, >>> >>> -Olof >>> >> >> Hi Olof, >> >> Please note that this patch has to be abandoned as Ludovic BARRE pushed >> a new version of this change: >> https://patchwork.codeaurora.org/patch/400563/ >> >> You can find it in Russell's tracker here: >> http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8803/1 > > And I'm not going to merge that because: > > 1) it's not for me to merge - it doesn't go through my tree, but through > arm-soc, which Olof and Arnd manage. > 2) it's not been on the mailing list as per normal submission process. > > Sorry. > Ok, thank you for the feedback. So Olof, can you please ignore my previous email and merge my patch as you proposed it for 4.21. Ludovic's patch will be abandoned instead. Thanks, Bich
Re: [GIT PULL] PCI changes for v4.20
On Tue, Nov 13, 2018 at 08:17:12AM +0100, Ingo Molnar wrote: > > * Bjorn Helgaas wrote: > > > PCI changes: > > > > - Pay attention to device-specific _PXM node values (Jonathan Cameron) > > There's a new boot regression, my AMD ThreadRipper system (MSI X399 SLI > PLUS (MS-7B09)) hangs during early bootup, and I have bisected it down to > this commit: > > bad7dcd94f39: ACPI/PCI: Pay attention to device-specific _PXM node values > > Reverting it solves the hang. > > Unfortunately there's no console output when it hangs, even with > earlyprintk. It just hangs after the "loading initrd" line. > > Config is an Ubuntu-ish config with PROVE_LOCKING=y and a few other debug > options. > > All my other testsystems boot fine with similar configs, so it's probably > something specific to this system. Lemme add Tom, he might have an idea. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.
[PATCH v3 3/6] spi: pxa2xx: Add slave mode support
Tested on an OLPC XO-1.75 machine, where the Embedded Controller happens
to be a SPI master.
Signed-off-by: Lubomir Rintel
Acked-by: Pavel Machek
---
drivers/spi/spi-pxa2xx.c | 81 +++---
include/linux/spi/pxa2xx_spi.h | 1 +
2 files changed, 75 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 612cc49db28f..54ae77f1227c 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -626,6 +626,11 @@ static irqreturn_t interrupt_transfer(struct driver_data
*drv_data)
return IRQ_HANDLED;
}
+ if (irq_status & SSSR_TUR) {
+ int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
+ return IRQ_HANDLED;
+ }
+
if (irq_status & SSSR_TINT) {
pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
if (drv_data->read(drv_data)) {
@@ -1073,6 +1078,11 @@ static int pxa2xx_spi_transfer_one(struct spi_controller
*master,
pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
}
+ if (spi_controller_is_slave(master)) {
+ while (drv_data->write(drv_data))
+ ;
+ }
+
/*
* Release the data by enabling service requests and interrupts,
* without changing any mode bits
@@ -1082,6 +1092,27 @@ static int pxa2xx_spi_transfer_one(struct spi_controller
*master,
return 1;
}
+static int pxa2xx_spi_slave_abort(struct spi_master *master)
+{
+ struct driver_data *drv_data = spi_controller_get_devdata(master);
+
+ /* Stop and reset SSP */
+ write_SSSR_CS(drv_data, drv_data->clear_sr);
+ reset_sccr1(drv_data);
+ if (!pxa25x_ssp_comp(drv_data))
+ pxa2xx_spi_write(drv_data, SSTO, 0);
+ pxa2xx_spi_flush(drv_data);
+ pxa2xx_spi_write(drv_data, SSCR0,
+pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
+
+ dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
+
+ drv_data->master->cur_msg->status = -EINTR;
+ spi_finalize_current_transfer(drv_data->master);
+
+ return 0;
+}
+
static void pxa2xx_spi_handle_err(struct spi_controller *master,
struct spi_message *msg)
{
@@ -1209,9 +1240,14 @@ static int setup(struct spi_device *spi)
rx_thres = config->rx_threshold;
break;
default:
- tx_thres = TX_THRESH_DFLT;
tx_hi_thres = 0;
- rx_thres = RX_THRESH_DFLT;
+ if (spi_controller_is_slave(drv_data->master)) {
+ tx_thres = 1;
+ rx_thres = 2;
+ } else {
+ tx_thres = TX_THRESH_DFLT;
+ rx_thres = RX_THRESH_DFLT;
+ }
break;
}
@@ -1255,6 +1291,12 @@ static int setup(struct spi_device *spi)
if (chip_info->enable_loopback)
chip->cr1 = SSCR1_LBM;
}
+ if (spi_controller_is_slave(drv_data->master)) {
+ chip->cr1 |= SSCR1_SCFR;
+ chip->cr1 |= SSCR1_SCLKDIR;
+ chip->cr1 |= SSCR1_SFRMDIR;
+ chip->cr1 |= SSCR1_SPH;
+ }
chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
@@ -1494,6 +1536,13 @@ pxa2xx_spi_init_pdata(struct platform_device *pdev)
}
#endif
+#if CONFIG_OF
+ if (of_id) {
+ pdata->is_slave = of_property_read_bool(pdev->dev.of_node,
+ "spi-slave");
+ }
+#endif
+
ssp->clk = devm_clk_get(&pdev->dev, NULL);
ssp->irq = platform_get_irq(pdev, 0);
ssp->type = type;
@@ -1559,7 +1608,11 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
return -ENODEV;
}
- master = spi_alloc_master(dev, sizeof(struct driver_data));
+ if (platform_info->is_slave)
+ master = spi_alloc_slave(dev, sizeof(struct driver_data));
+ else
+ master = spi_alloc_master(dev, sizeof(struct driver_data));
+
if (!master) {
dev_err(&pdev->dev, "cannot alloc spi_master\n");
pxa_ssp_free(ssp);
@@ -1581,6 +1634,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
master->setup = setup;
master->set_cs = pxa2xx_spi_set_cs;
master->transfer_one = pxa2xx_spi_transfer_one;
+ master->slave_abort = pxa2xx_spi_slave_abort;
master->handle_err = pxa2xx_spi_handle_err;
master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
master->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
@@ -1610,7 +1664,8 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
Re: [PATCH 3/4] drm/v3d: Clean up the reservation object setup.
On Thu, 8 Nov 2018 08:16:53 -0800
Eric Anholt wrote:
> The extra to_v3d_bo() calls came from copying this from the vc4
> driver, which stored the cma gem object in the structs.
>
> Signed-off-by: Eric Anholt
Reviewed-by: Boris Brezillon
> ---
> drivers/gpu/drm/v3d/v3d_gem.c | 32 +++-
> 1 file changed, 11 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c
> index b88c96911453..d0dfdcbbd42c 100644
> --- a/drivers/gpu/drm/v3d/v3d_gem.c
> +++ b/drivers/gpu/drm/v3d/v3d_gem.c
> @@ -214,10 +214,8 @@ v3d_attach_object_fences(struct v3d_exec_info *exec)
> int i;
>
> for (i = 0; i < exec->bo_count; i++) {
> - bo = to_v3d_bo(&exec->bo[i]->base);
> -
> /* XXX: Use shared fences for read-only objects. */
> - reservation_object_add_excl_fence(bo->resv, out_fence);
> + reservation_object_add_excl_fence(exec->bo[i]->resv, out_fence);
> }
> }
>
> @@ -228,11 +226,8 @@ v3d_unlock_bo_reservations(struct drm_device *dev,
> {
> int i;
>
> - for (i = 0; i < exec->bo_count; i++) {
> - struct v3d_bo *bo = to_v3d_bo(&exec->bo[i]->base);
> -
> - ww_mutex_unlock(&bo->resv->lock);
> - }
> + for (i = 0; i < exec->bo_count; i++)
> + ww_mutex_unlock(&exec->bo[i]->resv->lock);
>
> ww_acquire_fini(acquire_ctx);
> }
> @@ -251,13 +246,13 @@ v3d_lock_bo_reservations(struct drm_device *dev,
> {
> int contended_lock = -1;
> int i, ret;
> - struct v3d_bo *bo;
>
> ww_acquire_init(acquire_ctx, &reservation_ww_class);
>
> retry:
> if (contended_lock != -1) {
> - bo = to_v3d_bo(&exec->bo[contended_lock]->base);
> + struct v3d_bo *bo = exec->bo[contended_lock];
> +
> ret = ww_mutex_lock_slow_interruptible(&bo->resv->lock,
> acquire_ctx);
> if (ret) {
> @@ -270,19 +265,16 @@ v3d_lock_bo_reservations(struct drm_device *dev,
> if (i == contended_lock)
> continue;
>
> - bo = to_v3d_bo(&exec->bo[i]->base);
> -
> - ret = ww_mutex_lock_interruptible(&bo->resv->lock, acquire_ctx);
> + ret = ww_mutex_lock_interruptible(&exec->bo[i]->resv->lock,
> + acquire_ctx);
> if (ret) {
> int j;
>
> - for (j = 0; j < i; j++) {
> - bo = to_v3d_bo(&exec->bo[j]->base);
> - ww_mutex_unlock(&bo->resv->lock);
> - }
> + for (j = 0; j < i; j++)
> + ww_mutex_unlock(&exec->bo[j]->resv->lock);
>
> if (contended_lock != -1 && contended_lock >= i) {
> - bo = to_v3d_bo(&exec->bo[contended_lock]->base);
> + struct v3d_bo *bo = exec->bo[contended_lock];
>
> ww_mutex_unlock(&bo->resv->lock);
> }
> @@ -303,9 +295,7 @@ v3d_lock_bo_reservations(struct drm_device *dev,
>* before we commit the CL to the hardware.
>*/
> for (i = 0; i < exec->bo_count; i++) {
> - bo = to_v3d_bo(&exec->bo[i]->base);
> -
> - ret = reservation_object_reserve_shared(bo->resv, 1);
> + ret = reservation_object_reserve_shared(exec->bo[i]->resv, 1);
> if (ret) {
> v3d_unlock_bo_reservations(dev, exec, acquire_ctx);
> return ret;
Re: [PATCH] config: arm: omap2: remove PROVE_LOCKING from defconfig
Hi Tony, On 11/8/18 5:59 PM, Tony Lindgren wrote: > Hi, > > * Lukasz Luba [181009 08:36]: >> PROVE_LOCKING enables LOCKDEP, which causes big overhead on cache and >> bus transactions. >> >> On some ARM big.LITTLE architecutres (Exynos 5433) the overhead is really >> big. >> The overhead can be measures using hackbench which will speed up >> by x3 times (11sec -> 3.4sec). >> When you check transaction on cache or buses, the results are way higher >> than normal for the same hackbench test: >> L1d cache invalidations: 26mln vs 4mln >> L2u cache invalidations: 42mln vs 12mln >> bus cyc/access: 30cyc/access vs. 20cyc/access >> context switch is x3 times cheaper >> >> Enable this option only when you have some locking issue to investigate. > > I'm all for this, but this disables also other less intrusive > debug options. It used to be that we'd get locking issues merged > into drivers and I think that's how it originally got enabled. That's common reason for a few defconfigs in mainline. > > So we should take a look which ones we can or want to keep. > Or just disable CONFIG_DEBUG completely. Ideally, the CI should try a few 'types' of configs, generated based on the 'defconfig'. Some 'smart' script might cut the debug options for an image for performance regression tests. > > For distros, that's multi_v7_defconfig nowadays for most part > so I think most people using omap2plus_defconfig are developers > working on various devices. > > Regards, > > Tony Regards, Lukasz
[PATCH v3 2/6] spi: Deal with slaves that return from transfer_one() unfinished
Some drivers, such as spi-pxa2xx return from the transfer_one callback
immediately, idicating that the transfer will be finished asynchronously.
Normally, spi_transfer_one_message() synchronously waits for the
transfer to finish with wait_for_completion_timeout(). For slaves, we
don't want the transaction to time out as it can complete in a long time
in future. Use wait_for_completion_interruptible() instead.
Signed-off-by: Lubomir Rintel
Acked-by: Pavel Machek
---
Changed since v2:
- Corrected the spi_transfer_wait() return value handling to avoid early
bail out without the necessary cleanup (thanks Geert Uytterhoeven)
drivers/spi/spi.c | 62 +--
1 file changed, 39 insertions(+), 23 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 6ca59406b0b7..498d3b9bf3ae 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1037,6 +1037,42 @@ static int spi_map_msg(struct spi_controller *ctlr,
struct spi_message *msg)
return __spi_map_msg(ctlr, msg);
}
+static int spi_transfer_wait(struct spi_controller *ctlr,
+struct spi_message *msg,
+struct spi_transfer *xfer)
+{
+ struct spi_statistics *statm = &ctlr->statistics;
+ struct spi_statistics *stats = &msg->spi->statistics;
+ unsigned long long ms = 1;
+
+ if (spi_controller_is_slave(ctlr)) {
+ if (wait_for_completion_interruptible(&ctlr->xfer_completion)) {
+ dev_dbg(&msg->spi->dev, "SPI transfer interrupted\n");
+ return -EINTR;
+ }
+ } else {
+ ms = 8LL * 1000LL * xfer->len;
+ do_div(ms, xfer->speed_hz);
+ ms += ms + 200; /* some tolerance */
+
+ if (ms > UINT_MAX)
+ ms = UINT_MAX;
+
+ ms = wait_for_completion_timeout(&ctlr->xfer_completion,
+msecs_to_jiffies(ms));
+
+ if (ms == 0) {
+ SPI_STATISTICS_INCREMENT_FIELD(statm, timedout);
+ SPI_STATISTICS_INCREMENT_FIELD(stats, timedout);
+ dev_err(&msg->spi->dev,
+ "SPI transfer timed out\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
/*
* spi_transfer_one_message - Default implementation of transfer_one_message()
*
@@ -1050,7 +1086,6 @@ static int spi_transfer_one_message(struct spi_controller
*ctlr,
struct spi_transfer *xfer;
bool keep_cs = false;
int ret = 0;
- unsigned long long ms = 1;
struct spi_statistics *statm = &ctlr->statistics;
struct spi_statistics *stats = &msg->spi->statistics;
@@ -1079,28 +1114,9 @@ static int spi_transfer_one_message(struct
spi_controller *ctlr,
goto out;
}
- if (ret > 0) {
- ret = 0;
- ms = 8LL * 1000LL * xfer->len;
- do_div(ms, xfer->speed_hz);
- ms += ms + 200; /* some tolerance */
-
- if (ms > UINT_MAX)
- ms = UINT_MAX;
-
- ms =
wait_for_completion_timeout(&ctlr->xfer_completion,
-
msecs_to_jiffies(ms));
- }
-
- if (ms == 0) {
- SPI_STATISTICS_INCREMENT_FIELD(statm,
- timedout);
- SPI_STATISTICS_INCREMENT_FIELD(stats,
- timedout);
- dev_err(&msg->spi->dev,
- "SPI transfer timed out\n");
- msg->status = -ETIMEDOUT;
- }
+ ret = spi_transfer_wait(ctlr, msg, xfer);
+ if (ret < 0)
+ msg->status = ret;
} else {
if (xfer->len)
dev_err(&msg->spi->dev,
--
2.19.1
[PATCH v3 4/6] spi: pxa2xx: dt-bindings: Add ready GPIO signal
This this is used to let the SPI master know that our FIFO is filled and we're ready to service a transfer. Only useful in slave mode. A signal like this is used by an embedded controller on a OLPC XO 1.75 machine, that happens to be a SPI master. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek --- Changes since v2: - s/ready-gpio/ready-gpios/ - Updated the subject line to conform with subsystem customs Documentation/devicetree/bindings/spi/spi-pxa2xx.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt index 89b2832283e3..e30e0c2a4bce 100644 --- a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt +++ b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt @@ -12,6 +12,8 @@ Optional properties: - cs-gpios: list of GPIO chip selects. See the SPI bus bindings, Documentation/devicetree/bindings/spi/spi-bus.txt - spi-slave: Empty property indicating the SPI controller is used in slave mode. +- ready-gpios: GPIO used to signal a SPI master that the FIFO is filled + and we're ready to service a transfer. Only useful in slave mode. Child nodes represent devices on the SPI bus See ../spi/spi-bus.txt -- 2.19.1
[PATCH v3 6/6] spi: pxa2xx: Deal with the leftover garbage in TXFIFO
There doesn't seem to be a way to empty TXFIFO on MMP2. The datasheet is
super-secret and the method described in Armada 16x manual won't work:
"The TXFIFO and RXFIFO are cleared to 0b0 when the SSPx port is reset or
disabled (by writing a 0b0 to the field
in the SSP Control Register 0)."
# devmem 0xd4037008 # read SSSR
0xF204
# devmem 0xd4037000 32 0x07 # SSE off in SSCR0
# devmem 0xd4037000 32 0x87 # SSE on
# devmem 0xd4037008
0xF204
^ TXFIFO level is still 2. Sigh.
The OLPC 1.75 boot firmware leaves two bytes in the TXFIFO. Those are
basically throwaway bytes used in response to the messages from the EC.
The OLPC kernel copes with this by power-cycling the hardware. Perhaps
the firmware should do this instead.
Other than that, there's not much we can do other than complain loudly
until the garbage gets drained and discard the actual data... For the
OLPC EC this will work just fine and pushing more data to TXFIFO would
break further transactions.
Signed-off-by: Lubomir Rintel
Acked-by: Pavel Machek
---
Changes since v1:
- Fixed a commit message typo (spotted by James Cameron)
drivers/spi/spi-pxa2xx.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 7e5aab0af501..29e6025f104c 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1078,6 +1078,20 @@ static int pxa2xx_spi_transfer_one(struct spi_controller
*master,
pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
}
+ if (drv_data->ssp_type == MMP2_SSP) {
+ u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
+ & SSSR_TFL_MASK) >> 8;
+
+ if (tx_level) {
+ /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
+ dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
+ tx_level);
+ if (tx_level > transfer->len)
+ tx_level = transfer->len;
+ drv_data->tx += tx_level;
+ }
+ }
+
if (spi_controller_is_slave(master)) {
while (drv_data->write(drv_data))
;
--
2.19.1
[PATCH v3 5/6] spi: pxa2xx: Add ready signal
Strobe a GPIO line when the slave TX FIFO is filled. This is how the
Embedded Controller on an OLPC XO-1.75 machine, that happens to be a SPI
master, learns that it can initiate a transaction.
Signed-off-by: Lubomir Rintel
Tested-by: Pavel Machek
---
Changes since v2
- Avoid an useless delay if there's no ready GPIO
- Remove useless (int)PTR_ERR(...) casts from pxa2xx_spi_probe()
(thanks to Geert Uytterhoeven)
drivers/spi/spi-pxa2xx.c | 16 +++-
drivers/spi/spi-pxa2xx.h | 3 +++
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 54ae77f1227c..7e5aab0af501 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1081,6 +1081,11 @@ static int pxa2xx_spi_transfer_one(struct spi_controller
*master,
if (spi_controller_is_slave(master)) {
while (drv_data->write(drv_data))
;
+ if (drv_data->gpiod_ready) {
+ gpiod_set_value(drv_data->gpiod_ready, 1);
+ udelay(1);
+ gpiod_set_value(drv_data->gpiod_ready, 0);
+ }
}
/*
@@ -1778,7 +1783,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
if (PTR_ERR(gpiod) == -ENOENT)
continue;
- status = (int)PTR_ERR(gpiod);
+ status = PTR_ERR(gpiod);
goto out_error_clock_enabled;
} else {
drv_data->cs_gpiods[i] = gpiod;
@@ -1786,6 +1791,15 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
}
}
+ if (platform_info->is_slave) {
+ drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
+ "ready", GPIOD_OUT_LOW);
+ if (IS_ERR(drv_data->gpiod_ready)) {
+ status = PTR_ERR(drv_data->gpiod_ready);
+ goto out_error_clock_enabled;
+ }
+ }
+
pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h
index 513c53aaeab2..4e324da66ef7 100644
--- a/drivers/spi/spi-pxa2xx.h
+++ b/drivers/spi/spi-pxa2xx.h
@@ -64,6 +64,9 @@ struct driver_data {
/* GPIOs for chip selects */
struct gpio_desc **cs_gpiods;
+
+ /* Optional slave FIFO ready signal */
+ struct gpio_desc *gpiod_ready;
};
struct chip_data {
--
2.19.1
[PATCH v3 0/6] spi: pxa2xx: add slave mode support
Hello, this patch set adds slave mode support to pxa2xx. The objective is that it will be able to support the OLPC XO 1.75 embedded controller that is a SPI master talking to a MMP2 SOC with an extra "ready" signal for handshaking. The patches have been submitted previously along with DT support for the controller which has already been accepted, hence the "v3". These are the remaining ones. Reviewed/Ack-ed by tags have been collected. Other changes to the pataches are described in the respective messages. The EC driver itself is being reviewed in a separate patch set. Verified on a OLPC XO 1.75 machine. Thanks to everyone who kindly provided feedback to make the patch set better. Thank you, Lubo
[PATCH v3 1/6] spi: pxa2xx: dt-bindings: Add spi-slave property
This is used to indicate that the chip attached to this controller is a SPI master. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring Acked-by: Pavel Machek --- Changes since v2: - Updated the subject line to conform with subsystem customs Documentation/devicetree/bindings/spi/spi-pxa2xx.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt index 0335a9bd2e8a..89b2832283e3 100644 --- a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt +++ b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt @@ -11,6 +11,7 @@ Required properties: Optional properties: - cs-gpios: list of GPIO chip selects. See the SPI bus bindings, Documentation/devicetree/bindings/spi/spi-bus.txt +- spi-slave: Empty property indicating the SPI controller is used in slave mode. Child nodes represent devices on the SPI bus See ../spi/spi-bus.txt -- 2.19.1
RE: [RFC PATCH v2 1/2] x86/fpu: detect AVX task
From: Li, Aubrey > Sent: 12 November 2018 01:41 ... > VZEROUPPER instruction resets the init state. If context switch happens > to occur exactly after VZEROUPPER instruction, XINUSE bitmap is empty(all > zeros), which indicates the task is not using AVX. That's why the state > decay count is used here. Isn't there an obvious optimisation to execute VZEROALL during system call entry? If that is done does any of this actually work? David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
Re: [PATCH] fork: Fix two -Wmissing-prototypes warnings
On 13/11/2018 08.26, Yi Wang wrote: > We get two warning when building kernel with W=1: > kernel/fork.c:167:13: warning: no previous prototype for > ‘arch_release_thread_stack’ [-Wmissing-prototypes] > kernel/fork.c:779:13: warning: no previous prototype for ‘fork_init’ > [-Wmissing-prototypes] I think you should also remove the "manual" declarations from the .c files that call the function, in this case fork_init() in init/main.c; otherwise there's no guarantee that those translation units actually include the header that contain the proper declaration. arch_release_thread_stack can probably just be removed completely after the recent arch cleanup, since bb9d81264 (arch: remove tile port) no arch seems to implement it. Rasmus
Re: [PATCH 1/2] exec: load_script: don't blindly truncate shebang string
On Mon 12-11-18 17:09:31, Oleg Nesterov wrote:
> load_script() simply truncates bprm->buf and this is very wrong if the
> length of shebang string exceeds BINPRM_BUF_SIZE-2. This can silently
> truncate i_arg or (worse) we can execute the wrong binary if buf[2:126]
> happens to be the valid executable path.
>
> Change load_script() to return ENOEXEC if it can't find '\n' or zero in
> bprm->buf. Note that '\0' can come from either prepare_binprm()->memset()
> or from kernel_read(), we do not care.
>
> Signed-off-by: Oleg Nesterov
A bit cryptic to my taste but it looks correct. I have tried to come up
with something more tasty but I am afraid it would be just a matter of
taste.
Acked-by: Michal Hocko
> ---
> fs/binfmt_script.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/fs/binfmt_script.c b/fs/binfmt_script.c
> index 7cde3f4..d0078cb 100644
> --- a/fs/binfmt_script.c
> +++ b/fs/binfmt_script.c
> @@ -42,10 +42,14 @@ static int load_script(struct linux_binprm *bprm)
> fput(bprm->file);
> bprm->file = NULL;
>
> - bprm->buf[BINPRM_BUF_SIZE - 1] = '\0';
> - if ((cp = strchr(bprm->buf, '\n')) == NULL)
> - cp = bprm->buf+BINPRM_BUF_SIZE-1;
> + for (cp = bprm->buf+2;; cp++) {
> + if (cp >= bprm->buf + BINPRM_BUF_SIZE)
> + return -ENOEXEC;
> + if (!*cp || (*cp == '\n'))
> + break;
> + }
> *cp = '\0';
> +
> while (cp > bprm->buf) {
> cp--;
> if ((*cp == ' ') || (*cp == '\t'))
> --
> 2.5.0
>
>
--
Michal Hocko
SUSE Labs
Re: [PATCH] media: videobuf2-core: Fix error handling when fileio is deallocated
Hi Myungho,
On 2018-11-12 01:49, Myungho Jung wrote:
> The mutex that is held from vb2_fop_read() can be unlocked while waiting
> for a buffer if the queue is streaming and blocking. Meanwhile, fileio
> can be released. So, it should return an error if the fileio address is
> changed.
>
> Signed-off-by: Myungho Jung
> Reported-by: syzbot+4180ff9ca6810b06c...@syzkaller.appspotmail.com
Acked-by: Marek Szyprowski
Thanks for analyzing the code and fixing this issue!
> ---
> drivers/media/common/videobuf2/videobuf2-core.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/media/common/videobuf2/videobuf2-core.c
> b/drivers/media/common/videobuf2/videobuf2-core.c
> index 975ff5669f72..bff94752eb27 100644
> --- a/drivers/media/common/videobuf2/videobuf2-core.c
> +++ b/drivers/media/common/videobuf2/videobuf2-core.c
> @@ -2564,6 +2564,10 @@ static size_t __vb2_perform_fileio(struct vb2_queue
> *q, char __user *data, size_
> dprintk(5, "vb2_dqbuf result: %d\n", ret);
> if (ret)
> return ret;
> + if (fileio != q->fileio) {
> + dprintk(3, "fileio deallocated\n");
> + return -EFAULT;
> + }
> fileio->dq_count += 1;
>
> fileio->cur_index = index;
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
Re: [PATCH v3 1/6] spi: pxa2xx: dt-bindings: Add spi-slave property
On Tue, Nov 13, 2018 at 11:23 AM Lubomir Rintel wrote:
> This is used to indicate that the chip attached to this controller is a SPI
> master.
>
> Signed-off-by: Lubomir Rintel
> Reviewed-by: Rob Herring
> Acked-by: Pavel Machek
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [BUG] Nuvoton NCPT650 TPM 2.0 mode not working
On Sun, Nov 11, 2018 at 06:55:36PM +0100, Michael Niewöhner wrote: > Hi all, > > Nuvoton NCPT650 does not work in TPM 2.0 mode with tpm_tis / tpm_i2c_nuvoton > while it works in TPM 1.2 mode (I can reflash it via UEFI setup). > Kernel version is 4.19.1 Can you check what ACPI dump would show up [1]? [1] acpidump > acpidump.out /Jarkko
Re: [PATCH 2/2] exec: increase BINPRM_BUF_SIZE to 256
On Mon 12-11-18 17:09:56, Oleg Nesterov wrote: > Large enterprise clients often times run applications out of networked > file systems where the IT mandated layout of project volumes can end up > leading to paths that are longer than 128 characters. Bumping this up to > the next order of two solves this problem in all but the most egregious > case while still fitting into a 512b slab. > > Reported-by: Ben Woodard > Signed-off-by: Oleg Nesterov Acked-by: Michal Hocko Increasing it to a larger value wouldn't hurt but I wouldn't bind it to the page size because the layout might change and result in higher order request. > --- > include/uapi/linux/binfmts.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/uapi/linux/binfmts.h b/include/uapi/linux/binfmts.h > index 4abad03..689025d 100644 > --- a/include/uapi/linux/binfmts.h > +++ b/include/uapi/linux/binfmts.h > @@ -16,6 +16,6 @@ struct pt_regs; > #define MAX_ARG_STRINGS 0x7FFF > > /* sizeof(linux_binprm->buf) */ > -#define BINPRM_BUF_SIZE 128 > +#define BINPRM_BUF_SIZE 256 > > #endif /* _UAPI_LINUX_BINFMTS_H */ > -- > 2.5.0 > > -- Michal Hocko SUSE Labs
Re: [PATCH v3 4/6] spi: pxa2xx: dt-bindings: Add ready GPIO signal
On Tue, Nov 13, 2018 at 11:23 AM Lubomir Rintel wrote:
> This this is used to let the SPI master know that our FIFO is filled and
> we're ready to service a transfer. Only useful in slave mode.
>
> A signal like this is used by an embedded controller on a OLPC XO 1.75
> machine, that happens to be a SPI master.
>
> Signed-off-by: Lubomir Rintel
> Acked-by: Pavel Machek
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 5/6] spi: pxa2xx: Add ready signal
On Tue, Nov 13, 2018 at 11:23 AM Lubomir Rintel wrote:
> Strobe a GPIO line when the slave TX FIFO is filled. This is how the
> Embedded Controller on an OLPC XO-1.75 machine, that happens to be a SPI
> master, learns that it can initiate a transaction.
>
> Signed-off-by: Lubomir Rintel
> Tested-by: Pavel Machek
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 2/6] spi: Deal with slaves that return from transfer_one() unfinished
On Tue, Nov 13, 2018 at 11:23 AM Lubomir Rintel wrote:
> Some drivers, such as spi-pxa2xx return from the transfer_one callback
> immediately, idicating that the transfer will be finished asynchronously.
>
> Normally, spi_transfer_one_message() synchronously waits for the
> transfer to finish with wait_for_completion_timeout(). For slaves, we
> don't want the transaction to time out as it can complete in a long time
> in future. Use wait_for_completion_interruptible() instead.
>
> Signed-off-by: Lubomir Rintel
> Acked-by: Pavel Machek
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 1/5] dt-bindings: media: Add Allwinner A10 CSI binding
Hi Maxime, On Tue, Nov 13, 2018 at 09:24:13AM +0100, Maxime Ripard wrote: > The Allwinner A10 CMOS Sensor Interface is a camera capture interface also ... > +Optional properties: > + - allwinner,csi-channels: Number of channels available in the CSI > +controller. If not present, the default > +will be 1. Is this virtual channels or something else btw.? -- Sakari Ailus sakari.ai...@linux.intel.com
Re: KASAN: use-after-free Read in locks_delete_block
On Mon, 2018-11-12 at 12:34 -0800, syzbot wrote: > Hello, > > syzbot found the following crash on: > > HEAD commit:442b8cea2477 Add linux-next specific files for 20181109 > git tree: linux-next > console output: https://syzkaller.appspot.com/x/log.txt?x=115dbad540 > kernel config: https://syzkaller.appspot.com/x/.config?x=2f72bdb11df9fbe8 > dashboard link: https://syzkaller.appspot.com/bug?extid=a4a3d526b4157113ec6a > compiler: gcc (GCC) 8.0.1 20180413 (experimental) > > Unfortunately, I don't have any reproducer for this crash yet. > > IMPORTANT: if you fix the bug, please add the following tag to the commit: > Reported-by: syzbot+a4a3d526b4157113e...@syzkaller.appspotmail.com > > device loop0 blocksize: 4096 > __find_get_block_slow() failed. block=1, b_blocknr=8 > b_state=0x0029, b_size=512 > device loop0 blocksize: 4096 > == > BUG: KASAN: use-after-free in __list_del_entry_valid+0xf1/0x100 > lib/list_debug.c:51 > Read of size 8 at addr 88017eb47b70 by task syz-executor3/13461 > > CPU: 0 PID: 13461 Comm: syz-executor3 Not tainted 4.20.0-rc1-next-20181109+ > #110 > Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS > Google 01/01/2011 > Call Trace: > __dump_stack lib/dump_stack.c:77 [inline] > dump_stack+0x244/0x39d lib/dump_stack.c:113 > print_address_description.cold.7+0x9/0x1ff mm/kasan/report.c:256 > kasan_report_error mm/kasan/report.c:354 [inline] > kasan_report.cold.8+0x242/0x309 mm/kasan/report.c:412 > __asan_report_load8_noabort+0x14/0x20 mm/kasan/report.c:433 > __list_del_entry_valid+0xf1/0x100 lib/list_debug.c:51 > __list_del_entry include/linux/list.h:117 [inline] > list_del_init include/linux/list.h:159 [inline] > __locks_delete_block fs/locks.c:683 [inline] > locks_delete_block+0xce/0x3d0 fs/locks.c:716 > locks_mandatory_area+0x48b/0x6a0 fs/locks.c:1398 > rw_verify_area+0x2f2/0x360 fs/read_write.c:386 > vfs_write+0x149/0x560 fs/read_write.c:544 > ksys_write+0x101/0x260 fs/read_write.c:598 > __do_sys_write fs/read_write.c:610 [inline] > __se_sys_write fs/read_write.c:607 [inline] > __x64_sys_write+0x73/0xb0 fs/read_write.c:607 > do_syscall_64+0x1b9/0x820 arch/x86/entry/common.c:290 > entry_SYSCALL_64_after_hwframe+0x49/0xbe > RIP: 0033:0x457569 > Code: fd b3 fb ff c3 66 2e 0f 1f 84 00 00 00 00 00 66 90 48 89 f8 48 89 f7 > 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff > ff 0f 83 cb b3 fb ff c3 66 2e 0f 1f 84 00 00 00 00 > RSP: 002b:7ff2e8194c78 EFLAGS: 0246 ORIG_RAX: 0001 > RAX: ffda RBX: 0003 RCX: 00457569 > RDX: 0010 RSI: 2180 RDI: 0006 > RBP: 0072c0e0 R08: R09: > R10: R11: 0246 R12: 7ff2e81956d4 > R13: 004c571f R14: 004d9360 R15: > > The buggy address belongs to the page: > page:ea0005fad1c0 count:0 mapcount:0 mapping: index:0x0 > flags: 0x2fffc00() > raw: 02fffc00 ea0005fad1c8 > raw: > page dumped because: kasan: bad access detected > > Memory state around the buggy address: > 88017eb47a00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff > 88017eb47a80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff > > 88017eb47b00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff > > ^ > 88017eb47b80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff > 88017eb47c00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff > == > Ouch, crash down in the mandatory locking code. This is with Neil's set from last week. I haven't merged the series he sent the other day yet, but they don't seem to be different in this regard. Looks like the fl_blocked list might have had an entry on it that was freed without being removed? locks_mandatory_area declares a file_lock on the stack, but it seems to be initialized properly. The one weird thing is that locks_mandatory_area sets FL_ACCESS and FL_SLEEP, but I don't see anything wrong with that right offhand. Neil, any thoughts? -- Jeff Layton
Re: [PATCH 2/3] pinctrl: stm32: protect configuration registers with a hwspinlock
Hi Benjamin
On 11/13/18 10:51 AM, Benjamin Gaignard wrote:
If a hwspinlock if defined in device tree use it to protect
configuration registers.
Signed-off-by: Benjamin Gaignard
---
drivers/pinctrl/stm32/pinctrl-stm32.c | 71 ++-
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index a9bec6e6fdd1..dce9dabaf4d5 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -8,6 +8,7 @@
Acked-by: Alexandre TORGUE
*/
#include
#include
+#include
#include
#include
#include
@@ -51,6 +52,8 @@
#define gpio_range_to_bank(chip) \
container_of(chip, struct stm32_gpio_bank, range)
+#define HWSPINLOCK_TIMEOUT 5 /* msec */
+
static const char * const stm32_gpio_functions[] = {
"gpio", "af0", "af1",
"af2", "af3", "af4",
@@ -91,6 +94,7 @@ struct stm32_pinctrl {
struct irq_domain *domain;
struct regmap *regmap;
struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
+ struct hwspinlock *hwlock;
};
static inline int stm32_gpio_pin(int gpio)
@@ -576,14 +580,24 @@ static int stm32_pmx_get_func_groups(struct pinctrl_dev
*pctldev,
static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
int pin, u32 mode, u32 alt)
{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
u32 val;
int alt_shift = (pin % 8) * 4;
int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
unsigned long flags;
+ int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock)
+ err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
+
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+
val = readl_relaxed(bank->base + alt_offset);
val &= ~GENMASK(alt_shift + 3, alt_shift);
val |= (alt << alt_shift);
@@ -594,6 +608,10 @@ static void stm32_pmx_set_mode(struct stm32_gpio_bank
*bank,
val |= mode << (pin * 2);
writel_relaxed(val, bank->base + STM32_GPIO_MODER);
+ if (pctl->hwlock)
+ hwspin_unlock(pctl->hwlock);
+
+unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@@ -683,17 +701,31 @@ static const struct pinmux_ops stm32_pmx_ops = {
static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
unsigned offset, u32 drive)
{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
+ int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock)
+ err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
+
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+
val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
val &= ~BIT(offset);
val |= drive << offset;
writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
+ if (pctl->hwlock)
+ hwspin_unlock(pctl->hwlock);
+
+unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@@ -719,17 +751,31 @@ static u32 stm32_pconf_get_driving(struct stm32_gpio_bank
*bank,
static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
unsigned offset, u32 speed)
{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
+ int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock)
+ err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
+
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+
val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
val &= ~GENMASK(offset * 2 + 1, offset * 2);
val |= speed << (offset * 2);
writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
+ if (pctl->hwlock)
+ hwspin_unlock(pctl->hwlock);
+
+unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@@ -755,17 +801,31 @@ static u32 stm32_pconf_get_speed(struct stm32_gpio_bank
*bank,
static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
unsigned offset, u32 bias)
{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
+ int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock)
+ err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
+
+ if (err) {
+
Re: [PATCH RFC] hist lookups
On Sun, Nov 11, 2018 at 03:32:59PM -0800, David Miller wrote: > From: Jiri Olsa > Date: Mon, 12 Nov 2018 00:26:27 +0100 > > > On Sun, Nov 11, 2018 at 03:08:01PM -0800, David Miller wrote: > >> From: Jiri Olsa > >> Date: Sun, 11 Nov 2018 20:41:32 +0100 > >> > >> > On Thu, Nov 08, 2018 at 05:07:21PM -0800, David Miller wrote: > >> >> From: Jiri Olsa > >> >> Date: Thu, 8 Nov 2018 08:13:03 +0100 > >> >> > >> >> > we could separated fork/mmaps to separate dummy event map, or just > >> >> > parse them out in the read thread and create special queue for them > >> >> > and drop just samples in case we are behind > >> >> > >> >> What you say at the end here is basically what I am proposing. > >> >> > >> >> Perf dequeues events from mmap ring as fast as possible. > >> >> > >> >> Perf has two internal queues, high priority and low priority. > >> >> > >> >> High priority events are never dropped. > >> >> > >> >> Low priority events are dropped on overload, oldest first. > >> > > >> > I added the dropping logic, it's simple so far.. > >> > >> So for me perf top gets into a state where the samples counter stops > >> incrementing, but the event counter does keep moving (which is the > >> histogram code decaying histogram entries from the display thread). > >> > >> Which means the event processing has basically stopped. > >> > >> The event threads are not stuck in a loop, because they respond to > >> the "q" keypress and we can exit. > > > > is the drop count showing something? > > It does soon after starting up, then it drops to zero. ok I see it on ~200 cpu server now.. we actuly spawn the UI message box in the reader thread and wait for user to press a key with some timeout.. which is not good ;-) I removed that and add it to bottom line notification line instead and now under heave load I can see lines updates together with events being lost/drop I also changed the lost/drop counts format to: lost: current/total where current is the count within the refresh period and total is overall counts I pushed/rebased what I have to perf/fixes branch again please note I had to change our compile changes, because they wouldn't compile on x86, but I can't verify on sparc, so you might see some compile fails again jirka
Re: [PATCH 00/12 v5] locks: avoid thundering-herd wake-ups
On Mon, 2018-11-12 at 12:14 +1100, NeilBrown wrote: > Changes: > - field names improved as requested by Bruce. >"fl_blocked_requests" is a list of blocked requests, >linked through fl_block_member > - the introductory text has been moved to a commit comment >as suggested by Bruce > - documentation added to locks.c as suggested by Bruce - I made >a few little changes > - flock_make_lock() now properly initialized a lock - using >the code from Jeff > - code actually compiles for ocfs2 and gfs2 > > Thanks, > NeilBrown > > > --- > > NeilBrown (12): > fs/locks: rename some lists and pointers. > fs/locks: split out __locks_wake_up_blocks(). > NFS: use locks_copy_lock() to copy locks. > gfs2: properly initial file_lock used for unlock. > ocfs2: properly initial file_lock used for unlock. > locks: use properly initialized file_lock when unlocking. > fs/locks: allow a lock request to block other requests. > fs/locks: always delete_block after waiting. > fs/locks: change all *_conflict() functions to return bool. > fs/locks: create a tree of dependent requests. > locks: merge posix_unblock_lock() and locks_delete_block() > VFS: locks: remove unnecessary white space. > > > fs/cifs/file.c |4 > fs/gfs2/file.c | 10 + > fs/lockd/svclock.c |2 > fs/locks.c | 319 > --- > fs/nfs/nfs4proc.c |6 - > fs/nfsd/nfs4state.c |6 - > fs/ocfs2/locks.c| 10 + > include/linux/fs.h | 13 +- > include/trace/events/filelock.h | 16 +- > 9 files changed, 230 insertions(+), 156 deletions(-) > > -- > Signature > Thanks Neil, I'll pull this into locks-next. I also went ahead and fixed up the comment that Bruce pointed out. -- Jeff Layton
[PATCH 1/1] ACPI / tables: add DSDT AmlCode new declaration name support
The new naming rule is added in acpica version 20180427.
So the dsdt aml code name changes from "AmlCode" to "dsdt_aml_code".
The patch that introduces naming rules is:
https://github.com/acpica/acpica/commit/f9a88a4c1cd020b6a5475d63b29626852a0b5f37
Tested:
ACPICA release version 20180427+.
ARM64: QCOM QDF2400
GCC: 4.8.5 20150623
Signed-off-by: Wang Dongsheng
---
drivers/acpi/Kconfig | 2 +-
drivers/acpi/tables.c | 10 --
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index 9705fc986da9..15ab53a52fdc 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -336,7 +336,7 @@ config ACPI_CUSTOM_DSDT_FILE
See Documentation/acpi/dsdt-override.txt
Enter the full path name to the file which includes the AmlCode
- declaration.
+ or dsdt_aml_code declaration.
If unsure, don't enter a file name.
diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c
index a3d012b08fc5..297020bbaade 100644
--- a/drivers/acpi/tables.c
+++ b/drivers/acpi/tables.c
@@ -713,6 +713,9 @@ acpi_os_physical_table_override(struct acpi_table_header
*existing_table,
table_length);
}
+static void *amlcode __attribute__ ((weakref("AmlCode")));
+static void *dsdt_amlcode __attribute__ ((weakref("dsdt_aml_code")));
+
acpi_status
acpi_os_table_override(struct acpi_table_header *existing_table,
struct acpi_table_header **new_table)
@@ -723,8 +726,11 @@ acpi_os_table_override(struct acpi_table_header
*existing_table,
*new_table = NULL;
#ifdef CONFIG_ACPI_CUSTOM_DSDT
- if (strncmp(existing_table->signature, "DSDT", 4) == 0)
- *new_table = (struct acpi_table_header *)AmlCode;
+ if (!strncmp(existing_table->signature, "DSDT", 4)) {
+ *new_table = (struct acpi_table_header *)&amlcode;
+ if (!(*new_table))
+ *new_table = (struct acpi_table_header *)&dsdt_amlcode;
+ }
#endif
if (*new_table != NULL)
acpi_table_taint(existing_table);
--
2.18.0
Re: [BUG] Nuvoton NCPT650 TPM 2.0 mode not working
On Sun, Nov 11, 2018 at 10:11:33PM +0100, Michael Niewöhner wrote: > Very strange... When I pull the power cord, then replug and boot, I get these > dmesg messages: > [0.00] efi: ACPI > 2.0=0x9ea78000 ACPI=0x9ea78000 SMBIOS=0x9f5e5000 SMBIOS > 3.0=0x9f5e4000 MPS=0xfca00 ESRT=0x9c06e918 MEMATTR=0x99cb9018 > TPMEventLog=0x > 98d0c018 > [0.001794] ACPI: TPM2 0x9EAB1F70 34 (v03 LENOVO TC- > S06 1260 AMI ) > [3.096587] tpm_tis MSFT0101:00: 2.0 TPM (device-id 0xFE, rev-id 2) > [3.105684] tpm tpm0: A TPM error (2314) occurred attempting the self test > > After a reboot I get those "ima: ..." message again. Pulling the plug seems to > reset anything (the TPM). > > The PTT TPM 2.0 shows exactly the same behaviour. The error in question is TPM_RC_TESTING i.e. TPM is still processing selftests in the background. It is clearly a regression but unfortanely it is harmless and unrelated i.e. tpm2_do_selftest() should not print an error message because it is legit behavior. The function actually masks the whole error: if (rc == TPM2_RC_TESTING) rc = TPM2_RC_SUCCESS; /Jarkko
[PATCH] pinctrl: meson: fix pull enable register calculation
We just changed the code so we apply bias disable on the correct
register but forgot to align the register calculation. The result
is that we apply the change on the correct register, but possibly
at the incorrect offset/bit
This went undetected because offsets tends to be the same between
REG_PULL and REG_PULLEN for a given pin the EE controller. This
is not true for the AO controller.
Fixes: e39f9dd8206a ("pinctrl: meson: fix pinconf bias disable")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c
b/drivers/pinctrl/meson/pinctrl-meson.c
index 53d449076dee..ea87d739f534 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -191,7 +191,8 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev,
unsigned int pin,
case PIN_CONFIG_BIAS_DISABLE:
dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
- meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
+ meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®,
+ &bit);
ret = regmap_update_bits(pc->reg_pullen, reg,
BIT(bit), 0);
if (ret)
--
2.19.1
Re: [PATCH RESEND] UAPI: move RENAME_* definitions to separated file
* Yury Norov: > diff --git a/include/uapi/linux/fs.h b/include/uapi/linux/fs.h > index 53a22e8e0408..dbf58bbf5bad 100644 > --- a/include/uapi/linux/fs.h > +++ b/include/uapi/linux/fs.h Could you move it to a dedicated header? Or add a comment that the header is only for rename flags? Then we can change glibc to include it if it is present and when compiling under _GNU_SOURCE. Thanks, Florian
Re: [PATCH v5 16/17] tpm: take TPM chip power gating out of tpm_transmit()
On Fri, Nov 09, 2018 at 09:37:48PM +, Winkler, Tomas wrote: > > On Thu, Nov 08, 2018 at 06:38:59PM +, Winkler, Tomas wrote: > > > > Call tpm_chip_start() and tpm_chip_stop() in > > > > > > > > * tpm_try_get_ops() and tpm_put_ops() > > > > * tpm_chip_register() > > > > * tpm2_del_space() > > > > > > > > And remove these calls from tpm_transmit(). The core reason for this > > > > change is that in tpm_vtpm_proxy a locality change requires a > > > > virtual TPM command (a command made up just for that driver). > > > > > > > I don't think you can do that, locality has to be request for each > > > command, as for example tboot can request higher locality any time. > > > > That could be a potential problem. How tboot intervention gets prevented > > without this patch? > As it was said, need to request locality and relinquish it for each > command, I believe thought this is not required for client platforms > only for servers. And what I'm trying to under is why so. If the intervention can happen at any time that would imply that even if you would request and relinquish locality for a single TPM command, the intervention could happen in the middle. That is why I'm asking why without this patch things are just fine. /Jarkko
Re: [PATCH v4 3/6] mfd: lochnagar: Add initial binding documentation
On Tue, Nov 13, 2018 at 08:28:25AM +, Lee Jones wrote: > On Thu, 08 Nov 2018, Charles Keepax wrote: > > > Lochnagar is an evaluation and development board for Cirrus > > Logic Smart CODEC and Amp devices. It allows the connection of > > most Cirrus Logic devices on mini-cards, as well as allowing > > connection of various application processor systems to provide a > > full evaluation platform. This driver supports the board > > controller chip on the Lochnagar board. > > > > Signed-off-by: Charles Keepax > > --- > > > > I have dropped Rob and Stephen's Acks from this patch on > > account of the scale of the changes since v3. > > > > Changes since v3: > > - Split the binding up into separate parts for the individual subsystems > > - Added documentation for the fixed clocks that are done through DT > > > > Thanks, > > Charles > > > > .../devicetree/bindings/clock/cirrus,lochnagar.txt | 89 + > > .../devicetree/bindings/mfd/cirrus,lochnagar.txt | 70 ++ > > I think these should all be seperate patches. > I will need to do a respin for the regulator changes anyway so can split them up then. Thanks, Charles
[PATCH v4 08/26] drm/sun4i: sun6i_mipi_dsi: Fix VBP size calculation
The horizontal and vertical back porch calculation in BSP code is simply following the Linux drm comment diagram, in include/drm/drm_modes.h which is [hv]back porch = [hv]total - [hv]sync_end BSP code form BPI-M64-bsp is calculating vertical back porch as (from linux-sunxi/drivers/video/sunxi/disp2/disp/de/disp_lcd.c) timmings->ver_sync_time= panel_info->lcd_vspw; timmings->ver_back_porch= panel_info->lcd_vbp-panel_info->lcd_vspw; vbp = panel->lcd_vbp; vspw = panel->lcd_vspw; dsi_dev[sel]->dsi_basic_size0.bits.vbp = vbp-vspw; dsi_dev[sel]->dsi_basic_size0.bits.vbp = panel->lcd_vbp - panel->lcd_vspw; => timmings->ver_back_porch + panel_info->lcd_vspw - panel_info->lcd_vspw => timmings->ver_back_porch => mode->vtotal - mode->end Which evatually same as mode->vtotal - mode->vsync_end so update the same in SUN6I_DSI_BASIC_SIZE0_VBP On the information note, existing SUN6I_DSI_BASIC_SIZE0_VSA is proper value. Signed-off-by: Jagan Teki --- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index cdd44a1307b3..eeea977604ac 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -526,8 +526,8 @@ static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi, regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG, SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end - mode->vsync_start) | -SUN6I_DSI_BASIC_SIZE0_VBP(mode->vsync_start - - mode->vdisplay)); +SUN6I_DSI_BASIC_SIZE0_VBP(mode->vtotal - + mode->vsync_end)); regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE1_REG, SUN6I_DSI_BASIC_SIZE1_VACT(mode->vdisplay) | -- 2.18.0.321.gffc6fa0e3
[PATCH v4 09/26] drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits
TCON DRQ set bits for non-burst DSI mode can computed via
horizontal front porch instead of front porch + sync timings.
BSP code form BPI-M64-bsp is computing TCON DRQ set bits
for non-burts as (from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
=> panel->lcd_ht -panel->lcd_x - panel->lcd_hbp
=> (timmings->hor_front_porch + panel->lcd_hbp + panel->lcd_x)
- panel->lcd_x - panel->hbp
=> timmings->hor_front_porch
=> mode->hsync_start - mode->hdisplay
So, update the DRQ set bits accordingly.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index eeea977604ac..fc4252d96c38 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -367,9 +367,9 @@ static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
struct mipi_dsi_device *device = dsi->device;
u32 val = 0;
- if ((mode->hsync_end - mode->hdisplay) > 20) {
+ if ((mode->hsync_start - mode->hdisplay) > 20) {
/* Maagic */
- u16 drq = (mode->hsync_end - mode->hdisplay) - 20;
+ u16 drq = (mode->hsync_start - mode->hdisplay) - 20;
drq *= mipi_dsi_pixel_format_to_bpp(device->format);
drq /= 32;
--
2.18.0.321.gffc6fa0e3
[PATCH v4 01/26] clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index f7d297368eb2..019d67bf97c4 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -581,7 +581,7 @@ static const char * const dsi_dphy_parents[] = {
"pll-video0", "pll-periph0" };
static const u8 dsi_dphy_table[] = { 0, 2, };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
dsi_dphy_parents, dsi_dphy_table,
- 0x168, 0, 4, 8, 2, BIT(31),
CLK_SET_RATE_PARENT);
+ 0x168, 0, 4, 8, 2, BIT(15),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
--
2.18.0.321.gffc6fa0e3
[PATCH v5 2/4] dt-bindings: iio: adc: Add common ADCs properties to a separate file
There are several ADC drivers that depend on the same device tree
bindings. Rather than continue to duplicate the properties, this patch
adds a common adc binding document that can be referenced. For beginning,
only two properties are documented.
Signed-off-by: Stefan Popa
---
Changes in v2, v3:
- N/A.
Changes in v4:
- Added this commit.
Changes in v5:
- Nothing changed.
Documentation/devicetree/bindings/iio/adc/adc.txt | 23 +++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/adc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/adc.txt
b/Documentation/devicetree/bindings/iio/adc/adc.txt
new file mode 100644
index 000..5bbaa33
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/adc.txt
@@ -0,0 +1,23 @@
+Common ADCs properties
+
+Optional properties for child nodes:
+- bipolar : Boolean, if set the channel is used in bipolar mode.
+- diff-channels : Differential channels muxed for this ADC. The first value
+ specifies the positive input pin, the second value the negative
+ input pin.
+
+Example:
+ adc@0 {
+ compatible = "some,adc";
+ ...
+ channel@0 {
+ bipolar;
+ diff-channels = <0 1>;
+ ...
+ };
+
+ channel@1 {
+ diff-channels = <2 3>;
+ ...
+ };
+ };
--
2.7.4
[PATCH v5 1/4] iio: ad_sigma_delta: Allow to provide custom data register address
From: Lars-Peter Clausen
Some newer devices from the Sigma-Delta ADC family do have their data
register at a different address than the current default address. Add a
parameter to the ad_sigma_delta_info struct which allows to override the
default address.
Signed-off-by: Lars-Peter Clausen
Signed-off-by: Stefan Popa
---
Changes in v2:
- Added this commit.
Changes in v3:
- Nothing changed.
Changes in v4:
- Nothing changed.
Changes in v5:
- Nothing changed.
drivers/iio/adc/ad_sigma_delta.c | 22 +-
include/linux/iio/adc/ad_sigma_delta.h | 3 +++
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/iio/adc/ad_sigma_delta.c b/drivers/iio/adc/ad_sigma_delta.c
index fc95107..ff5f2da 100644
--- a/drivers/iio/adc/ad_sigma_delta.c
+++ b/drivers/iio/adc/ad_sigma_delta.c
@@ -278,6 +278,7 @@ int ad_sigma_delta_single_conversion(struct iio_dev
*indio_dev,
{
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
unsigned int sample, raw_sample;
+ unsigned int data_reg;
int ret = 0;
if (iio_buffer_enabled(indio_dev))
@@ -305,7 +306,12 @@ int ad_sigma_delta_single_conversion(struct iio_dev
*indio_dev,
if (ret < 0)
goto out;
- ret = ad_sd_read_reg(sigma_delta, AD_SD_REG_DATA,
+ if (sigma_delta->info->data_reg != 0)
+ data_reg = sigma_delta->info->data_reg;
+ else
+ data_reg = AD_SD_REG_DATA;
+
+ ret = ad_sd_read_reg(sigma_delta, data_reg,
DIV_ROUND_UP(chan->scan_type.realbits + chan->scan_type.shift,
8),
&raw_sample);
@@ -392,6 +398,7 @@ static irqreturn_t ad_sd_trigger_handler(int irq, void *p)
struct iio_dev *indio_dev = pf->indio_dev;
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
unsigned int reg_size;
+ unsigned int data_reg;
uint8_t data[16];
int ret;
@@ -401,18 +408,23 @@ static irqreturn_t ad_sd_trigger_handler(int irq, void *p)
indio_dev->channels[0].scan_type.shift;
reg_size = DIV_ROUND_UP(reg_size, 8);
+ if (sigma_delta->info->data_reg != 0)
+ data_reg = sigma_delta->info->data_reg;
+ else
+ data_reg = AD_SD_REG_DATA;
+
switch (reg_size) {
case 4:
case 2:
case 1:
- ret = ad_sd_read_reg_raw(sigma_delta, AD_SD_REG_DATA,
- reg_size, &data[0]);
+ ret = ad_sd_read_reg_raw(sigma_delta, data_reg, reg_size,
+ &data[0]);
break;
case 3:
/* We store 24 bit samples in a 32 bit word. Keep the upper
* byte set to zero. */
- ret = ad_sd_read_reg_raw(sigma_delta, AD_SD_REG_DATA,
- reg_size, &data[1]);
+ ret = ad_sd_read_reg_raw(sigma_delta, data_reg, reg_size,
+ &data[1]);
break;
}
diff --git a/include/linux/iio/adc/ad_sigma_delta.h
b/include/linux/iio/adc/ad_sigma_delta.h
index 730ead1..7e84351 100644
--- a/include/linux/iio/adc/ad_sigma_delta.h
+++ b/include/linux/iio/adc/ad_sigma_delta.h
@@ -39,6 +39,8 @@ struct iio_dev;
* if there is just one read-only sample data shift register.
* @addr_shift: Shift of the register address in the communications register.
* @read_mask: Mask for the communications register having the read bit set.
+ * @data_reg: Address of the data register, if 0 the default address of 0x3
will
+ * be used.
*/
struct ad_sigma_delta_info {
int (*set_channel)(struct ad_sigma_delta *, unsigned int channel);
@@ -47,6 +49,7 @@ struct ad_sigma_delta_info {
bool has_registers;
unsigned int addr_shift;
unsigned int read_mask;
+ unsigned int data_reg;
};
/**
--
2.7.4
[PATCH v5 4/4] dt-bindings: iio: adc: Add docs for ad7124
Add support for Analog Devices AD7124 4-channels and 8-channels ADC.
Signed-off-by: Stefan Popa
---
Changes in v2:
- Nothing changed.
Changes in v3:
- Removed the "adi,channels" property.
- Used the "reg" property to get the channel number and
"adi,diff-channels"
for the differential pins. The "adi,channel-number" property was
removed.
- adi,bipolar is of boolean type.
Changes in v4:
- Used the bipolar and diff-channels properties defined in the new
adc.txt doc.
Changes in v5:
- Removed the gain and odr properties from the example.
.../devicetree/bindings/iio/adc/adi,ad7124.txt | 75 ++
MAINTAINERS| 1 +
2 files changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad7124.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.txt
b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.txt
new file mode 100644
index 000..416273d
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.txt
@@ -0,0 +1,75 @@
+Analog Devices AD7124 ADC device driver
+
+Required properties for the AD7124:
+ - compatible: Must be one of "adi,ad7124-4" or "adi,ad7124-8"
+ - reg: SPI chip select number for the device
+ - spi-max-frequency: Max SPI frequency to use
+ see: Documentation/devicetree/bindings/spi/spi-bus.txt
+ - clocks: phandle to the master clock (mclk)
+ see: Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - clock-names: Must be "mclk".
+ - interrupts: IRQ line for the ADC
+ see:
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+ Required properties:
+ * #address-cells: Must be 1.
+ * #size-cells: Must be 0.
+
+ Subnode(s) represent the external channels which are connected to the
ADC.
+ Each subnode represents one channel and has the following properties:
+ Required properties:
+ * reg: The channel number. It can have up to 4 channels
on ad7124-4
+ and 8 channels on ad7124-8, numbered from 0 to 15.
+ * diff-channels: see:
Documentation/devicetree/bindings/iio/adc/adc.txt
+
+ Optional properties:
+ * bipolar: see:
Documentation/devicetree/bindings/iio/adc/adc.txt
+ * adi,reference-select: Select the reference source to
use when
+ converting on the the specific channel. Valid values
are:
+ 0: REFIN1(+)/REFIN1(−).
+ 1: REFIN2(+)/REFIN2(−).
+ 3: AVDD
+ If this field is left empty, internal reference is
selected.
+
+Optional properties:
+ - refin1-supply: refin1 supply can be used as reference for conversion.
+ - refin2-supply: refin2 supply can be used as reference for conversion.
+ - avdd-supply: avdd supply can be used as reference for conversion.
+
+Example:
+ adc@0 {
+ compatible = "adi,ad7124-4";
+ reg = <0>;
+ spi-max-frequency = <500>;
+ interrupts = <25 2>;
+ interrupt-parent = <&gpio>;
+ refin1-supply = <&adc_vref>;
+ clocks = <&ad7124_mclk>;
+ clock-names = "mclk";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ diff-channels = <0 1>;
+ adi,reference-select = <0>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ bipolar;
+ diff-channels = <2 3>;
+ adi,reference-select = <0>;
+ };
+
+ channel@2 {
+ reg = <2>;
+ diff-channels = <4 5>;
+ };
+
+ channel@3 {
+ reg = <3>;
+ diff-channels = <6 7>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 3a1bfcb..f2fa508 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -845,6 +845,7 @@ L: linux-...@vger.kernel.org
W: http://ez.analog.com/community/linux-device-drivers
S: Supported
F: drivers/iio/adc/ad7124.c
+F: Documentation/devicetree/bindings/iio/adc/adi,ad7124.txt
ANALOG DEVICES INC AD9389B DRIVER
M: Hans Verkuil
--
2.7.4
[PATCH v5 3/4] iio: adc: Add ad7124 support
The ad7124-4 and ad7124-8 are a family of 4 and 8 channel sigma-delta ADCs with 24-bit precision and reference. Three power modes are available which in turn affect the output data rate: * Full power: 9.38 SPS to 19,200 SPS * Mid power: 2.34 SPS to 4800 SPS * Low power: 1.17 SPS to 2400 SPS The ad7124-4 can be configured to have four differential inputs, while ad7124-8 can have 8. Moreover, ad7124 also supports per channel configuration. Each configuration consists of gain, reference source, output data rate and bipolar/unipolar configuration. Datasheets: Link: http://www.analog.com/media/en/technical-documentation/data-sheets/AD7124-4.pdf Link: http://www.analog.com/media/en/technical-documentation/data-sheets/ad7124-8.pdf Signed-off-by: Stefan Popa --- Changes in v2: - Nothing changed. Changes in v3: - Removed channel, address, scan_index and shift fields from ad7124_channel_template. - Added a sanity check for val2 in ad7124_write_raw(). - Used the "reg" property to get the channel address and "adi,diff-channels" for the differential pins. The "adi,channel-number" property was removed. - When calling regulator_get_optional, the probe is given up in case of error, but continues in case of -ENODEV. - clk_disable_unprepare() is called before ad_sd_cleanup_buffer_and_trigger in ad7124_remove(). Changes in v4: - Added the .shift and .endianness fields as part of the ad7124_channel_template. - Made the gain configurable from the user space. - Removed the odr_hz and gain properties from the DT. - Used the bipolar and diff-channels properties defined in the new adc.txt doc. - Misc style fixes. Changes in v5: - Fixed the way the offset is determined. - Dropped the hardware gain. - Added a scale_available attribute. - The scale can be set from user space. - In ad7124_read_raw(), the gain in applied to *val2. MAINTAINERS | 7 + drivers/iio/adc/Kconfig | 11 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad7124.c | 686 +++ 4 files changed, 705 insertions(+) create mode 100644 drivers/iio/adc/ad7124.c diff --git a/MAINTAINERS b/MAINTAINERS index f642044..3a1bfcb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -839,6 +839,13 @@ S: Supported F: drivers/iio/dac/ad5758.c F: Documentation/devicetree/bindings/iio/dac/ad5758.txt +ANALOG DEVICES INC AD7124 DRIVER +M: Stefan Popa +L: linux-...@vger.kernel.org +W: http://ez.analog.com/community/linux-device-drivers +S: Supported +F: drivers/iio/adc/ad7124.c + ANALOG DEVICES INC AD9389B DRIVER M: Hans Verkuil L: linux-me...@vger.kernel.org diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index a52fea8..148a10f 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -10,6 +10,17 @@ config AD_SIGMA_DELTA select IIO_BUFFER select IIO_TRIGGERED_BUFFER +config AD7124 + tristate "Analog Devices AD7124 and similar sigma-delta ADCs driver" + depends on SPI_MASTER + select AD_SIGMA_DELTA + help + Say yes here to build support for Analog Devices AD7124-4 and AD7124-8 + SPI analog to digital converters (ADC). + + To compile this driver as a module, choose M here: the module will be + called ad7124. + config AD7266 tristate "Analog Devices AD7265/AD7266 ADC driver" depends on SPI_MASTER diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index a6e6a0b..76168b2 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -5,6 +5,7 @@ # When adding new entries keep the list in alphabetical order obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o +obj-$(CONFIG_AD7124) += ad7124.o obj-$(CONFIG_AD7266) += ad7266.o obj-$(CONFIG_AD7291) += ad7291.o obj-$(CONFIG_AD7298) += ad7298.o diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c new file mode 100644 index 000..187675e --- /dev/null +++ b/drivers/iio/adc/ad7124.c @@ -0,0 +1,686 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AD7124 SPI ADC driver + * + * Copyright 2018 Analog Devices Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* AD7124 registers */ +#define AD7124_COMMS 0x00 +#define AD7124_STATUS 0x00 +#define AD7124_ADC_CONTROL 0x01 +#define AD7124_DATA0x02 +#define AD7124_IO_CONTROL_10x03 +#define AD7124_IO_CONTROL_20x04 +#define AD7124_ID 0x05 +#define AD7124_ERROR 0x06 +#define AD7124_ERROR_EN0x07 +#define AD7124_MCLK_COUNT 0x08 +#define AD7124_CHANNEL(x) (0x09 + (x)) +#define AD7124_CONFIG(x) (0x
[PATCH v3] ARM: module: Fix function kallsyms on Thumb-2
Thumb-2 functions have the lowest bit set in the symbol value in the
symtab. When kallsyms are generated for the vmlinux, the kallsyms are
generated from the output of nm, and nm clears the lowest bit.
$ arm-linux-gnueabihf-readelf -a vmlinux | grep show_interrupts
95947: 8015dc89 686 FUNCGLOBAL DEFAULT2 show_interrupts
$ arm-linux-gnueabihf-nm vmlinux | grep show_interrupts
8015dc88 T show_interrupts
$ cat /proc/kallsyms | grep show_interrupts
8015dc88 T show_interrupts
However, for modules, the kallsyms uses the values in the symbol table
without modification, so for functions in modules, the lowest bit is set
in kallsyms.
$ arm-linux-gnueabihf-readelf -a drivers/net/tun.ko | grep tun_get_socket
268: 00e144 FUNCGLOBAL DEFAULT2 tun_get_socket
$ arm-linux-gnueabihf-nm drivers/net/tun.ko | grep tun_get_socket
00e0 T tun_get_socket
$ cat /proc/kallsyms | grep tun_get_socket
7fcd30e1 t tun_get_socket [tun]
Because of this, the offset of the crashing instruction shown in oopses
is incorrect when the crash is in a module. For example, given a
tun_get_socket which starts like this,
00e0 :
e0: b500push{lr}
e2: f7ff fffe bl 0 <__gnu_mcount_nc>
e6: 4b08ldr r3, [pc, #32]
e8: 6942ldr r2, [r0, #20]
ea: 429acmp r2, r3
ec: d002beq.n f4
a crash when tun_get_socket is called with NULL results in:
PC is at tun_get_socket+0x7/0x2c [tun]
pc : [<7fcdb0e8>]
which can result in the incorrect line being reported by gdb if this
symbol+offset is used there. If the crash is on the first instruction
of a function, the "PC is at" line would also report the symbol name of
the preceding function.
To solve this, introduce a weak module_kallsyms_symbol_value() function
which arches can override to fix up these symbol values, and implement
this for Thumb-2. We need to move elf_type() to st_other so that the
original value of st_info is preserved.
After the fix:
$ cat /proc/kallsyms | grep tun_get_socket
7fcd30e0 t tun_get_socket [tun]
PC is at tun_get_socket+0x8/0x2c [tun]
pc : [<7fcdb0e8>]
Signed-off-by: Vincent Whitchurch
---
v3: Do not overwrite st_value
v2: Fix build warning with !MODULES
arch/arm/kernel/module.c | 10 ++
include/linux/moduleloader.h | 2 ++
kernel/module.c | 34 +-
3 files changed, 33 insertions(+), 13 deletions(-)
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 3ff571c2c71c..89ab84a83600 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -336,6 +336,16 @@ static const Elf_Shdr *find_mod_section(const Elf32_Ehdr
*hdr,
extern void fixup_pv_table(const void *, unsigned long);
extern void fixup_smp(const void *, unsigned long);
+#ifdef CONFIG_THUMB2_KERNEL
+unsigned long module_kallsyms_symbol_value(Elf_Sym *sym)
+{
+ if (ELF_ST_TYPE(sym->st_info) == STT_FUNC)
+ return sym->st_value & ~1;
+
+ return sym->st_value;
+}
+#endif
+
int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
struct module *mod)
{
diff --git a/include/linux/moduleloader.h b/include/linux/moduleloader.h
index 31013c2effd3..6395409b01a4 100644
--- a/include/linux/moduleloader.h
+++ b/include/linux/moduleloader.h
@@ -86,6 +86,8 @@ void module_arch_cleanup(struct module *mod);
/* Any cleanup before freeing mod->module_init */
void module_arch_freeing_init(struct module *mod);
+unsigned long module_kallsyms_symbol_value(Elf_Sym *sym);
+
#ifdef CONFIG_KASAN
#include
#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
diff --git a/kernel/module.c b/kernel/module.c
index 49a405891587..5a588cfbb8f8 100644
--- a/kernel/module.c
+++ b/kernel/module.c
@@ -2682,7 +2682,7 @@ static void add_kallsyms(struct module *mod, const struct
load_info *info)
/* Set types up while we still have access to sections. */
for (i = 0; i < mod->kallsyms->num_symtab; i++)
- mod->kallsyms->symtab[i].st_info
+ mod->kallsyms->symtab[i].st_other
= elf_type(&mod->kallsyms->symtab[i], info);
/* Now populate the cut down core kallsyms for after init. */
@@ -3916,6 +3916,11 @@ static const char *symname(struct mod_kallsyms
*kallsyms, unsigned int symnum)
return kallsyms->strtab + kallsyms->symtab[symnum].st_name;
}
+unsigned long __weak module_kallsyms_symbol_value(Elf_Sym *sym)
+{
+ return sym->st_value;
+}
+
static const char *get_ksymbol(struct module *mod,
unsigned long addr,
unsigned long *size,
@@ -3934,6 +3939,9 @@ static const char *get_ksymbol(struct module *mod,
/* Scan for closest preceding symbol, and next symbol. (ELF
starts real symbols at 1). */
for (i = 1; i < ka
[PATCH 2/3] MAINTAINERS: add maintainer for MCP16502 PMIC driver
This patch adds a maintainer for the MCP16502 PMIC driver. Signed-off-by: Andrei Stefanescu --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f485597..edfad02 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9723,6 +9723,13 @@ M: Ludovic Desroches S: Maintained F: drivers/mmc/host/atmel-mci.c +MICROCHIP MCP16502 PMIC DRIVER +M: Andrei Stefanescu +L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/regulator/mcp16502-regulator.txt +F: drivers/regulator/mcp16502.c + MICROCHIP MCP3911 ADC DRIVER M: Marcus Folkesson M: Kent Gustavsson -- 2.7.4
[PATCH 3/3] regulator: mcp16502: add regulator driver for MCP16502
This patch adds a regulator driver for the MCP16502 PMIC.
This drivers supports basic operations through the
regulator interface such as:
- setting/reading voltage
- setting/reading operating mode
- reading current status
- transitioning to/from suspend-to-ram and standby
power states
Signed-off-by: Andrei Stefanescu
---
drivers/regulator/Kconfig| 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/mcp16502.c | 524 +++
3 files changed, 534 insertions(+)
create mode 100644 drivers/regulator/mcp16502.c
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 926cee0..719d9d6 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -567,6 +567,15 @@ config REGULATOR_MC13892
Say y here to support the regulators found on the Freescale MC13892
PMIC.
+config REGULATOR_MCP16502
+ tristate "Microchip MCP16502 PMIC"
+ depends on I2C && OF
+ help
+ Say y here to support the MCP16502 PMIC. This driver supports
+ basic operations (get/set voltage, get/set operating mode)
+ through the regulator interface. In addition it enables
+ suspend-to-ram/standby transition.
+
config REGULATOR_MT6311
tristate "MediaTek MT6311 PMIC"
depends on I2C
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 72488ef..b12e1c9 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -74,6 +74,7 @@ obj-$(CONFIG_REGULATOR_MAX77802) += max77802-regulator.o
obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o
obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o
+obj-$(CONFIG_REGULATOR_MCP16502) += mcp16502.o
obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o
obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o
obj-$(CONFIG_REGULATOR_MT6380) += mt6380-regulator.o
diff --git a/drivers/regulator/mcp16502.c b/drivers/regulator/mcp16502.c
new file mode 100644
index 000..29c72d3
--- /dev/null
+++ b/drivers/regulator/mcp16502.c
@@ -0,0 +1,524 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MCP16502 PMIC driver
+ *
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Andrei Stefanescu
+ *
+ * Inspired from tps65086-regulator.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define VDD_LOW_SEL 0x0D
+#define VDD_HIGH_SEL 0x3F
+
+#define MCP16502_VOL_SEL_MASK 0x3F
+#define MCP16502_EN_MASK BIT(7)
+#define MCP16502_MODE_MASK BIT(6)
+
+/*
+ *
+ * The PMIC has four sets of registers corresponding to four power modes:
+ * Performance, Active, Low-power, Hibernate.
+ *
+ * Registers:
+ * Each regulator has a register for each power mode. To access a register
+ * for a specific regulator and mode BASE_* and OFFSET_* need to be added.
+ *
+ * Operating modes:
+ * In order for the PMIC to transition to operating modes it has to be
+ * controlled via GPIO lines called LPM and HPM.
+ *
+ * The registers are fully configurable such that you can put all regulators in
+ * a low-power state while the PMIC is in Active mode. They are supposed to be
+ * configured at startup and then simply transition to/from a global low-power
+ * state by setting the GPIO lpm pin high/low.
+ *
+ * This driver keeps the PMIC in Active mode, Low-power state is set for the
+ * regulators by enabling/disabling operating mode (FPWM or Auto PFM).
+ *
+ * The PMIC's Low-power and Hibernate modes are used during standby/suspend.
+ * To enter standby/suspend the PMIC will go to Low-power mode. From there, it
+ * will transition to Hibernate when the PWRHLD line is set to low by the MPU.
+ */
+
+/*
+ * This macro is useful for iterating over all regulators and accessing their
+ * registers in a generic way or accessing a regulator device by its id.
+ */
+#define BASE(i) (((i) + 1) << 4)
+
+#define OFFSET_MODE_A 0
+#define OFFSET_MODE_HIB 2
+
+#define MCP16502_MODE_ACTIVE REGULATOR_MODE_NORMAL
+#define MCP16502_MODE_HIB REGULATOR_MODE_STANDBY
+
+#define MCP16502_MODE_AUTO_PFM 0
+#define MCP16502_MODE_FPWM BIT(6)
+
+#define MIN_REG 0x0
+#define MAX_REG 0x65
+
+static unsigned int mcp16502_of_map_mode(unsigned int mode)
+{
+ if (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE)
+ return mode;
+
+ return REGULATOR_MODE_INVALID;
+}
+
+#define MCP16502_REGULATOR(_name, _id, _ranges, _ops) \
+ [_id] = { \
+ .name = _name,\
+ .regulators_node= of_match_ptr("regulators"), \
+ .id = _id, \
+ .ops= &(_ops), \
+ .type = REGULATOR_VOLTAGE,\
+ .owner
