[PATCH 1/2] dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation
Signed-off-by: Girish Mahadevan
---
.../devicetree/bindings/spi/qcom,spi-qcom-qspi.txt | 36 ++
err.txt| 27
2 files changed, 36 insertions(+), 27 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
delete mode 100644 err.txt
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
new file mode 100644
index 000..3baa893
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
@@ -0,0 +1,36 @@
+QTI [Qualcomm Technologies Inc] Quad Serial Peripheral Interface (QSPI)
+
+QSPI [Quad Serial Peripheral Interface] allows single dual and quad read/write
+access to slaves. QTI's QSPI controller implements the QSPI protocol to
interface
+with slaves like NOR Flash devices.
+
+Required properties:
+- compatible: Should contain:
+ "qcom,qspi-v1"
+- reg: Contains the base register location and length
+- interrupts: Interrupt number used by the controller.
+- clocks: Contains the core and AHB clock names.
+- clock-names: "core" for core clock and "iface" for AHB clock.
+- spi-max-frequency: Maximum SPI core clock frequency in Hz.
+
+SPI slave nodes must be children of the SPI master node and can contain
+properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+ qspi: qspi@7418000 {
+ compatible = "qcom,qspi-v1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7418000 0x600>;
+ interrupts = <0 459 0>;
+ clock-names = "iface", "core";
+ clocks = <&clock_gcc clk_gcc_qspi_ahb_clk>,
+<&clock_gcc clk_gcc_qspi_ser_clk>;
+
+ device@0 {
+ compatible = "dummy_device";
+ reg = ; /* CS for the device */
+ spi-max-frequency = ; /* Max supported frequency of
the slave (Hz) */
+ };
+ };
diff --git a/err.txt b/err.txt
deleted file mode 100644
index 09000e4..000
--- a/err.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-Skipping hidl generation
-arch/arm64/Makefile:23: ld does not support --fix-cortex-a53-843419; kernel
may be susceptible to erratum
-arch/arm64/Makefile:44: Detected assembler with broken .inst; disassembly will
be unreliable
- CHK include/config/kernel.release
- CHK include/generated/uapi/linux/version.h
- CHK include/generated/utsrelease.h
- CHK include/generated/bounds.h
- CHK include/generated/timeconst.h
- CHK include/generated/asm-offsets.h
- CALLscripts/checksyscalls.sh
- CHK scripts/mod/devicetable-offsets.h
- CHK include/generated/compile.h
- CHK kernel/config_data.h
- CC drivers/mtd/devices/m25p80.o
- AR drivers/mtd/devices/built-in.o
- AR drivers/mtd/built-in.o
- CC drivers/spi/spi-mem.o
-drivers/spi/spi-mem.c:12:23: fatal error: internals.h: No such file or
directory
- #include "internals.h"
- ^
-compilation terminated.
-make[2]: *** [drivers/spi/spi-mem.o] Error 1
-make[1]: *** [drivers/spi] Error 2
-make: *** [drivers] Error 2
-
-[0;31m failed to build some targets (12 seconds) [00m
-
--
1.9.1
[PATCH 2/2] spi: Introduce new driver for Qualcomm QuadSPI controller
New driver for Qualcomm QuadSPI(QSPI) controller that is used to communicate with slaves such flash memory devices. The QSPI controller can operate in 2 or 4 wire mode but only supports SPI Mode 0 and SPI Mode 3. The controller can also operate in Single or Dual data rate modes. Signed-off-by: Girish Mahadevan --- drivers/spi/Kconfig | 7 + drivers/spi/Makefile| 1 + drivers/spi/spi-qcom-qspi.c | 728 3 files changed, 736 insertions(+) create mode 100644 drivers/spi/spi-qcom-qspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 97e1fa9..bc71cd3 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -571,6 +571,13 @@ config SPI_QCOM_GENI This driver can also be built as a module. If so, the module will be called spi-geni-qcom. +config SPI_QCOM_QSPI + tristate "QTI QPSPI controller" + depends on ARCH_QCOM + help + QSPI(Quad SPI) driver for Qualcomm QSPI controller. + config SPI_QUP tristate "Qualcomm SPI controller with QUP interface" depends on ARCH_QCOM || (ARM && COMPILE_TEST) diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 5a0ce66..93cea68 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -113,3 +113,4 @@ obj-$(CONFIG_SPI_ZYNQMP_GQSPI) += spi-zynqmp-gqspi.o # SPI slave protocol handlers obj-$(CONFIG_SPI_SLAVE_TIME) += spi-slave-time.o obj-$(CONFIG_SPI_SLAVE_SYSTEM_CONTROL) += spi-slave-system-control.o +obj-$(CONFIG_SPI_QCOM_QSPI)+= spi-qcom-qspi.o diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c new file mode 100644 index 000..6a86605 --- /dev/null +++ b/drivers/spi/spi-qcom-qspi.c @@ -0,0 +1,728 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017-2018, The Linux foundation. All rights reserved. + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AHB_MIN_HZ 960UL +#define QSPI_NUM_CS2 +#define QSPI_BYTES_PER_WORD4 +#define MSTR_CONFIG0x +#define AHB_MASTER_CFG 0x0004 +#define MSTR_INT_EN0x000C +#define MSTR_INT_STATUS0x0010 +#define PIO_XFER_CTRL 0x0014 +#define PIO_XFER_CFG 0x0018 +#define PIO_XFER_STATUS0x001c +#define PIO_DATAOUT_1B 0x0020 +#define PIO_DATAOUT_4B 0x0024 +#define RD_FIFO_CFG0x0028 +#define RD_FIFO_STATUS 0x002c +#define RD_FIFO_RESET 0x0030 +#define CUR_MEM_ADDR 0x0048 +#define HW_VERSION 0x004c +#define RD_FIFOk 0x0050 +#define SAMPLING_CLK_CFG 0x0090 +#define SAMPLING_CLK_STATUS0x0094 + +/* Macros to help set/get fields in MSTR_CONFIG register */ +#defineFULL_CYCLE_MODE BIT(3) +#defineFB_CLK_EN BIT(4) +#definePIN_HOLDN BIT(6) +#definePIN_WPN (BIT(7)) +#defineDMA_ENABLE (BIT(8)) +#defineBIG_ENDIAN_MODE (BIT(9)) +#defineSPI_MODE_MSK(0xc00) +#defineSPI_MODE_SHFT (10) +#defineCHIP_SELECT_NUM BIT(12) +#defineSBL_EN BIT(13) +#defineLPA_BASE_MSK(0x3c000) +#defineLPA_BASE_SHFT (14) +#defineTX_DATA_DELAY_MSK (0xc) +#defineTX_DATA_DELAY_SHFT (18) +#defineTX_CLK_DELAY_MSK(0x30) +#defineTX_CLK_DELAY_SHFT (20) +#defineTX_CS_N_DELAY_MSK (0xc0) +#defineTX_CS_N_DELAY_SHFT (22) +#defineTX_DATA_OE_DELAY_MSK(0x300) +#defineTX_DATA_OE_DELAY_SHFT (24) + +/* Macros to help set/get fields in AHB_MSTR_CFG register */ +#defineHMEM_TYPE_START_MID_TRANS_MSK (0x7) +#defineHMEM_TYPE_START_MID_TRANS_SHFT (0) +#defineHMEM_TYPE_LAST_TRANS_MSK(0x38) +#defineHMEM_TYPE_LAST_TRANS_SHFT (3) +#defineUSE_HMEMTYPE_LAST_ON_DESC_OR_CHAIN_MSK (0xc0) +#defineUSE_HMEMTYPE_LAST_ON_DESC_OR_CHAIN_SHFT (6) +#defineHMEMTYPE_READ_TRANS_MSK (0x700) +#defineHMEMTYPE_READ_TRANS_SHFT(8) +#defineHSHARED (BIT(11)) +#defineHINNERSHARED(BIT(12)) + +/* Macros to help set/get fields in MSTR_INT_EN/MSTR_INT_STATUS registers */ +#defineRESP_FIFO_UNDERRUN (BIT(0)) +#defineRESP_FIFO_NOT_EMPTY (BIT(1)) +#defineRESP_FIFO_RDY (BIT(2)) +#defineHRESP_FROM_NOC_ERR (BIT(3)) +#defineWR_FIFO_EMPTY (BIT(9)) +#defineWR_FIFO_FULL(BIT(10)) +#defineWR_FIFO_OVERRUN (BIT(11)) +#defineTRANSACTION_DONE(BIT(16)) +#defineENABLE_ALL_IRQ (RESP_FIFO_UNDERRUN | RESP_FIFO_RDY | \ + HRESP_FROM_NOC_ERR | WR_FIFO_EMPTY | WR_FIFO_FULL |\ + WR_FIF
[PATCH] spi: spi-geni-qcom: Add SPI driver support for GENI based QUP
This driver supports GENI based SPI Controller in the Qualcomm SOCs. The
Qualcomm Generic Interface (GENI) is a programmable module supporting a
wide range of serial interfaces including SPI. This driver supports SPI
operations using FIFO mode of transfer.
Signed-off-by: Girish Mahadevan
---
drivers/spi/Kconfig | 12 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-geni-qcom.c | 766 ++
include/linux/spi/spi-geni-qcom.h | 14 +
4 files changed, 793 insertions(+)
create mode 100644 drivers/spi/spi-geni-qcom.c
create mode 100644 include/linux/spi/spi-geni-qcom.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9b31351..358d60a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -564,6 +564,18 @@ config SPI_QUP
This driver can also be built as a module. If so, the module
will be called spi_qup.
+config SPI_QCOM_GENI
+ tristate "Qualcomm SPI controller with QUP interface"
+ depends on ARCH_QCOM || (ARM && COMPILE_TEST)
+ help
+ This driver supports GENI serial engine based SPI controller in
+ master mode on the Qualcomm Technologies Inc.'s SoCs. If you say
+ yes to this option, support will be included for the built-in SPI
+ interface on the Qualcomm Technologies Inc.'s SoCs.
+
+ This driver can also be built as a module. If so, the module
+ will be called spi-geni-qcom.
+
config SPI_S3C24XX
tristate "Samsung S3C24XX series SPI"
depends on ARCH_S3C24XX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index a3ae2b7..cc90d6e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -77,6 +77,7 @@ spi-pxa2xx-platform-objs := spi-pxa2xx.o
spi-pxa2xx-dma.o
obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
obj-$(CONFIG_SPI_QUP) += spi-qup.o
+obj-$(CONFIG_SPI_QCOM_GENI)+= spi-geni-qcom.o
obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
obj-$(CONFIG_SPI_RB4XX)+= spi-rb4xx.o
obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
new file mode 100644
index 000..eecc634
--- /dev/null
+++ b/drivers/spi/spi-geni-qcom.c
@@ -0,0 +1,766 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SPI_NUM_CHIPSELECT 4
+#define SPI_XFER_TIMEOUT_MS250
+/* SPI SE specific registers */
+#define SE_SPI_CPHA0x224
+#define SE_SPI_LOOPBACK0x22c
+#define SE_SPI_CPOL0x230
+#define SE_SPI_DEMUX_OUTPUT_INV0x24c
+#define SE_SPI_DEMUX_SEL 0x250
+#define SE_SPI_TRANS_CFG 0x25c
+#define SE_SPI_WORD_LEN0x268
+#define SE_SPI_TX_TRANS_LEN0x26c
+#define SE_SPI_RX_TRANS_LEN0x270
+#define SE_SPI_PRE_POST_CMD_DLY0x274
+#define SE_SPI_DELAY_COUNTERS 0x278
+
+/* SE_SPI_CPHA register fields */
+#define CPHA BIT(0)
+
+/* SE_SPI_LOOPBACK register fields */
+#define LOOPBACK_ENABLE0x1
+#define NORMAL_MODE0x0
+#define LOOPBACK_MSK GENMASK(1, 0)
+
+/* SE_SPI_CPOL register fields */
+#define CPOL BIT(2)
+
+/* SE_SPI_DEMUX_OUTPUT_INV register fields */
+#define CS_DEMUX_OUTPUT_INV_MSKGENMASK(3, 0)
+
+/* SE_SPI_DEMUX_SEL register fields */
+#define CS_DEMUX_OUTPUT_SELGENMASK(3, 0)
+
+/* SE_SPI_TX_TRANS_CFG register fields */
+#define CS_TOGGLE BIT(0)
+
+/* SE_SPI_WORD_LEN register fields */
+#define WORD_LEN_MSK GENMASK(9, 0)
+#define MIN_WORD_LEN 4
+
+/* SPI_TX/SPI_RX_TRANS_LEN fields */
+#define TRANS_LEN_MSK GENMASK(23, 0)
+
+/* SE_SPI_DELAY_COUNTERS */
+#define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0)
+#define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)
+#define SPI_CS_CLK_DELAY_SHFT 10
+
+/* M_CMD OP codes for SPI */
+#define SPI_TX_ONLY1
+#define SPI_RX_ONLY2
+#define SPI_FULL_DUPLEX3
+#define SPI_TX_RX 7
+#define SPI_CS_ASSERT 8
+#define SPI_CS_DEASSERT9
+#define SPI_SCK_ONLY 10
+/* M_CMD params for SPI */
+#define SPI_PRE_CMD_DELAY BIT(0)
+#define TIMESTAMP_BEFORE BIT(1)
+#define FRAGMENTATION BIT(2)
+#define TIMESTAMP_AFTERBIT(3)
+#define POST_CMD_DELAY BIT(4)
+
+static irqreturn_t geni_spi_isr(int irq, void *dev);
+
+struct spi_geni_master {
+ struct geni_se se;
+ int irq;
+ struct device *dev;
+ int rx_fifo_depth;
+ int tx_fifo_depth;
+ int tx_fifo_width;
+ int tx_wm;
+
[PATCH RFCv1 1/1] spi: Expand tx_nbits/rx_nbits to add 8-bit transfer
Expand the tx_nbits/rx_nbits member of the spi_transfer struct to a 4 bit
value to allow specifying 8 bit transfers (SPI_NBITS_OCTO).
Change-Id: I0b7ab41b2caa8495da431944ccbc0b90942d5dd9
Signed-off-by: Girish Mahadevan
---
include/linux/spi/spi.h | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 857a9a1..45b958a 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -717,10 +717,11 @@ extern void spi_res_release(struct spi_master *master,
* by the results of previous messages and where the whole transaction
* ends when the chipselect goes intactive.
*
- * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
+ * When SPI can transfer in 1x,2x,4x or 8x. It can get this transfer
information
* from device through @tx_nbits and @rx_nbits. In Bi-direction, these
* two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
- * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
+ * SPI_NBITS_DUAL(2x) SPI_NBITS_QUAD(4x) and SPI_NBITS_OCTO(8x) to support
+ * these four transfers.
*
* The code that submits an spi_message (and its spi_transfers)
* to the lower layers is responsible for managing its memory.
@@ -744,11 +745,12 @@ struct spi_transfer {
struct sg_table rx_sg;
unsignedcs_change:1;
- unsignedtx_nbits:3;
- unsignedrx_nbits:3;
+ unsignedtx_nbits:4;
+ unsignedrx_nbits:4;
#defineSPI_NBITS_SINGLE0x01 /* 1bit transfer */
#defineSPI_NBITS_DUAL 0x02 /* 2bits transfer */
#defineSPI_NBITS_QUAD 0x04 /* 4bits transfer */
+#defineSPI_NBITS_OCTO 0x08 /* 4bits transfer */
u8 bits_per_word;
u16 delay_usecs;
u32 speed_hz;
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux
Foundation Collaborative Project
[PATCH RFCv1 0/1] Update struct spi_transfer to specify 8x bit transfers
We’re working on a driver for a Quad SPI controller [using up to 4 data lines] which can use dual-data-sampling to implement 8-bit transfers. To allow a slave driver to specify the 8-bit transfer we'd like to make this change to the spi_transfer data structure. We are still working on the driver we will send an RFC for the driver patches separately once it is ready. Girish Mahadevan (1): spi: Expand tx_nbits/rx_nbits to add 8-bit transfer include/linux/spi/spi.h | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
