[PATCH] thermal: core: fix some format issues on critical shutdown string

[Icenowy Zheng]

The critical shutdown notice string used to have some spaces missing,
which makes it not so pretty.

Add the spaces to satisfy usual English space rules.

Reported-by: Mingcong Bai <jeff...@aosc.io>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/thermal/thermal_core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c
index 5a51c740e372..671e4d15599d 100644
--- a/drivers/thermal/thermal_core.c
+++ b/drivers/thermal/thermal_core.c
@@ -390,7 +390,7 @@ static void handle_critical_trips(struct 
thermal_zone_device *tz,
 
if (trip_type == THERMAL_TRIP_CRITICAL) {
dev_emerg(>device,
- "critical temperature reached(%d C),shutting down\n",
+ "critical temperature reached (%d C), shutting 
down\n",
  tz->temperature / 1000);
mutex_lock(_lock);
if (!power_off_triggered) {
-- 
2.13.0

[PATCH v3 3/5] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

[Icenowy Zheng]

This adds support for the Allwinner H3 thermal sensor.

Allwinner H3 has a thermal sensor like the one in A33, but have its
registers nearly all re-arranged, sample clock moved to CCU and a pair
of bus clock and reset added. It's also the base of newer SoCs' thermal
sensors.

Some new options is added to gpadc_data struct, to mark the difference
between the old GPADCs and THS's and the new THS's.

Thermal sampling via interrupts are still not supported, and polling
is used instead.

The thermal sensors on A64 and H5 is like the one on H3, but with of
course different formula factors.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Clock name changes.
- Fixed some small issues pointed out by Quentin.

 drivers/iio/adc/sun4i-gpadc-iio.c | 228 +++---
 include/linux/mfd/sun4i-gpadc.h   |  27 +
 2 files changed, 215 insertions(+), 40 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 41769bc6a429..5c79ba4d5ef5 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -22,6 +22,7 @@
  * shutdown for not being used.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -31,6 +32,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -49,6 +51,8 @@ static unsigned int sun6i_gpadc_chan_select(unsigned int chan)
return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
 }
 
+struct sun4i_gpadc_iio;
+
 struct gpadc_data {
int temp_offset;
int temp_scale;
@@ -56,39 +60,12 @@ struct gpadc_data {
unsigned inttp_adc_select;
unsigned int(*adc_chan_select)(unsigned int chan);
unsigned intadc_chan_mask;
-};
-
-static const struct gpadc_data sun4i_gpadc_data = {
-   .temp_offset = -1932,
-   .temp_scale = 133,
-   .tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
-   .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
-   .adc_chan_select = _gpadc_chan_select,
-   .adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
-};
-
-static const struct gpadc_data sun5i_gpadc_data = {
-   .temp_offset = -1447,
-   .temp_scale = 100,
-   .tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
-   .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
-   .adc_chan_select = _gpadc_chan_select,
-   .adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
-};
-
-static const struct gpadc_data sun6i_gpadc_data = {
-   .temp_offset = -1623,
-   .temp_scale = 167,
-   .tp_mode_en = SUN6I_GPADC_CTRL1_TP_MODE_EN,
-   .tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
-   .adc_chan_select = _gpadc_chan_select,
-   .adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
-};
-
-static const struct gpadc_data sun8i_a33_gpadc_data = {
-   .temp_offset = -1662,
-   .temp_scale = 162,
-   .tp_mode_en = SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN,
+   unsigned inttemp_data;
+   int (*sample_start)(struct sun4i_gpadc_iio *info);
+   int (*sample_end)(struct sun4i_gpadc_iio *info);
+   boolhas_bus_clk;
+   boolhas_bus_rst;
+   boolhas_mod_clk;
 };
 
 struct sun4i_gpadc_iio {
@@ -103,6 +80,9 @@ struct sun4i_gpadc_iio {
atomic_tignore_temp_data_irq;
const struct gpadc_data *data;
boolno_irq;
+   struct clk  *ths_bus_clk;
+   struct clk  *mod_clk;
+   struct reset_control*reset;
/* prevents concurrent reads of temperature and ADC */
struct mutexmutex;
struct thermal_zone_device  *tzd;
@@ -276,7 +256,7 @@ static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, 
int *val)
if (info->no_irq) {
pm_runtime_get_sync(indio_dev->dev.parent);
 
-   regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
+   regmap_read(info->regmap, info->data->temp_data, val);
 
pm_runtime_mark_last_busy(indio_dev->dev.parent);
pm_runtime_put_autosuspend(indio_dev->dev.parent);
@@ -384,10 +364,8 @@ static irqreturn_t sun4i_gpadc_fifo_data_irq_handler(int 
irq, void *dev_id)
return IRQ_HANDLED;
 }
 
-static int sun4i_gpadc_runtime_suspend(struct device *dev)
+static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info)
 {
-   struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
-
/* Disable the ADC on IP */
regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0);
/* Disable temperature sensor on IP */
@@ -396,10 +374,23 @@ static int sun4i_gpadc_runtime_suspend(struct device *dev)
return 0;
 }
 
-static int sun4i_gpadc_runtime_resume(struct device *dev)
+static int sun8i_h3_gpadc_sample_end(struct sun4i_gpadc_iio *info)
+{
+   /* Disable temperature sensor */

[PATCH v3 4/5] ARM: sun8i: h3: add support for the thermal sensor in H3

[Icenowy Zheng]

As we have gained the support for the thermal sensor in H3, we can now
add its device nodes to the device tree.

Add them to the H3 device tree.

The H5 thermal sensor has some differences, and will be added furtherly.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Clock name changes.
- Splited out thermal zone addition.

 arch/arm/boot/dts/sun8i-h3.dtsi | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index a0cee17fe44b..efe3a8e4f2af 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -108,6 +108,23 @@
};
};
 
+   iio-hwmon {
+   compatible = "iio-hwmon";
+   io-channels = <>;
+   };
+
+   soc {
+   ths: thermal-sensor@1c25000 {
+   compatible = "allwinner,sun8i-h3-ths";
+   reg = <0x01c25000 0x100>;
+   clocks = < CLK_BUS_THS>, < CLK_THS>;
+   clock-names = "bus", "mod";
+   resets = < RST_BUS_THS>;
+   #thermal-sensor-cells = <0>;
+   #io-channel-cells = <0>;
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
-- 
2.13.0

[PATCH v3 2/5] iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to contain A23

[Icenowy Zheng]

As the H3 SoC, which is also in sun8i line, has totally different
register map for the thermal sensor (a cut down version of GPADC), we
should rename A23/A33-specified registers to contain A23, in order to
prevent obfuscation with H3 registers. Currently these registers are
only prefixed "SUN8I", not "SUN8I_A23".

Add "_A23" after "SUN8I" on the register names.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 2 +-
 include/linux/mfd/sun4i-gpadc.h   | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 81d4c39e414a..41769bc6a429 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -88,7 +88,7 @@ static const struct gpadc_data sun6i_gpadc_data = {
 static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_offset = -1662,
.temp_scale = 162,
-   .tp_mode_en = SUN8I_GPADC_CTRL1_CHOP_TEMP_EN,
+   .tp_mode_en = SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN,
 };
 
 struct sun4i_gpadc_iio {
diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h
index 139872c2e0fe..d31d962bb7d8 100644
--- a/include/linux/mfd/sun4i-gpadc.h
+++ b/include/linux/mfd/sun4i-gpadc.h
@@ -38,9 +38,9 @@
 #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x)   (GENMASK(3, 0) & BIT(x))
 #define SUN6I_GPADC_CTRL1_ADC_CHAN_MASKGENMASK(3, 0)
 
-/* TP_CTRL1 bits for sun8i SoCs */
-#define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
-#define SUN8I_GPADC_CTRL1_GPADC_CALI_ENBIT(7)
+/* TP_CTRL1 bits for sun8i A23/A33 SoCs */
+#define SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
+#define SUN8I_A23_GPADC_CTRL1_GPADC_CALI_ENBIT(7)
 
 #define SUN4I_GPADC_CTRL2  0x08
 
-- 
2.13.0

[PATCH v3 0/5] IIO-based thermal sensor driver for Allwinner H3 SoC

[Icenowy Zheng]

Allwiner H3 SoC has a thermal sensor, which is a large refactored version of
the old Allwinner "GPADC" (although it have already only thermal part left
in A33).

This patch tried to add support for the sensor in H3 based on the A33 thermal
sensor driver by Quentin Schulz, which is already merged.

Icenowy Zheng (5):
  dt-bindings: update the Allwinner GPADC device tree binding for H3
  iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to
contain A23
  iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
  ARM: sun8i: h3: add support for the thermal sensor in H3
  ARM: sun8i: h3: add partial CPU thermal zone

 .../devicetree/bindings/mfd/sun4i-gpadc.txt|  25 ++-
 arch/arm/boot/dts/sun8i-h3.dtsi|  26 +++
 drivers/iio/adc/sun4i-gpadc-iio.c  | 228 +
 include/linux/mfd/sun4i-gpadc.h|  33 ++-
 4 files changed, 267 insertions(+), 45 deletions(-)

-- 
2.13.0

[PATCH v3 1/5] dt-bindings: update the Allwinner GPADC device tree binding for H3

[Icenowy Zheng]

Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.

Update the binding document to cover H3.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Clock name changes.
- Example node name changes.
- Add interupts (not yet used by the driver).

 .../devicetree/bindings/mfd/sun4i-gpadc.txt| 25 --
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt 
b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
index badff3611a98..986265c59b2a 100644
--- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
+++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
@@ -4,12 +4,21 @@ The Allwinner SoCs all have an ADC that can also act as a 
thermal sensor
 and sometimes as a touchscreen controller.
 
 Required properties:
-  - compatible: "allwinner,sun8i-a33-ths",
+  - compatible: must contain one of the following compatibles:
+   - "allwinner,sun8i-a33-ths"
+   - "allwinner,sun8i-h3-ths"
   - reg: mmio address range of the chip,
   - #thermal-sensor-cells: shall be 0,
   - #io-channel-cells: shall be 0,
 
-Example:
+Required properties for the following compatibles:
+   - "allwinner,sun8i-h3-ths"
+  - clocks: the bus clock and the input clock of the ADC,
+  - clock-names: should be "bus" and "mod",
+  - resets: the bus reset of the ADC,
+  - interrupts: the sampling interrupt of the ADC,
+
+Example for A33:
ths: ths@01c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
@@ -17,6 +26,18 @@ Example:
#io-channel-cells = <0>;
};
 
+Example for H3:
+   ths: thermal-sensor@1c25000 {
+   compatible = "allwinner,sun8i-h3-ths";
+   reg = <0x01c25000 0x400>;
+   clocks = < CLK_BUS_THS>, < CLK_THS>;
+   clock-names = "bus", "mod";
+   resets = < RST_BUS_THS>;
+   interrupts = ;
+   #thermal-sensor-cells = <0>;
+   #io-channel-cells = <0>;
+   };
+
 sun4i, sun5i and sun6i SoCs are also supported via the older binding:
 
 sun4i resistive touchscreen controller
-- 
2.13.0

[PATCH v3 5/5] ARM: sun8i: h3: add partial CPU thermal zone

[Icenowy Zheng]

Because of the restriction of the OF thermal framework, the thermal
sensor will fail to probe if the thermal zone doesn't exist.

Add a partial thermal zone which claims the H3 THS as the thermal sensor.

The cooling device (CPU DVFS) is still not added as it's not ready, and
the trip points are also not added yet.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index efe3a8e4f2af..551efecaab5d 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -125,6 +125,15 @@
};
};
 
+   thermal-zones {
+   cpu-thermal {
+   /* milliseconds */
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = <>;
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
-- 
2.13.0

Re: [PATCH 2/3] ARM: sunxi: h3/h5: Add sun8i-h3-ephy compatible

[Icenowy Zheng]

于 2017年7月28日 GMT+08:00 下午5:44:51, Chen-Yu Tsai  写到:
>On Fri, Jul 28, 2017 at 5:28 PM, Corentin Labbe
> wrote:
>> This patch adds the sun8i-h3-ephy compatible to the internal PHY.
>>
>> Signed-off-by: Corentin Labbe 
>> ---
>>  arch/arm/boot/dts/sunxi-h3-h5.dtsi | 3 ++-
>
>To avoid repeating the past, this patch, if approved, will be merged
>through the sunxi tree, not netdev nor net-next.
>
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
>b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
>> index 4b599b5d26f6..7aaa837c2388 100644
>> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
>> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
>> @@ -421,7 +421,8 @@
>> #address-cells = <1>;
>> #size-cells = <0>;
>> int_mii_phy: ethernet-phy@1 {
>> -   compatible =
>"ethernet-phy-ieee802.3-c22";
>> +   compatible =
>"allwinner,sun8i-h3-ephy",
>> +  
>"ethernet-phy-ieee802.3-c22";
>
>Are you expecting people to override this properly?
>
>As it currently is, any external phy at address 1 will simply
>reuse the same device node. And if they don't override the
>property correctly, the driver will end up trying to use
>the internal phy, while the user is expecting the external
>one to be used.
>
>Maybe you could move this to some other address, maybe the last
>valid one, or second last valid one?

Some board designers may use other address.

For example, on Nano Pi NEO2 the PHY is attached at address 0x7.

>
>ChenYu
>
>> reg = <1>;
>> clocks = < CLK_BUS_EPHY>;
>> resets = < RST_BUS_EPHY>;
>> --
>> 2.13.0
>>

Re: [linux-sunxi] [PATCH 10/10] ARM: dts: sun8i: Add SY8106A regulator to Orange Pi PC

[Icenowy Zheng]

于 2017年7月26日 GMT+08:00 下午3:08:06, Chen-Yu Tsai <w...@csie.org> 写到:
>On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng <icen...@aosc.io> wrote:
>> From: Ondrej Jirman <meg...@megous.com>
>>
>> Add SY8106A regulator to r_i2c bus and enable the r_i2c bus on
>> Orange Pi PC, then set the power supply of the ARM cores to this
>> regulator, in order to enable DVFS.
>>
>> Signed-off-by: Ondrej Jirman <meg...@megous.com>
>> [Icenowy: Enable DVFS in this patch, slight changes and change commit
>>  message]
>> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>> ---
>>  arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 19 +++
>>  1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
>b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
>> index 998b60f8d295..d855f8b6254e 100644
>> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
>> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
>> @@ -98,6 +98,10 @@
>> status = "okay";
>>  };
>>
>> + {
>> +   cpu-supply = <_sy8106a>;
>> +};
>> +
>>   {
>> status = "okay";
>>  };
>> @@ -160,6 +164,21 @@
>> };
>>  };
>>
>> +_i2c {
>> +   status = "okay";
>> +
>> +   reg_sy8106a: regulator@65 {
>> +   compatible = "silergy,sy8106a";
>> +   reg = <0x65>;
>> +   regulator-name = "vdd-cpux";
>> +   regulator-min-microvolt = <100>;
>
>According to the H3 datasheet, the minimum voltage is 1.1V, not 1V.

But the Armbian OPP table for H3 contains several
OPP under 1.1V...

>
>Otherwse
>
>> +   regulator-max-microvolt = <140>;
>> +   regulator-ramp-delay = <200>;
>
>Is this an actual constraint of the SoC? Or is it a characteristic
>of the regulator? If it is the latter, it belongs in the driver.
>AFAIK the regulator supports varying the ramp delay (slew rate).
>
>ChenYu
>
>> +   regulator-boot-on;
>> +   regulator-always-on;
>> +   };
>> +};
>> +
>>  _pio {
>> leds_r_opc: led_pins@0 {
>> pins = "PL10";
>> --
>> 2.13.0
>>
>> --
>> You received this message because you are subscribed to the Google
>Groups "linux-sunxi" group.
>> To unsubscribe from this group and stop receiving emails from it,
>send an email to linux-sunxi+unsubscr...@googlegroups.com.
>> For more options, visit https://groups.google.com/d/optout.

[PATCH 0/2] Last step to working Allwinner R40 pinctrl

[Icenowy Zheng]

This patchset contains only two patches.

The first one is a minor fix for the A10 pinctrl driver, add a function
of a pin, which used to be missing in A10/A20 pinctrl driver.

The second one is the real R40 pinctrl part, with fixes suggested by
Chen-Yu.

Icenowy Zheng (2):
  pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver
  pinctrl: sunxi: add support of R40 to A10 pinctrl driver

 drivers/pinctrl/sunxi/Kconfig |   2 +-
 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 281 +-
 2 files changed, 204 insertions(+), 79 deletions(-)

-- 
2.13.0

[PATCH 1/2] pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver

[Icenowy Zheng]

The PH16 pin has a function with mux id 0x5, which is the DET pin of the
"sim" (smart card reader) IP block.

This function is missing both in the old A10 and A20 drivers, so it's
not found during the merge of these two drivers.

Add it to the driver. As we now merged A20 pinctrl driver to the A10
one, we need to only fix the A10 driver now.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c 
b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 159580c04b14..47a392bc73c8 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -918,6 +918,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
  SUNXI_FUNCTION_VARIANT(0x3, "emac",   /* ETXD1 */
 PINCTRL_SUN7I_A20),
  SUNXI_FUNCTION(0x4, "keypad"),/* IN6 */
+ SUNXI_FUNCTION(0x5, "sim"),   /* DET */
  SUNXI_FUNCTION_IRQ(0x6, 16),  /* EINT16 */
  SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
-- 
2.13.0

[PATCH 2/2] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

[Icenowy Zheng]

R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).

Add support for R40 to the A10 pinctrl driver.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/pinctrl/sunxi/Kconfig |   2 +-
 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 280 +-
 2 files changed, 203 insertions(+), 79 deletions(-)

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 31f85ca92669..bfce99d86dfc 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -7,7 +7,7 @@ config PINCTRL_SUNXI
select GPIOLIB
 
 config PINCTRL_SUN4I_A10
-   def_bool MACH_SUN4I || MACH_SUN7I
+   def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
select PINCTRL_SUNXI
 
 config PINCTRL_SUN5I
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c 
b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 47a392bc73c8..2bd2060c3cb1 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -26,7 +26,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
  SUNXI_FUNCTION(0x3, "spi1"),  /* CS0 */
  SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GRXD3 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -34,7 +35,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
  SUNXI_FUNCTION(0x3, "spi1"),  /* CLK */
  SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GRXD2 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -42,7 +44,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
  SUNXI_FUNCTION(0x3, "spi1"),  /* MOSI */
  SUNXI_FUNCTION(0x4, "uart2"), /* TX */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GRXD1 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -50,65 +53,75 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
  SUNXI_FUNCTION(0x3, "spi1"),  /* MISO */
  SUNXI_FUNCTION(0x4, "uart2"), /* RX */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GRXD0 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ETXD3 */
  SUNXI_FUNCTION(0x3, "spi1"),  /* CS1 */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GTXD3 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ETXD2 */
  SUNXI_FUNCTION(0x3, "spi3"),  /* CS0 */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GTXD2 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ETXD1 */
  SUNXI_FUNCTION(0x3, "

Re: [PATCH 2/2] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

[Icenowy Zheng]

于 2017年7月7日 GMT+08:00 上午4:50:30, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Thu, Jul 06, 2017 at 10:28:22PM +0800, Icenowy Zheng wrote:
>>  SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
>>SUNXI_FUNCTION(0x0, "gpio_in"),
>>SUNXI_FUNCTION(0x1, "gpio_out"),
>> -  SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
>> +  SUNXI_FUNCTION(0x2, "i2c0"),  /* SCK */
>> +  SUNXI_FUNCTION_VARIANT(0x3,
>> + "pll_lock_dbg",
>> + PINCTRL_SUN8I_R40)),
>
>You have a number of lines where the wrapping is not consistent with
>the rest, such as this one, but also...

I think this one is because of extraordinary function name.

>
>>  SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
>>SUNXI_FUNCTION(0x0, "gpio_in"),
>>SUNXI_FUNCTION(0x1, "gpio_out"),
>> -  SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
>> +  SUNXI_FUNCTION(0x2, "i2c2"),  /* SCK */
>> +  SUNXI_FUNCTION_VARIANT(0x4,
>> + "pwm", /* PWM4 */
>> + PINCTRL_SUN8I_R40)),
>
>... this one for example. Please fix this.
>
>Looks good otherwise.
>
>Maxime

[PATCH v5 06/10] regulator: axp20x-regulator: add support for AXP803

[Icenowy Zheng]

AXP803 PMIC also have a series of regulators (DCDCs and LDOs)
controllable via I2C/RSB bus.

Add support for them.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v4:
- Fixed somewhere which mention AXP806 before 803.
Changes in v2:
- Place AXP803 codes before AXP806/809 ones.
- Fixed some errors in regulator description.
- Reuse AXP803 DLDO2 range for AXP806 CLDO2 & AXP809 DLDO1.

 drivers/regulator/axp20x-regulator.c | 153 ++-
 include/linux/mfd/axp20x.h   |  37 +
 2 files changed, 168 insertions(+), 22 deletions(-)

diff --git a/drivers/regulator/axp20x-regulator.c 
b/drivers/regulator/axp20x-regulator.c
index 0b9d4e3e52c7..e2608fe770b9 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -244,6 +244,82 @@ static const struct regulator_desc 
axp22x_drivevbus_regulator = {
.ops= _ops_sw,
 };
 
+static const struct regulator_linear_range axp803_dcdc234_ranges[] = {
+   REGULATOR_LINEAR_RANGE(50, 0x0, 0x46, 1),
+   REGULATOR_LINEAR_RANGE(122, 0x47, 0x4b, 2),
+};
+
+static const struct regulator_linear_range axp803_dcdc5_ranges[] = {
+   REGULATOR_LINEAR_RANGE(80, 0x0, 0x20, 1),
+   REGULATOR_LINEAR_RANGE(114, 0x21, 0x44, 2),
+};
+
+static const struct regulator_linear_range axp803_dcdc6_ranges[] = {
+   REGULATOR_LINEAR_RANGE(60, 0x0, 0x32, 1),
+   REGULATOR_LINEAR_RANGE(112, 0x33, 0x47, 2),
+};
+
+/* AXP806's CLDO2 and AXP809's DLDO1 shares the same range */
+static const struct regulator_linear_range axp803_dldo2_ranges[] = {
+   REGULATOR_LINEAR_RANGE(70, 0x0, 0x1a, 10),
+   REGULATOR_LINEAR_RANGE(340, 0x1b, 0x1f, 20),
+};
+
+static const struct regulator_desc axp803_regulators[] = {
+   AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
+AXP803_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(0)),
+   AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2", axp803_dcdc234_ranges,
+   76, AXP803_DCDC2_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
+   BIT(1)),
+   AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3", axp803_dcdc234_ranges,
+   76, AXP803_DCDC3_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
+   BIT(2)),
+   AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4", axp803_dcdc234_ranges,
+   76, AXP803_DCDC4_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
+   BIT(3)),
+   AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5", axp803_dcdc5_ranges,
+   68, AXP803_DCDC5_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
+   BIT(4)),
+   AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6", axp803_dcdc6_ranges,
+   72, AXP803_DCDC6_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
+   BIT(5)),
+   /* secondary switchable output of DCDC1 */
+   AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2,
+   BIT(7)),
+   AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
+AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(5)),
+   AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
+AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(6)),
+   AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
+AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(7)),
+   AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
+AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(3)),
+   AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin", axp803_dldo2_ranges,
+   32, AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2,
+   BIT(4)),
+   AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
+AXP22X_DLDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)),
+   AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
+AXP22X_DLDO4_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(6)),
+   AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
+AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)),
+   AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
+AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)),
+   AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
+AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)),
+   AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 

[PATCH v5 10/10] arm64: allwinner: a64: enable Wi-Fi for Pine64

[Icenowy Zheng]

The Wi-Fi module of Pine64 is powered via DLDO4 and ELDO1 (the latter
one provides I/O voltage).

Add device node for it.

Although the Wi-Fi module is an external module which should be inserted
to a header, according to my personal talk with TL Lim, he does not want
this header to be used as GPIO (so it's with 2.0mm pitch, not 2.54mm as
other GPIO headers).

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index abc1879e91f2..2e4f44800162 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -64,6 +64,11 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
};
+
+   wifi_pwrseq: wifi_pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   reset-gpios = <_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+   };
 };
 
  {
@@ -91,6 +96,17 @@
status = "okay";
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   vmmc-supply = <_dldo4>;
+   vqmmc-supply = <_eldo1>;
+   mmc-pwrseq = <_pwrseq>;
+   non-removable;
+   bus-width = <4>;
+   status = "okay";
+};
+
  {
status = "okay";
 };
-- 
2.12.2

[PATCH v5 00/10] AXP803 PMIC support for Pine64

[Icenowy Zheng]

The Pine64 (including Pine64+) boards have an AXP803 PMIC, which is a PMIC
similar to AXP288, but tweaked to use with Allwinner SoCs rather than Intel
tablets (with DCIN and Vbus re-splitted like other AXP PMICs, and RSB bus
support added).

This patchset adds support for it and enabled it in Pine64 device tree.

The basical part of AXP803 MFD driver is already applied, according to Lee.

Thus this patchset is now still two parts, but a bit different to older
revisions:

- Part1: from PATCH 1/10 to PATCH 5/10, which focus on enabling AXP803 in
  the device tree: the RSB bus, the R_INTC interrupt controller (for the
  NMI line, which is connected to AXP803 on Pine64), and finally the basical
  AXP803 node.
- Part2: from PATCH 5/10 to PATCH 10/10, which are enabling the regulator
  function of the AXP803 PMIC. Finally Wi-Fi function is added
  as a usage of regulators function.

PATCH 1 adds RSB device nodes, which is used for the communication between
A64 and AXP803.

PATCH 2 adds device tree binding of A64 R_INTC.

PATCH 3 really adds support for A64 R_INTC in NMI driver.

PATCH 4 adds R_INTC node in A64 device tree.

PATCH 5 adds AXP803 node to the Pine64 device tree by using already
applied drivers/bindings.

PATCH 6 adds support for AXP803 regulators in AXP20x regulatoe driver.
(The binding is already applied)

PATCH 7 enables the AXP803 regulator cell in MFD driver.

PATCH 8 adds a DTSI file for AXP803, like other older AXP PMICs.

PATCH 9 enables AXP803 regulators in Pine64 device tree.

PATCH 10 enables Wi-Fi for Pine64.

Icenowy Zheng (10):
  arm64: allwinner: a64: enable RSB on A64
  irqchip/sunxi-nmi: add A64 R_INTC to the binding doc
  irqchip/sunxi-nmi: add support for the NMI in A64 R_INTC
  arm64: allwinner: a64: add NMI (R_INTC) controller on A64
  arm64: allwinner: a64: add AXP803 node to Pine64 device tree
  regulator: axp20x-regulator: add support for AXP803
  mfd: axp20x: add axp20x-regulator cell for AXP803
  arm64: allwinner: a64: add DTSI file for AXP803 PMIC
  arm64: allwinner: a64: enable AXP803 regulators for Pine64
  arm64: allwinner: a64: enable Wi-Fi for Pine64

 .../interrupt-controller/allwinner,sunxi-nmi.txt   |   7 +-
 arch/arm64/boot/dts/allwinner/axp803.dtsi  | 150 
 .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 136 ++
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi  |  27 
 drivers/irqchip/irq-sunxi-nmi.c|  13 ++
 drivers/mfd/axp20x.c   |   3 +-
 drivers/regulator/axp20x-regulator.c   | 153 ++---
 include/linux/mfd/axp20x.h |  37 +
 8 files changed, 501 insertions(+), 25 deletions(-)
 create mode 100644 arch/arm64/boot/dts/allwinner/axp803.dtsi

-- 
2.12.2

[PATCH v5 05/10] arm64: allwinner: a64: add AXP803 node to Pine64 device tree

[Icenowy Zheng]

The Pine64 (including Pine64+) boards have an AXP803 as its main PMIC.

Add its device node.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index c680ed385da3..3e1b44292534 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -95,6 +95,17 @@
status = "okay";
 };
 
+_rsb {
+   status = "okay";
+
+   axp803: pmic@3a3 {
+   compatible = "x-powers,axp803";
+   reg = <0x3a3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   };
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.12.2

[PATCH v5 01/10] arm64: allwinner: a64: enable RSB on A64

[Icenowy Zheng]

Allwinner A64 have a RSB controller like the one on A23/A33 SoCs.

Add it and its pinmux.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v2:
- Removed bonus properties in pio node.
- Added Chen-Yu's ACK.

 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index c7f669f5884f..05ec9fc5e81f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -422,6 +422,25 @@
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
+
+   r_rsb_pins: rsb@0 {
+   pins = "PL0", "PL1";
+   function = "s_rsb";
+   };
+   };
+
+   r_rsb: rsb@1f03400 {
+   compatible = "allwinner,sun8i-a23-rsb";
+   reg = <0x01f03400 0x400>;
+   interrupts = ;
+   clocks = <_ccu 6>;
+   clock-frequency = <300>;
+   resets = <_ccu 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_rsb_pins>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
};
};
 };
-- 
2.12.2

[PATCH v5 03/10] irqchip/sunxi-nmi: add support for the NMI in A64 R_INTC

[Icenowy Zheng]

Add support for the newly imported compatible for the A64 R_INTC in
irq-sunxi-nmi driver.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v5:
- Fix A64 R_INTC compatible.

 drivers/irqchip/irq-sunxi-nmi.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index 668730c5cb66..5559c1d593bf 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -56,6 +56,12 @@ static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = {
.enable = 0x04,
 };
 
+static struct sunxi_sc_nmi_reg_offs sun50i_reg_offs = {
+   .ctrl   = 0x0c,
+   .pend   = 0x10,
+   .enable = 0x40,
+};
+
 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
  u32 val)
 {
@@ -220,3 +226,10 @@ static int __init sun9i_nmi_irq_init(struct device_node 
*node,
return sunxi_sc_nmi_irq_init(node, _reg_offs);
 }
 IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);
+
+static int __init sun50i_nmi_irq_init(struct device_node *node,
+struct device_node *parent)
+{
+   return sunxi_sc_nmi_irq_init(node, _reg_offs);
+}
+IRQCHIP_DECLARE(sun50i_nmi, "allwinner,sun50i-a64-r-intc", 
sun50i_nmi_irq_init);
-- 
2.12.2

[PATCH v5 04/10] arm64: allwinner: a64: add NMI (R_INTC) controller on A64

[Icenowy Zheng]

Allwinner A64 SoC features a R_INTC controller, which controls the NMI
line, and this interrupt line is usually connected to the AXP PMIC.

Add support for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Changes it to use R_INTC binding and change node label to r_intc.
- Fixed MMIO region.
- Dropped Chen-Yu's ACK due to big change.
Changes in v2:
- Added Chen-Yu's ACK.

 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 05ec9fc5e81f..a6566d292934 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -403,6 +403,14 @@
 ;
};
 
+   r_intc: interrupt-controller@1f00c00 {
+   compatible = "allwinner,sun50i-a64-r-intc";
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   reg = <0x01f00c00 0x400>;
+   interrupts = ;
+   };
+
r_ccu: clock@1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
-- 
2.12.2

[PATCH v5 07/10] mfd: axp20x: add axp20x-regulator cell for AXP803

[Icenowy Zheng]

As axp20x-regulator now supports AXP803, add a cell for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v5:
- Removed wrong snippet.
Changes in v4:
- Added a trailing comma for new cell, for easier further cell addition.
Changes in v3:
- Make the new cell one-liner.

 drivers/mfd/axp20x.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 1dc6235778eb..917b6ddc4f15 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -848,7 +848,8 @@ static struct mfd_cell axp803_cells[] = {
.name   = "axp20x-pek",
.num_resources  = ARRAY_SIZE(axp803_pek_resources),
.resources  = axp803_pek_resources,
-   }
+   },
+   {   .name   = "axp20x-regulator" },
 };
 
 static struct mfd_cell axp806_cells[] = {
-- 
2.12.2

[PATCH v5 02/10] irqchip/sunxi-nmi: add A64 R_INTC to the binding doc

[Icenowy Zheng]

The A31 NMI driver seems to be using wrong base address.

As we're going to convert to use a correct NMI base address (and
correctly name it to R_INTC as the datasheet suggests), add a new
compatible string for the "correct" R_INTC, which we will use for A64
SoC.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 .../bindings/interrupt-controller/allwinner,sunxi-nmi.txt  | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
 
b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
index 81cd3692405e..fea0c6a6211f 100644
--- 
a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
@@ -3,8 +3,11 @@ Allwinner Sunxi NMI Controller
 
 Required properties:
 
-- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
-  "allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi"
+- compatible : should be one of:
+   "allwinner,sun6i-a31-sc-nmi"
+   "allwinner,sun7i-a20-sc-nmi"
+   "allwinner,sun9i-a80-nmi"
+   "allwinner,sun50i-a64-r-intc"
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.12.2

[PATCH v5 08/10] arm64: allwinner: a64: add DTSI file for AXP803 PMIC

[Icenowy Zheng]

As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it,
like the old DTSI files for AXP20x/22x, for the common parts of the
PMIC.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Mark Brown <broo...@kernel.org>
---
Changes in v5:
- Added Mark Brown's ACK.
Changes in v4:
- Re-sorted the nodes.

 arch/arm64/boot/dts/allwinner/axp803.dtsi | 150 ++
 1 file changed, 150 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/axp803.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi 
b/arch/arm64/boot/dts/allwinner/axp803.dtsi
new file mode 100644
index ..ff8af52743ff
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2017 Icenowy Zheng <icen...@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * AXP803 Integrated Power Management Chip
+ * http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf
+ */
+
+ {
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   regulators {
+   /* Default work frequency for buck regulators */
+   x-powers,dcdc-freq = <3000>;
+
+   reg_aldo1: aldo1 {
+   regulator-name = "aldo1";
+   };
+
+   reg_aldo2: aldo2 {
+   regulator-name = "aldo2";
+   };
+
+   reg_aldo3: aldo3 {
+   regulator-name = "aldo3";
+   };
+
+   reg_dc1sw: dc1sw {
+   regulator-name = "dc1sw";
+   };
+
+   reg_dcdc1: dcdc1 {
+   regulator-name = "dcdc1";
+   };
+
+   reg_dcdc2: dcdc2 {
+   regulator-name = "dcdc2";
+   };
+
+   reg_dcdc3: dcdc3 {
+   regulator-name = "dcdc3";
+   };
+
+   reg_dcdc4: dcdc4 {
+   regulator-name = "dcdc4";
+   };
+
+   reg_dcdc5: dcdc5 {
+   regulator-name = "dcdc5";
+   };
+
+   reg_dcdc6: dcdc6 {
+   regulator-name = "dcdc6";
+   };
+
+   reg_dldo1: dldo1 {
+   regulator-name = "dldo1";
+   };
+
+   reg_dldo2: dldo2 {
+   regulator-name = "dldo2";
+   };
+
+   reg_dldo3: dldo3 {
+   regulator-name = "dldo3";
+   };
+
+   reg_dldo4: dldo4 {
+   regulator-name = "dldo4";
+   };
+
+   reg_eldo1: eldo1 {
+   regulator-name = "eldo1";
+   };
+
+   reg_eldo2: eldo2 {
+   regulator-name = "eldo2";

[PATCH v5 09/10] arm64: allwinner: a64: enable AXP803 regulators for Pine64

[Icenowy Zheng]

Add support of AXP803 regulators in the Pine64 device tree, in order to
enable many future functionalities, e.g. Wi-Fi.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109 +
 1 file changed, 109 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 3e1b44292534..abc1879e91f2 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -106,6 +106,115 @@
};
 };
 
+#include "axp803.dtsi"
+
+_aldo1 {
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   regulator-name = "vcc-csi";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pl";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc1sw {
+   regulator-name = "vcc-phy";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-3v3";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <100>;
+   regulator-max-microvolt = <130>;
+   regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_dcdc6 {
+   regulator-always-on;
+   regulator-min-microvolt = <110>;
+   regulator-max-microvolt = <110>;
+   regulator-name = "vdd-sys";
+};
+
+_dldo1 {
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-hdmi";
+};
+
+_dldo2 {
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-mipi";
+};
+
+_dldo3 {
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "avdd-csi";
+};
+
+_dldo4 {
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-wifi";
+};
+
+_eldo1 {
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "cpvdd";
+};
+
+_eldo3 {
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "vdd-1v8-csi";
+};
+
+_fldo1 {
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   regulator-name = "vcc-1v2-hsic";
+};
+
+_fldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <110>;
+   regulator-max-microvolt = <110>;
+   regulator-name = "vdd-cpus";
+};
+
+_rtc_ldo {
+   regulator-name = "vcc-rtc";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.12.2

Re: [linux-sunxi] Re: [PATCH v4 07/10] mfd: axp20x: add axp20x-regulator cell for AXP803

[Icenowy Zheng]

于 2017年4月25日 GMT+08:00 下午3:57:17, Lee Jones <lee.jo...@linaro.org> 写到:
>On Tue, 25 Apr 2017, Icenowy Zheng wrote:
>
>> As axp20x-regulator now supports AXP803, add a cell for it.
>> 
>> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>> Acked-by: Chen-Yu Tsai <w...@csie.org>
>> ---
>> Changes in v4:
>> - Added a trailing comma for new cell, for easier further cell
>addition.
>> Changes in v3:
>> - Make the new cell one-liner.
>> 
>>  drivers/mfd/axp20x.c | 3 ++-
>>  drivers/regulator/axp20x-regulator.c | 6 +++---
>
>These 2 changes are orthogonal, thus there is no reason to send them
>bundled into a single patch.  Doing so complicates things greatly.
>Please resubmit the two changes separately, so that they may be
>absorbed by our respective subsystems.

Yes. As Chen-Yu said, I wrongly squashed the regulator renaming patch here...

It should be squashed into the regulator patch.

Sorry for it.

>
>>  2 files changed, 5 insertions(+), 4 deletions(-)
>> 
>> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
>> index 1dc6235778eb..917b6ddc4f15 100644
>> --- a/drivers/mfd/axp20x.c
>> +++ b/drivers/mfd/axp20x.c
>> @@ -848,7 +848,8 @@ static struct mfd_cell axp803_cells[] = {
>>  .name   = "axp20x-pek",
>>  .num_resources  = ARRAY_SIZE(axp803_pek_resources),
>>  .resources  = axp803_pek_resources,
>> -}
>> +},
>> +{   .name   = "axp20x-regulator" },
>>  };
>>  
>>  static struct mfd_cell axp806_cells[] = {
>> diff --git a/drivers/regulator/axp20x-regulator.c
>b/drivers/regulator/axp20x-regulator.c
>> index 9356ec8a9a1f..e2608fe770b9 100644
>> --- a/drivers/regulator/axp20x-regulator.c
>> +++ b/drivers/regulator/axp20x-regulator.c
>> @@ -311,13 +311,13 @@ static const struct regulator_desc
>axp803_regulators[] = {
>>   AXP803_FLDO1_V_OUT, 0x0f, AXP22X_PWR_OUT_CTRL3, BIT(2)),
>>  AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
>>   AXP803_FLDO2_V_OUT, 0x0f, AXP22X_PWR_OUT_CTRL3, BIT(3)),
>> -AXP_DESC_IO(AXP803, LDO_IO0, "ldo_io0", "ips", 700, 3300, 100,
>> +AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
>>  AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07,
>>  AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
>> -AXP_DESC_IO(AXP803, LDO_IO1, "ldo_io1", "ips", 700, 3300, 100,
>> +AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
>>  AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07,
>>  AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
>> -AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc_ldo", "ips", 3000),
>> +AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),
>>  };
>>  
>>  static const struct regulator_linear_range axp806_dcdca_ranges[] = {

Re: [linux-sunxi] [PATCH v4 09/10] arm64: allwinner: a64: enable AXP803 regulators for Pine64

[Icenowy Zheng]

于 2017年4月25日 GMT+08:00 下午5:24:13, Andre Przywara <andre.przyw...@arm.com> 写到:
>Hi,
>
>On 24/04/17 17:01, Icenowy Zheng wrote:
>> Add support of AXP803 regulators in the Pine64 device tree, in order
>to
>> enable many future functionalities, e.g. Wi-Fi.
>
>In general that's quite some code to just achieve some device power
>plane switching, but that's another discussion, I guess ;-)
>
>To me this patch here like a lot of churn to be duplicated in each
>board's DT.
>Can't we provide some sane defaults, either in axp803.dtsi or in an
>extra file (allwinner-ref-axp803.dtsi?), and only overwrite them in a
>board's DT if a board deviates?

For critical regulators you're right, however, peripherals' power seems to vary 
a lot, e.g. Wi-Fi and HDMI.

The DLDO1 for HDMI and DLDO4 for Wi-Fi design is only adopted by Pine64; 
according to BPi M64 schematics, Wi-Fi is DLDO2 and Wi-Fi IO voltage is DLDO4 
(on Pine64 it's ELDO1 which is forced to be 1.8v because it's connected to 
CPVDD); on Orange Pi Win {,Plus} Wi-Fi is ALDO1, Wi-Fi IO is DLDO4 and HDMI is 
DLDO3.

>Because it seems like many boards are actually based on some Allwinner
>reference design and use very similar, if not identical settings.
>
>Also one thing below ...
>
>> 
>> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>> ---
>>  .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109
>+
>>  1 file changed, 109 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
>b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
>> index 3e1b44292534..abc1879e91f2 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
>> @@ -106,6 +106,115 @@
>>  };
>>  };
>>  
>> +#include "axp803.dtsi"
>> +
>> +_aldo1 {
>> +regulator-min-microvolt = <280>;
>> +regulator-max-microvolt = <280>;
>> +regulator-name = "vcc-csi";
>> +};
>> +
>> +_aldo2 {
>> +regulator-always-on;
>> +regulator-min-microvolt = <180>;
>> +regulator-max-microvolt = <330>;
>> +regulator-name = "vcc-pl";
>> +};
>> +
>> +_aldo3 {
>> +regulator-always-on;
>> +regulator-min-microvolt = <270>;
>> +regulator-max-microvolt = <330>;
>> +regulator-name = "vcc-pll-avcc";
>> +};
>> +
>> +_dc1sw {
>> +regulator-name = "vcc-phy";
>> +};
>> +
>> +_dcdc1 {
>> +regulator-always-on;
>> +regulator-min-microvolt = <330>;
>> +regulator-max-microvolt = <330>;
>> +regulator-name = "vcc-3v3";
>> +};
>> +
>> +_dcdc2 {
>> +regulator-always-on;
>> +regulator-min-microvolt = <100>;
>> +regulator-max-microvolt = <130>;
>> +regulator-name = "vdd-cpux";
>> +};
>> +
>> +/* DCDC3 is polyphased with DCDC2 */
>> +
>> +_dcdc5 {
>> +regulator-always-on;
>> +regulator-min-microvolt = <150>;
>> +regulator-max-microvolt = <150>;
>
>On the Pine64 there is DDR3L DRAM, running at 1.35V.
>
>Cheers,
>Andre.
>
>
>> +regulator-name = "vcc-dram";
>> +};
>> +
>> +_dcdc6 {
>> +regulator-always-on;
>> +regulator-min-microvolt = <110>;
>> +regulator-max-microvolt = <110>;
>> +regulator-name = "vdd-sys";
>> +};
>> +
>> +_dldo1 {
>> +regulator-min-microvolt = <330>;
>> +regulator-max-microvolt = <330>;
>> +regulator-name = "vcc-hdmi";
>> +};
>> +
>> +_dldo2 {
>> +regulator-min-microvolt = <330>;
>> +regulator-max-microvolt = <330>;
>> +regulator-name = "vcc-mipi";
>> +};
>> +
>> +_dldo3 {
>> +regulator-min-microvolt = <330>;
>> +regulator-max-microvolt = <330>;
>> +regulator-name = "avdd-csi";
>> +};
>> +
>> +_dldo4 {
>> +regulator-min-microvolt = <330>;
>> +regulator-max-microvolt = <330>;
>> +regulator-name = "vcc-wifi";
>> +};
>> +
>> +_eldo1 {
>> +regulator-min-microvolt = <180>;
>> +regulator-max-microvolt = <180>;
>> +regulator-name = "cpvdd";
>> +};
>> +
>> +_eldo3 {
>> +regulator-min-microvolt = <180>;
>> +regulator-max-microvolt = <180>;
>> +regulator-name = "vdd-1v8-csi";
>> +};
>> +
>> +_fldo1 {
>> +regulator-min-microvolt = <120>;
>> +regulator-max-microvolt = <120>;
>> +regulator-name = "vcc-1v2-hsic";
>> +};
>> +
>> +_fldo2 {
>> +regulator-always-on;
>> +regulator-min-microvolt = <110>;
>> +regulator-max-microvolt = <110>;
>> +regulator-name = "vdd-cpus";
>> +};
>> +
>> +_rtc_ldo {
>> +regulator-name = "vcc-rtc";
>> +};
>> +
>>   {
>>  pinctrl-names = "default";
>>  pinctrl-0 = <_pins_a>;
>> 

[PATCH 1/2] mmc: sunxi: fix support for new timings mode only SoCs

[Icenowy Zheng]

The A83T MMC support code introduces the timings mode switch, however
such a switch doesn't exist on new SoCs with only new timings mode.

Only execute the switch if the SoC really have the timings mode switch,
to fix the regression shown on new timings mode only SoCs (A64, H5,
etc).

Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use both
old and new timings")

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/mmc/host/sunxi-mmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 3777517982dd..59aba93beffb 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -784,7 +784,7 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
clock <<= 1;
}
 
-   if (host->use_new_timings) {
+   if (host->use_new_timings && host->cfg->has_timings_switch) {
ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
if (ret) {
dev_err(mmc_dev(mmc),
-- 
2.13.0

[PATCH 2/2] mmc: sunxi: fix new timings mode on A64 EMMC (MMC2) controller

[Icenowy Zheng]

The configuration struct of A64 EMMC(MMC2) compatible used to
have the needs_new_timings variable missing, which lead to NULL
pointer dereference now when trying to set up the old timings mode, as
the old timings mode doesn't exist at all on A64.

Fix this issue by adding this variable and setting it to true in
the configuration struct.

Fixes: 4fb3ce07eafa ("mmc: sunxi: Add EMMC (MMC2) controller compatible")

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/mmc/host/sunxi-mmc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 59aba93beffb..4ad643e37014 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1142,6 +1142,7 @@ static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
.idma_des_size_bits = 13,
.clk_delays = NULL,
.can_calibrate = true,
+   .needs_new_timings = true,
 };
 
 static const struct of_device_id sunxi_mmc_of_match[] = {
-- 
2.13.0

Re: [linux-sunxi] [PATCH 2/2] mmc: sunxi: fix new timings mode on A64 EMMC (MMC2) controller

[Icenowy Zheng]

于 2017年8月6日 GMT+08:00 上午10:39:54, Chen-Yu Tsai <w...@csie.org> 写到:
>On Sat, Aug 05, 2017 at 05:35:55AM +0800, Icenowy Zheng wrote:
>> The configuration struct of A64 EMMC(MMC2) compatible used to
>> have the needs_new_timings variable missing, which lead to NULL
>> pointer dereference now when trying to set up the old timings mode,
>as
>> the old timings mode doesn't exist at all on A64.
>
>I'm not familiar with the A64's eMMC controller. The datasheet says
>it does not have the timing switch register. It does not say whether
>it is always in the old or new timing mode. "needs_new_timings"
>probably meant that the switch has to be set.

As I know, it supports DDR mode, but the CCU has no clk delays.
So it should be the new timings mode.

>
>This fix doesn't really fix the underlying issue, which is the check
>for clk_delays was incorrectly replaced. sun4i/sun5i is also broken.
>
>Could you try this patch instead:
>
><---
>
>From 23b841a11294cb6a0cf1e146616b068f60c2ec7d Mon Sep 17 00:00:00 2001
>From: Chen-Yu Tsai <w...@csie.org>
>Date: Sun, 6 Aug 2017 10:24:47 +0800
>Subject: [PATCH] mmc: sunxi: Fix NULL pointer reference on clk_delays
>
>Some SoCs do not support clk delays for MMC in the clock control unit.
>These include the old controllers in A10/A10s/A13/R8, and the new eMMC
>controller in A64. The config structure for these controllers do not
>specify clk_delays, but the check for this was replaced in commit
>b0600daebf31 ("mmc: sunxi: Support controllers that can use both old
>and new timings").
>
>This patch adds back the check for clk_delays, and also adds comments
>for both checks in sunxi_mmc_clk_set_phase().
>
>Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use
> both old and new timings")
>Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>---
> drivers/mmc/host/sunxi-mmc.c | 5 +
> 1 file changed, 5 insertions(+)
>
>diff --git a/drivers/mmc/host/sunxi-mmc.c
>b/drivers/mmc/host/sunxi-mmc.c
>index 3777517982dd..020547e5fa45 100644
>--- a/drivers/mmc/host/sunxi-mmc.c
>+++ b/drivers/mmc/host/sunxi-mmc.c
>@@ -722,9 +722,14 @@ static int sunxi_mmc_clk_set_phase(struct
>sunxi_mmc_host *host,
> {
>   int index;
> 
>+  /* No need to set clk controller delays under new timings */
>   if (host->use_new_timings)
>   return 0;
> 
>+  /* Some old controllers don't support delays */
>+  if (!host->cfg->clk_delays)
>+  return 0;
>+
>   /* determine delays */
>   if (rate <= 40) {
>   index = SDXC_CLK_400K;

[PATCH v2] mmc: sunxi: fix support for new timings mode only SoCs

[Icenowy Zheng]

The A83T MMC support code introduces the timings mode switch, however
such a switch doesn't exist on new SoCs with only new timings mode.

Only execute the switch if the SoC really have the timings mode switch,
to fix the regression shown on new timings mode only SoCs (A64, H5,
etc).

Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use
  both old and new timings")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v2:
- Slightly adjusted the format of the Fixes: line/
- Added review tag from Chen-Yu.

 drivers/mmc/host/sunxi-mmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 020547e5fa45..7447d41833ee 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -789,7 +789,7 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
clock <<= 1;
}
 
-   if (host->use_new_timings) {
+   if (host->use_new_timings && host->cfg->has_timings_switch) {
ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
if (ret) {
dev_err(mmc_dev(mmc),
-- 
2.13.0

[PATCH 2/4] drivers: soc: sunxi: fix error processing on base address when claiming

[Icenowy Zheng]

When claiming SRAM, if the base is set to an error, it means that the
SRAM controller has been probed, but failed to remap the controller
memory zone. If the base is zero, thus the SRAM controller should be not
probed at all, and it should return -EPROBE_DEFER. However, currently we
returned -EPROBE_DEFER in the former situation, and ignored the latter
situation (which will lead to the kernel to panic).

Fix the behavior on abnormal base address processing when claiming.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/soc/sunxi/sunxi_sram.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index 99e354c8f53f..c1ff7fa62cb4 100644
--- a/drivers/soc/sunxi/sunxi_sram.c
+++ b/drivers/soc/sunxi/sunxi_sram.c
@@ -190,6 +190,9 @@ int sunxi_sram_claim(struct device *dev)
u32 val, mask;
 
if (IS_ERR(base))
+   return PTR_ERR(base);
+
+   if (!base)
return -EPROBE_DEFER;
 
if (!dev || !dev->of_node)
-- 
2.13.0

[PATCH 3/4] drivers: soc: sunxi: add support for remapping func value to reg value

[Icenowy Zheng]

On some Allwinner SoCs, sometimes the value needed to write into the
register to claim SRAM is not equal to the value specified in the
device tree.

We now defines 0 as "CPU" and 1 as "Device", however, for VE SRAM, the
register needs to be written 0x7FFF to claim it to VE, and for
Allwinner A64's SRAM C the needed register value to claim it to DE2 is
0, and the value that enables CPU's access to the SRAM is 1.

Add a value remapping in sunxi_sram_func structure, and let the
sunxi_sram_of_parse function set the remapped register value.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/soc/sunxi/sunxi_sram.c | 43 +-
 1 file changed, 34 insertions(+), 9 deletions(-)

diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index c1ff7fa62cb4..edc993480020 100644
--- a/drivers/soc/sunxi/sunxi_sram.c
+++ b/drivers/soc/sunxi/sunxi_sram.c
@@ -23,6 +23,7 @@
 struct sunxi_sram_func {
char*func;
u8  val;
+   u32 reg_val;
 };
 
 struct sunxi_sram_data {
@@ -39,10 +40,11 @@ struct sunxi_sram_desc {
boolclaimed;
 };
 
-#define SUNXI_SRAM_MAP(_val, _func)\
+#define SUNXI_SRAM_MAP(_reg_val, _val, _func)  \
{   \
.func = _func,  \
.val = _val,\
+   .reg_val = _reg_val,\
}
 
 #define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...)\
@@ -57,14 +59,14 @@ struct sunxi_sram_desc {
 
 static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = {
.data   = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
- SUNXI_SRAM_MAP(0, "cpu"),
- SUNXI_SRAM_MAP(1, "emac")),
+ SUNXI_SRAM_MAP(0, 0, "cpu"),
+ SUNXI_SRAM_MAP(1, 1, "emac")),
 };
 
 static struct sunxi_sram_desc sun4i_a10_sram_d = {
.data   = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
- SUNXI_SRAM_MAP(0, "cpu"),
- SUNXI_SRAM_MAP(1, "usb-otg")),
+ SUNXI_SRAM_MAP(0, 0, "cpu"),
+ SUNXI_SRAM_MAP(1, 1, "usb-otg")),
 };
 
 static const struct of_device_id sunxi_sram_dt_ids[] = {
@@ -121,7 +123,8 @@ static int sunxi_sram_show(struct seq_file *s, void *data)
 
for (func = sram_data->func; func->func; func++) {
seq_printf(s, "\t\t%s%c\n", func->func,
-  func->val == val ? '*' : ' ');
+  func->reg_val == val ?
+  '*' : ' ');
}
}
 
@@ -149,10 +152,13 @@ static inline struct sunxi_sram_desc *to_sram_desc(const 
struct sunxi_sram_data
 }
 
 static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node 
*node,
-unsigned int *value)
+unsigned int 
*reg_value)
 {
const struct of_device_id *match;
+   const struct sunxi_sram_data *data;
+   struct sunxi_sram_func *func;
struct of_phandle_args args;
+   u8 val;
int ret;
 
ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0,
@@ -165,8 +171,7 @@ static const struct sunxi_sram_data 
*sunxi_sram_of_parse(struct device_node *nod
goto err;
}
 
-   if (value)
-   *value = args.args[0];
+   val = args.args[0];
 
match = of_match_node(sunxi_sram_dt_ids, args.np);
if (!match) {
@@ -174,6 +179,26 @@ static const struct sunxi_sram_data 
*sunxi_sram_of_parse(struct device_node *nod
goto err;
}
 
+   data = match->data;
+   if (!data) {
+   ret = -EINVAL;
+   goto err;
+   };
+
+   for (func = data->func; func->func; func++) {
+   if (val == func->val) {
+   if (reg_value)
+   *reg_value = func->reg_val;
+
+   break;
+   }
+   }
+
+   if (!func->func) {
+   ret = -EINVAL;
+   goto err;
+   }
+
of_node_put(args.np);
return match->data;
 
-- 
2.13.0

[PATCH 0/4] Allwinner A64 SRAM C (DE2 SRAM) support

[Icenowy Zheng]

The DE2 in Allwinner A64 SoC requires the SRAM C to be claimed to work.

This patchset adds the support of SRAM C in A64 for the sunxi-sram driver.

As the SRAM C controlling bit is a little different with other peripherals'
SRAM controlling bit (inverted), a function value to register value
remapping is added, which is also useful for the SRAM C1 (VE SRAM) on some
SoCs.

Patch 1 is the device tree binding patch.

Patch 2 is a fix for the usage of the DE2 SRAM -- as it's claimed by a
clock driver, and kernel are trying to probe the DE2 clock driver before
probing sunxi-sram driver; this patch fixed probe defering when claiming
SRAM region.

Patch 3 adds the remapping code.

Patch 4 adds necessary codes for A64 SRAM C.

Icenowy Zheng (4):
  dt-bindings: add binding for Allwinner A64 SRAM controller and SRAM C
  drivers: soc: sunxi: fix error processing on base address when
claiming
  drivers: soc: sunxi: add support for remapping func value to reg value
  drivers: soc: sunxi: add support for A64 and its SRAM C

 .../devicetree/bindings/sram/sunxi-sram.txt|  9 +++-
 drivers/soc/sunxi/sunxi_sram.c | 57 ++
 2 files changed, 55 insertions(+), 11 deletions(-)

-- 
2.13.0

[PATCH 1/4] dt-bindings: add binding for Allwinner A64 SRAM controller and SRAM C

[Icenowy Zheng]

The display engine on Allwinner A64 wants to claim the SRAM C section.

Add a SRAM controller compatible for A64, and a SRAM section compatible
for its SRAM C.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 Documentation/devicetree/bindings/sram/sunxi-sram.txt | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt 
b/Documentation/devicetree/bindings/sram/sunxi-sram.txt
index 8d5665468fe7..f34b3a553d7c 100644
--- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt
+++ b/Documentation/devicetree/bindings/sram/sunxi-sram.txt
@@ -9,7 +9,9 @@ Controller Node
 ---
 
 Required properties:
-- compatible : "allwinner,sun4i-a10-sram-controller"
+- compatible : should be:
+- "allwinner,sun4i-a10-sram-controller"
+- "allwinner,sun50i-a64-sram-controller"
 - reg : sram controller register offset + length
 
 SRAM nodes
@@ -22,10 +24,13 @@ Each SRAM will have SRAM sections that are going to be 
handled by the
 SRAM controller as subnodes. These sections are represented following
 once again the representation described in the mmio-sram binding.
 
-The valid sections compatible are:
+The valid sections compatible for A10 are:
 - allwinner,sun4i-a10-sram-a3-a4
 - allwinner,sun4i-a10-sram-d
 
+The valid sections compatible for A64 are:
+- allwinner,sun50i-a64-sram-c
+
 Devices using SRAM sections
 ---
 
-- 
2.13.0

[PATCH 4/4] drivers: soc: sunxi: add support for A64 and its SRAM C

[Icenowy Zheng]

Allwinner A64's display engine claims the SRAM C section to work.

Add support for the A64 SRAM controller and the SRAM C section of it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/soc/sunxi/sunxi_sram.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index edc993480020..882be5ed7e84 100644
--- a/drivers/soc/sunxi/sunxi_sram.c
+++ b/drivers/soc/sunxi/sunxi_sram.c
@@ -69,6 +69,12 @@ static struct sunxi_sram_desc sun4i_a10_sram_d = {
  SUNXI_SRAM_MAP(1, 1, "usb-otg")),
 };
 
+static struct sunxi_sram_desc sun50i_a64_sram_c = {
+   .data   = SUNXI_SRAM_DATA("C", 0x4, 24, 1,
+ SUNXI_SRAM_MAP(0, 1, "cpu"),
+ SUNXI_SRAM_MAP(1, 0, "de2")),
+};
+
 static const struct of_device_id sunxi_sram_dt_ids[] = {
{
.compatible = "allwinner,sun4i-a10-sram-a3-a4",
@@ -78,6 +84,10 @@ static const struct of_device_id sunxi_sram_dt_ids[] = {
.compatible = "allwinner,sun4i-a10-sram-d",
.data   = _a10_sram_d.data,
},
+   {
+   .compatible = "allwinner,sun50i-a64-sram-c",
+   .data   = _a64_sram_c.data,
+   },
{}
 };
 
@@ -295,6 +305,7 @@ static int sunxi_sram_probe(struct platform_device *pdev)
 
 static const struct of_device_id sunxi_sram_dt_match[] = {
{ .compatible = "allwinner,sun4i-a10-sram-controller" },
+   { .compatible = "allwinner,sun50i-a64-sram-controller" },
{ },
 };
 MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
-- 
2.13.0

[PATCH] pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base

[Icenowy Zheng]

The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not workarounded when
developing the driver, which makes IRQ not working.

Fix the IRQ bank base.

Fixes: 56d9e4a76039 ("pinctrl: sunxi: add driver for V3s SoC")
Cc: sta...@vger.kernel.org
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c 
b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
index c86d3c42a905..496ba34e1f5f 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
@@ -297,6 +297,7 @@ static const struct sunxi_pinctrl_desc 
sun8i_v3s_pinctrl_data = {
.pins = sun8i_v3s_pins,
.npins = ARRAY_SIZE(sun8i_v3s_pins),
.irq_banks = 2,
+   .irq_bank_base = 1,
.irq_read_needs_mux = true
 };
 
-- 
2.13.0

[PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

[Icenowy Zheng]

Allwinner H3 features a "Display Engine 2.0".

Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- H3 Display engine

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 .../bindings/display/sunxi/sun4i-drm.txt   | 25 ++
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 2ee6ff0ef98e..92512953943e 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -87,18 +87,17 @@ Required properties:
* allwinner,sun6i-a31-tcon
* allwinner,sun6i-a31s-tcon
* allwinner,sun8i-a33-tcon
+   * allwinner,sun8i-h3-tcon
* allwinner,sun8i-v3s-tcon
  - reg: base address and size of memory-mapped region
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the TCON. Three are needed:
- 'ahb': the interface clocks
-   - 'tcon-ch0': The clock driving the TCON channel 0
  - resets: phandles to the reset controllers driving the encoder
- "lcd": the reset line for the TCON channel 0
 
  - clock-names: the clock names mentioned above
  - reset-names: the reset names mentioned above
- - clock-output-names: Name of the pixel clock created
 
 - ports: A ports node with endpoint definitions as defined in
   Documentation/devicetree/bindings/media/video-interfaces.txt. The
@@ -112,7 +111,23 @@ Required properties:
   channel the endpoint is associated to. If that property is not
   present, the endpoint number will be used as the channel number.
 
-On SoCs other than the A33 and V3s, there is one more clock required:
+For the following compatibles:
+   * allwinner,sun5i-a13-tcon
+   * allwinner,sun6i-a31-tcon
+   * allwinner,sun6i-a31s-tcon
+   * allwinner,sun8i-a33-tcon
+   * allwinner,sun8i-v3s-tcon
+there is one more clock and one more property required:
+ - clocks:
+   - 'tcon-ch0': The clock driving the TCON channel 0
+ - clock-output-names: Name of the pixel clock created
+
+For the following compatibles:
+   * allwinner,sun5i-a13-tcon
+   * allwinner,sun6i-a31-tcon
+   * allwinner,sun6i-a31s-tcon
+   * allwinner,sun8i-h3-tcon
+there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
 
 DRC
@@ -207,6 +222,8 @@ supported.
 Required properties:
   - compatible: value must be one of:
 * allwinner,sun8i-v3s-de2-mixer
+* allwinner,sun8i-h3-de2-mixer0
+* allwinner,sun8i-h3-de2-mixer1
   - reg: base address and size of the memory-mapped region.
   - clocks: phandles to the clocks feeding the mixer
 * bus: the mixer interface clock
@@ -218,7 +235,6 @@ Required properties:
   Documentation/devicetree/bindings/media/video-interfaces.txt. The
   first port should be the input endpoints, the second one the output
 
-
 Display Engine Pipeline
 ---
 
@@ -233,6 +249,7 @@ Required properties:
 * allwinner,sun6i-a31-display-engine
 * allwinner,sun6i-a31s-display-engine
 * allwinner,sun8i-a33-display-engine
+* allwinner,sun8i-h3-display-engine
 * allwinner,sun8i-v3s-display-engine
 
   - allwinner,pipelines: list of phandle to the display engine
-- 
2.13.0

[PATCH 08/13] [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi

[Icenowy Zheng]

From: Jernej Skrabec 

Some custom phys don't support hpd interrupts. Add support for polling
such events.

Signed-off-by: Jernej Skrabec 
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 60faf2d2bc6b..6c6466c6297c 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1942,7 +1942,11 @@ static int dw_hdmi_bridge_attach(struct drm_bridge 
*bridge)
struct drm_connector *connector = >connector;
 
connector->interlace_allowed = 1;
-   connector->polled = DRM_CONNECTOR_POLL_HPD;
+   if (hdmi->phy.ops->setup_hpd)
+   connector->polled = DRM_CONNECTOR_POLL_HPD;
+   else
+   connector->polled = DRM_CONNECTOR_POLL_CONNECT |
+   DRM_CONNECTOR_POLL_DISCONNECT;
 
drm_connector_helper_add(connector, _hdmi_connector_helper_funcs);
 
-- 
2.13.0

[PATCH 09/13] [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the dw_hdmi driver

[Icenowy Zheng]

From: Jernej Skrabec 

Some platform glues of DesignWare HDMI controller require some
initialization to be performed before probing the main HDMI controller.

Add a pre_init function for this kind of work.

Signed-off-by: Jernej Skrabec 
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 +++
 include/drm/bridge/dw_hdmi.h  | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 6c6466c6297c..1e69b7631cae 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2343,6 +2343,9 @@ __dw_hdmi_probe(struct platform_device *pdev,
goto err_isfr;
}
 
+   if (plat_data->pre_init)
+   plat_data->pre_init(plat_data->pre_init_data);
+
/* Product and revision IDs */
hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
  | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 182f83283e24..6e109c336ca1 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -128,6 +128,8 @@ struct dw_hdmi_plat_data {
   const struct drm_display_mode *mode);
unsigned long input_bus_format;
unsigned long input_bus_encoding;
+   void (*pre_init)(void *data);
+   void *pre_init_data;
 
/* Vendor PHY support */
const struct dw_hdmi_phy_ops *phy_ops;
-- 
2.13.0

[PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

[Icenowy Zheng]

As we have already the support for the DE2 on Allwinner H3, add the
display engine pipeline device tree nodes to its DTSI file.

The H5 pipeline has some differences and will be enabled later.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 170 
 1 file changed, 170 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..75ad7b65a7fc 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -41,6 +41,8 @@
  */
 
 #include "sunxi-h3-h5.dtsi"
+#include 
+#include 
 
 / {
cpus {
@@ -72,6 +74,174 @@
};
};
 
+   de: display-engine {
+   compatible = "allwinner,sun8i-h3-display-engine";
+   allwinner,pipelines = <>,
+ <>;
+   status = "disabled";
+   };
+
+   soc {
+   display_clocks: clock@100 {
+   compatible = "allwinner,sun8i-a83t-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_BUS_DE>,
+< CLK_DE>;
+   clock-names = "bus",
+ "mod";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   assigned-clocks = < CLK_DE>;
+   assigned-clock-parents = < CLK_PLL_DE>;
+   assigned-clock-rates = <43200>;
+   };
+
+   mixer0: mixer@110 {
+   compatible = "allwinner,sun8i-h3-de2-mixer0";
+   reg = <0x0110 0x10>;
+   clocks = <_clocks CLK_BUS_MIXER0>,
+<_clocks CLK_MIXER0>;
+   clock-names = "bus",
+ "mod";
+   resets = <_clocks RST_MIXER0>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mixer0_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   mixer0_out_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_in_mixer0>;
+   };
+
+   mixer0_out_tcon1: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<_in_mixer0>;
+   };
+   };
+   };
+   };
+
+   mixer1: mixer@120 {
+   compatible = "allwinner,sun8i-h3-de2-mixer1";
+   reg = <0x0120 0x10>;
+   clocks = <_clocks CLK_BUS_MIXER1>,
+<_clocks CLK_MIXER1>;
+   clock-names = "bus",
+ "mod";
+   resets = <_clocks RST_WB>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mixer1_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   mixer1_out_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_in_mixer1>;
+   };
+
+   mixer1_out_tcon1: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<_in_mixer1>;
+   };
+   };
+   };
+   };
+
+   tcon0: lcd-controller@1c0c000 {
+   compatible = "allwinner,sun8i-h3-tcon"

[PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

[Icenowy Zheng]

From: Jernej Skrabec <jernej.skra...@siol.net>

When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.

Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.

Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index b1127e8629d9..2ebb3d865b01 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,  "avs",  
"osc24M",
 
 static const char * const hdmi_parents[] = { "pll-video" };
 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
-0x150, 0, 4, 24, 2, BIT(31), 0);
+0x150, 0, 4, 24, 2, BIT(31), 
CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_GATE(hdmi_ddc_clk,"hdmi-ddc", "osc24M",
  0x154, BIT(31), 0);
-- 
2.13.0

[PATCH 02/13] drm: sun4i: add support for H3 mixers

[Icenowy Zheng]

From: Icenowy Zheng <icen...@aosc.xyz>

Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels,
and the other has 1 VI and 1 UI. There's also some graphics post-process
function that is missing on mixer1, however, as we currently support
none of these functions, the only difference that is shown to us is the
channel number difference.

Add support for these two variants.

Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
 drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c 
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index cb193c5f1686..d658a3a8159a 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -390,11 +390,29 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = 
{
.ui_num = 1,
 };
 
+static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
+   .vi_num = 1,
+   .ui_num = 3,
+};
+
+static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = {
+   .vi_num = 1,
+   .ui_num = 1,
+};
+
 static const struct of_device_id sun8i_mixer_of_table[] = {
{
.compatible = "allwinner,sun8i-v3s-de2-mixer",
.data = _v3s_mixer_cfg,
},
+   {
+   .compatible = "allwinner,sun8i-h3-de2-mixer0",
+   .data = _h3_mixer0_cfg
+   },
+   {
+   .compatible = "allwinner,sun8i-h3-de2-mixer1",
+   .data = _h3_mixer1_cfg
+   },
{ }
 };
 MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
-- 
2.13.0

[PATCH 04/13] drm: sun4i: add compatible for H3 display engine

[Icenowy Zheng]

Add a compatible string for H3 display engine in sun4i_drv code.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index fd99fe8a4df7..02c80bb7b385 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -314,6 +314,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun6i-a31-display-engine" },
{ .compatible = "allwinner,sun6i-a31s-display-engine" },
{ .compatible = "allwinner,sun8i-a33-display-engine" },
+   { .compatible = "allwinner,sun8i-h3-display-engine" },
{ .compatible = "allwinner,sun8i-v3s-display-engine" },
{ }
 };
-- 
2.13.0

[PATCH 06/13] clk: sunxi-ng: export CLK_PLL_DE for H3

[Icenowy Zheng]

The CLK_PLL_DE is needed to be referenced in device tree for H3, for
both forcing the parent of PLL_DE.

So export it to the device tree binding header.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.h  | 3 +--
 include/dt-bindings/clock/sun8i-h3-ccu.h | 2 ++
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h 
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
index 1b4baea37d81..add3a7c18212 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
@@ -35,9 +35,8 @@
 #define CLK_PLL_PERIPH0_2X 10
 #define CLK_PLL_GPU11
 #define CLK_PLL_PERIPH112
-#define CLK_PLL_DE 13
 
-/* The CPUX clock is exported */
+/* The PLL_DE and CPUX clocks is exported */
 
 #define CLK_AXI15
 #define CLK_AHB1   16
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h 
b/include/dt-bindings/clock/sun8i-h3-ccu.h
index e139fe5c62ec..5345957a8c2e 100644
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -45,6 +45,8 @@
 
 #define CLK_PLL_PERIPH09
 
+#define CLK_PLL_DE 13
+
 #define CLK_CPUX   14
 
 #define CLK_BUS_CE 20
-- 
2.13.0

[PATCH 05/13] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3

[Icenowy Zheng]

Allwinner H3 features a PLL named CLK_PLL_DE, and a mod clock for the
"Display Engine 2.0" named CLK_DE. As the name indicated, the CLK_PLL_DE
is a PLL for CLK_DE.

Only CLK_DE and CLK_TVE have a parent of CLK_PLL_DE, and CLK_TVE is also
one part of the display clocks.

So allow CLK_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it).

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index d1ab0d713fa6..b1127e8629d9 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -439,7 +439,7 @@ static SUNXI_CCU_GATE(dram_ts_clk,  "dram-ts",  "dram",
 
 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
-0x104, 0, 4, 24, 3, BIT(31), 0);
+0x104, 0, 4, 24, 3, BIT(31), 
CLK_SET_RATE_PARENT);
 
 static const char * const tcon_parents[] = { "pll-video" };
 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
-- 
2.13.0

[PATCH 11/13] [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI controller in H3

[Icenowy Zheng]

From: Jernej Skrabec 

Allwinner H3 features DesignWare HDMI Transmitter paired with custom
PHY.

For now, only video is supported by the driver. However, audio and CEC
are also supported by the hardware.

Signed-off-by: Jernej Skrabec 
---
 drivers/gpu/drm/sun4i/Kconfig |   9 +
 drivers/gpu/drm/sun4i/Makefile|   1 +
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 462 ++
 3 files changed, 472 insertions(+)
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c

diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 06f05302ee75..589502ffe31a 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -40,6 +40,15 @@ config DRM_SUN4I_BACKEND
  do some alpha blending and feed graphics to TCON. If M is
  selected the module will be called sun4i-backend.
 
+config DRM_SUN8I_DW_HDMI
+   tristate "Support for Allwinner version of DesignWare HDMI"
+   depends on DRM_SUN4I
+   select DRM_DW_HDMI
+   help
+ Choose this option if you have an Allwinner SoC with the
+ DesignWare HDMI controller with custom HDMI PHY. If M is
+ selected the module will be called sun8i_dw_hdmi.
+
 config DRM_SUN8I_MIXER
tristate "Support for Allwinner Display Engine 2.0 Mixer"
default MACH_SUN8I
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 43c753cafc88..9c56173bf140 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_DRM_SUN4I)   += sun4i_tv.o
 obj-$(CONFIG_DRM_SUN4I_BACKEND)+= sun4i-backend.o
 obj-$(CONFIG_DRM_SUN4I_HDMI)   += sun4i-drm-hdmi.o
 obj-$(CONFIG_DRM_SUN8I_MIXER)  += sun8i-mixer.o
+obj-$(CONFIG_DRM_SUN8I_DW_HDMI)+= sun8i_dw_hdmi.o
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c 
b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
new file mode 100644
index ..fa1ecbcf08b8
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -0,0 +1,462 @@
+/*
+ * Copyright (c) 2017, Jernej Skrabec 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "sun4i_crtc.h"
+#include "sun4i_tcon.h"
+
+#define SUN8I_HDMI_PHY_REG_POL 0x
+
+#define SUN8I_HDMI_PHY_REG_READ_EN 0x0010
+#define SUN8I_HDMI_PHY_REG_READ_EN_MAGIC   0x54524545
+
+#define SUN8I_HDMI_PHY_REG_UNSCRAMBLE  0x0014
+#define SUN8I_HDMI_PHY_REG_UNSCRAMBLE_MAGIC0x42494E47
+
+#define SUN8I_HDMI_PHY_REG_CTRL0x0020
+#define SUN8I_HDMI_PHY_REG_UNK10x0024
+#define SUN8I_HDMI_PHY_REG_UNK20x0028
+#define SUN8I_HDMI_PHY_REG_PLL 0x002c
+#define SUN8I_HDMI_PHY_REG_CLK 0x0030
+#define SUN8I_HDMI_PHY_REG_UNK30x0034
+
+#define SUN8I_HDMI_PHY_REG_STATUS  0x0038
+#define SUN8I_HDMI_PHY_REG_STATUS_READYBIT(7)
+#define SUN8I_HDMI_PHY_REG_STATUS_HPD  BIT(19)
+
+#define to_sun8i_dw_hdmi(x)container_of(x, struct sun8i_dw_hdmi, x)
+#define set_bits(p, v) writel(readl(p) | (v), p)
+
+struct sun8i_dw_hdmi {
+   struct clk *clk_ddc;
+   struct clk *clk_hdmi;
+   struct device *dev;
+   struct drm_encoder encoder;
+   void __iomem *phy_base;
+   struct dw_hdmi_plat_data plat_data;
+   struct reset_control *rst_ddc;
+   struct reset_control *rst_hdmi;
+};
+
+static u32 sun8i_dw_hdmi_get_divider(int clk_khz)
+{
+   /*
+* Due to missing documentaion of HDMI PHY, we know correct
+* settings only for following four PHY dividers. Select one
+* based on clock speed.
+*/
+   if (clk_khz <= 27000)
+   return 11;
+   else if (clk_khz <= 74250)
+   return 4;
+   else if (clk_khz <= 148500)
+   return 2;
+   else
+   return 1;
+}
+
+static void sun8i_dw_hdmi_encoder_disable(struct drm_encoder *encoder)
+{
+   struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
+   struct sun4i_tcon *tcon = crtc->tcon;
+
+   DRM_DEBUG_DRIVER("Disabling HDMI Output\n");
+
+   sun4i_tcon_channel_disable(tcon, 1);
+}
+
+static void sun8i_dw_hdmi_encoder_enable(struct drm_encoder *encoder)
+{
+   struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
+   struct sun4i_tcon *tcon = crtc->tcon;
+
+   DRM_DEBUG_DRIVER("Enabling HDMI Output\n");
+
+   sun4i_tcon_channel_enable(tcon, 1);
+}
+
+static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder,
+ 

[PATCH 13/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi PC

[Icenowy Zheng]

Orange Pi PC board has a HDMI-A port connected to the HDMI controller of
Allwinner H3 SoC.

Enable the HDMI output in Orange Pi PC device tree.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts 
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 998b60f8d295..0e3326399590 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -98,6 +98,10 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
@@ -121,12 +125,20 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin>;
@@ -177,6 +189,10 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.13.0

[PATCH 12/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller

[Icenowy Zheng]

The H3 SoC has a DesignWare HDMI controller with some Allwinner-specific
glues.

Add the related device nodes.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 35 +++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 75ad7b65a7fc..cd38d7e04606 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -197,6 +197,11 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+   tcon0_out_hdmi: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<_in_tcon0>;
+   };
};
};
};
@@ -240,6 +245,36 @@
};
};
};
+
+   hdmi: hdmi@1ee {
+   compatible = "allwinner,h3-dw-hdmi";
+   reg = <0x01ee 0x1>,
+ <0x01ef 0x1>;
+   reg-io-width = <1>;
+   interrupts = ;
+   clocks = < CLK_BUS_HDMI>, < CLK_HDMI>,
+< CLK_HDMI_DDC>;
+   clock-names = "iahb", "isfr", "iddc";
+   resets = < RST_BUS_HDMI0>, < RST_BUS_HDMI1>;
+   reset-names = "hdmi", "ddc";
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   hdmi_in: port@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+   hdmi_in_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_out_hdmi>;
+   };
+   };
+   };
+   };
};
 
timer {
-- 
2.13.0

[PATCH 00/13] Allwinner H3 DE2 basical support

[Icenowy Zheng]

Allwinner H3 features a "Display Engine 2.0", which needs some support
to be present in the DRM driver.

This patchset is now a basical version, which dropped some features I
used to submitted:
- TVE support (not so high priority now)
- Multi-pipeline support (also not so high priority now due to no TVE)

The last 6 patches are only used for testing this patchset, and they're
going to be sent by Jernej Skrabec after this patchset is applied.

Icenowy Zheng (9):
  dt-bindings: update the binding for Allwinner H3 DE2 support
  drm: sun4i: add support for H3 mixers
  drm: sun4i: add support for H3's TCON
  drm: sun4i: add compatible for H3 display engine
  clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3
  clk: sunxi-ng: export CLK_PLL_DE for H3
  ARM: sun8i: h3: add display engine pipeline barebone
  [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller
  [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi
PC

Jernej Skrabec (4):
  [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi
  [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the
dw_hdmi driver
  [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3
HDMI clock
  [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI
controller in H3

 .../bindings/display/sunxi/sun4i-drm.txt   |  25 +-
 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts |  16 +
 arch/arm/boot/dts/sun8i-h3.dtsi| 205 +
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c|   4 +-
 drivers/clk/sunxi-ng/ccu-sun8i-h3.h|   3 +-
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c  |   9 +-
 drivers/gpu/drm/sun4i/Kconfig  |   9 +
 drivers/gpu/drm/sun4i/Makefile |   1 +
 drivers/gpu/drm/sun4i/sun4i_drv.c  |   2 +
 drivers/gpu/drm/sun4i/sun4i_tcon.c |  43 +-
 drivers/gpu/drm/sun4i/sun4i_tcon.h |   1 +
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c  | 462 +
 drivers/gpu/drm/sun4i/sun8i_mixer.c|  18 +
 include/drm/bridge/dw_hdmi.h   |   2 +
 include/dt-bindings/clock/sun8i-h3-ccu.h   |   2 +
 15 files changed, 781 insertions(+), 21 deletions(-)
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c

-- 
2.13.0

[PATCH 03/13] drm: sun4i: add support for H3's TCON

[Icenowy Zheng]

From: Icenowy Zheng <icen...@aosc.xyz>

Allwinner H3 has two special TCONs without channel 0.

Add support for this kind of TCON.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_drv.c  |  1 +
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 43 +++---
 drivers/gpu/drm/sun4i/sun4i_tcon.h |  1 +
 3 files changed, 33 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index ace59651892f..fd99fe8a4df7 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -188,6 +188,7 @@ static bool sun4i_drv_node_is_tcon(struct device_node *node)
of_device_is_compatible(node, "allwinner,sun6i-a31-tcon") ||
of_device_is_compatible(node, "allwinner,sun6i-a31s-tcon") ||
of_device_is_compatible(node, "allwinner,sun8i-a33-tcon") ||
+   of_device_is_compatible(node, "allwinner,sun8i-h3-tcon") ||
of_device_is_compatible(node, "allwinner,sun8i-v3s-tcon");
 }
 
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index d9791292553e..270f09e381a5 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -59,6 +59,7 @@ void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int 
channel)
 
/* Disable the TCON's channel */
if (channel == 0) {
+   WARN_ON(!tcon->quirks->has_channel_0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
   SUN4I_TCON0_CTL_TCON_ENABLE, 0);
clk_disable_unprepare(tcon->dclk);
@@ -78,6 +79,7 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int 
channel)
 
/* Enable the TCON's channel */
if (channel == 0) {
+   WARN_ON(!tcon->quirks->has_channel_0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
   SUN4I_TCON0_CTL_TCON_ENABLE,
   SUN4I_TCON0_CTL_TCON_ENABLE);
@@ -157,6 +159,8 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
u8 clk_delay;
u32 val = 0;
 
+   WARN_ON(!tcon->quirks->has_channel_0);
+
/* Configure the dot clock */
clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
 
@@ -366,10 +370,12 @@ static int sun4i_tcon_init_clocks(struct device *dev,
}
clk_prepare_enable(tcon->clk);
 
-   tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
-   if (IS_ERR(tcon->sclk0)) {
-   dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
-   return PTR_ERR(tcon->sclk0);
+   if (tcon->quirks->has_channel_0) {
+   tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
+   if (IS_ERR(tcon->sclk0)) {
+   dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
+   return PTR_ERR(tcon->sclk0);
+   }
}
 
if (tcon->quirks->has_channel_1) {
@@ -551,10 +557,12 @@ static int sun4i_tcon_bind(struct device *dev, struct 
device *master,
goto err_free_clocks;
}
 
-   ret = sun4i_dclk_create(dev, tcon);
-   if (ret) {
-   dev_err(dev, "Couldn't create our TCON dot clock\n");
-   goto err_free_clocks;
+   if (tcon->quirks->has_channel_0) {
+   ret = sun4i_dclk_create(dev, tcon);
+   if (ret) {
+   dev_err(dev, "Couldn't create our TCON dot clock\n");
+   goto err_free_clocks;
+   }
}
 
ret = sun4i_tcon_init_irq(dev, tcon);
@@ -579,7 +587,8 @@ static int sun4i_tcon_bind(struct device *dev, struct 
device *master,
return 0;
 
 err_free_dotclock:
-   sun4i_dclk_free(tcon);
+   if (tcon->quirks->has_channel_0)
+   sun4i_dclk_free(tcon);
 err_free_clocks:
sun4i_tcon_free_clocks(tcon);
 err_assert_reset:
@@ -593,7 +602,9 @@ static void sun4i_tcon_unbind(struct device *dev, struct 
device *master,
struct sun4i_tcon *tcon = dev_get_drvdata(dev);
 
list_del(>list);
-   sun4i_dclk_free(tcon);
+
+   if (tcon->quirks->has_channel_0)
+   sun4i_dclk_free(tcon);
sun4i_tcon_free_clocks(tcon);
 }
 
@@ -625,23 +636,30 @@ static int sun4i_tcon_remove(struct platform_device *pdev)
 
 static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
.has_unknown_mux = true,
+   .has_channel_0  = true,
.has_channel_1  = true,
 };
 
 static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
+   .has_channel_0  = true,
.has_channel_1  = true,
 };
 
 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
+   .has_c

Re: [linux-sunxi] [PATCH 2/4] drivers: soc: sunxi: fix error processing on base address when claiming

[Icenowy Zheng]

于 2017年8月18日 GMT+08:00 下午2:21:07, Chen-Yu Tsai <w...@csie.org> 写到:
>Hi,
>
>On Wed, Aug 9, 2017 at 4:56 PM, Icenowy Zheng <icen...@aosc.io> wrote:
>> When claiming SRAM, if the base is set to an error, it means that the
>> SRAM controller has been probed, but failed to remap the controller
>> memory zone. If the base is zero, thus the SRAM controller should be
>not
>> probed at all, and it should return -EPROBE_DEFER. However, currently
>we
>> returned -EPROBE_DEFER in the former situation, and ignored the
>latter
>> situation (which will lead to the kernel to panic).
>>
>> Fix the behavior on abnormal base address processing when claiming.
>
>Could you describe how you actually ran into this? The failure seems
>unlikely for a properly written device tree.

In fact it's possible, as the probe defering used to be broken.

On the A64 situation, the SRAM is referenced by the DE2 CCU driver, which will 
be probed very early -- before SRAM is probed, and the problem happens.

>
>Thanks
>ChenYu

[PATCH 2/2] ARM: sunxi: add support for R40 SoC

[Icenowy Zheng]

Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.

Add support for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 Documentation/arm/sunxi/README  | 6 ++
 Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
 arch/arm/mach-sunxi/sunxi.c | 1 +
 3 files changed, 8 insertions(+)

diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index d7b1f016bd62..4fa836782e46 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -75,6 +75,12 @@ SunXi family
 + Datasheet
   http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
 
+  - Allwinner R40 (sun8i)
++ Datasheet
+  https://github.com/tinalinux/docs/raw/r40-v1.y/R40_Datasheet_V1.0.pdf
++ User Manual
+  
https://github.com/tinalinux/docs/raw/r40-v1.y/Allwinner_R40_User_Manual_V1.0.pdf
+
 * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
   - Allwinner A80
 + Datasheet
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt 
b/Documentation/devicetree/bindings/arm/sunxi.txt
index f35c6ada5a65..e4beec3d9ad3 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
   allwinner,sun8i-a83t
   allwinner,sun8i-h2-plus
   allwinner,sun8i-h3
+  allwinner-sun8i-r40
   allwinner,sun8i-v3s
   allwinner,sun9i-a80
   allwinner,sun50i-a64
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 7ab353fb25f2..311e6c4fc4f4 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -66,6 +66,7 @@ static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-v3s",
+   "allwinner,sun8i-r40",
NULL,
 };
 
-- 
2.13.0

[PATCH 1/2] dt-bindings: add compatible string for Allwinner V3s SoC

[Icenowy Zheng]

The compatible string for Allwinner V3s SoC used to be missing.

Add it to the binding document.

Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt 
b/Documentation/devicetree/bindings/arm/sunxi.txt
index d2c46449b4eb..f35c6ada5a65 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
   allwinner,sun8i-a83t
   allwinner,sun8i-h2-plus
   allwinner,sun8i-h3
+  allwinner,sun8i-v3s
   allwinner,sun9i-a80
   allwinner,sun50i-a64
   nextthing,gr8
-- 
2.13.0

Re: [PATCH 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

[Icenowy Zheng]

于 2017年8月23日 GMT+08:00 上午4:10:43, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>Hi,
>
>On Tue, Aug 22, 2017 at 02:17:41PM +0800, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai <w...@csie.org>
>> 
>> The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
>> form factor and position of various connectors, leds and buttons is
>> similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
>> as the latest Banana Pi M64.
>> 
>> It features:
>> 
>>   - X-Powers AXP221s PMIC connected to i2c0
>>   - 2 GB DDR3 DRAM
>>   - 8 GB eMMC
>>   - micro SD card slot
>>   - DC power jack
>>   - HDMI output
>>   - MIPI DSI connector
>>   - 2x USB 2.0 hosts
>>   - 1x USB 2.0 OTG
>>   - gigabit ethernet with Realtek RTL8211E transceiver
>>   - WiFi/Bluetooth with AP6212 chip, with external antenna connector
>>   - SATA and power connectors for native SATA support
>>   - camera sensor connector
>>   - consumer IR receiver
>>   - audio out headphone jack
>>   - onboard microphone
>>   - red, green, and blue LEDs
>>   - debug UART pins
>>   - Li-Po battery connector
>>   - Raspberry Pi B+ compatible GPIO header
>>   - power, reset, and boot control buttons
>> 
>> This patch adds a dts file that enables UART, MMC and PMIC support.
>> 
>> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>> ---
>>  arch/arm/boot/dts/Makefile|   1 +
>>  arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 181
>++
>>  2 files changed, 182 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>> 
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 570e107bf702..e0b1ed3e2e24 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -927,6 +927,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>>  sun8i-h3-orangepi-plus2e.dtb \
>>  sun8i-r16-bananapi-m2m.dtb \
>>  sun8i-r16-parrot.dtb \
>> +sun8i-r40-bananapi-m2-ultra.dtb \
>>  sun8i-v3s-licheepi-zero.dtb \
>>  sun8i-v3s-licheepi-zero-dock.dtb
>>  dtb-$(CONFIG_MACH_SUN9I) += \
>> diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>> new file mode 100644
>> index ..daf6036f
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
>> @@ -0,0 +1,181 @@
>> +/*
>> + * Copyright (C) 2017 Chen-Yu Tsai <w...@csie.org>
>> + * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this
>dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>as
>> + * published by the Free Software Foundation; either version 2
>of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty
>of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated
>documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom
>the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall
>be
>> + * included in all copies or substantial portions of the
>Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
>KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
>WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

[Icenowy Zheng]

于 2017年8月23日 GMT+08:00 上午4:05:21, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>Hi,
>
>On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai <w...@csie.org>
>> 
>> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
>> The R40 is a smaller chip than the A20, but features the same set
>> of programmable pins, with a couple extra pins and some new pin
>> functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
>> GPU. It retains most if not all features from the A20, while adding
>> some new features, such as MIPI DSI output, or updating various
>> hardware blocks, such as DE 2.0.
>> 
>> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
>> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>
>I'm not sure why you have two series to achieve one thing here. And
>the fact that you don't have a cover letter doesn't make it any
>clearer.
>
>Please make series based on what you're trying to do and not split it
>arbitrarily. And document what you're doing in a cover letter.
>
>> ---
>>  arch/arm/boot/dts/sun8i-r40.dtsi | 396
>+++
>>  1 file changed, 396 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
>> 
>> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
>b/arch/arm/boot/dts/sun8i-r40.dtsi
>> new file mode 100644
>> index 0000..5b48801bdd01
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
>> @@ -0,0 +1,396 @@
>> +/*
>> + * Copyright 2017 Chen-Yu Tsai <w...@csie.org>
>> + * Copyright 2017 Icenowy Zheng <icen...@aosc.io>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this
>dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>as
>> + * published by the Free Software Foundation; either version 2
>of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty
>of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated
>documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom
>the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall
>be
>> + * included in all copies or substantial portions of the
>Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
>KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
>WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/ {
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +interrupt-parent = <>;
>> +
>> +clocks {
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +ranges;
>> +
>> +osc24M: osc24M {
>> +#clock-cells = <0>;
>> +compatible = "fixed-clock";
>> +clock-frequency = <2400>;
>> +clock-output-names = "osc24M";
>> +};
>> +
>> +osc32k: osc32k {
>> +#clock-cells = <0&

Re: [PATCH 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

[Icenowy Zheng]

于 2017年8月23日 GMT+08:00 上午4:12:15, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Tue, Aug 22, 2017 at 02:17:42PM +0800, Icenowy Zheng wrote:
>> +_vcc5v0 {
>> +gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
>> +enable-active-high;
>> +};
>
>Same thing here, you're not using that regulator anywhere. You don't
>even use any of the regulators in sunxi-common-regulators.

Maybe I should drop the regulator now, and re-introduce it when adding USB/SATA?

>
>Maxime

[PATCH v7 06/13] drm/sun4i: add a dedicated module for sun4i-backend and sun4i-layer

[Icenowy Zheng]

Currently the direct call from CRTC code to layer code has disappeared,
instead the layer's init function is called via the backend's ops.

Add a dedicated module for sun4i-backend and sun4i-layer, and drop the
EXPORT_SYMBOL from backend code to layer code.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v7:
- Added Chen-Yu's Reviewed-by.

 drivers/gpu/drm/sun4i/Makefile| 5 +++--
 drivers/gpu/drm/sun4i/sun4i_backend.c | 4 
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 59b757350a1f..a251fb36c951 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -5,9 +5,10 @@ sun4i-tcon-y += sun4i_tcon.o
 sun4i-tcon-y += sun4i_rgb.o
 sun4i-tcon-y += sun4i_dotclock.o
 sun4i-tcon-y += sun4i_crtc.o
-sun4i-tcon-y += sun4i_layer.o
+
+sun4i-backend-y += sun4i_backend.o sun4i_layer.o
 
 obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o
-obj-$(CONFIG_DRM_SUN4I)+= sun4i_backend.o
+obj-$(CONFIG_DRM_SUN4I)+= sun4i-backend.o
 obj-$(CONFIG_DRM_SUN4I)+= sun6i_drc.o
 obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c 
b/drivers/gpu/drm/sun4i/sun4i_backend.c
index 611cdcb9c182..fac1a414ba49 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -83,7 +83,6 @@ void sun4i_backend_layer_enable(struct sun4i_backend *backend,
regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
   SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
 }
-EXPORT_SYMBOL(sun4i_backend_layer_enable);
 
 static int sun4i_backend_drm_format_to_layer(struct drm_plane *plane,
 u32 format, u32 *mode)
@@ -170,7 +169,6 @@ int sun4i_backend_update_layer_coord(struct sun4i_backend 
*backend,
 
return 0;
 }
-EXPORT_SYMBOL(sun4i_backend_update_layer_coord);
 
 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
   int layer, struct drm_plane *plane)
@@ -205,7 +203,6 @@ int sun4i_backend_update_layer_formats(struct sun4i_backend 
*backend,
 
return 0;
 }
-EXPORT_SYMBOL(sun4i_backend_update_layer_formats);
 
 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
  int layer, struct drm_plane *plane)
@@ -246,7 +243,6 @@ int sun4i_backend_update_layer_buffer(struct sun4i_backend 
*backend,
 
return 0;
 }
-EXPORT_SYMBOL(sun4i_backend_update_layer_buffer);
 
 static int sun4i_backend_init_sat(struct device *dev) {
struct sun4i_backend *backend = dev_get_drvdata(dev);
-- 
2.12.2

[PATCH v7 10/13] drm/sun4i: tcon: add support for V3s TCON

[Icenowy Zheng]

Allwinner V3s SoC features a TCON without channel 1.

Add support for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v7:
- Added Chen-Yu's Reviewed-by.

 drivers/gpu/drm/sun4i/sun4i_drv.c  | 3 ++-
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 4a979d17ddaa..1dd1948025d2 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -178,7 +178,8 @@ static bool sun4i_drv_node_is_tcon(struct device_node *node)
return of_device_is_compatible(node, "allwinner,sun5i-a13-tcon") ||
of_device_is_compatible(node, "allwinner,sun6i-a31-tcon") ||
of_device_is_compatible(node, "allwinner,sun6i-a31s-tcon") ||
-   of_device_is_compatible(node, "allwinner,sun8i-a33-tcon");
+   of_device_is_compatible(node, "allwinner,sun8i-a33-tcon") ||
+   of_device_is_compatible(node, "allwinner,sun8i-v3s-tcon");
 }
 
 static int compare_of(struct device *dev, void *data)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 288275802f92..add349f5e012 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -601,11 +601,16 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
/* nothing is supported */
 };
 
+static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
+   /* nothing is supported */
+};
+
 static const struct of_device_id sun4i_tcon_of_table[] = {
{ .compatible = "allwinner,sun5i-a13-tcon", .data = _a13_quirks },
{ .compatible = "allwinner,sun6i-a31-tcon", .data = _a31_quirks },
{ .compatible = "allwinner,sun6i-a31s-tcon", .data = _a31s_quirks 
},
{ .compatible = "allwinner,sun8i-a33-tcon", .data = _a33_quirks },
+   { .compatible = "allwinner,sun8i-v3s-tcon", .data = _v3s_quirks },
{ }
 };
 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
-- 
2.12.2

[PATCH v7 03/13] dt-bindings: add bindings for DE2 on V3s SoC

[Icenowy Zheng]

Allwinner V3s SoC have a display engine which have a different pipeline
with older SoCs.

Add document for it (new compatibles and the new "mixer" part).

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v7:
- Reduced some text.
Changes in v4:
- Removed the refactor at TCON chapter.
Changes in v3:
- Remove the description of having a BE directly as allwinner,pipeline.

 .../bindings/display/sunxi/sun4i-drm.txt   | 26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 7acdbf14ae1c..66b85a195ef2 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -41,6 +41,7 @@ Required properties:
* allwinner,sun6i-a31-tcon
* allwinner,sun6i-a31s-tcon
* allwinner,sun8i-a33-tcon
+   * allwinner,sun8i-v3s-tcon
  - reg: base address and size of memory-mapped region
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the TCON. Three are needed:
@@ -62,7 +63,7 @@ Required properties:
   second the block connected to the TCON channel 1 (usually the TV
   encoder)
 
-On SoCs other than the A33, there is one more clock required:
+On SoCs other than the A33 and V3s, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
 
 DRC
@@ -148,6 +149,26 @@ Required properties:
   Documentation/devicetree/bindings/media/video-interfaces.txt. The
   first port should be the input endpoints, the second one the outputs
 
+Display Engine 2.0 Mixer
+
+
+The DE2 mixer have many functionalities, currently only layer blending is
+supported.
+
+Required properties:
+  - compatible: value must be one of:
+* allwinner,sun8i-v3s-de2-mixer
+  - reg: base address and size of the memory-mapped region.
+  - clocks: phandles to the clocks feeding the mixer
+* bus: the mixer interface clock
+* mod: the mixer module clock
+  - clock-names: the clock names mentioned above
+  - resets: phandles to the reset controllers driving the mixer
+
+- ports: A ports node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt. The
+  first port should be the input endpoints, the second one the output
+
 
 Display Engine Pipeline
 ---
@@ -162,9 +183,10 @@ Required properties:
 * allwinner,sun6i-a31-display-engine
 * allwinner,sun6i-a31s-display-engine
 * allwinner,sun8i-a33-display-engine
+* allwinner,sun8i-v3s-display-engine
 
   - allwinner,pipelines: list of phandle to the display engine
-frontends available.
+frontends (DE 1.0) or mixers (DE 2.0) available.
 
 Example:
 
-- 
2.12.2

[PATCH v7 02/13] clk: sunxi-ng: add support for DE2 CCU

[Icenowy Zheng]

The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.

Add a sunxi-ng style driver for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v7:
- Fixed some parent clocks that are left open if the probe failed.
- Added V3s compatible (only one mixer).
Changes in v5:
- Removed dt-bindings headers (they're now in patch 1).
Changes in v4:
- Fixed the inconsistence between mixer_div clocks' number and real clock.
Changes in v2:
- Rename sunxi-de2-ccu to sun8i-de2-ccu.

 drivers/clk/sunxi-ng/Kconfig |   5 +
 drivers/clk/sunxi-ng/Makefile|   1 +
 drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 260 +++
 drivers/clk/sunxi-ng/ccu-sun8i-de2.h |  28 
 4 files changed, 294 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-de2.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-de2.h

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index b0d551a8efe4..747662565545 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -140,6 +140,11 @@ config SUN8I_V3S_CCU
default MACH_SUN8I
depends on MACH_SUN8I || COMPILE_TEST
 
+config SUN8I_DE2_CCU
+   bool "Support for the Allwinner SoCs DE2 CCU"
+   select SUNXI_CCU_DIV
+   select SUNXI_CCU_GATE
+
 config SUN9I_A80_CCU
bool "Support for the Allwinner A80 CCU"
select SUNXI_CCU_DIV
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 0ec02fe14c50..be616279450e 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_SUN8I_A23_CCU)   += ccu-sun8i-a23.o
 obj-$(CONFIG_SUN8I_A33_CCU)+= ccu-sun8i-a33.o
 obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
 obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o
+obj-$(CONFIG_SUN8I_DE2_CCU)+= ccu-sun8i-de2.o
 obj-$(CONFIG_SUN8I_R_CCU)  += ccu-sun8i-r.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-de.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
new file mode 100644
index ..15aaa9c4a3af
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icen...@aosc.io>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "ccu_common.h"
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_reset.h"
+
+#include "ccu-sun8i-de2.h"
+
+static SUNXI_CCU_GATE(bus_mixer0_clk,  "bus-mixer0",   "bus-de",
+ 0x04, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_mixer1_clk,  "bus-mixer1",   "bus-de",
+ 0x04, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_wb_clk,  "bus-wb",   "bus-de",
+ 0x04, BIT(2), 0);
+
+static SUNXI_CCU_GATE(mixer0_clk,  "mixer0",   "mixer0-div",
+ 0x00, BIT(0), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_GATE(mixer1_clk,  "mixer1",   "mixer1-div",
+ 0x00, BIT(1), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_GATE(wb_clk,  "wb",   "wb-div",
+ 0x00, BIT(2), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
+  CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
+  CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
+  CLK_SET_RATE_PARENT);
+
+static struct ccu_common *sun8i_a83t_de2_clks[] = {
+   _clk.common,
+   _clk.common,
+   _clk.common,
+
+   _mixer0_clk.common,
+   _mixer1_clk.common,
+   _wb_clk.common,
+
+   _div_clk.common,
+   _div_clk.common,
+   _div_clk.common,
+};
+
+static struct ccu_common *sun8i_v3s_de2_clks[] = {
+   _clk.common,
+   _clk.common,
+
+   _mixer0_clk.common,
+   _wb_clk.common,
+
+   _div_clk.common,
+   _div_clk.common,
+};
+
+static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
+   .hws= {
+   [CLK_MIXER0]= _clk.common.hw,
+   [CLK_MIXER1]   

[PATCH v7 13/13] [DO NOT MERGE] ARM: sun8i: v3s: enable LCD panel of Lichee Pi Zero

[Icenowy Zheng]

A 480x272 QiaoDian QD43003C0-40-7LED panel is available from Lichee Pi.

This commit connects this panel to Lichee Pi Zero.

Lichee Pi also provides a 800x480 panel without accurate model number,
so do not merge this patch. It will finally come as device tree overlay.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 36 +++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts 
b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index 387fc2aa546d..7ae72bf63cd0 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -75,6 +75,28 @@
gpios = < 6 2 GPIO_ACTIVE_LOW>; /* PG2 */
};
};
+
+   panel: panel {
+   compatible = "qiaodian,qd43003c0-40", "simple-panel";
+   enable-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* Should be 
backlight */
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   panel_input: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_out_lcd>;
+   };
+   };
+   };
+};
+
+ {
+   status = "okay";
 };
 
  {
@@ -86,6 +108,20 @@
status = "okay";
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_rgb666_pins>;
+   status = "okay";
+
+};
+
+_out {
+   tcon0_out_lcd: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_input>;
+   };
+};
+
  {
pinctrl-0 = <_pins_a>;
pinctrl-names = "default";
-- 
2.12.2

[PATCH v7 12/13] ARM: sun8i: v3s: add pinmux for LCD pins of V3s SoC

[Icenowy Zheng]

Allwinner V3s SoC features a set of pins that have functionality of RGB
LCD, the pins are at different pin ban than other SoCs.

Add pinctrl node for them.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v7:
- Dropped the trailing "@0" in rgb666 pinmux node name.
- Added Chen-Yu's ACK.

 arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index b71b35734515..a7026517ed99 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -297,6 +297,15 @@
function = "i2c0";
};
 
+   lcd_rgb666_pins: lcd_rgb666 {
+   pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+  "PE5", "PE6", "PE7", "PE8", "PE9",
+  "PE10", "PE11", "PE12", "PE13", "PE14",
+  "PE15", "PE16", "PE17", "PE18", "PE19",
+  "PE23", "PE24";
+   function = "lcd";
+   };
+
uart0_pins_a: uart0@0 {
pins = "PB8", "PB9";
function = "uart0";
-- 
2.12.2

[PATCH v7 11/13] ARM: sun8i: v3s: add device nodes for DE2 display pipeline

[Icenowy Zheng]

Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer
and only one TCON connected to this mixer, which have RGB LCD output.

Add device nodes for this display pipeline.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v7:
- Change DE2 clock compatible to V3s one.
- Mention only one TCON in commit message.
- Changed commit brief.

 arch/arm/boot/dts/sun8i-v3s.dtsi | 87 
 1 file changed, 87 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 71075969e5e6..b71b35734515 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -41,6 +41,10 @@
  */
 
 #include 
+#include 
+#include 
+#include 
+#include 
 
 / {
#address-cells = <1>;
@@ -59,6 +63,12 @@
};
};
 
+   de: display-engine {
+   compatible = "allwinner,sun8i-v3s-display-engine";
+   allwinner,pipelines = <_mixer0>;
+   status = "disabled";
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
@@ -93,6 +103,83 @@
#size-cells = <1>;
ranges;
 
+   de2_clocks: clock@100 {
+   compatible = "allwinner,sun8i-v3s-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_DE>,
+< CLK_BUS_DE>;
+   clock-names = "mod",
+ "bus";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+   de2_mixer0: mixer@110 {
+   compatible = "allwinner,sun8i-v3s-de2-mixer";
+   reg = <0x0110 0x10>;
+   clocks = <_clocks CLK_MIXER0>,
+<_clocks CLK_BUS_MIXER0>;
+   clock-names = "mod",
+ "bus";
+   resets = <_clocks RST_MIXER0>;
+   assigned-clocks = <_clocks CLK_MIXER0>;
+   assigned-clock-rates = <15000>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mixer0_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   mixer0_out_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_in_mixer0>;
+   };
+   };
+   };
+   };
+
+   tcon0: lcd-controller@1c0c000 {
+   compatible = "allwinner,sun8i-v3s-tcon";
+   reg = <0x01c0c000 0x1000>;
+   interrupts = ;
+   clocks = < CLK_BUS_TCON0>,
+< CLK_TCON0>;
+   clock-names = "ahb",
+ "tcon-ch0";
+   clock-output-names = "tcon-pixel-clock";
+   resets = < RST_BUS_TCON0>;
+   reset-names = "lcd";
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   tcon0_in: port@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+   tcon0_in_mixer0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_out_tcon0>;
+   };
+   };
+
+   tcon0_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+   };
+   };
+   };
+
+
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
-- 
2.12.2

[PATCH v7 09/13] drm/sun4i: Add compatible string for V3s display engine

[Icenowy Zheng]

Allwinner V3s features the new "Display Engine 2.0", which can now also
be driven with our subdrivers in sun4i-drm.

Add the compatible string for in sun4i_drv.c, in order to make the
display engine and its components probed.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 35cad9cb44c5..4a979d17ddaa 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -296,6 +296,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun6i-a31-display-engine" },
{ .compatible = "allwinner,sun6i-a31s-display-engine" },
{ .compatible = "allwinner,sun8i-a33-display-engine" },
+   { .compatible = "allwinner,sun8i-v3s-display-engine" },
{ }
 };
 MODULE_DEVICE_TABLE(of, sun4i_drv_of_table);
-- 
2.12.2

[PATCH v7 08/13] drm/sun4i: add support for Allwinner DE2 mixers

[Icenowy Zheng]

Allwinner have a new "Display Engine 2.0" in their new SoCs, which comes
with mixers to do graphic processing and feed data to TCON, like the old
backends and frontends.

Add support for the mixer on Allwinner V3s SoC; it's the simplest one.

Currently a lot of functions are still missing -- more investigations
are needed to gain enough information for them.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v7:
- Small fixed advised by Maxime Ripard.
- Added fixup on CRTC destination coordinate.
Changes in v6:
- Rebased on wens's multi-pipeline patchset.
Changes in v5:
- Changed some code alignment.
- Request real 32-bit DMA (prepare for 64-bit SoCs).
Changes in v4:
- Killed some dead code according to Jernej.

 drivers/gpu/drm/sun4i/Kconfig   |  10 +
 drivers/gpu/drm/sun4i/Makefile  |   3 +
 drivers/gpu/drm/sun4i/sun8i_layer.c | 134 
 drivers/gpu/drm/sun4i/sun8i_layer.h |  36 
 drivers/gpu/drm/sun4i/sun8i_mixer.c | 412 
 drivers/gpu/drm/sun4i/sun8i_mixer.h | 137 
 6 files changed, 732 insertions(+)
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.h
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.h

diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 5a8227f37cc4..15557484520d 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -22,3 +22,13 @@ config DRM_SUN4I_BACKEND
  original Allwinner Display Engine, which has a backend to
  do some alpha blending and feed graphics to TCON. If M is
  selected the module will be called sun4i-backend.
+
+config DRM_SUN8I_MIXER
+   tristate "Support for Allwinner Display Engine 2.0 Mixer"
+   depends on DRM_SUN4I
+   default MACH_SUN8I
+   help
+ Choose this option if you have an Allwinner SoC with the
+ Allwinner Display Engine 2.0, which has a mixer to do some
+ graphics mixture and feed graphics to TCON, If M is
+ selected the module will be called sun8i-mixer.
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index da561d064ab8..d81c9319dadf 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -8,8 +8,11 @@ sun4i-tcon-y += sun4i_crtc.o
 
 sun4i-backend-y += sun4i_backend.o sun4i_layer.o
 
+sun8i-mixer-y += sun8i_mixer.o sun8i_layer.o
+
 obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o
 obj-$(CONFIG_DRM_SUN4I)+= sun6i_drc.o
 obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o
 
 obj-$(CONFIG_DRM_SUN4I_BACKEND)+= sun4i-backend.o
+obj-$(CONFIG_DRM_SUN8I_MIXER)  += sun8i-mixer.o
diff --git a/drivers/gpu/drm/sun4i/sun8i_layer.c 
b/drivers/gpu/drm/sun4i/sun8i_layer.c
new file mode 100644
index ..e627eeece658
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun8i_layer.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) Icenowy Zheng <icen...@aosc.io>
+ *
+ * Based on sun4i_layer.h, which is:
+ *   Copyright (C) 2015 Free Electrons
+ *   Copyright (C) 2015 NextThing Co
+ *
+ *   Maxime Ripard <maxime.rip...@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+
+#include "sun8i_layer.h"
+#include "sun8i_mixer.h"
+
+struct sun8i_plane_desc {
+  enum drm_plane_type type;
+  const uint32_t  *formats;
+  uint32_tnformats;
+};
+
+static void sun8i_mixer_layer_atomic_disable(struct drm_plane *plane,
+  struct drm_plane_state 
*old_state)
+{
+   struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+   struct sun8i_mixer *mixer = layer->mixer;
+
+   sun8i_mixer_layer_enable(mixer, layer->id, false);
+}
+
+static void sun8i_mixer_layer_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+   struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+   struct sun8i_mixer *mixer = layer->mixer;
+
+   sun8i_mixer_update_layer_coord(mixer, layer->id, plane);
+   sun8i_mixer_update_layer_formats(mixer, layer->id, plane);
+   sun8i_mixer_update_layer_buffer(mixer, layer->id, plane);
+   sun8i_mixer_layer_enable(mixer, layer->id, true);
+}
+
+static struct drm_plane_helper_funcs sun8i_mixer_layer_helper_funcs = {
+   .atomic_disable = sun8i_mixer_layer_atomic_disable,
+   .atomic_update  = sun8i_mixer_layer_atomic_update,
+};
+
+static const struct drm_plane_funcs sun8i_mixer_layer_fu

[PATCH v7 07/13] drm/sun4i: add a Kconfig option for sun4i-backend

[Icenowy Zheng]

As sun4i-backend is now a dedicated module, add an Kconfig option for
it to make it optional, since some build may only use other engines.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v7:
- Adjusted the position of BACKEND makefile item. (It's now after
  common codes shared between sun4i-backend and sun8i-mixer.)

 drivers/gpu/drm/sun4i/Kconfig  | 10 ++
 drivers/gpu/drm/sun4i/Makefile |  3 ++-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index a4b357db8856..5a8227f37cc4 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -12,3 +12,13 @@ config DRM_SUN4I
  Choose this option if you have an Allwinner SoC with a
  Display Engine. If M is selected the module will be called
  sun4i-drm.
+
+config DRM_SUN4I_BACKEND
+   tristate "Support for Allwinner A10 Display Engine Backend"
+   depends on DRM_SUN4I
+   default DRM_SUN4I
+   help
+ Choose this option if you have an Allwinner SoC with the
+ original Allwinner Display Engine, which has a backend to
+ do some alpha blending and feed graphics to TCON. If M is
+ selected the module will be called sun4i-backend.
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index a251fb36c951..da561d064ab8 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -9,6 +9,7 @@ sun4i-tcon-y += sun4i_crtc.o
 sun4i-backend-y += sun4i_backend.o sun4i_layer.o
 
 obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o
-obj-$(CONFIG_DRM_SUN4I)+= sun4i-backend.o
 obj-$(CONFIG_DRM_SUN4I)+= sun6i_drc.o
 obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o
+
+obj-$(CONFIG_DRM_SUN4I_BACKEND)+= sun4i-backend.o
-- 
2.12.2

[PATCH v7 04/13] drm/sun4i: return only planes for layers created

[Icenowy Zheng]

As we are going to add support for the Allwinner DE2 Mixer in sun4i-drm
driver, we will finally have two types of layers.

Each layer is bound to a drm_plane that is CRTC-specific, so we create
them when initializing CRTC (calling sun4i_layers_init, which will be
generalized in next patch). The drm_plane's will be used when creating
CRTC, but the CRTC initialization code do not care other properties of
the layer, so we let the sun4i_layers_init function return drm_plane's
only.

As we have no need to trace the layers after the CRTC is properly
created, we drop the layers pointer in sun4i_crtc struct.

Doing this uncouples the CRTC code from the type of layer (the
sun4i_layers_init function name is still hardcoded and will be changed
in the next patch), so that we can finally gain support for the
mixer in DE2, which has different layers.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
 drivers/gpu/drm/sun4i/sun4i_crtc.c  | 23 ---
 drivers/gpu/drm/sun4i/sun4i_crtc.h  |  1 -
 drivers/gpu/drm/sun4i/sun4i_layer.c | 18 ++
 drivers/gpu/drm/sun4i/sun4i_layer.h |  4 ++--
 4 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c 
b/drivers/gpu/drm/sun4i/sun4i_crtc.c
index 3c876c3a356a..708b3543d4e9 100644
--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
@@ -139,6 +139,7 @@ struct sun4i_crtc *sun4i_crtc_init(struct drm_device *drm,
   struct sun4i_tcon *tcon)
 {
struct sun4i_crtc *scrtc;
+   struct drm_plane **planes;
struct drm_plane *primary = NULL, *cursor = NULL;
int ret, i;
 
@@ -149,22 +150,22 @@ struct sun4i_crtc *sun4i_crtc_init(struct drm_device *drm,
scrtc->tcon = tcon;
 
/* Create our layers */
-   scrtc->layers = sun4i_layers_init(drm, scrtc->backend);
-   if (IS_ERR(scrtc->layers)) {
+   planes = sun4i_layers_init(drm, scrtc);
+   if (IS_ERR(planes)) {
dev_err(drm->dev, "Couldn't create the planes\n");
return NULL;
}
 
/* find primary and cursor planes for drm_crtc_init_with_planes */
-   for (i = 0; scrtc->layers[i]; i++) {
-   struct sun4i_layer *layer = scrtc->layers[i];
+   for (i = 0; planes[i]; i++) {
+   struct drm_plane *plane = planes[i];
 
-   switch (layer->plane.type) {
+   switch (plane->type) {
case DRM_PLANE_TYPE_PRIMARY:
-   primary = >plane;
+   primary = plane;
break;
case DRM_PLANE_TYPE_CURSOR:
-   cursor = >plane;
+   cursor = plane;
break;
default:
break;
@@ -188,12 +189,12 @@ struct sun4i_crtc *sun4i_crtc_init(struct drm_device *drm,
   1);
 
/* Set possible_crtcs to this crtc for overlay planes */
-   for (i = 0; scrtc->layers[i]; i++) {
+   for (i = 0; planes[i]; i++) {
uint32_t possible_crtcs = BIT(drm_crtc_index(>crtc));
-   struct sun4i_layer *layer = scrtc->layers[i];
+   struct drm_plane *plane = planes[i];
 
-   if (layer->plane.type == DRM_PLANE_TYPE_OVERLAY)
-   layer->plane.possible_crtcs = possible_crtcs;
+   if (plane->type == DRM_PLANE_TYPE_OVERLAY)
+   plane->possible_crtcs = possible_crtcs;
}
 
return scrtc;
diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.h 
b/drivers/gpu/drm/sun4i/sun4i_crtc.h
index 230cb8f0d601..4dae3508424a 100644
--- a/drivers/gpu/drm/sun4i/sun4i_crtc.h
+++ b/drivers/gpu/drm/sun4i/sun4i_crtc.h
@@ -19,7 +19,6 @@ struct sun4i_crtc {
 
struct sun4i_backend*backend;
struct sun4i_tcon   *tcon;
-   struct sun4i_layer  **layers;
 };
 
 static inline struct sun4i_crtc *drm_crtc_to_sun4i_crtc(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c 
b/drivers/gpu/drm/sun4i/sun4i_layer.c
index f26bde5b9117..e1f03e1cc0ac 100644
--- a/drivers/gpu/drm/sun4i/sun4i_layer.c
+++ b/drivers/gpu/drm/sun4i/sun4i_layer.c
@@ -16,6 +16,7 @@
 #include 
 
 #include "sun4i_backend.h"
+#include "sun4i_crtc.h"
 #include "sun4i_layer.h"
 
 struct sun4i_plane_desc {
@@ -128,15 +129,16 @@ static struct sun4i_layer *sun4i_layer_init_one(struct 
drm_device *drm,
return layer;
 }
 
-struct sun4i_layer **sun4i_layers_init(struct drm_device *drm,
-  struct sun4i_backend *backend)
+struct drm_plane **sun4i_layers_init(struct drm_device *drm,
+struct sun4i_crtc *crtc)
 {
-   struct sun4i_layer **layer

[PATCH v7 05/13] drm/sun4i: abstract a engine type

[Icenowy Zheng]

As we are going to add support for the Allwinner DE2 engine in sun4i-drm
driver, we will finally have two types of display engines -- the DE1
backend and the DE2 mixer. They both do some display blending and feed
graphics data to TCON, and is part of the "Display Engine" called by
Allwinner, so I choose to call them both "engine" here.

Abstract the engine type to a new struct with an ops struct, which contains
functions that should be called outside the engine-specified code (in
TCON, CRTC or TV Encoder code).

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v7:
- Mention "Display Engine" for the name "engine".
- Fixed some small issues found by Chen-Yu and added his ACK.
Changes in v6:
- Rebased on wens's multi-pipeline patchset.
- Split out Makefile changes.
Changes in v5:
- Really made a sunxi_engine struct type, and moved ops pointer
  into it.
- Added checked ops wrappers.
- Changed the second parameter of layers_init from crtc to engine.
Changes in v4:
- Comments to tag the color correction functions as optional.
- Check before calling the optional functions.
- Change layers_init to satisfy new PATCH v4 04/11.

 drivers/gpu/drm/sun4i/sun4i_backend.c |  68 -
 drivers/gpu/drm/sun4i/sun4i_backend.h |  17 +++---
 drivers/gpu/drm/sun4i/sun4i_crtc.c|  11 ++--
 drivers/gpu/drm/sun4i/sun4i_crtc.h|   4 +-
 drivers/gpu/drm/sun4i/sun4i_drv.c |   2 +-
 drivers/gpu/drm/sun4i/sun4i_drv.h |   2 +-
 drivers/gpu/drm/sun4i/sun4i_layer.c   |   9 ++-
 drivers/gpu/drm/sun4i/sun4i_layer.h   |   4 +-
 drivers/gpu/drm/sun4i/sun4i_tcon.c|  38 ++--
 drivers/gpu/drm/sun4i/sun4i_tv.c  |   9 ++-
 drivers/gpu/drm/sun4i/sunxi_engine.h  | 111 ++
 11 files changed, 199 insertions(+), 76 deletions(-)
 create mode 100644 drivers/gpu/drm/sun4i/sunxi_engine.h

diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c 
b/drivers/gpu/drm/sun4i/sun4i_backend.c
index e53107418add..611cdcb9c182 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -25,6 +25,8 @@
 
 #include "sun4i_backend.h"
 #include "sun4i_drv.h"
+#include "sun4i_layer.h"
+#include "sunxi_engine.h"
 
 static const u32 sunxi_rgb2yuv_coef[12] = {
0x0107, 0x0204, 0x0064, 0x0108,
@@ -32,41 +34,38 @@ static const u32 sunxi_rgb2yuv_coef[12] = {
0x01c1, 0x3e88, 0x3fb8, 0x0808
 };
 
-void sun4i_backend_apply_color_correction(struct sun4i_backend *backend)
+static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
 {
int i;
 
DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
 
/* Set color correction */
-   regmap_write(backend->regs, SUN4I_BACKEND_OCCTL_REG,
+   regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
 SUN4I_BACKEND_OCCTL_ENABLE);
 
for (i = 0; i < 12; i++)
-   regmap_write(backend->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
+   regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
 sunxi_rgb2yuv_coef[i]);
 }
-EXPORT_SYMBOL(sun4i_backend_apply_color_correction);
 
-void sun4i_backend_disable_color_correction(struct sun4i_backend *backend)
+static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
 {
DRM_DEBUG_DRIVER("Disabling color correction\n");
 
/* Disable color correction */
-   regmap_update_bits(backend->regs, SUN4I_BACKEND_OCCTL_REG,
+   regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
   SUN4I_BACKEND_OCCTL_ENABLE, 0);
 }
-EXPORT_SYMBOL(sun4i_backend_disable_color_correction);
 
-void sun4i_backend_commit(struct sun4i_backend *backend)
+static void sun4i_backend_commit(struct sunxi_engine *engine)
 {
DRM_DEBUG_DRIVER("Committing changes\n");
 
-   regmap_write(backend->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
+   regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
 SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
 SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
 }
-EXPORT_SYMBOL(sun4i_backend_commit);
 
 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
int layer, bool enable)
@@ -81,7 +80,7 @@ void sun4i_backend_layer_enable(struct sun4i_backend *backend,
else
val = 0;
 
-   regmap_update_bits(backend->regs, SUN4I_BACKEND_MODCTL_REG,
+   regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
   SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
 }
 EXPORT_SYMBOL(sun4i_backend_layer_enable);
@@ -144,27 +143,28 @@ int sun4i_backend_update_layer_coord(struct sun4i_backend 
*backend,
if (plane->type == DRM_PLANE_TYPE_P

[PATCH v7 01/13] dt-bindings: add binding for the Allwinner DE2 CCU

[Icenowy Zheng]

Allwinner "Display Engine 2.0" contains some clock controls in it.

In order to add them as clock drivers, we need a device tree binding.
Add the binding here.

Also add the device tree binding headers.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v7:
- Added V3s compatible.
Changes in v6:
- Added Rob's ACK.
- Droped A64's compatible as it's not appropriate now.
Changes in v5:
- Moved dt-binding headers here.
- Changed dt-binding headers' license header to SPDX license.
Changes in v4:
- Dropped the leading 0 in clock at 100 .
Changes in v3:
- Fill the address space length of DE2 CCU to 0x10, just reach the start of 
mixer0.

 .../devicetree/bindings/clock/sun8i-de2.txt| 31 ++
 include/dt-bindings/clock/sun8i-de2.h  | 18 +
 include/dt-bindings/reset/sun8i-de2.h  | 14 ++
 3 files changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sun8i-de2.txt
 create mode 100644 include/dt-bindings/clock/sun8i-de2.h
 create mode 100644 include/dt-bindings/reset/sun8i-de2.h

diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt 
b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
new file mode 100644
index ..631d27cd89d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -0,0 +1,31 @@
+Allwinner Display Engine 2.0 Clock Control Binding
+--
+
+Required properties :
+- compatible: must contain one of the following compatibles:
+   - "allwinner,sun8i-a83t-de2-clk"
+   - "allwinner,sun8i-v3s-de2-clk"
+   - "allwinner,sun50i-h5-de2-clk"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the clocks feeding the display engine subsystem.
+ Three are needed:
+  - "mod": the display engine module clock
+  - "bus": the bus clock for the whole display engine subsystem
+- clock-names: Must contain the clock names described just above
+- resets: phandle to the reset control for the display engine subsystem.
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+de2_clocks: clock@100 {
+   compatible = "allwinner,sun8i-a83t-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_BUS_DE>,
+< CLK_DE>;
+   clock-names = "bus",
+ "mod";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+};
diff --git a/include/dt-bindings/clock/sun8i-de2.h 
b/include/dt-bindings/clock/sun8i-de2.h
new file mode 100644
index ..3bed63b524aa
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-de2.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icen...@aosc.io>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
+
+#define CLK_BUS_MIXER0 0
+#define CLK_BUS_MIXER1 1
+#define CLK_BUS_WB 2
+
+#define CLK_MIXER0 6
+#define CLK_MIXER1 7
+#define CLK_WB 8
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
diff --git a/include/dt-bindings/reset/sun8i-de2.h 
b/include/dt-bindings/reset/sun8i-de2.h
new file mode 100644
index ..9526017432f0
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-de2.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icen...@aosc.io>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_
+#define _DT_BINDINGS_RESET_SUN8I_DE2_H_
+
+#define RST_MIXER0 0
+#define RST_MIXER1 1
+#define RST_WB 2
+
+#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */
-- 
2.12.2

[PATCH v7 00/13] Initial Allwinner Display Engine 2.0 Support

[Icenowy Zheng]

This patchset is the initial patchset for Allwinner DE2 support.

It contains the support of clocks in DE2 and the mixers in DE2.

The SoC used to develop this patchset is V3s, as V3s is the simplest
one of the SoCs that have DE2.

(Allwinner V3s features only one mixer, and its only video output is
RGB LCD, which is already supported in our TCON driver)

The last patch is only a testing patch, it shouldn't be merged; and
for the patch to be really usable, the RFC fix of the TCON driver [1]
is needed.

No HDMI, TV encoder or other internal bridges' support is included
in this patchset, which makes it currently not usable on H3. (For TVE
I have some code that made it working; for HDMI there is a driver by
Jernej Skrabec which is based on the dw-hdmi common code.)

Thanks to Jean-Francois Moine and Jernej Skrabec for their efforts
to discover the internal of DE2!

[1] https://lists.freedesktop.org/archives/dri-devel/2016-December/126264.html

Icenowy Zheng (13):
  dt-bindings: add binding for the Allwinner DE2 CCU
  clk: sunxi-ng: add support for DE2 CCU
  dt-bindings: add bindings for DE2 on V3s SoC
  drm/sun4i: return only planes for layers created
  drm/sun4i: abstract a engine type
  drm/sun4i: add a dedicated module for sun4i-backend and sun4i-layer
  drm/sun4i: add a Kconfig option for sun4i-backend
  drm/sun4i: add support for Allwinner DE2 mixers
  drm/sun4i: Add compatible string for V3s display engine
  drm/sun4i: tcon: add support for V3s TCON
  ARM: sun8i: v3s: add device nodes for DE2 display pipeline
  ARM: sun8i: v3s: add pinmux for LCD pins of V3s SoC
  [DO NOT MERGE] ARM: sun8i: v3s: enable LCD panel of Lichee Pi Zero

 .../devicetree/bindings/clock/sun8i-de2.txt|  31 ++
 .../bindings/display/sunxi/sun4i-drm.txt   |  26 +-
 arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts  |  36 ++
 arch/arm/boot/dts/sun8i-v3s.dtsi   |  96 +
 drivers/clk/sunxi-ng/Kconfig   |   5 +
 drivers/clk/sunxi-ng/Makefile  |   1 +
 drivers/clk/sunxi-ng/ccu-sun8i-de2.c   | 260 +
 drivers/clk/sunxi-ng/ccu-sun8i-de2.h   |  28 ++
 drivers/gpu/drm/sun4i/Kconfig  |  20 +
 drivers/gpu/drm/sun4i/Makefile |   9 +-
 drivers/gpu/drm/sun4i/sun4i_backend.c  |  72 ++--
 drivers/gpu/drm/sun4i/sun4i_backend.h  |  17 +-
 drivers/gpu/drm/sun4i/sun4i_crtc.c |  32 +-
 drivers/gpu/drm/sun4i/sun4i_crtc.h |   5 +-
 drivers/gpu/drm/sun4i/sun4i_drv.c  |   6 +-
 drivers/gpu/drm/sun4i/sun4i_drv.h  |   2 +-
 drivers/gpu/drm/sun4i/sun4i_layer.c|  21 +-
 drivers/gpu/drm/sun4i/sun4i_layer.h|   6 +-
 drivers/gpu/drm/sun4i/sun4i_tcon.c |  43 ++-
 drivers/gpu/drm/sun4i/sun4i_tv.c   |   9 +-
 drivers/gpu/drm/sun4i/sun8i_layer.c| 134 +++
 drivers/gpu/drm/sun4i/sun8i_layer.h|  36 ++
 drivers/gpu/drm/sun4i/sun8i_mixer.c| 412 +
 drivers/gpu/drm/sun4i/sun8i_mixer.h| 137 +++
 drivers/gpu/drm/sun4i/sunxi_engine.h   | 111 ++
 include/dt-bindings/clock/sun8i-de2.h  |  18 +
 include/dt-bindings/reset/sun8i-de2.h  |  14 +
 27 files changed, 1485 insertions(+), 102 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/sun8i-de2.txt
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-de2.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-de2.h
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.h
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.h
 create mode 100644 drivers/gpu/drm/sun4i/sunxi_engine.h
 create mode 100644 include/dt-bindings/clock/sun8i-de2.h
 create mode 100644 include/dt-bindings/reset/sun8i-de2.h

-- 
2.12.2

Re: [linux-sunxi] Re: [PATCH v7 05/13] drm/sun4i: abstract a engine type

[Icenowy Zheng]

于 2017年5月15日 GMT+08:00 下午5:20:01, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Mon, May 15, 2017 at 12:30:37AM +0800, Icenowy Zheng wrote:
>> As we are going to add support for the Allwinner DE2 engine in
>sun4i-drm
>> driver, we will finally have two types of display engines -- the DE1
>> backend and the DE2 mixer. They both do some display blending and
>feed
>> graphics data to TCON, and is part of the "Display Engine" called by
>> Allwinner, so I choose to call them both "engine" here.
>> 
>> Abstract the engine type to a new struct with an ops struct, which
>contains
>> functions that should be called outside the engine-specified code (in
>> TCON, CRTC or TV Encoder code).
>> 
>> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>> Reviewed-by: Chen-Yu Tsai <w...@csie.org>
>> ---
>> Changes in v7:
>> - Mention "Display Engine" for the name "engine".
>> - Fixed some small issues found by Chen-Yu and added his ACK.
>> Changes in v6:
>> - Rebased on wens's multi-pipeline patchset.
>> - Split out Makefile changes.
>
>You also added a get_id callback here...
>
>> +static const struct sunxi_engine_ops sun4i_backend_engine_ops = {
>> +.commit = sun4i_backend_commit,
>> +.layers_init= sun4i_layers_init,
>> +.apply_color_correction = sun4i_backend_apply_color_correction,
>> +.disable_color_correction   = 
>> sun4i_backend_disable_color_correction,
>> +};
>> +
>
>... that you don't populate ...
>
>> @@ -477,7 +481,7 @@ static int sun4i_tcon_bind(struct device *dev,
>struct device *master,
>>  dev_set_drvdata(dev, tcon);
>>  tcon->drm = drm;
>>  tcon->dev = dev;
>> -tcon->id = backend->id;
>> +tcon->id = sunxi_engine_get_id(engine);
>
>... that you call to fill the TCON ID ...
>
>> +/**
>> + * sunxi_engine_get_id - Get the ID of the engine.
>> + * @engine: pointer to the engine
>> + *
>> + * If the ID is not necessary, just do not implement it in
>sunxi_engine_ops,
>> + * and a default -1 will be returned.
>> + */
>> +static inline int
>> +sunxi_engine_get_id(struct sunxi_engine *engine)
>> +{
>> +if (engine->ops && engine->ops->get_id)
>> +return engine->ops->get_id(engine);
>> +
>> +return -1;
>
>... and will return -1 if not populated, which essentially means that
>instead of having 0 or 1, we're now having -1 as our id.
>
>This is a regression, and I'm even wondering if we can't just store
>the ID in the sunxi_engine structure. Is anything preventing us to do
>that, instead of using a callback?

Some engines (de2 mixer) doesn't use the ID. But 0 is a valid ID here.

If we just store it in sunxi_engine, it should be assigned -1 for de2 mixer.
Is this applicable?

If it's okay I will do so.

>
>Maxime

Re: [linux-sunxi] Re: [PATCH] pinctrl: use non-devm kmalloc versions for free functions

[Icenowy Zheng]

于 2017年5月11日 GMT+08:00 下午10:01:54, Linus Walleij  写到:
>On Thu, May 4, 2017 at 1:57 AM, Andre Przywara 
>wrote:
>
>> When a pinctrl driver gets interrupted during its probe process
>> (returning -EPROBE_DEFER), the devres system cleans up all allocated
>> resources. During this process it calls
>pinmux_generic_free_functions()
>> and pinctrl_generic_free_groups(), which in turn use managed kmalloc
>> calls for temporarily allocating some memory. Now those calls seem to
>> get added to the devres list, but are apparently not covered by the
>> cleanup process, because this is actually just running and iterating
>the
>> existing list. This leads to those mallocs being left with the
>device,
>> which the devres manager complains about when the driver eventually
>gets
>> probed again:
>> [0.825239] [ cut here ]
>> [0.825256] WARNING: CPU: 1 PID: 89 at drivers/base/dd.c:349
>driver_probe_device+0x2ac/0x2e8
>> [0.825258] Modules linked in:
>> [0.825262]
>> [0.825270] CPU: 1 PID: 89 Comm: kworker/1:1 Not tainted 4.11.0
>#307
>> [0.825272] Hardware name: Pine64+ (DT)
>> [0.825283] Workqueue: events deferred_probe_work_func
>> [0.825288] task: 80007c19c100 task.stack: 80007c16c000
>> [0.825292] PC is at driver_probe_device+0x2ac/0x2e8
>> [0.825296] LR is at driver_probe_device+0x108/0x2e8
>> [0.825300] pc : [] lr : []
>pstate: 2045
>> 
>> This warning is triggered because the devres list is not empty. In
>this
>> case the allocations were using 0 bytes, so no real leaks, but still
>this
>> ugly warning.
>> Looking more closely at these *cleanup* functions, devm_kzalloc() is
>actually
>> not needed, because the memory is just allocated temporarily and can
>be
>> freed just before returning from this function.
>> So fix this issue by using the bog standard kcalloc() call instead of
>> devm_kzalloc() and kfree()ing the memory at the end.
>>
>> This fixes above warnings on boot, which can be observed on *some*
>builds
>> for the Pine64, where the pinctrl driver gets loaded early, but it
>missing
>> resources, so gets deferred and is loaded again (successfully) later.
>> kernelci caught this as well [1].
>>
>> Signed-off-by: Andre Przywara 
>>
>> [1]
>https://storage.kernelci.org/net-next/master/v4.11-rc8-2122-gc08bac03d289/arm64/defconfig/lab-baylibre-seattle/boot-sun50i-a64-pine64-plus.html
>> ---
>> Hi,
>>
>> not sure this is the right fix, I am open to suggestions.
>
>I have queued this as a tentative v4.12-rc1 fix, but a bit undertain.

I think 4.11 has also this issue.

>
>Tejun, do I read your comments on the patch as an ACK?
>
>Yours,
>Linus Walleij

[RFC PATCH 03/11] drm: sun4i: ignore swapped mixer<->tcon connection for DE2

[Icenowy Zheng]

Some SoC's DE2 has two mixers. Defaultly the mixer0 is connected to
tcon0 and mixer1 is connected to tcon1; however by setting a bit
the connection can be swapped.

As we now hardcode the default connection, ignore the bonus endpoint for
the mixer's output and the TCON's input, as they stands for the swapped
connection.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_drv.c  | 27 ++
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 39 +-
 drivers/gpu/drm/sun4i/sun4i_tcon.h |  2 ++
 3 files changed, 59 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 1dd1948025d2..29bf1325ded6 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -173,6 +173,13 @@ static bool sun4i_drv_node_is_frontend(struct device_node 
*node)
of_device_is_compatible(node, 
"allwinner,sun8i-a33-display-frontend");
 }
 
+static bool sun4i_drv_node_is_swappable_de2_mixer(struct device_node *node)
+{
+   /* The V3s has only one mixer-tcon pair, so it's not listed here. */
+   return of_device_is_compatible(node, "allwinner,sun8i-h3-de2-mixer0") ||
+   of_device_is_compatible(node, "allwinner,sun8i-h3-de2-mixer1");
+}
+
 static bool sun4i_drv_node_is_tcon(struct device_node *node)
 {
return of_device_is_compatible(node, "allwinner,sun5i-a13-tcon") ||
@@ -249,6 +256,26 @@ static int sun4i_drv_add_endpoints(struct device *dev,
}
}
 
+   /*
+* The second endpoint of the output of a swappable DE2 mixer
+* is the TCON after connection swapping.
+* Ignore it now, as we now hardcode mixer0->tcon0,
+* mixer1->tcon1 connection.
+*/
+   if (sun4i_drv_node_is_swappable_de2_mixer(node)) {
+   struct of_endpoint endpoint;
+
+   if (of_graph_parse_endpoint(ep, )) {
+   DRM_DEBUG_DRIVER("Couldn't parse endpoint\n");
+   continue;
+   }
+
+   if (endpoint.id) {
+   DRM_DEBUG_DRIVER("Endpoint is an unused 
connection for DE2 mixer... skipping\n");
+   continue;
+   }
+   }
+
/* Walk down our tree */
count += sun4i_drv_add_endpoints(dev, match, remote);
 
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index f44a37a5993d..89a215ff2370 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -425,7 +425,8 @@ static int sun4i_tcon_init_regmap(struct device *dev,
  * requested via the get_id function of the engine.
  */
 static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
-  struct device_node *node)
+  struct device_node *node,
+  bool skip_bonus_ep)
 {
struct device_node *port, *ep, *remote;
struct sunxi_engine *engine;
@@ -439,6 +440,20 @@ static struct sunxi_engine *sun4i_tcon_find_engine(struct 
sun4i_drv *drv,
if (!remote)
continue;
 
+   if (skip_bonus_ep) {
+   struct of_endpoint endpoint;
+
+   if (of_graph_parse_endpoint(ep, )) {
+   DRM_DEBUG_DRIVER("Couldn't parse endpoint\n");
+   continue;
+   }
+
+   if (endpoint.id) {
+   DRM_DEBUG_DRIVER("Skipping bonus mixer->TCON 
connection when searching engine\n");
+   continue;
+   }
+   }
+
/* does this node match any registered engines? */
list_for_each_entry(engine, >engine_list, list) {
if (remote == engine->node) {
@@ -449,7 +464,7 @@ static struct sunxi_engine *sun4i_tcon_find_engine(struct 
sun4i_drv *drv,
}
 
/* keep looking through upstream ports */
-   engine = sun4i_tcon_find_engine(drv, remote);
+   engine = sun4i_tcon_find_engine(drv, remote, skip_bonus_ep);
if (!IS_ERR(engine)) {
of_node_put(remote);
of_node_put(port);
@@ -469,21 +484,27 @@ static int sun4i_tcon_bind(struct device *dev, struct 
device *master,
struct sun4i_tcon *tcon;
int ret;
 
-   engine = sun4i_tcon_find_engine(drv, dev->of_node);
-   if (IS_ERR(engine)) {
-   dev_err

[RFC PATCH 05/11] drm: sun4i: add compatible for H3 display engine

[Icenowy Zheng]

Add a compatible string for H3 display engine in sun4i_drv code.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 29bf1325ded6..c0de0741c923 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -324,6 +324,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun6i-a31-display-engine" },
{ .compatible = "allwinner,sun6i-a31s-display-engine" },
{ .compatible = "allwinner,sun8i-a33-display-engine" },
+   { .compatible = "allwinner,sun8i-h3-display-engine" },
{ .compatible = "allwinner,sun8i-v3s-display-engine" },
{ }
 };
-- 
2.12.2

[RFC PATCH 04/11] drm: sun4i: add support for H3's TCON0/1

[Icenowy Zheng]

From: Icenowy Zheng <icen...@aosc.xyz>

Allwinner H3 has two special TCONs, both come without channel0. And the
TCON1 of H3 has no special clocks even for the channel1.

Add support for these kinds of TCON.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 78 --
 drivers/gpu/drm/sun4i/sun4i_tcon.h |  3 ++
 2 files changed, 61 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 89a215ff2370..7009292f99e4 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -57,6 +57,7 @@ void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int 
channel)
 {
/* Disable the TCON's channel */
if (channel == 0) {
+   WARN_ON(!tcon->quirks->has_channel_0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
   SUN4I_TCON0_CTL_TCON_ENABLE, 0);
clk_disable_unprepare(tcon->dclk);
@@ -66,7 +67,8 @@ void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int 
channel)
WARN_ON(!tcon->quirks->has_channel_1);
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
   SUN4I_TCON1_CTL_TCON_ENABLE, 0);
-   clk_disable_unprepare(tcon->sclk1);
+   if (tcon->quirks->has_channel_1_clk)
+   clk_disable_unprepare(tcon->sclk1);
 }
 EXPORT_SYMBOL(sun4i_tcon_channel_disable);
 
@@ -74,6 +76,7 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int 
channel)
 {
/* Enable the TCON's channel */
if (channel == 0) {
+   WARN_ON(!tcon->quirks->has_channel_0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
   SUN4I_TCON0_CTL_TCON_ENABLE,
   SUN4I_TCON0_CTL_TCON_ENABLE);
@@ -85,7 +88,8 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int 
channel)
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
   SUN4I_TCON1_CTL_TCON_ENABLE,
   SUN4I_TCON1_CTL_TCON_ENABLE);
-   clk_prepare_enable(tcon->sclk1);
+   if (tcon->quirks->has_channel_1_clk)
+   clk_prepare_enable(tcon->sclk1);
 }
 EXPORT_SYMBOL(sun4i_tcon_channel_enable);
 
@@ -132,6 +136,7 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
 
/* Configure the dot clock */
clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
+   WARN_ON(!tcon->quirks->has_channel_0);
 
/* Adjust clock delay */
clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
@@ -209,7 +214,8 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
WARN_ON(!tcon->quirks->has_channel_1);
 
/* Configure the dot clock */
-   clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
+   if (tcon->quirks->has_channel_1_clk)
+   clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
 
/* Adjust clock delay */
clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
@@ -327,13 +333,15 @@ static int sun4i_tcon_init_clocks(struct device *dev,
}
clk_prepare_enable(tcon->clk);
 
-   tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
-   if (IS_ERR(tcon->sclk0)) {
-   dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
-   return PTR_ERR(tcon->sclk0);
+   if (tcon->quirks->has_channel_0) {
+   tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
+   if (IS_ERR(tcon->sclk0)) {
+   dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
+   return PTR_ERR(tcon->sclk0);
+   }
}
 
-   if (tcon->quirks->has_channel_1) {
+   if (tcon->quirks->has_channel_1 && tcon->quirks->has_channel_1_clk) {
tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
if (IS_ERR(tcon->sclk1)) {
dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
@@ -533,10 +541,12 @@ static int sun4i_tcon_bind(struct device *dev, struct 
device *master,
goto err_free_clocks;
}
 
-   ret = sun4i_dclk_create(dev, tcon);
-   if (ret) {
-   dev_err(dev, "Couldn't create our TCON dot clock\n");
-   goto err_free_clocks;
+   if (tcon->quirks->has_channel_0) {
+   ret = sun4i_dclk_create(dev, tcon);
+   if (ret) {
+   dev_err(dev, "Couldn't create our TCON dot clock\n");
+   goto err_free_clocks;
+   }
}
 
ret = sun4i_tcon_init_irq(dev, tcon);
@@ -561,7 +571,8 @@ static int sun4i_tcon_bind(struct device *dev, struct 
device *

[RFC PATCH 02/11] drm: sun4i: add support for H3 mixers

[Icenowy Zheng]

From: Icenowy Zheng <icen...@aosc.xyz>

Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels,
and the other has 1 VI and 1 UI.

Add support for these two variants.

Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
 drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c 
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index cb193c5f1686..d658a3a8159a 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -390,11 +390,29 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = 
{
.ui_num = 1,
 };
 
+static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
+   .vi_num = 1,
+   .ui_num = 3,
+};
+
+static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = {
+   .vi_num = 1,
+   .ui_num = 1,
+};
+
 static const struct of_device_id sun8i_mixer_of_table[] = {
{
.compatible = "allwinner,sun8i-v3s-de2-mixer",
.data = _v3s_mixer_cfg,
},
+   {
+   .compatible = "allwinner,sun8i-h3-de2-mixer0",
+   .data = _h3_mixer0_cfg
+   },
+   {
+   .compatible = "allwinner,sun8i-h3-de2-mixer1",
+   .data = _h3_mixer1_cfg
+   },
{ }
 };
 MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
-- 
2.12.2

[PATCH v8 0/9] Initial Allwinner Display Engine 2.0 Support

[Icenowy Zheng]

This patchset is the initial patchset for Allwinner DE2 support.

As the DE2 CCU support is already applied, this patchset now contains
only DRM changes and device tree changes. 

The SoC used to develop this patchset is V3s, as V3s is the simplest
one of the SoCs that have DE2.

(Allwinner V3s features only one mixer, and its only video output is
RGB LCD, which is already supported in our TCON driver)

The last patch is only a testing patch, it shouldn't be merged; and
for the patch to be really usable, the RFC fix of the TCON driver [1]
is needed.

No HDMI, TV encoder or other internal bridges' support is included
in this patchset, which makes it currently not usable on H3.

Thanks to Jean-Francois Moine and Jernej Skrabec for their efforts
to discover the internal of DE2!

[1] https://lists.freedesktop.org/archives/dri-devel/2016-December/126264.html

Icenowy Zheng (9):
  drm/sun4i: abstract a engine type
  drm/sun4i: add a dedicated module for sun4i-backend and sun4i-layer
  drm/sun4i: add a Kconfig option for sun4i-backend
  drm/sun4i: add support for Allwinner DE2 mixers
  drm/sun4i: Add compatible string for V3s display engine
  drm/sun4i: tcon: add support for V3s TCON
  ARM: sun8i: v3s: add device nodes for DE2 display pipeline
  ARM: sun8i: v3s: add pinmux for LCD pins of V3s SoC
  [DO NOT MERGE] ARM: sun8i: v3s: enable LCD panel of Lichee Pi Zero

 arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts |  36 +++
 arch/arm/boot/dts/sun8i-v3s.dtsi  |  96 ++
 drivers/gpu/drm/sun4i/Kconfig |  20 ++
 drivers/gpu/drm/sun4i/Makefile|   9 +-
 drivers/gpu/drm/sun4i/sun4i_backend.c |  78 ++---
 drivers/gpu/drm/sun4i/sun4i_backend.h |  19 +-
 drivers/gpu/drm/sun4i/sun4i_crtc.c|  11 +-
 drivers/gpu/drm/sun4i/sun4i_crtc.h|   4 +-
 drivers/gpu/drm/sun4i/sun4i_drv.c |   6 +-
 drivers/gpu/drm/sun4i/sun4i_drv.h |   2 +-
 drivers/gpu/drm/sun4i/sun4i_layer.c   |   9 +-
 drivers/gpu/drm/sun4i/sun4i_layer.h   |   4 +-
 drivers/gpu/drm/sun4i/sun4i_tcon.c|  43 +--
 drivers/gpu/drm/sun4i/sun4i_tv.c  |   9 +-
 drivers/gpu/drm/sun4i/sun8i_layer.c   | 134 +
 drivers/gpu/drm/sun4i/sun8i_layer.h   |  36 +++
 drivers/gpu/drm/sun4i/sun8i_mixer.c   | 414 ++
 drivers/gpu/drm/sun4i/sun8i_mixer.h   | 137 +
 drivers/gpu/drm/sun4i/sunxi_engine.h  |  98 ++
 19 files changed, 1077 insertions(+), 88 deletions(-)
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.h
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.h
 create mode 100644 drivers/gpu/drm/sun4i/sunxi_engine.h

-- 
2.12.2

[RFC PATCH 00/11] Support for H3 Composite Output support

[Icenowy Zheng]

This patchset depends on the DE2 patchset, version 8 of that patchset
is available at [1].

Allwinner H3 SoC features a TV Encoder like the one in Allwinner A13,
which can only output TV Composite signal.

The display pipeline of H3 is also special -- it has two mixers and
two TCONs, of which the connection can be swapped. The TCONs do not
have channel 0 (as they are all connected to internal bridges, TVE
and HDMI TX).

Add support for the display pipeline and the TVE in H3, in order to
make it possible to display something with mainline kernel with H3.

The image quality of TVE is bad, so HDMI is a better output -- this
patchset also prepared the mixers and TCONs for HDMI output, and
the HDMI controller driver is already done by Jernej Skrabec.

Currently the jack detection feature of the TVE is still not so
clear -- so it's not implemented in this version. Thus the TV
output shouldn't be defaultly enabled now.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-May/506806.html

Icenowy Zheng (11):
  dt-bindings: update the binding for Allwinner H3 TVE support
  drm: sun4i: add support for H3 mixers
  drm: sun4i: ignore swapped mixer<->tcon connection for DE2
  drm: sun4i: add support for H3's TCON0/1
  drm: sun4i: add compatible for H3 display engine
  drm: sun4i: add color space correction support for DE2 mixer
  drm: sun4i: add support for the TV encoder in H3 SoC
  clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3
  clk: sunxi-ng: export CLK_PLL_DE for H3
  ARM: sun8i: h3: add display engine pipeline for TVE
  [DO NOT MERGE] ARM: sun8i: h3: enable TV output on Orange Pi PC

 .../bindings/display/sunxi/sun4i-drm.txt   |  47 -
 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts |  12 ++
 arch/arm/boot/dts/sun8i-h3.dtsi| 189 +
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c|   2 +-
 drivers/clk/sunxi-ng/ccu-sun8i-h3.h|   3 +-
 drivers/gpu/drm/sun4i/sun4i_drv.c  |  28 +++
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 117 +
 drivers/gpu/drm/sun4i/sun4i_tcon.h |   5 +
 drivers/gpu/drm/sun4i/sun4i_tv.c   |  65 ++-
 drivers/gpu/drm/sun4i/sun8i_mixer.c|  53 ++
 drivers/gpu/drm/sun4i/sun8i_mixer.h|   6 +-
 include/dt-bindings/clock/sun8i-h3-ccu.h   |   2 +
 12 files changed, 488 insertions(+), 41 deletions(-)

-- 
2.12.2

[RFC PATCH 01/11] dt-bindings: update the binding for Allwinner H3 TVE support

[Icenowy Zheng]

Allwinner H3 features a "DE2.0" and a TV Encoder.

Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- The connection between H3 TCONs and H3 Mixers
- H3 TV Encoder
- H3 Display engine

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 .../bindings/display/sunxi/sun4i-drm.txt   | 47 --
 1 file changed, 43 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 66b85a195ef2..52781943713b 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -21,7 +21,9 @@ The TV Encoder supports the composite and VGA output. It is 
one end of
 the pipeline.
 
 Required properties:
- - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
+ - compatible: value must be either:
+* allwinner,sun4i-a10-tv-encoder
+* allwinner,sun8i-h3-tv-encoder
  - reg: base address and size of memory-mapped region
  - clocks: the clocks driving the TV encoder
  - resets: phandle to the reset controller driving the encoder
@@ -30,6 +32,13 @@ Required properties:
   Documentation/devicetree/bindings/media/video-interfaces.txt. The
   first port should be the input endpoint.
 
+For "allwinner,sun4i-a10-tv-encoder", there is only one clock required,
+and it's not named.
+
+For "allwinner,sun8i-h3-tv-encoder", these clocks are needed:
+- 'bus': the AHB bus clock of TVE
+- 'mod': the mod clock of TVE
+
 TCON
 
 
@@ -41,29 +50,51 @@ Required properties:
* allwinner,sun6i-a31-tcon
* allwinner,sun6i-a31s-tcon
* allwinner,sun8i-a33-tcon
+   * allwinner,sun8i-h3-tcon0
+   * allwinner,sun8i-h3-tcon1
* allwinner,sun8i-v3s-tcon
  - reg: base address and size of memory-mapped region
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the TCON. Three are needed:
- 'ahb': the interface clocks
-   - 'tcon-ch0': The clock driving the TCON channel 0
  - resets: phandles to the reset controllers driving the encoder
- "lcd": the reset line for the TCON channel 0
 
  - clock-names: the clock names mentioned above
  - reset-names: the reset names mentioned above
- - clock-output-names: Name of the pixel clock created
 
 - ports: A ports node with endpoint definitions as defined in
   Documentation/devicetree/bindings/media/video-interfaces.txt. The
   first port should be the input endpoint, the second one the output
 
+  In the situation of Display Engine 2.0 that the connection between
+  the mixer and the TCON can be swapped, the input should have two
+  endpoints. The first is the default mixer connected to the TCON,
+  the second the mixer which will be connected to the TCON if the
+  swap bit is set.
+
   The output should have two endpoints. The first is the block
   connected to the TCON channel 0 (usually a panel or a bridge), the
   second the block connected to the TCON channel 1 (usually the TV
   encoder)
 
-On SoCs other than the A33 and V3s, there is one more clock required:
+For the following compatibles:
+   * allwinner,sun5i-a13-tcon
+   * allwinner,sun6i-a31-tcon
+   * allwinner,sun6i-a31s-tcon
+   * allwinner,sun8i-a33-tcon
+   * allwinner,sun8i-v3s-tcon
+there is one more clock and one more property required:
+ - clocks:
+   - 'tcon-ch0': The clock driving the TCON channel 0
+ - clock-output-names: Name of the pixel clock created
+
+For the following compatibles:
+   * allwinner,sun5i-a13-tcon
+   * allwinner,sun6i-a31-tcon
+   * allwinner,sun6i-a31s-tcon
+   * allwinner,sun8i-h3-tcon0
+there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
 
 DRC
@@ -158,6 +189,8 @@ supported.
 Required properties:
   - compatible: value must be one of:
 * allwinner,sun8i-v3s-de2-mixer
+* allwinner,sun8i-h3-de2-mixer0
+* allwinner,sun8i-h3-de2-mixer1
   - reg: base address and size of the memory-mapped region.
   - clocks: phandles to the clocks feeding the mixer
 * bus: the mixer interface clock
@@ -169,6 +202,11 @@ Required properties:
   Documentation/devicetree/bindings/media/video-interfaces.txt. The
   first port should be the input endpoints, the second one the output
 
+  In the situation of Display Engine 2.0 that the connection between
+  the mixer and the TCON can be swapped, the output should have two
+  endpoints. The first is the default TCON connected to the mixer,
+  the second the TCON which will be connected to the mixer if the
+  swap bit is set.
 
 Display Engine Pipeline
 ---
@@ -183,6 +221,7 @@ Required properties:
 * allwinner,sun6i-a31-display-engine
 * allwinner,sun6i-a31s-display-engine
 * allwinner,sun8i-a33-display-engine
+* allwinner,sun8i-h3-display-engine
 * allwinner,sun8i-v3s-display-engine
 
   - allwinner,pipelines: list of phandle to the display engine
-- 
2.12.2

[RFC PATCH 11/11] [DO NOT MERGE] ARM: sun8i: h3: enable TV output on Orange Pi PC

[Icenowy Zheng]

Orange Pi PC features a 3.5mm jack with TV output in it.

Enable the TV output.

As it currently do not have jack detection feature, do not merge this
patch.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts 
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 1a044b17d6c6..9c50ac3e82f3 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -97,6 +97,10 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
@@ -169,6 +173,14 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.12.2

[RFC PATCH 06/11] drm: sun4i: add color space correction support for DE2 mixer

[Icenowy Zheng]

The DE2 mixer can do color space correction needed by TV Encoder with
its DCSC sub-engine.

Add support for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/gpu/drm/sun4i/sun8i_mixer.c | 35 +++
 drivers/gpu/drm/sun4i/sun8i_mixer.h |  6 +-
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c 
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index d658a3a8159a..65f86641eca3 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -29,6 +29,14 @@
 #include "sun8i_layer.h"
 #include "sunxi_engine.h"
 
+static const u32 sun8i_rgb2yuv_coef[12] = {
+   0x0107, 0x0204, 0x0064, 0x4200,
+   0x1f68, 0x1ed6, 0x01c2, 0x00020200,
+   0x01c2, 0x1e87, 0x1fb7, 0x00020200,
+};
+
+static const u32 sun8i_rgb2yuv_dcsc_alpha = 0x00020200;
+
 static void sun8i_mixer_commit(struct sunxi_engine *engine)
 {
DRM_DEBUG_DRIVER("Committing changes\n");
@@ -37,6 +45,31 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine)
 SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
 }
 
+static void sun8i_mixer_apply_color_correction(struct sunxi_engine *engine)
+{
+   int i;
+
+   DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
+
+   /* Set color correction */
+   regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 1);
+
+   for (i = 0; i < 12; i++)
+   regmap_write(engine->regs, SUN8I_MIXER_DCSC_COEF_REG(i),
+sun8i_rgb2yuv_coef[i]);
+
+   regmap_write(engine->regs, SUN8I_MIXER_DCSC_COEF_ALPHA,
+sun8i_rgb2yuv_dcsc_alpha);
+}
+
+static void sun8i_mixer_disable_color_correction(struct sunxi_engine *engine)
+{
+   DRM_DEBUG_DRIVER("Disabling color correction\n");
+
+   /* Disable color correction */
+   regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 0);
+}
+
 void sun8i_mixer_layer_enable(struct sun8i_mixer *mixer,
int layer, bool enable)
 {
@@ -229,6 +262,8 @@ int sun8i_mixer_update_layer_buffer(struct sun8i_mixer 
*mixer,
 static const struct sunxi_engine_ops sun8i_engine_ops = {
.commit = sun8i_mixer_commit,
.layers_init= sun8i_layers_init,
+   .apply_color_correction = sun8i_mixer_apply_color_correction,
+   .disable_color_correction   = sun8i_mixer_disable_color_correction,
 };
 
 static struct regmap_config sun8i_mixer_regmap_config = {
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h 
b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index 4785ac090b8c..d7f7513898b6 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -88,6 +88,11 @@
 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_RGB888(8 << 8)
 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_DEF   (0xff << 24)
 
+/* The DCSC sub-engine is used to do color space conversation */
+#define SUN8I_MIXER_DCSC_EN0xb
+#define SUN8I_MIXER_DCSC_COEF_REG(x)   (0xb0010 + 0x4 * x)
+#define SUN8I_MIXER_DCSC_COEF_ALPHA0xb0040
+
 /*
  * These sub-engines are still unknown now, the EN registers are here only to
  * be used to disable these sub-engines.
@@ -102,7 +107,6 @@
 #define SUN8I_MIXER_PEAK_EN0xa6000
 #define SUN8I_MIXER_ASE_EN 0xa8000
 #define SUN8I_MIXER_FCC_EN 0xaa000
-#define SUN8I_MIXER_DCSC_EN0xb
 
 struct sun8i_mixer_cfg {
int vi_num;
-- 
2.12.2

[RFC PATCH 07/11] drm: sun4i: add support for the TV encoder in H3 SoC

[Icenowy Zheng]

Allwinner H3 features a TV encoder similar to the one in earlier SoCs,
but with some different points about clocks:
- It has a mod clock and a bus clock.
- The mod clock must be at a fixed rate to generate signal.

Add support for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_tv.c | 65 +---
 1 file changed, 61 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index a9cad00d4ee8..c9943103f499 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -169,14 +170,23 @@ struct tv_mode {
const struct resync_parameters  *resync_params;
 };
 
+struct sun4i_tv_quirks {
+   bool has_mod_clk;
+   bool fixed_clock;
+   unsigned long fixed_clock_rate;
+};
+
 struct sun4i_tv {
struct drm_connectorconnector;
struct drm_encoder  encoder;
 
struct clk  *clk;
+   struct clk  *mod_clk;
struct regmap   *regs;
struct reset_control*reset;
 
+   const struct sun4i_tv_quirks *quirks;
+
struct sun4i_drv*drv;
 };
 
@@ -578,6 +588,10 @@ static int sun4i_tv_bind(struct device *dev, struct device 
*master,
tv->drv = drv;
dev_set_drvdata(dev, tv);
 
+   tv->quirks = of_device_get_match_data(dev);
+   if (!tv->quirks)
+   return -EINVAL;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(dev, res);
if (IS_ERR(regs)) {
@@ -604,7 +618,10 @@ static int sun4i_tv_bind(struct device *dev, struct device 
*master,
return ret;
}
 
-   tv->clk = devm_clk_get(dev, NULL);
+   if (tv->quirks->has_mod_clk)
+   tv->clk = devm_clk_get(dev, "bus");
+   else
+   tv->clk = devm_clk_get(dev, NULL);
if (IS_ERR(tv->clk)) {
dev_err(dev, "Couldn't get the TV encoder clock\n");
ret = PTR_ERR(tv->clk);
@@ -612,6 +629,26 @@ static int sun4i_tv_bind(struct device *dev, struct device 
*master,
}
clk_prepare_enable(tv->clk);
 
+   if (tv->quirks->has_mod_clk) {
+   tv->mod_clk = devm_clk_get(dev, "mod");
+   if (IS_ERR(tv->mod_clk)) {
+   dev_err(dev, "Couldn't get the TV encoder mod clock\n");
+   ret = PTR_ERR(tv->mod_clk);
+   goto err_disable_clk;
+   };
+
+   if (tv->quirks->fixed_clock) {
+   ret = clk_set_rate(tv->mod_clk,
+  tv->quirks->fixed_clock_rate);
+   if (ret) {
+   dev_err(dev, "Couldn't set TV encoder mod clock 
rate\n");
+   goto err_disable_clk;
+   }
+   }
+
+   clk_prepare_enable(tv->mod_clk);
+   }
+
drm_encoder_helper_add(>encoder,
   _tv_helper_funcs);
ret = drm_encoder_init(drm,
@@ -621,14 +658,14 @@ static int sun4i_tv_bind(struct device *dev, struct 
device *master,
   NULL);
if (ret) {
dev_err(dev, "Couldn't initialise the TV encoder\n");
-   goto err_disable_clk;
+   goto err_disable_mod_clk;
}
 
tv->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
dev->of_node);
if (!tv->encoder.possible_crtcs) {
ret = -EPROBE_DEFER;
-   goto err_disable_clk;
+   goto err_disable_mod_clk;
}
 
drm_connector_helper_add(>connector,
@@ -649,6 +686,9 @@ static int sun4i_tv_bind(struct device *dev, struct device 
*master,
 
 err_cleanup_connector:
drm_encoder_cleanup(>encoder);
+err_disable_mod_clk:
+   if (tv->quirks->has_mod_clk)
+   clk_disable_unprepare(tv->mod_clk);
 err_disable_clk:
clk_disable_unprepare(tv->clk);
 err_assert_reset:
@@ -683,8 +723,25 @@ static int sun4i_tv_remove(struct platform_device *pdev)
return 0;
 }
 
+static const struct sun4i_tv_quirks sun4i_a10_tv_quirks = {
+   /* Nothing special */
+};
+
+static const struct sun4i_tv_quirks sun8i_h3_tv_quirks = {
+   .has_mod_clk = true,
+   .fixed_clock = true,
+   .fixed_clock_rate = 21600UL,
+};
+
 static const struct of_device_id sun4i_tv_of_table[] = {
-   { .compatible = "allwinner,sun4i-a10-tv-encoder" },
+   {
+   .compatible = "allwinner,sun4i-a

[RFC PATCH 09/11] clk: sunxi-ng: export CLK_PLL_DE for H3

[Icenowy Zheng]

The CLK_PLL_DE is needed to be referenced in device tree for H3, for
both forcing the parent of PLL_DE.

So export it to the device tree binding header.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.h  | 3 +--
 include/dt-bindings/clock/sun8i-h3-ccu.h | 2 ++
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h 
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
index 85973d1e8165..7029091a6c9f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
@@ -33,9 +33,8 @@
 #define CLK_PLL_PERIPH0_2X 10
 #define CLK_PLL_GPU11
 #define CLK_PLL_PERIPH112
-#define CLK_PLL_DE 13
 
-/* The CPUX clock is exported */
+/* The PLL_DE and CPUX clocks is exported */
 
 #define CLK_AXI15
 #define CLK_AHB1   16
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h 
b/include/dt-bindings/clock/sun8i-h3-ccu.h
index c2afc41d6964..82496a57efd4 100644
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -43,6 +43,8 @@
 #ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
 #define _DT_BINDINGS_CLK_SUN8I_H3_H_
 
+#define CLK_PLL_DE 13
+
 #define CLK_CPUX   14
 
 #define CLK_BUS_CE 20
-- 
2.12.2

[RFC PATCH 10/11] ARM: sun8i: h3: add display engine pipeline for TVE

[Icenowy Zheng]

As we have already the support for the TV encoder on Allwinner H3, add
the display engine pipeline device tree nodes to its DTSI file.

The H5 pipeline has some differences and will be enabled later.

The currently-unused mixer0 and tcon0 are also needed, for the
completement of the pipeline.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 189 
 1 file changed, 189 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..20172ef92415 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -41,6 +41,8 @@
  */
 
 #include "sunxi-h3-h5.dtsi"
+#include 
+#include 
 
 / {
cpus {
@@ -72,6 +74,193 @@
};
};
 
+   de: display-engine {
+   compatible = "allwinner,sun8i-h3-display-engine";
+   allwinner,pipelines = <>,
+ <>;
+   status = "disabled";
+   };
+
+   soc {
+   display_clocks: clock@100 {
+   compatible = "allwinner,sun8i-a83t-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_BUS_DE>,
+< CLK_DE>;
+   clock-names = "bus",
+ "mod";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   assigned-clocks = < CLK_DE>;
+   assigned-clock-parents = < CLK_PLL_DE>;
+   assigned-clock-rates = <43200>;
+   };
+
+   mixer0: mixer@110 {
+   compatible = "allwinner,sun8i-h3-de2-mixer0";
+   reg = <0x0110 0x10>;
+   clocks = <_clocks CLK_BUS_MIXER0>,
+<_clocks CLK_MIXER0>;
+   clock-names = "bus",
+ "mod";
+   resets = <_clocks RST_MIXER0>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mixer0_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   mixer0_out_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_in_mixer0>;
+   };
+
+   mixer0_out_tcon1: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<_in_mixer0>;
+   };
+   };
+   };
+   };
+
+   mixer1: mixer@120 {
+   compatible = "allwinner,sun8i-h3-de2-mixer1";
+   reg = <0x0120 0x10>;
+   clocks = <_clocks CLK_BUS_MIXER1>,
+<_clocks CLK_MIXER1>;
+   clock-names = "bus",
+ "mod";
+   resets = <_clocks RST_WB>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mixer1_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   mixer1_out_tcon1: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_in_mixer1>;
+   };
+
+   mixer1_out_tcon0: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<_in_mixer1>;
+   };
+   };
+   };
+   };
+
+   tcon0: lcd-controller@1c0c000 {
+   compatible = &

[RFC PATCH 08/11] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3

[Icenowy Zheng]

Allwinner H3 features a PLL named CLK_PLL_DE, and a mod clock for the
"Display Engine 2.0" named CLK_DE. As the name indicated, the CLK_PLL_DE
is a PLL for CLK_DE.

Only CLK_DE and CLK_TVE have a parent of CLK_PLL_DE, and CLK_TVE is also
one part of the display clocks.

So allow CLK_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it).

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 4cbc1b701b7c..6e39ba7cb173 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -439,7 +439,7 @@ static SUNXI_CCU_GATE(dram_ts_clk,  "dram-ts",  "dram",
 
 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
-0x104, 0, 4, 24, 3, BIT(31), 0);
+0x104, 0, 4, 24, 3, BIT(31), 
CLK_SET_RATE_PARENT);
 
 static const char * const tcon_parents[] = { "pll-video" };
 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
-- 
2.12.2

Re: [PATCH v8 0/9] Initial Allwinner Display Engine 2.0 Support

[Icenowy Zheng]

于 2017年5月18日 GMT+08:00 上午1:37:39, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Wed, May 17, 2017 at 10:47:16PM +0800, Icenowy Zheng wrote:
>> This patchset is the initial patchset for Allwinner DE2 support.
>> 
>> As the DE2 CCU support is already applied, this patchset now contains
>> only DRM changes and device tree changes. 
>> 
>> The SoC used to develop this patchset is V3s, as V3s is the simplest
>> one of the SoCs that have DE2.
>> 
>> (Allwinner V3s features only one mixer, and its only video output is
>> RGB LCD, which is already supported in our TCON driver)
>> 
>> The last patch is only a testing patch, it shouldn't be merged; and
>> for the patch to be really usable, the RFC fix of the TCON driver [1]
>> is needed.
>> 
>> No HDMI, TV encoder or other internal bridges' support is included
>> in this patchset, which makes it currently not usable on H3.
>> 
>> Thanks to Jean-Francois Moine and Jernej Skrabec for their efforts
>> to discover the internal of DE2!
>> 
>> [1]
>https://lists.freedesktop.org/archives/dri-devel/2016-December/126264.html
>> 
>> Icenowy Zheng (9):
>>   drm/sun4i: abstract a engine type
>>   drm/sun4i: add a dedicated module for sun4i-backend and sun4i-layer
>>   drm/sun4i: add a Kconfig option for sun4i-backend
>>   drm/sun4i: add support for Allwinner DE2 mixers
>>   drm/sun4i: Add compatible string for V3s display engine
>>   drm/sun4i: tcon: add support for V3s TCON
>
>Applied all those patches...
>
>>   ARM: sun8i: v3s: add device nodes for DE2 display pipeline
>
>But this one doesn't apply. Please rebase and resend.

OK. Will rebase it once all these patches entered linux-next.

>
>Maxime

[PATCH v6 2/9] irqchip/sunxi-nmi: add support for the NMI in A64 R_INTC

[Icenowy Zheng]

Add support for the newly imported compatible for the A64 R_INTC in
irq-sunxi-nmi driver.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v5:
- Fix A64 R_INTC compatible.

 drivers/irqchip/irq-sunxi-nmi.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index 668730c5cb66..5559c1d593bf 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -56,6 +56,12 @@ static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = {
.enable = 0x04,
 };
 
+static struct sunxi_sc_nmi_reg_offs sun50i_reg_offs = {
+   .ctrl   = 0x0c,
+   .pend   = 0x10,
+   .enable = 0x40,
+};
+
 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
  u32 val)
 {
@@ -220,3 +226,10 @@ static int __init sun9i_nmi_irq_init(struct device_node 
*node,
return sunxi_sc_nmi_irq_init(node, _reg_offs);
 }
 IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);
+
+static int __init sun50i_nmi_irq_init(struct device_node *node,
+struct device_node *parent)
+{
+   return sunxi_sc_nmi_irq_init(node, _reg_offs);
+}
+IRQCHIP_DECLARE(sun50i_nmi, "allwinner,sun50i-a64-r-intc", 
sun50i_nmi_irq_init);
-- 
2.12.2

[PATCH v6 3/9] arm64: allwinner: a64: add NMI (R_INTC) controller on A64

[Icenowy Zheng]

Allwinner A64 SoC features a R_INTC controller, which controls the NMI
line, and this interrupt line is usually connected to the AXP PMIC.

Add support for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Changes it to use R_INTC binding and change node label to r_intc.
- Fixed MMIO region.
- Dropped Chen-Yu's ACK due to big change.
Changes in v2:
- Added Chen-Yu's ACK.

 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 90dc4ec79485..45c7c3145248 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -445,6 +445,14 @@
 ;
};
 
+   r_intc: interrupt-controller@1f00c00 {
+   compatible = "allwinner,sun50i-a64-r-intc";
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   reg = <0x01f00c00 0x400>;
+   interrupts = ;
+   };
+
r_ccu: clock@1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
-- 
2.12.2

[PATCH v6 4/9] arm64: allwinner: a64: add AXP803 node to Pine64 device tree

[Icenowy Zheng]

The Pine64 (including Pine64+) boards have an AXP803 as its main PMIC.

Add its device node.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v6:
- Rebase on next-20170517.

 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 7c533b6d4ba9..36001884ed33 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -107,6 +107,17 @@
status = "okay";
 };
 
+_rsb {
+   status = "okay";
+
+   axp803: pmic@3a3 {
+   compatible = "x-powers,axp803";
+   reg = <0x3a3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   };
+};
+
 /* On Exp and Euler connectors */
  {
pinctrl-names = "default";
-- 
2.12.2

[PATCH v6 8/9] arm64: allwinner: a64: enable AXP803 regulators for Pine64

[Icenowy Zheng]

Add support of AXP803 regulators in the Pine64 device tree, in order to
enable many future functionalities, e.g. Wi-Fi.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v6:
- Rebased on next-20170517.

 .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109 +
 1 file changed, 109 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 36001884ed33..40921bacb39c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -118,6 +118,115 @@
};
 };
 
+#include "axp803.dtsi"
+
+_aldo1 {
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   regulator-name = "vcc-csi";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pl";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc1sw {
+   regulator-name = "vcc-phy";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-3v3";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <100>;
+   regulator-max-microvolt = <130>;
+   regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_dcdc6 {
+   regulator-always-on;
+   regulator-min-microvolt = <110>;
+   regulator-max-microvolt = <110>;
+   regulator-name = "vdd-sys";
+};
+
+_dldo1 {
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-hdmi";
+};
+
+_dldo2 {
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-mipi";
+};
+
+_dldo3 {
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "avdd-csi";
+};
+
+_dldo4 {
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-wifi";
+};
+
+_eldo1 {
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "cpvdd";
+};
+
+_eldo3 {
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "vdd-1v8-csi";
+};
+
+_fldo1 {
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   regulator-name = "vcc-1v2-hsic";
+};
+
+_fldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <110>;
+   regulator-max-microvolt = <110>;
+   regulator-name = "vdd-cpus";
+};
+
+_rtc_ldo {
+   regulator-name = "vcc-rtc";
+};
+
 /* On Exp and Euler connectors */
  {
pinctrl-names = "default";
-- 
2.12.2

[PATCH v6 9/9] arm64: allwinner: a64: enable Wi-Fi for Pine64

[Icenowy Zheng]

The Wi-Fi module of Pine64 is powered via DLDO4 and ELDO1 (the latter
one provides I/O voltage).

Add device node for it.

Although the Wi-Fi module is an external module which should be inserted
to a header, according to my personal talk with TL Lim, he does not want
this header to be used as GPIO (so it's with 2.0mm pitch, not 2.54mm as
other GPIO headers).

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 40921bacb39c..6e43e2c07025 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -68,6 +68,11 @@
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
};
+
+   wifi_pwrseq: wifi_pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   reset-gpios = <_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+   };
 };
 
  {
@@ -99,6 +104,17 @@
status = "okay";
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   vmmc-supply = <_dldo4>;
+   vqmmc-supply = <_eldo1>;
+   mmc-pwrseq = <_pwrseq>;
+   non-removable;
+   bus-width = <4>;
+   status = "okay";
+};
+
  {
status = "okay";
 };
-- 
2.12.2

[PATCH v6 7/9] arm64: allwinner: a64: add DTSI file for AXP803 PMIC

[Icenowy Zheng]

As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it,
like the old DTSI files for AXP20x/22x, for the common parts of the
PMIC.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Mark Brown <broo...@kernel.org>
---
Changes in v5:
- Added Mark Brown's ACK.
Changes in v4:
- Re-sorted the nodes.

 arch/arm64/boot/dts/allwinner/axp803.dtsi | 150 ++
 1 file changed, 150 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/axp803.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi 
b/arch/arm64/boot/dts/allwinner/axp803.dtsi
new file mode 100644
index ..ff8af52743ff
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2017 Icenowy Zheng <icen...@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * AXP803 Integrated Power Management Chip
+ * http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf
+ */
+
+ {
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   regulators {
+   /* Default work frequency for buck regulators */
+   x-powers,dcdc-freq = <3000>;
+
+   reg_aldo1: aldo1 {
+   regulator-name = "aldo1";
+   };
+
+   reg_aldo2: aldo2 {
+   regulator-name = "aldo2";
+   };
+
+   reg_aldo3: aldo3 {
+   regulator-name = "aldo3";
+   };
+
+   reg_dc1sw: dc1sw {
+   regulator-name = "dc1sw";
+   };
+
+   reg_dcdc1: dcdc1 {
+   regulator-name = "dcdc1";
+   };
+
+   reg_dcdc2: dcdc2 {
+   regulator-name = "dcdc2";
+   };
+
+   reg_dcdc3: dcdc3 {
+   regulator-name = "dcdc3";
+   };
+
+   reg_dcdc4: dcdc4 {
+   regulator-name = "dcdc4";
+   };
+
+   reg_dcdc5: dcdc5 {
+   regulator-name = "dcdc5";
+   };
+
+   reg_dcdc6: dcdc6 {
+   regulator-name = "dcdc6";
+   };
+
+   reg_dldo1: dldo1 {
+   regulator-name = "dldo1";
+   };
+
+   reg_dldo2: dldo2 {
+   regulator-name = "dldo2";
+   };
+
+   reg_dldo3: dldo3 {
+   regulator-name = "dldo3";
+   };
+
+   reg_dldo4: dldo4 {
+   regulator-name = "dldo4";
+   };
+
+   reg_eldo1: eldo1 {
+   regulator-name = "eldo1";
+   };
+
+   reg_eldo2: eldo2 {
+   regulator-name = "eldo2";

[PATCH v6 5/9] regulator: axp20x-regulator: add support for AXP803

[Icenowy Zheng]

AXP803 PMIC also have a series of regulators (DCDCs and LDOs)
controllable via I2C/RSB bus.

Add support for them.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v4:
- Fixed somewhere which mention AXP806 before 803.
Changes in v2:
- Place AXP803 codes before AXP806/809 ones.
- Fixed some errors in regulator description.
- Reuse AXP803 DLDO2 range for AXP806 CLDO2 & AXP809 DLDO1.

 drivers/regulator/axp20x-regulator.c | 153 ++-
 include/linux/mfd/axp20x.h   |  37 +
 2 files changed, 168 insertions(+), 22 deletions(-)

diff --git a/drivers/regulator/axp20x-regulator.c 
b/drivers/regulator/axp20x-regulator.c
index 0b9d4e3e52c7..e2608fe770b9 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -244,6 +244,82 @@ static const struct regulator_desc 
axp22x_drivevbus_regulator = {
.ops= _ops_sw,
 };
 
+static const struct regulator_linear_range axp803_dcdc234_ranges[] = {
+   REGULATOR_LINEAR_RANGE(50, 0x0, 0x46, 1),
+   REGULATOR_LINEAR_RANGE(122, 0x47, 0x4b, 2),
+};
+
+static const struct regulator_linear_range axp803_dcdc5_ranges[] = {
+   REGULATOR_LINEAR_RANGE(80, 0x0, 0x20, 1),
+   REGULATOR_LINEAR_RANGE(114, 0x21, 0x44, 2),
+};
+
+static const struct regulator_linear_range axp803_dcdc6_ranges[] = {
+   REGULATOR_LINEAR_RANGE(60, 0x0, 0x32, 1),
+   REGULATOR_LINEAR_RANGE(112, 0x33, 0x47, 2),
+};
+
+/* AXP806's CLDO2 and AXP809's DLDO1 shares the same range */
+static const struct regulator_linear_range axp803_dldo2_ranges[] = {
+   REGULATOR_LINEAR_RANGE(70, 0x0, 0x1a, 10),
+   REGULATOR_LINEAR_RANGE(340, 0x1b, 0x1f, 20),
+};
+
+static const struct regulator_desc axp803_regulators[] = {
+   AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
+AXP803_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(0)),
+   AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2", axp803_dcdc234_ranges,
+   76, AXP803_DCDC2_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
+   BIT(1)),
+   AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3", axp803_dcdc234_ranges,
+   76, AXP803_DCDC3_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
+   BIT(2)),
+   AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4", axp803_dcdc234_ranges,
+   76, AXP803_DCDC4_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
+   BIT(3)),
+   AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5", axp803_dcdc5_ranges,
+   68, AXP803_DCDC5_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
+   BIT(4)),
+   AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6", axp803_dcdc6_ranges,
+   72, AXP803_DCDC6_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
+   BIT(5)),
+   /* secondary switchable output of DCDC1 */
+   AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2,
+   BIT(7)),
+   AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
+AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(5)),
+   AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
+AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(6)),
+   AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
+AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(7)),
+   AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
+AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(3)),
+   AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin", axp803_dldo2_ranges,
+   32, AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2,
+   BIT(4)),
+   AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
+AXP22X_DLDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)),
+   AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
+AXP22X_DLDO4_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(6)),
+   AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
+AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)),
+   AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
+AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)),
+   AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
+AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)),
+   AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 

[PATCH v6 6/9] mfd: axp20x: add axp20x-regulator cell for AXP803

[Icenowy Zheng]

As axp20x-regulator now supports AXP803, add a cell for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v5:
- Removed wrong snippet.
Changes in v4:
- Added a trailing comma for new cell, for easier further cell addition.
Changes in v3:
- Make the new cell one-liner.

 drivers/mfd/axp20x.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 1dc6235778eb..917b6ddc4f15 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -848,7 +848,8 @@ static struct mfd_cell axp803_cells[] = {
.name   = "axp20x-pek",
.num_resources  = ARRAY_SIZE(axp803_pek_resources),
.resources  = axp803_pek_resources,
-   }
+   },
+   {   .name   = "axp20x-regulator" },
 };
 
 static struct mfd_cell axp806_cells[] = {
-- 
2.12.2

[PATCH v6 1/9] irqchip/sunxi-nmi: add A64 R_INTC to the binding doc

[Icenowy Zheng]

The A31 NMI driver seems to be using wrong base address.

As we're going to convert to use a correct NMI base address (and
correctly name it to R_INTC as the datasheet suggests), add a new
compatible string for the "correct" R_INTC, which we will use for A64
SoC.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v6:
- Added Rob's ACK.

 .../bindings/interrupt-controller/allwinner,sunxi-nmi.txt  | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
 
b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
index 81cd3692405e..fea0c6a6211f 100644
--- 
a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
@@ -3,8 +3,11 @@ Allwinner Sunxi NMI Controller
 
 Required properties:
 
-- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
-  "allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi"
+- compatible : should be one of:
+   "allwinner,sun6i-a31-sc-nmi"
+   "allwinner,sun7i-a20-sc-nmi"
+   "allwinner,sun9i-a80-nmi"
+   "allwinner,sun50i-a64-r-intc"
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.12.2

[PATCH v6 0/9] AXP803 PMIC support for Pine64

[Icenowy Zheng]

The Pine64 (including Pine64+) boards have an AXP803 PMIC, which is a PMIC
similar to AXP288, but tweaked to use with Allwinner SoCs rather than Intel
tablets (with DCIN and Vbus re-splitted like other AXP PMICs, and RSB bus
support added).

This patchset adds support for it and enabled it in Pine64 device tree.

Some parts of this patchset is already applied, including basical AXP803
MFD code and A64 RSB device node.

Thus this patchset is now still two parts, but a bit different to older
revisions:

- Part1: from PATCH 1/9 to PATCH 4/9, which focus on enabling AXP803 in the
  device tree: the R_INTC interrupt controller (for the NMI line, which is
  connected to AXP803 on Pine64), and finally the basical AXP803 node.
- Part2: from PATCH 5/9 to PATCH 9/9, which are enabling the regulator
  function of the AXP803 PMIC. Finally Wi-Fi function is added
  as a usage of regulators function.

PATCH 1 adds device tree binding of A64 R_INTC.

PATCH 2 really adds support for A64 R_INTC in NMI driver.

PATCH 3 adds R_INTC node in A64 device tree.

PATCH 4 adds AXP803 node to the Pine64 device tree by using already
applied drivers/bindings.

PATCH 5 adds support for AXP803 regulators in AXP20x regulatoe driver.
(The binding is already applied)

PATCH 6 enables the AXP803 regulator cell in MFD driver.

PATCH 7 adds a DTSI file for AXP803, like other older AXP PMICs.

PATCH 8 enables AXP803 regulators in Pine64 device tree.

PATCH 9 enables Wi-Fi for Pine64.

Icenowy Zheng (9):
  irqchip/sunxi-nmi: add A64 R_INTC to the binding doc
  irqchip/sunxi-nmi: add support for the NMI in A64 R_INTC
  arm64: allwinner: a64: add NMI (R_INTC) controller on A64
  arm64: allwinner: a64: add AXP803 node to Pine64 device tree
  regulator: axp20x-regulator: add support for AXP803
  mfd: axp20x: add axp20x-regulator cell for AXP803
  arm64: allwinner: a64: add DTSI file for AXP803 PMIC
  arm64: allwinner: a64: enable AXP803 regulators for Pine64
  arm64: allwinner: a64: enable Wi-Fi for Pine64

 .../interrupt-controller/allwinner,sunxi-nmi.txt   |   7 +-
 arch/arm64/boot/dts/allwinner/axp803.dtsi  | 150 
 .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 136 ++
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi  |   8 ++
 drivers/irqchip/irq-sunxi-nmi.c|  13 ++
 drivers/mfd/axp20x.c   |   3 +-
 drivers/regulator/axp20x-regulator.c   | 153 ++---
 include/linux/mfd/axp20x.h |  37 +
 8 files changed, 482 insertions(+), 25 deletions(-)
 create mode 100644 arch/arm64/boot/dts/allwinner/axp803.dtsi

-- 
2.12.2

[PATCH] ARM: sun8i: v3s: fix build of Lichee Pi Zero Dock dtb

[Icenowy Zheng]

The Lichee Pi Zero Dock dtb file is not added to the Makefile, so that
it won't be built; and the file contains a problem that prevents it
from being correctly built.

Fix these issues.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/Makefile | 3 ++-
 arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c5e1d944d1c..929a4167fcaa 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -905,7 +905,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-r16-parrot.dtb \
-   sun8i-v3s-licheepi-zero.dtb
+   sun8i-v3s-licheepi-zero.dtb \
+   sun8i-v3s-licheepi-zero-dock.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts 
b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
index d2bfccf47149..d1311098ea45 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
@@ -42,6 +42,8 @@
 
 #include "sun8i-v3s-licheepi-zero.dts"
 
+#include 
+
 / {
model = "Lichee Pi Zero with Dock";
compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
-- 
2.12.2

[PATCH] ARM: sun8i: v3s: enable SPI

[Icenowy Zheng]

Allwinner V3s SoC has a SPI controller, muxed with the MMC2 controller
at PC bank. The controller itself is identical to the one in H3 SoC.

Add device tree node and the only pinmux node for it.

Tested with a Winbond W25Q128FV SPI NOR soldered on the Lichee Pi
early sample.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 6ff50665e5e6..a49ebef53c91 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -234,6 +234,11 @@
drive-strength = <30>;
bias-pull-up;
};
+
+   spi0_pins: spi0 {
+   pins = "PC0", "PC1", "PC2", "PC3";
+   function = "spi0";
+   };
};
 
timer@01c20c00 {
@@ -314,6 +319,20 @@
#size-cells = <0>;
};
 
+   spi0: spi@1c68000 {
+   compatible = "allwinner,sun8i-h3-spi";
+   reg = <0x01c68000 0x1000>;
+   interrupts = ;
+   clocks = < CLK_BUS_SPI0>, < CLK_SPI0>;
+   clock-names = "ahb", "mod";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   resets = < RST_BUS_SPI0>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
-- 
2.12.2

[PATCH v8 1/9] drm/sun4i: abstract a engine type

[Icenowy Zheng]

As we are going to add support for the Allwinner DE2 engine in sun4i-drm
driver, we will finally have two types of display engines -- the DE1
backend and the DE2 mixer. They both do some display blending and feed
graphics data to TCON, and is part of the "Display Engine" called by
Allwinner, so I choose to call them both "engine" here.

Abstract the engine type to a new struct with an ops struct, which contains
functions that should be called outside the engine-specified code (in
TCON, CRTC or TV Encoder code).

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v8:
- Changed id into a field in sunxi_engine struct.
Changes in v7:
- Mention "Display Engine" for the name "engine".
- Fixed some small issues found by Chen-Yu and added his ACK.
Changes in v6:
- Rebased on wens's multi-pipeline patchset.
- Split out Makefile changes.
Changes in v5:
- Really made a sunxi_engine struct type, and moved ops pointer
  into it.
- Added checked ops wrappers.
- Changed the second parameter of layers_init from crtc to engine.
Changes in v4:
- Comments to tag the color correction functions as optional.
- Check before calling the optional functions.
- Change layers_init to satisfy new PATCH v4 04/11.

 drivers/gpu/drm/sun4i/sun4i_backend.c | 74 ++
 drivers/gpu/drm/sun4i/sun4i_backend.h | 19 +++
 drivers/gpu/drm/sun4i/sun4i_crtc.c| 11 ++--
 drivers/gpu/drm/sun4i/sun4i_crtc.h|  4 +-
 drivers/gpu/drm/sun4i/sun4i_drv.c |  2 +-
 drivers/gpu/drm/sun4i/sun4i_drv.h |  2 +-
 drivers/gpu/drm/sun4i/sun4i_layer.c   |  9 ++--
 drivers/gpu/drm/sun4i/sun4i_layer.h   |  4 +-
 drivers/gpu/drm/sun4i/sun4i_tcon.c| 38 --
 drivers/gpu/drm/sun4i/sun4i_tv.c  |  9 ++--
 drivers/gpu/drm/sun4i/sunxi_engine.h  | 98 +++
 11 files changed, 189 insertions(+), 81 deletions(-)
 create mode 100644 drivers/gpu/drm/sun4i/sunxi_engine.h

diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c 
b/drivers/gpu/drm/sun4i/sun4i_backend.c
index e53107418add..4af8ccb10bff 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -25,6 +25,8 @@
 
 #include "sun4i_backend.h"
 #include "sun4i_drv.h"
+#include "sun4i_layer.h"
+#include "sunxi_engine.h"
 
 static const u32 sunxi_rgb2yuv_coef[12] = {
0x0107, 0x0204, 0x0064, 0x0108,
@@ -32,41 +34,38 @@ static const u32 sunxi_rgb2yuv_coef[12] = {
0x01c1, 0x3e88, 0x3fb8, 0x0808
 };
 
-void sun4i_backend_apply_color_correction(struct sun4i_backend *backend)
+static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
 {
int i;
 
DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
 
/* Set color correction */
-   regmap_write(backend->regs, SUN4I_BACKEND_OCCTL_REG,
+   regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
 SUN4I_BACKEND_OCCTL_ENABLE);
 
for (i = 0; i < 12; i++)
-   regmap_write(backend->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
+   regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
 sunxi_rgb2yuv_coef[i]);
 }
-EXPORT_SYMBOL(sun4i_backend_apply_color_correction);
 
-void sun4i_backend_disable_color_correction(struct sun4i_backend *backend)
+static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
 {
DRM_DEBUG_DRIVER("Disabling color correction\n");
 
/* Disable color correction */
-   regmap_update_bits(backend->regs, SUN4I_BACKEND_OCCTL_REG,
+   regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
   SUN4I_BACKEND_OCCTL_ENABLE, 0);
 }
-EXPORT_SYMBOL(sun4i_backend_disable_color_correction);
 
-void sun4i_backend_commit(struct sun4i_backend *backend)
+static void sun4i_backend_commit(struct sunxi_engine *engine)
 {
DRM_DEBUG_DRIVER("Committing changes\n");
 
-   regmap_write(backend->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
+   regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
 SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
 SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
 }
-EXPORT_SYMBOL(sun4i_backend_commit);
 
 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
int layer, bool enable)
@@ -81,7 +80,7 @@ void sun4i_backend_layer_enable(struct sun4i_backend *backend,
else
val = 0;
 
-   regmap_update_bits(backend->regs, SUN4I_BACKEND_MODCTL_REG,
+   regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
   SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
 }
 EXPORT_SYMBOL(sun4i_backend_layer_enable);
@@ -144,27 +143,28 @@ int sun4i_backend_update_layer_coord(struct sun4i_b

[PATCH v8 4/9] drm/sun4i: add support for Allwinner DE2 mixers

[Icenowy Zheng]

Allwinner have a new "Display Engine 2.0" in their new SoCs, which comes
with mixers to do graphic processing and feed data to TCON, like the old
backends and frontends.

Add support for the mixer on Allwinner V3s SoC; it's the simplest one.

Currently a lot of functions are still missing -- more investigations
are needed to gain enough information for them.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v8:
- Set id manually to -1.
Changes in v7:
- Small fixed advised by Maxime Ripard.
- Added fixup on CRTC destination coordinate.
Changes in v6:
- Rebased on wens's multi-pipeline patchset.
Changes in v5:
- Changed some code alignment.
- Request real 32-bit DMA (prepare for 64-bit SoCs).
Changes in v4:
- Killed some dead code according to Jernej.

 drivers/gpu/drm/sun4i/Kconfig   |  10 +
 drivers/gpu/drm/sun4i/Makefile  |   3 +
 drivers/gpu/drm/sun4i/sun8i_layer.c | 134 
 drivers/gpu/drm/sun4i/sun8i_layer.h |  36 
 drivers/gpu/drm/sun4i/sun8i_mixer.c | 414 
 drivers/gpu/drm/sun4i/sun8i_mixer.h | 137 
 6 files changed, 734 insertions(+)
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.h
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.h

diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 5a8227f37cc4..978ed5032762 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -22,3 +22,13 @@ config DRM_SUN4I_BACKEND
  original Allwinner Display Engine, which has a backend to
  do some alpha blending and feed graphics to TCON. If M is
  selected the module will be called sun4i-backend.
+
+config DRM_SUN8I_MIXER
+   tristate "Support for Allwinner Display Engine 2.0 Mixer"
+   depends on DRM_SUN4I
+   default MACH_SUN8I
+   help
+ Choose this option if you have an Allwinner SoC with the
+ Allwinner Display Engine 2.0, which has a mixer to do some
+ graphics mixture and feed graphics to TCON, If M is
+ selected the module will be called sun8i-mixer.
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index da561d064ab8..7fce97a6f4b8 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -8,8 +8,11 @@ sun4i-tcon-y += sun4i_crtc.o
 
 sun4i-backend-y += sun4i_backend.o sun4i_layer.o
 
+sun8i-mixer-y += sun8i_mixer.o sun8i_layer.o
+
 obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o
 obj-$(CONFIG_DRM_SUN4I)+= sun6i_drc.o
 obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o
 
 obj-$(CONFIG_DRM_SUN4I_BACKEND)+= sun4i-backend.o
+obj-$(CONFIG_DRM_SUN8I_MIXER)  += sun8i-mixer.o
diff --git a/drivers/gpu/drm/sun4i/sun8i_layer.c 
b/drivers/gpu/drm/sun4i/sun8i_layer.c
new file mode 100644
index ..e627eeece658
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun8i_layer.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) Icenowy Zheng <icen...@aosc.io>
+ *
+ * Based on sun4i_layer.h, which is:
+ *   Copyright (C) 2015 Free Electrons
+ *   Copyright (C) 2015 NextThing Co
+ *
+ *   Maxime Ripard <maxime.rip...@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+
+#include "sun8i_layer.h"
+#include "sun8i_mixer.h"
+
+struct sun8i_plane_desc {
+  enum drm_plane_type type;
+  const uint32_t  *formats;
+  uint32_tnformats;
+};
+
+static void sun8i_mixer_layer_atomic_disable(struct drm_plane *plane,
+  struct drm_plane_state 
*old_state)
+{
+   struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+   struct sun8i_mixer *mixer = layer->mixer;
+
+   sun8i_mixer_layer_enable(mixer, layer->id, false);
+}
+
+static void sun8i_mixer_layer_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+   struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+   struct sun8i_mixer *mixer = layer->mixer;
+
+   sun8i_mixer_update_layer_coord(mixer, layer->id, plane);
+   sun8i_mixer_update_layer_formats(mixer, layer->id, plane);
+   sun8i_mixer_update_layer_buffer(mixer, layer->id, plane);
+   sun8i_mixer_layer_enable(mixer, layer->id, true);
+}
+
+static struct drm_plane_helper_funcs sun8i_mixer_layer_helper_funcs = {
+   .atomic_disable = sun8i_mixer_layer_atomic_disable,
+   .atomic_update  = sun8i_mixer_layer_atomic_update,
+};
+
+static const s