from:"Icenowy Zheng"

[PATCH v6 01/13] dt-bindings: add binding for the Allwinner DE2 CCU

2017-05-04 Thread Icenowy Zheng

Allwinner "Display Engine 2.0" contains some clock controls in it.

In order to add them as clock drivers, we need a device tree binding.
Add the binding here.

Also add the device tree binding headers.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v6:
- Added Rob's ACK.
- Drpoped A64's compatible as it's not appropriate now.
Changes in v5:
- Moved dt-binding headers here.
- Changed dt-binding headers' license header to SPDX license.
Changes in v4:
- Dropped the leading 0 in clock at 100 .
Changes in v3:
- Fill the address space length of DE2 CCU to 0x10, just reach the start of 
mixer0.

 .../devicetree/bindings/clock/sun8i-de2.txt| 30 ++
 include/dt-bindings/clock/sun8i-de2.h  | 18 +
 include/dt-bindings/reset/sun8i-de2.h  | 14 ++
 3 files changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sun8i-de2.txt
 create mode 100644 include/dt-bindings/clock/sun8i-de2.h
 create mode 100644 include/dt-bindings/reset/sun8i-de2.h

diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt 
b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
new file mode 100644
index ..d710c0111cd3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -0,0 +1,30 @@
+Allwinner Display Engine 2.0 Clock Control Binding
+--
+
+Required properties :
+- compatible: must contain one of the following compatibles:
+   - "allwinner,sun8i-a83t-de2-clk"
+   - "allwinner,sun50i-h5-de2-clk"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the clocks feeding the display engine subsystem.
+ Three are needed:
+  - "mod": the display engine module clock
+  - "bus": the bus clock for the whole display engine subsystem
+- clock-names: Must contain the clock names described just above
+- resets: phandle to the reset control for the display engine subsystem.
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+de2_clocks: clock@100 {
+   compatible = "allwinner,sun8i-a83t-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_DE>,
+< CLK_BUS_DE>;
+   clock-names = "mod",
+ "bus";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+};
diff --git a/include/dt-bindings/clock/sun8i-de2.h 
b/include/dt-bindings/clock/sun8i-de2.h
new file mode 100644
index 00000000..3bed63b524aa
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-de2.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icen...@aosc.io>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
+
+#define CLK_BUS_MIXER0 0
+#define CLK_BUS_MIXER1 1
+#define CLK_BUS_WB 2
+
+#define CLK_MIXER0 6
+#define CLK_MIXER1 7
+#define CLK_WB 8
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
diff --git a/include/dt-bindings/reset/sun8i-de2.h 
b/include/dt-bindings/reset/sun8i-de2.h
new file mode 100644
index 0000..9526017432f0
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-de2.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icen...@aosc.io>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_
+#define _DT_BINDINGS_RESET_SUN8I_DE2_H_
+
+#define RST_MIXER0 0
+#define RST_MIXER1 1
+#define RST_WB 2
+
+#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */
-- 
2.12.2

[PATCH v6 09/13] drm/sun4i: Add compatible string for V3s display engine

2017-05-04 Thread Icenowy Zheng

Allwinner V3s features the new "Display Engine 2.0", which can now also
be driven with our subdrivers in sun4i-drm.

Add the compatible string for in sun4i_drv.c, in order to make the
display engine and its components probed.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 12ede8682b5c..dcfb241f817d 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -306,6 +306,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun6i-a31-display-engine" },
{ .compatible = "allwinner,sun6i-a31s-display-engine" },
{ .compatible = "allwinner,sun8i-a33-display-engine" },
+   { .compatible = "allwinner,sun8i-v3s-display-engine" },
{ }
 };
 MODULE_DEVICE_TABLE(of, sun4i_drv_of_table);
-- 
2.12.2

[PATCH v2 02/10] pinctrl: sunxi: add definitions for add A20 and R40 support to A10 driver

2017-05-04 Thread Icenowy Zheng

Allwinner A10, A20 and R40 SoCs have similar GPIO layout.

Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
into A10 driver, and add R40 support into it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h 
b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index a9d315a1256c..1bfc0d8a55df 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -87,6 +87,9 @@
 #define PINCTRL_SUN5I_GR8  BIT(3)
 #define PINCTRL_SUN6I_A31  BIT(4)
 #define PINCTRL_SUN6I_A31S BIT(5)
+#define PINCTRL_SUN4I_A10  BIT(6)
+#define PINCTRL_SUN7I_A20  BIT(7)
+#define PINCTRL_SUN8I_R40  BIT(8)
 
 struct sunxi_desc_function {
unsigned long   variant;
-- 
2.12.2

[PATCH v6 12/13] ARM: dts: sun8i: add pinmux for LCD pins of V3s SoC

2017-05-04 Thread Icenowy Zheng

Allwinner V3s SoC features a set of pins that have functionality of RGB
LCD, the pins are at different pin ban than other SoCs.

Add pinctrl node for them.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 0a895179d8ae..a37d68b227bc 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -297,6 +297,15 @@
function = "i2c0";
};
 
+   lcd_rgb666_pins: lcd_rgb666@0 {
+   pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+  "PE5", "PE6", "PE7", "PE8", "PE9",
+  "PE10", "PE11", "PE12", "PE13", "PE14",
+  "PE15", "PE16", "PE17", "PE18", "PE19",
+  "PE23", "PE24";
+   function = "lcd";
+   };
+
uart0_pins_a: uart0@0 {
pins = "PB8", "PB9";
function = "uart0";
-- 
2.12.2

[PATCH v6 11/13] ARM: dts: sun8i: add DE2 nodes for V3s SoC

2017-05-04 Thread Icenowy Zheng

Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON
which have RGB LCD output.

Add device nodes for it as well as the TCON.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-v3s.dtsi | 87 
 1 file changed, 87 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 71075969e5e6..0a895179d8ae 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -41,6 +41,10 @@
  */
 
 #include 
+#include 
+#include 
+#include 
+#include 
 
 / {
#address-cells = <1>;
@@ -59,6 +63,12 @@
};
};
 
+   de: display-engine {
+   compatible = "allwinner,sun8i-v3s-display-engine";
+   allwinner,pipelines = <_mixer0>;
+   status = "disabled";
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
@@ -93,6 +103,83 @@
#size-cells = <1>;
ranges;
 
+   de2_clocks: clock@100 {
+   compatible = "allwinner,sun50i-h5-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_DE>,
+< CLK_BUS_DE>;
+   clock-names = "mod",
+ "bus";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+   de2_mixer0: mixer@110 {
+   compatible = "allwinner,sun8i-v3s-de2-mixer";
+   reg = <0x0110 0x10>;
+   clocks = <_clocks CLK_MIXER0>,
+<_clocks CLK_BUS_MIXER0>;
+   clock-names = "mod",
+ "bus";
+   resets = <_clocks RST_MIXER0>;
+   assigned-clocks = <_clocks CLK_MIXER0>;
+   assigned-clock-rates = <15000>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mixer0_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   mixer0_out_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_in_mixer0>;
+   };
+   };
+   };
+   };
+
+   tcon0: lcd-controller@1c0c000 {
+   compatible = "allwinner,sun8i-v3s-tcon";
+   reg = <0x01c0c000 0x1000>;
+   interrupts = ;
+   clocks = < CLK_BUS_TCON0>,
+< CLK_TCON0>;
+   clock-names = "ahb",
+ "tcon-ch0";
+   clock-output-names = "tcon-pixel-clock";
+   resets = < RST_BUS_TCON0>;
+   reset-names = "lcd";
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   tcon0_in: port@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+   tcon0_in_mixer0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_out_tcon0>;
+   };
+   };
+
+   tcon0_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+   };
+   };
+   };
+
+
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
-- 
2.12.2

[PATCH v6 06/13] drm/sun4i: add a dedicated module for sun4i-backend and sun4i-layer

2017-05-04 Thread Icenowy Zheng

Currently the direct call from CRTC code to layer code has disappeared,
instead the layer's init function is called via the backend's ops.

Add a dedicated module for sun4i-backend and sun4i-layer, and drop the
EXPORT_SYMBOL from backend code to layer code.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Splited out patch.

 drivers/gpu/drm/sun4i/Makefile| 5 +++--
 drivers/gpu/drm/sun4i/sun4i_backend.c | 4 
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 59b757350a1f..a251fb36c951 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -5,9 +5,10 @@ sun4i-tcon-y += sun4i_tcon.o
 sun4i-tcon-y += sun4i_rgb.o
 sun4i-tcon-y += sun4i_dotclock.o
 sun4i-tcon-y += sun4i_crtc.o
-sun4i-tcon-y += sun4i_layer.o
+
+sun4i-backend-y += sun4i_backend.o sun4i_layer.o
 
 obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o
-obj-$(CONFIG_DRM_SUN4I)+= sun4i_backend.o
+obj-$(CONFIG_DRM_SUN4I)+= sun4i-backend.o
 obj-$(CONFIG_DRM_SUN4I)+= sun6i_drc.o
 obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c 
b/drivers/gpu/drm/sun4i/sun4i_backend.c
index 611cdcb9c182..fac1a414ba49 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -83,7 +83,6 @@ void sun4i_backend_layer_enable(struct sun4i_backend *backend,
regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
   SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
 }
-EXPORT_SYMBOL(sun4i_backend_layer_enable);
 
 static int sun4i_backend_drm_format_to_layer(struct drm_plane *plane,
 u32 format, u32 *mode)
@@ -170,7 +169,6 @@ int sun4i_backend_update_layer_coord(struct sun4i_backend 
*backend,
 
return 0;
 }
-EXPORT_SYMBOL(sun4i_backend_update_layer_coord);
 
 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
   int layer, struct drm_plane *plane)
@@ -205,7 +203,6 @@ int sun4i_backend_update_layer_formats(struct sun4i_backend 
*backend,
 
return 0;
 }
-EXPORT_SYMBOL(sun4i_backend_update_layer_formats);
 
 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
  int layer, struct drm_plane *plane)
@@ -246,7 +243,6 @@ int sun4i_backend_update_layer_buffer(struct sun4i_backend 
*backend,
 
return 0;
 }
-EXPORT_SYMBOL(sun4i_backend_update_layer_buffer);
 
 static int sun4i_backend_init_sat(struct device *dev) {
struct sun4i_backend *backend = dev_get_drvdata(dev);
-- 
2.12.2

[PATCH v2 10/10] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

2017-05-04 Thread Icenowy Zheng

From: Chen-Yu Tsai <w...@csie.org>

The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
form factor and position of various connectors, leds and buttons is
similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
as the latest Banana Pi M64.

It features:

  - X-Powers AXP221s PMIC connected to i2c0
  - 2 GB DDR3 DRAM
  - 8 GB eMMC
  - micro SD card slot
  - DC power jack
  - HDMI output
  - MIPI DSI connector
  - 2x USB 2.0 hosts
  - 1x USB 2.0 OTG
  - gigabit ethernet with Realtek RTL8211E transceiver
  - WiFi/Bluetooth with AP6212 chip, with external antenna connector
  - SATA and power connectors for native SATA support
  - camera sensor connector
  - consumer IR receiver
  - audio out headphone jack
  - onboard microphone
  - red, green, and blue LEDs
  - debug UART pins
  - Li-Po battery connector
  - Raspberry Pi B+ compatible GPIO header
  - power, reset, and boot control buttons

This patch adds a dts file that enables debug UART and MMC support.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
 arch/arm/boot/dts/Makefile|   1 +
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 161 ++
 2 files changed, 162 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c5e1d944d1c..07a662494eed 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -905,6 +905,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-r16-parrot.dtb \
+   sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v3s-licheepi-zero.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts 
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
new file mode 100644
index ..1d824830a1ad
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <w...@csie.org>
+ * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+   model = "Banana Pi BPI-M2-Ultra";
+   compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   wifi_pwrseq: wifi_pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+   };
+};
+
+ {
+   status = "okay";
+
+   axp22x: pmic@68 {
+   compatible = "x-powers,axp221";
+   reg = <0x34>;
+   interr

[PATCH v2 00/10] Initial Allwinner R40 support

2017-05-04 Thread Icenowy Zheng

This is the first non-RFC version of this patchset, which added basical
support including I2C, UART and MMC to the mainline Linux.

The pinctrl driver of A20 is also merged into the one of A10 before
R40 support is added into the A10 driver.

Chen-Yu Tsai (2):
  ARM: dts: sun8i: Add basic dtsi file for Allwinner R40
  ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

Icenowy Zheng (8):
  arm: sunxi: add support for R40 SoC
  pinctrl: sunxi: add definitions for add A20 and R40 support to A10
driver
  pinctrl: sunxi: add A20 support to A10 driver
  pinctrl: sunxi: switch A20's pinctrl driver to use the A10 version
  dt-bindings: add compatible string for Allwinner R40 pinctrl
  pinctrl: sunxi: add support of R40 to A10 pinctrl driver
  dt-bindings: add compatible string for Allwinner R40 CCU
  clk: sunxi-ng: support R40 SoC

 Documentation/arm/sunxi/README |4 +
 Documentation/devicetree/bindings/arm/sunxi.txt|1 +
 .../devicetree/bindings/clock/sunxi-ccu.txt|1 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |1 +
 arch/arm/boot/dts/Makefile |1 +
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts  |  161 +++
 arch/arm/boot/dts/sun8i-r40.dtsi   |  404 +++
 arch/arm/mach-sunxi/sunxi.c|1 +
 drivers/clk/sunxi-ng/Kconfig   |   10 +
 drivers/clk/sunxi-ng/Makefile  |1 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c   | 1153 
 drivers/clk/sunxi-ng/ccu-sun8i-r40.h   |   68 ++
 drivers/pinctrl/sunxi/Kconfig  |6 +-
 drivers/pinctrl/sunxi/Makefile |1 -
 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c  |  449 ++--
 drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c  | 1056 --
 drivers/pinctrl/sunxi/pinctrl-sunxi.h  |3 +
 include/dt-bindings/clock/sun8i-r40-ccu.h  |  191 
 include/dt-bindings/reset/sun8i-r40-ccu.h  |  129 +++
 19 files changed, 2495 insertions(+), 1146 deletions(-)
 create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
 create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
 delete mode 100644 drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
 create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h

-- 
2.12.2

Re: [PATCH v6 08/13] drm/sun4i: add support for Allwinner DE2 mixers

2017-05-05 Thread Icenowy Zheng



于 2017年5月5日 GMT+08:00 下午8:36:18, Maxime Ripard 
 写到:
>On Fri, May 05, 2017 at 12:50:51AM +0800, icen...@aosc.io wrote:
>> > > +void sun8i_mixer_layer_enable(struct sun8i_mixer *mixer,
>> > > +int layer, bool enable)
>> > > +{
>> > > +u32 val;
>> > > +/* Currently the first UI channel is used */
>> > > +int chan = mixer->cfg->vi_num;
>> > > +
>> > > +DRM_DEBUG_DRIVER("Enabling layer %d in channel %d\n", layer,
>chan);
>> > > +
>> > > +if (enable)
>> > > +val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
>> > > +else
>> > > +val = 0;
>> > > +
>> > > +regmap_update_bits(mixer->engine.regs,
>> > > +   SUN8I_MIXER_CHAN_UI_LAYER_ATTR(chan, layer),
>> > > +   SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
>> > > +
>> > > +/* Set the alpha configuration */
>> > > +regmap_update_bits(mixer->engine.regs,
>> > > +   SUN8I_MIXER_CHAN_UI_LAYER_ATTR(chan, layer),
>> > > +   
>> > > SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK,
>> > > +   
>> > > SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_DEF);
>> > > +regmap_update_bits(mixer->engine.regs,
>> > > +   SUN8I_MIXER_CHAN_UI_LAYER_ATTR(chan, layer),
>> > > +   SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK,
>> > > +   SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_DEF);
>> > > +}
>> > 
>> > This one too.
>> 
>> It's called from sun8i_layer.c, so it cannot be static.
>
>Fair enough.
>
>> > > +/* Set base coordinates */
>> > > +DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
>> > > + state->crtc_x, state->crtc_y);
>> > > +regmap_write(mixer->engine.regs,
>> > > + SUN8I_MIXER_CHAN_UI_LAYER_COORD(chan, layer),
>> > > + SUN8I_MIXER_COORD(state->crtc_x, state->crtc_y));
>> > 
>> > X and Y are fixed point numbers. You want to keep only the higher
>16
>> > bits there.
>> 
>> Do you mean "lower 16 bits"? Thus should I (x & 0x) or ((u16)x) ?
>
>Nevermind, I got confused with src_x and src_y.
>
>> P.S. The negative coordinates are broken, how should I deal with it?
>or
>> is the coordinates promised to be not negative?
>
>Adjust the buffer base address, and use a shorter line. You have such
>an example in the sun4i code.

Are they these two lines:
```
paddr += (state->src_x >> 16) * bpp;
paddr += (state->src_y >> 16) * fb->pitches[0];
```

I think I copied them here, so I don't need to mind this problem any more, 
right?

>
>Maxime

Re: [linux-sunxi] [PATCH v6 11/13] ARM: dts: sun8i: add DE2 nodes for V3s SoC

2017-05-05 Thread Icenowy Zheng



于 2017年5月5日 GMT+08:00 下午8:30:35, Maxime Ripard 
 写到:
>On Fri, May 05, 2017 at 04:53:43PM +0800, icen...@aosc.io wrote:
>> > > +   de2_clocks: clock@100 {
>> > > +   compatible =
>"allwinner,sun50i-h5-de2-clk";
>> > 
>> > I am a bit skeptical about this. Since the V3S only has one mixer,
>do
>> > the clocks
>> > for the second one even exist?
>> 
>> It's described in the de_clock.c in the BSP source code, and in
>hardware
>> these bits can be really set (although without clock output).
>> 
>> So I use this compatible which has still the extra clocks.
>
>If it's not usable, then it shouldn't be in the code, it's basically
>dead code.

Thus should we have one more DE2 CCU compatible without mixer1
clocks for V3s?

[PATCH v2 01/10] arm: sunxi: add support for R40 SoC

2017-05-04 Thread Icenowy Zheng

From: Icenowy Zheng <icen...@aosc.xyz>

Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.

Add support for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
 Documentation/arm/sunxi/README  | 4 
 Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
 arch/arm/mach-sunxi/sunxi.c | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index d7b1f016bd62..25c814adcd47 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -75,6 +75,10 @@ SunXi family
 + Datasheet
   http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
 
+  - Allwinner R40 (sun8i)
++ Datasheet Draft
+  http://linux-sunxi.org/File:Allwinner_R40_Datasheet_V0.1.pdf
+
 * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
   - Allwinner A80
 + Datasheet
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt 
b/Documentation/devicetree/bindings/arm/sunxi.txt
index d2c46449b4eb..b3ffe6cf821a 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
   allwinner,sun8i-a83t
   allwinner,sun8i-h2-plus
   allwinner,sun8i-h3
+  allwinner-sun8i-r40
   allwinner,sun9i-a80
   allwinner,sun50i-a64
   nextthing,gr8
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index f44e3acb5c90..aea616759451 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -66,6 +66,7 @@ static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-v3s",
+   "allwinner,sun8i-r40",
NULL,
 };
 
-- 
2.12.2

[PATCH v2 08/10] clk: sunxi-ng: support R40 SoC

2017-05-04 Thread Icenowy Zheng

From: Icenowy Zheng <icen...@aosc.xyz>

Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.

Add support for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Fixes according to the SoC's user manual.

 drivers/clk/sunxi-ng/Kconfig  |   10 +
 drivers/clk/sunxi-ng/Makefile |1 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c  | 1153 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.h  |   68 ++
 include/dt-bindings/clock/sun8i-r40-ccu.h |  191 +
 include/dt-bindings/reset/sun8i-r40-ccu.h |  129 
 6 files changed, 1552 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
 create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 64088e599404..e6884eafde44 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -140,6 +140,16 @@ config SUN8I_V3S_CCU
default MACH_SUN8I
depends on MACH_SUN8I || COMPILE_TEST
 
+config SUN8I_R40_CCU
+   bool "Support for the Allwinner R40 CCU"
+   select SUNXI_CCU_DIV
+   select SUNXI_CCU_NK
+   select SUNXI_CCU_NKM
+   select SUNXI_CCU_NKMP
+   select SUNXI_CCU_NM
+   select SUNXI_CCU_MP
+   default MACH_SUN8I
+
 config SUN9I_A80_CCU
bool "Support for the Allwinner A80 CCU"
select SUNXI_CCU_DIV
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 0ec02fe14c50..aa00b641484e 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_SUN8I_A33_CCU)   += ccu-sun8i-a33.o
 obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
 obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o
 obj-$(CONFIG_SUN8I_R_CCU)  += ccu-sun8i-r.o
+obj-$(CONFIG_SUN8I_R40_CCU)+= ccu-sun8i-r40.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-de.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-usb.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
new file mode 100644
index ..0cc1b1ab7c3f
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -0,0 +1,1153 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icen...@aosc.xyz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun8i-r40.h"
+
+static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
+"osc24M", 0x000,
+8, 5,  /* N */
+4, 2,  /* K */
+0, 2,  /* M */
+16, 2, /* P */
+BIT(31),   /* gate */
+BIT(28),   /* lock */
+0);
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names
+ */
+#define SUN8I_R40_PLL_AUDIO_REG0x008
+
+static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+  "osc24M", 0x008,
+  8, 7,/* N */
+  0, 5,/* M */
+  BIT(31), /* gate */
+  BIT(28), /* lock */
+  0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
+   "osc24M", 0x0010,
+   8, 7,   /* N */
+   0, 4,   /* M */

Re: [PATCH v2 02/10] pinctrl: sunxi: add definitions for add A20 and R40 support to A10 driver

2017-05-04 Thread Icenowy Zheng



于 2017年5月4日 GMT+08:00 下午10:04:31, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Thu, May 04, 2017 at 09:49:58PM +0800, Icenowy Zheng wrote:
>> Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
>> 
>> Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
>> into A10 driver, and add R40 support into it.
>
>While your commit log is good, the commit title is misleading since
>you're not adding it to the A10 driver. You just adding SoC IDs
>definitions

Is "pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs" OK?

>
>Maxime

[PATCH v2 07/10] dt-bindings: add compatible string for Allwinner R40 CCU

2017-05-04 Thread Icenowy Zheng

Allwinner R40 has a clock controlling unit like the ones on other
Allwinner SoCs after sun6i, and can also use a CCU-based driver.

Add a compatible string for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt 
b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index e9c5a1d9834a..b2ae26428423 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -8,6 +8,7 @@ Required properties :
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-h3-ccu"
- "allwinner,sun8i-h3-r-ccu"
+   - "allwinner,sun8i-r40-ccu"
- "allwinner,sun8i-v3s-ccu"
- "allwinner,sun9i-a80-ccu"
- "allwinner,sun50i-a64-ccu"
-- 
2.12.2

Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver

2017-05-04 Thread Icenowy Zheng



于 2017年5月4日 GMT+08:00 下午10:41:52, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
>> 
>> 
>> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
><maxime.rip...@free-electrons.com> 写到:
>> >On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
>> >>  static const struct of_device_id sun4i_a10_pinctrl_match[] = {
>> >> - { .compatible = "allwinner,sun4i-a10-pinctrl", },
>> >> + {
>> >> + .compatible = "allwinner,sun4i-a10-pinctrl",
>> >> + .data = (void *)PINCTRL_SUN4I_A10
>> >> + },
>> >> + {
>> >> + .compatible = "allwinner,sun7i-a20-pinctrl",
>> >> + .data = (void *)PINCTRL_SUN7I_A20
>> >> + },
>> >>   {}
>> >>  };
>> >
>> >This means you're going to have two drivers probing for the same
>> >device: this driver, and the old one. This is not ok, and probably
>> >introduces some corner cases.
>> 
>> The A20 driver is dropped in the next commit.
>
>Yes, and that is an issue for bisectability. Anyone that will checkout
>between those two commits will have a broken kernel, and that is not
>ok. Any commit should be in a working state.

Squash them together?

>
>Maxime

[PATCH v2 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-05-04 Thread Icenowy Zheng

From: Chen-Yu Tsai <w...@csie.org>

The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
 arch/arm/boot/dts/sun8i-r40.dtsi | 404 +++
 1 file changed, 404 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
new file mode 100644
index ..20d4705a8206
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,404 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai <w...@csie.org>
+ * Copyright 2017 Icenowy Zheng <icen...@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+
+   aliases {
+   };
+
+   chosen {
+   };
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   osc24M: osc24M {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   };
+
+   osc32k: osc32k {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "osc32k";
+   };
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <1>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <2>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <3>;
+   };
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x4000 0x8000>;
+   };
+
+

Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver

2017-05-04 Thread Icenowy Zheng



于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
>>  static const struct of_device_id sun4i_a10_pinctrl_match[] = {
>> -{ .compatible = "allwinner,sun4i-a10-pinctrl", },
>> +{
>> +.compatible = "allwinner,sun4i-a10-pinctrl",
>> +.data = (void *)PINCTRL_SUN4I_A10
>> +},
>> +{
>> +.compatible = "allwinner,sun7i-a20-pinctrl",
>> +.data = (void *)PINCTRL_SUN7I_A20
>> +},
>>  {}
>>  };
>
>This means you're going to have two drivers probing for the same
>device: this driver, and the old one. This is not ok, and probably
>introduces some corner cases.

The A20 driver is dropped in the next commit.

>
>Maxime

[PATCH v2 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

2017-05-04 Thread Icenowy Zheng

R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).

Add support for R40 to the A10 pinctrl driver.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/pinctrl/sunxi/Kconfig |   2 +-
 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 272 +-
 2 files changed, 197 insertions(+), 77 deletions(-)

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 624d84e6c936..9d01da3b90bd 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -7,7 +7,7 @@ config PINCTRL_SUNXI
select GPIOLIB
 
 config PINCTRL_SUN4I_A10
-   def_bool MACH_SUN4I || MACH_SUN7I
+   def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
select PINCTRL_SUNXI
 
 config PINCTRL_SUN5I
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c 
b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 159580c04b14..0f6ca8391ea7 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -26,7 +26,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
  SUNXI_FUNCTION(0x3, "spi1"),  /* CS0 */
  SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GRXD3 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -34,7 +35,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
  SUNXI_FUNCTION(0x3, "spi1"),  /* CLK */
  SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GRXD2 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -42,7 +44,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
  SUNXI_FUNCTION(0x3, "spi1"),  /* MOSI */
  SUNXI_FUNCTION(0x4, "uart2"), /* TX */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GRXD1 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -50,65 +53,75 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
  SUNXI_FUNCTION(0x3, "spi1"),  /* MISO */
  SUNXI_FUNCTION(0x4, "uart2"), /* RX */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GRXD0 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ETXD3 */
  SUNXI_FUNCTION(0x3, "spi1"),  /* CS1 */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GTXD3 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ETXD2 */
  SUNXI_FUNCTION(0x3, "spi3"),  /* CS0 */
  SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GTXD2 */
-PINCTRL_SUN7I_A20)),
+PINCTRL_SUN7I_A20 |
+PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ETXD1 */
  SUNXI_FUNCTION(0x3, "

[PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver

2017-05-04 Thread Icenowy Zheng

As A20 is designed as a pin-compatible upgrade of A10, their pin
controller are very similar, and can share one driver.

Add A20 support to the A10 driver.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 287 +++---
 1 file changed, 224 insertions(+), 63 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c 
b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index fb30b86a97ee..159580c04b14 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -24,101 +24,147 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ERXD3 */
  SUNXI_FUNCTION(0x3, "spi1"),  /* CS0 */
- SUNXI_FUNCTION(0x4, "uart2")),/* RTS */
+ SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GRXD3 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ERXD2 */
  SUNXI_FUNCTION(0x3, "spi1"),  /* CLK */
- SUNXI_FUNCTION(0x4, "uart2")),/* CTS */
+ SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GRXD2 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ERXD1 */
  SUNXI_FUNCTION(0x3, "spi1"),  /* MOSI */
- SUNXI_FUNCTION(0x4, "uart2")),/* TX */
+ SUNXI_FUNCTION(0x4, "uart2"), /* TX */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GRXD1 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ERXD0 */
  SUNXI_FUNCTION(0x3, "spi1"),  /* MISO */
- SUNXI_FUNCTION(0x4, "uart2")),/* RX */
+ SUNXI_FUNCTION(0x4, "uart2"), /* RX */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GRXD0 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ETXD3 */
- SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
+ SUNXI_FUNCTION(0x3, "spi1"),  /* CS1 */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GTXD3 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ETXD2 */
- SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
+ SUNXI_FUNCTION(0x3, "spi3"),  /* CS0 */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GTXD2 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ETXD1 */
- SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
+ SUNXI_FUNCTION(0x3, "spi3"),  /* CLK */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac",   /* GTXD1 */
+PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
  SUNXI_FUNCTION(0x0, "gpio_in"),
  SUNXI_FUNCTION(0x1, "gpio_out"),
  SUNXI_FUNCTION(0x2, "emac"),  /* ETXD0 */
- SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
+ SUNXI_FUNCTION(0x3, "

[PATCH v2 04/10] pinctrl: sunxi: switch A20's pinctrl driver to use the A10 version

2017-05-04 Thread Icenowy Zheng

As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, and enable A10 driver for A20.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/pinctrl/sunxi/Kconfig |6 +-
 drivers/pinctrl/sunxi/Makefile|1 -
 drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 1056 -
 3 files changed, 1 insertion(+), 1062 deletions(-)
 delete mode 100644 drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 793e6f94fa0b..624d84e6c936 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -7,7 +7,7 @@ config PINCTRL_SUNXI
select GPIOLIB
 
 config PINCTRL_SUN4I_A10
-   def_bool MACH_SUN4I
+   def_bool MACH_SUN4I || MACH_SUN7I
select PINCTRL_SUNXI
 
 config PINCTRL_SUN5I
@@ -23,10 +23,6 @@ config PINCTRL_SUN6I_A31_R
depends on RESET_CONTROLLER
select PINCTRL_SUNXI
 
-config PINCTRL_SUN7I_A20
-   def_bool MACH_SUN7I
-   select PINCTRL_SUNXI
-
 config PINCTRL_SUN8I_A23
def_bool MACH_SUN8I
select PINCTRL_SUNXI
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index df4ccd6cd44c..efe1e64ef4f1 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -6,7 +6,6 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
 obj-$(CONFIG_PINCTRL_SUN5I)+= pinctrl-sun5i.o
 obj-$(CONFIG_PINCTRL_SUN6I_A31)+= pinctrl-sun6i-a31.o
 obj-$(CONFIG_PINCTRL_SUN6I_A31_R)  += pinctrl-sun6i-a31-r.o
-obj-$(CONFIG_PINCTRL_SUN7I_A20)+= pinctrl-sun7i-a20.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23)+= pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)  += pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c 
b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
deleted file mode 100644
index b6f4c68ffb39..
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ /dev/null
@@ -1,1056 +0,0 @@
-/*
- * Allwinner A20 SoCs pinctrl driver.
- *
- * Copyright (C) 2014 Maxime Ripard
- *
- * Maxime Ripard <maxime.rip...@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "pinctrl-sunxi.h"
-
-static const struct sunxi_desc_pin sun7i_a20_pins[] = {
-   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"),  /* ERXD3 */
- SUNXI_FUNCTION(0x3, "spi1"),  /* CS0 */
- SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
- SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */
-   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"),  /* ERXD2 */
- SUNXI_FUNCTION(0x3, "spi1"),  /* CLK */
- SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
- SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */
-   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"),  /* ERXD1 */
- SUNXI_FUNCTION(0x3, "spi1"),  /* MOSI */
- SUNXI_FUNCTION(0x4, "uart2"), /* TX */
- SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */
-   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"),  /* ERXD0 */
- SUNXI_FUNCTION(0x3, "spi1"),  /* MISO */
- SUNXI_FUNCTION(0x4, "uart2"), /* RX */
- SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */
-   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "emac"),  /* ETXD3 */
- SUNXI_FUNCTION(0x3, "spi1"),  /* CS1 */
- SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */
-   SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5)

[PATCH v2 05/10] dt-bindings: add compatible string for Allwinner R40 pinctrl

2017-05-04 Thread Icenowy Zheng

Allwinner R40 has a pin controller like the ones in older Allwinner SoCs
(especially A20), and can use modified version of the A10/A20 pinctrl
driver.

Add a compatible string for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index b53224473672..3ab9f7849a19 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -22,6 +22,7 @@ Required properties:
   "allwinner,sun8i-a83t-pinctrl"
   "allwinner,sun8i-h3-pinctrl"
   "allwinner,sun8i-h3-r-pinctrl"
+  "allwinner,sun8i-r40-pinctrl"
   "allwinner,sun50i-a64-pinctrl"
   "allwinner,sun50i-a64-r-pinctrl"
   "allwinner,sun50i-h5-pinctrl"
-- 
2.12.2

[PATCH 02/13] clk: sunxi-ng: add support for DE2 CCU

2017-05-04 Thread Icenowy Zheng

The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.

Add a sunxi-ng style driver for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/clk/sunxi-ng/Kconfig |   5 +
 drivers/clk/sunxi-ng/Makefile|   1 +
 drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 218 +++
 drivers/clk/sunxi-ng/ccu-sun8i-de2.h |  28 +
 4 files changed, 252 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-de2.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-de2.h

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 64088e599404..2e4d804fbf61 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -140,6 +140,11 @@ config SUN8I_V3S_CCU
default MACH_SUN8I
depends on MACH_SUN8I || COMPILE_TEST
 
+config SUN8I_DE2_CCU
+   bool "Support for the Allwinner SoCs DE2 CCU"
+   select SUNXI_CCU_DIV
+   select SUNXI_CCU_GATE
+
 config SUN9I_A80_CCU
bool "Support for the Allwinner A80 CCU"
select SUNXI_CCU_DIV
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 0ec02fe14c50..be616279450e 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_SUN8I_A23_CCU)   += ccu-sun8i-a23.o
 obj-$(CONFIG_SUN8I_A33_CCU)+= ccu-sun8i-a33.o
 obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
 obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o
+obj-$(CONFIG_SUN8I_DE2_CCU)+= ccu-sun8i-de2.o
 obj-$(CONFIG_SUN8I_R_CCU)  += ccu-sun8i-r.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80.o
 obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-de.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
new file mode 100644
index ..adb2c344692a
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icen...@aosc.io>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "ccu_common.h"
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_reset.h"
+
+#include "ccu-sun8i-de2.h"
+
+static SUNXI_CCU_GATE(bus_mixer0_clk,  "bus-mixer0",   "bus-de",
+ 0x04, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_mixer1_clk,  "bus-mixer1",   "bus-de",
+ 0x04, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_wb_clk,  "bus-wb",   "bus-de",
+ 0x04, BIT(2), 0);
+
+static SUNXI_CCU_GATE(mixer0_clk,  "mixer0",   "mixer0-div",
+ 0x00, BIT(0), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_GATE(mixer1_clk,  "mixer1",   "mixer1-div",
+ 0x00, BIT(1), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_GATE(wb_clk,  "wb",   "wb-div",
+ 0x00, BIT(2), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
+  CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
+  CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
+  CLK_SET_RATE_PARENT);
+
+static struct ccu_common *sunxi_de2_clks[] = {
+   _clk.common,
+   _clk.common,
+   _clk.common,
+
+   _mixer0_clk.common,
+   _mixer1_clk.common,
+   _wb_clk.common,
+
+   _div_clk.common,
+   _div_clk.common,
+   _div_clk.common,
+};
+
+static struct clk_hw_onecell_data sunxi_de2_hw_clks = {
+   .hws= {
+   [CLK_MIXER0]= _clk.common.hw,
+   [CLK_MIXER1]= _clk.common.hw,
+   [CLK_WB]= _clk.common.hw,
+
+   [CLK_BUS_MIXER0]= _mixer0_clk.common.hw,
+   [CLK_BUS_MIXER1]= _mixer1_clk.common.hw,
+   [CLK_BUS_WB]= _wb_clk.common.hw,
+
+   [CLK_MIXER0_DIV]= _div_clk.common.hw,
+   [CLK_MIXER1_DIV]= _div_clk.common.hw,
+   [CLK_WB_DIV]= _div_clk.common.hw,
+   },
+   .num= CLK_NUMBER,
+};
+
+static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
+   [

[PATCH 04/13] drm/sun4i: return only planes for layers created

2017-05-04 Thread Icenowy Zheng

As we are going to add support for the Allwinner DE2 Mixer in sun4i-drm
driver, we will finally have two types of layers.

Each layer is bound to a drm_plane that is CRTC-specific, so we create
them when initializing CRTC (calling sun4i_layers_init, which will be
generalized in next patch). The drm_plane's will be used when creating
CRTC, but the CRTC initialization code do not care other properties of
the layer, so we let the sun4i_layers_init function return drm_plane's
only.

As we have no need to trace the layers after the CRTC is properly
created, we drop the layers pointer in sun4i_crtc struct.

Doing these things makes the CRTC code independent to the type of layer
(the sun4i_layers_init function name is still hardcoded and will be
changed in the next patch), so that we can finally gain support for the
mixer in DE2, which will has different layers.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_crtc.c  | 23 ---
 drivers/gpu/drm/sun4i/sun4i_crtc.h  |  1 -
 drivers/gpu/drm/sun4i/sun4i_layer.c | 18 ++
 drivers/gpu/drm/sun4i/sun4i_layer.h |  4 ++--
 4 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c 
b/drivers/gpu/drm/sun4i/sun4i_crtc.c
index 3c876c3a356a..708b3543d4e9 100644
--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
@@ -139,6 +139,7 @@ struct sun4i_crtc *sun4i_crtc_init(struct drm_device *drm,
   struct sun4i_tcon *tcon)
 {
struct sun4i_crtc *scrtc;
+   struct drm_plane **planes;
struct drm_plane *primary = NULL, *cursor = NULL;
int ret, i;
 
@@ -149,22 +150,22 @@ struct sun4i_crtc *sun4i_crtc_init(struct drm_device *drm,
scrtc->tcon = tcon;
 
/* Create our layers */
-   scrtc->layers = sun4i_layers_init(drm, scrtc->backend);
-   if (IS_ERR(scrtc->layers)) {
+   planes = sun4i_layers_init(drm, scrtc);
+   if (IS_ERR(planes)) {
dev_err(drm->dev, "Couldn't create the planes\n");
return NULL;
}
 
/* find primary and cursor planes for drm_crtc_init_with_planes */
-   for (i = 0; scrtc->layers[i]; i++) {
-   struct sun4i_layer *layer = scrtc->layers[i];
+   for (i = 0; planes[i]; i++) {
+   struct drm_plane *plane = planes[i];
 
-   switch (layer->plane.type) {
+   switch (plane->type) {
case DRM_PLANE_TYPE_PRIMARY:
-   primary = >plane;
+   primary = plane;
break;
case DRM_PLANE_TYPE_CURSOR:
-   cursor = >plane;
+   cursor = plane;
break;
default:
break;
@@ -188,12 +189,12 @@ struct sun4i_crtc *sun4i_crtc_init(struct drm_device *drm,
   1);
 
/* Set possible_crtcs to this crtc for overlay planes */
-   for (i = 0; scrtc->layers[i]; i++) {
+   for (i = 0; planes[i]; i++) {
uint32_t possible_crtcs = BIT(drm_crtc_index(>crtc));
-   struct sun4i_layer *layer = scrtc->layers[i];
+   struct drm_plane *plane = planes[i];
 
-   if (layer->plane.type == DRM_PLANE_TYPE_OVERLAY)
-   layer->plane.possible_crtcs = possible_crtcs;
+   if (plane->type == DRM_PLANE_TYPE_OVERLAY)
+   plane->possible_crtcs = possible_crtcs;
}
 
return scrtc;
diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.h 
b/drivers/gpu/drm/sun4i/sun4i_crtc.h
index 230cb8f0d601..4dae3508424a 100644
--- a/drivers/gpu/drm/sun4i/sun4i_crtc.h
+++ b/drivers/gpu/drm/sun4i/sun4i_crtc.h
@@ -19,7 +19,6 @@ struct sun4i_crtc {
 
struct sun4i_backend*backend;
struct sun4i_tcon   *tcon;
-   struct sun4i_layer  **layers;
 };
 
 static inline struct sun4i_crtc *drm_crtc_to_sun4i_crtc(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c 
b/drivers/gpu/drm/sun4i/sun4i_layer.c
index f26bde5b9117..e1f03e1cc0ac 100644
--- a/drivers/gpu/drm/sun4i/sun4i_layer.c
+++ b/drivers/gpu/drm/sun4i/sun4i_layer.c
@@ -16,6 +16,7 @@
 #include 
 
 #include "sun4i_backend.h"
+#include "sun4i_crtc.h"
 #include "sun4i_layer.h"
 
 struct sun4i_plane_desc {
@@ -128,15 +129,16 @@ static struct sun4i_layer *sun4i_layer_init_one(struct 
drm_device *drm,
return layer;
 }
 
-struct sun4i_layer **sun4i_layers_init(struct drm_device *drm,
-  struct sun4i_backend *backend)
+struct drm_plane **sun4i_layers_init(struct drm_device *drm,
+struct sun4i_crtc *crtc)
 {
-   struct sun4i_layer **layers;
+   struct drm_pl

[PATCH 03/13] dt-bindings: add bindings for DE2 on V3s SoC

2017-05-04 Thread Icenowy Zheng

Allwinner V3s SoC have a display engine which have a different pipeline
with older SoCs.

Add document for it (new compatibles and the new "mixer" part).

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../bindings/display/sunxi/sun4i-drm.txt   | 29 --
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 7acdbf14ae1c..33452884b96e 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -41,6 +41,7 @@ Required properties:
* allwinner,sun6i-a31-tcon
* allwinner,sun6i-a31s-tcon
* allwinner,sun8i-a33-tcon
+   * allwinner,sun8i-v3s-tcon
  - reg: base address and size of memory-mapped region
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the TCON. Three are needed:
@@ -62,7 +63,7 @@ Required properties:
   second the block connected to the TCON channel 1 (usually the TV
   encoder)
 
-On SoCs other than the A33, there is one more clock required:
+On SoCs other than the A33 and V3s, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
 
 DRC
@@ -148,6 +149,26 @@ Required properties:
   Documentation/devicetree/bindings/media/video-interfaces.txt. The
   first port should be the input endpoints, the second one the outputs
 
+Display Engine 2.0 Mixer
+
+
+The DE2 mixer have many functionalities, currently only layer blending is
+supported.
+
+Required properties:
+  - compatible: value must be one of:
+* allwinner,sun8i-v3s-de2-mixer
+  - reg: base address and size of the memory-mapped region.
+  - clocks: phandles to the clocks feeding the frontend and backend
+* bus: the backend interface clock
+* ram: the backend DRAM clock
+  - clock-names: the clock names mentioned above
+  - resets: phandles to the reset controllers driving the backend
+
+- ports: A ports node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt. The
+  first port should be the input endpoints, the second one the output
+
 
 Display Engine Pipeline
 ---
@@ -162,9 +183,13 @@ Required properties:
 * allwinner,sun6i-a31-display-engine
 * allwinner,sun6i-a31s-display-engine
 * allwinner,sun8i-a33-display-engine
+* allwinner,sun8i-v3s-display-engine
 
   - allwinner,pipelines: list of phandle to the display engine
-frontends available.
+pipeline entry point. For SoCs with original DE (currently
+all SoCs supported by display engine except V3s), this
+phandle should be a display frontend; for SoCs with DE2,
+this phandle should be a mixer.
 
 Example:
 
-- 
2.12.2

[PATCH 01/13] dt-bindings: add binding for the Allwinner DE2 CCU

2017-05-04 Thread Icenowy Zheng

Allwinner "Display Engine 2.0" contains some clock controls in it.

In order to add them as clock drivers, we need a device tree binding.
Add the binding here.

Also add the device tree binding headers.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/clock/sun8i-de2.txt| 30 ++
 include/dt-bindings/clock/sun8i-de2.h  | 18 +
 include/dt-bindings/reset/sun8i-de2.h  | 14 ++
 3 files changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sun8i-de2.txt
 create mode 100644 include/dt-bindings/clock/sun8i-de2.h
 create mode 100644 include/dt-bindings/reset/sun8i-de2.h

diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt 
b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
new file mode 100644
index ..d710c0111cd3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -0,0 +1,30 @@
+Allwinner Display Engine 2.0 Clock Control Binding
+--
+
+Required properties :
+- compatible: must contain one of the following compatibles:
+   - "allwinner,sun8i-a83t-de2-clk"
+   - "allwinner,sun50i-h5-de2-clk"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the clocks feeding the display engine subsystem.
+ Three are needed:
+  - "mod": the display engine module clock
+  - "bus": the bus clock for the whole display engine subsystem
+- clock-names: Must contain the clock names described just above
+- resets: phandle to the reset control for the display engine subsystem.
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+de2_clocks: clock@100 {
+   compatible = "allwinner,sun8i-a83t-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_DE>,
+< CLK_BUS_DE>;
+   clock-names = "mod",
+ "bus";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+};
diff --git a/include/dt-bindings/clock/sun8i-de2.h 
b/include/dt-bindings/clock/sun8i-de2.h
new file mode 100644
index 00000000..3bed63b524aa
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-de2.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icen...@aosc.io>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
+
+#define CLK_BUS_MIXER0 0
+#define CLK_BUS_MIXER1 1
+#define CLK_BUS_WB 2
+
+#define CLK_MIXER0 6
+#define CLK_MIXER1 7
+#define CLK_WB 8
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
diff --git a/include/dt-bindings/reset/sun8i-de2.h 
b/include/dt-bindings/reset/sun8i-de2.h
new file mode 100644
index 0000..9526017432f0
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-de2.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icen...@aosc.io>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_
+#define _DT_BINDINGS_RESET_SUN8I_DE2_H_
+
+#define RST_MIXER0 0
+#define RST_MIXER1 1
+#define RST_WB 2
+
+#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */
-- 
2.12.2

[PATCH v6 05/13] drm/sun4i: abstract a engine type

2017-05-04 Thread Icenowy Zheng

As we are going to add support for the Allwinner DE2 engine in sun4i-drm
driver, we will finally have two types of display engines -- the DE1
backend and the DE2 mixer. They both do some display blending and feed
graphics data to TCON, so I choose to call them both "engine" here.

Abstract the engine type to a new struct with an ops struct, which contains
functions that should be called outside the engine-specified code (in
TCON, CRTC or TV Encoder code).

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v6:
- Rebased on wens's multi-pipeline patchset.
- Split out Makefile changes.
Changes in v5:
- Really made a sunxi_engine struct type, and moved ops pointer
  into it.
- Added checked ops wrappers.
- Changed the second parameter of layers_init from crtc to engine.
Changes in v4:
- Comments to tag the color correction functions as optional.
- Check before calling the optional functions.
- Change layers_init to satisfy new PATCH v4 04/11.

 drivers/gpu/drm/sun4i/sun4i_backend.c |  68 -
 drivers/gpu/drm/sun4i/sun4i_backend.h |  17 +++---
 drivers/gpu/drm/sun4i/sun4i_crtc.c|  11 ++--
 drivers/gpu/drm/sun4i/sun4i_crtc.h|   4 +-
 drivers/gpu/drm/sun4i/sun4i_drv.c |   2 +-
 drivers/gpu/drm/sun4i/sun4i_drv.h |   2 +-
 drivers/gpu/drm/sun4i/sun4i_layer.c   |   8 +--
 drivers/gpu/drm/sun4i/sun4i_layer.h   |   5 +-
 drivers/gpu/drm/sun4i/sun4i_tcon.c|  36 ++-
 drivers/gpu/drm/sun4i/sun4i_tv.c  |   9 ++-
 drivers/gpu/drm/sun4i/sunxi_engine.h  | 112 ++
 11 files changed, 198 insertions(+), 76 deletions(-)
 create mode 100644 drivers/gpu/drm/sun4i/sunxi_engine.h

diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c 
b/drivers/gpu/drm/sun4i/sun4i_backend.c
index e53107418add..611cdcb9c182 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -25,6 +25,8 @@
 
 #include "sun4i_backend.h"
 #include "sun4i_drv.h"
+#include "sun4i_layer.h"
+#include "sunxi_engine.h"
 
 static const u32 sunxi_rgb2yuv_coef[12] = {
0x0107, 0x0204, 0x0064, 0x0108,
@@ -32,41 +34,38 @@ static const u32 sunxi_rgb2yuv_coef[12] = {
0x01c1, 0x3e88, 0x3fb8, 0x0808
 };
 
-void sun4i_backend_apply_color_correction(struct sun4i_backend *backend)
+static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
 {
int i;
 
DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
 
/* Set color correction */
-   regmap_write(backend->regs, SUN4I_BACKEND_OCCTL_REG,
+   regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
 SUN4I_BACKEND_OCCTL_ENABLE);
 
for (i = 0; i < 12; i++)
-   regmap_write(backend->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
+   regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
 sunxi_rgb2yuv_coef[i]);
 }
-EXPORT_SYMBOL(sun4i_backend_apply_color_correction);
 
-void sun4i_backend_disable_color_correction(struct sun4i_backend *backend)
+static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
 {
DRM_DEBUG_DRIVER("Disabling color correction\n");
 
/* Disable color correction */
-   regmap_update_bits(backend->regs, SUN4I_BACKEND_OCCTL_REG,
+   regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
   SUN4I_BACKEND_OCCTL_ENABLE, 0);
 }
-EXPORT_SYMBOL(sun4i_backend_disable_color_correction);
 
-void sun4i_backend_commit(struct sun4i_backend *backend)
+static void sun4i_backend_commit(struct sunxi_engine *engine)
 {
DRM_DEBUG_DRIVER("Committing changes\n");
 
-   regmap_write(backend->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
+   regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
 SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
 SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
 }
-EXPORT_SYMBOL(sun4i_backend_commit);
 
 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
int layer, bool enable)
@@ -81,7 +80,7 @@ void sun4i_backend_layer_enable(struct sun4i_backend *backend,
else
val = 0;
 
-   regmap_update_bits(backend->regs, SUN4I_BACKEND_MODCTL_REG,
+   regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
   SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
 }
 EXPORT_SYMBOL(sun4i_backend_layer_enable);
@@ -144,27 +143,28 @@ int sun4i_backend_update_layer_coord(struct sun4i_backend 
*backend,
if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: 
%u\n",
 state->crtc_w, state->crtc_h);
-   regmap_write(backend->regs, SUN4I_BACKEND_DISSIZE_REG,
+

[PATCH v6 13/13] [DO NOT MERGE] ARM: dts: sun8i: enable LCD panel of Lichee Pi Zero

2017-05-04 Thread Icenowy Zheng

A 480x272 QiaoDian QD43003C0-40-7LED panel is available from Lichee Pi.

This commit connects this panel to Lichee Pi Zero.

Lichee Pi also provides a 800x480 panel without accurate model number,
so do not merge this patch. It will finally come as device tree overlay.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 36 +++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts 
b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index 387fc2aa546d..7ae72bf63cd0 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -75,6 +75,28 @@
gpios = < 6 2 GPIO_ACTIVE_LOW>; /* PG2 */
};
};
+
+   panel: panel {
+   compatible = "qiaodian,qd43003c0-40", "simple-panel";
+   enable-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* Should be 
backlight */
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   panel_input: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_out_lcd>;
+   };
+   };
+   };
+};
+
+ {
+   status = "okay";
 };
 
  {
@@ -86,6 +108,20 @@
status = "okay";
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_rgb666_pins>;
+   status = "okay";
+
+};
+
+_out {
+   tcon0_out_lcd: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_input>;
+   };
+};
+
  {
pinctrl-0 = <_pins_a>;
pinctrl-names = "default";
-- 
2.12.2

[PATCH v6 08/13] drm/sun4i: add support for Allwinner DE2 mixers

2017-05-04 Thread Icenowy Zheng

Allwinner have a new "Display Engine 2.0" in their new SoCs, which comes
with mixers to do graphic processing and feed data to TCON, like the old
backends and frontends.

Add support for the mixer on Allwinner V3s SoC; it's the simplest one.

Currently a lot of functions are still missing -- more investigations
are needed to gain enough information for them.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v6:
- Rebased on wens's multi-pipeline patchset.
Changes in v5:
- Changed some code alignment.
- Request real 32-bit DMA (prepare for 64-bit SoCs).
Changes in v4:
- Killed some dead code according to Jernej.

 drivers/gpu/drm/sun4i/Kconfig   |  10 +
 drivers/gpu/drm/sun4i/Makefile  |   3 +
 drivers/gpu/drm/sun4i/sun8i_layer.c | 140 +
 drivers/gpu/drm/sun4i/sun8i_layer.h |  36 
 drivers/gpu/drm/sun4i/sun8i_mixer.c | 394 
 drivers/gpu/drm/sun4i/sun8i_mixer.h | 137 +
 6 files changed, 720 insertions(+)
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.h
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.h

diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 5a8227f37cc4..15557484520d 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -22,3 +22,13 @@ config DRM_SUN4I_BACKEND
  original Allwinner Display Engine, which has a backend to
  do some alpha blending and feed graphics to TCON. If M is
  selected the module will be called sun4i-backend.
+
+config DRM_SUN4I_SUN8I_MIXER
+   tristate "Support for Allwinner Display Engine 2.0 Mixer"
+   depends on DRM_SUN4I
+   default MACH_SUN8I
+   help
+ Choose this option if you have an Allwinner SoC with the
+ Allwinner Display Engine 2.0, which has a mixer to do some
+ graphics mixture and feed graphics to TCON, If M is
+ selected the module will be called sun8i-mixer.
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index a08df56759e3..a876c6b3027c 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -8,7 +8,10 @@ sun4i-tcon-y += sun4i_crtc.o
 
 sun4i-backend-y += sun4i_backend.o sun4i_layer.o
 
+sun8i-mixer-y += sun8i_mixer.o sun8i_layer.o
+
 obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o
 obj-$(CONFIG_DRM_SUN4I_BACKEND)+= sun4i-backend.o
+obj-$(CONFIG_DRM_SUN4I_SUN8I_MIXER)+= sun8i-mixer.o
 obj-$(CONFIG_DRM_SUN4I)+= sun6i_drc.o
 obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o
diff --git a/drivers/gpu/drm/sun4i/sun8i_layer.c 
b/drivers/gpu/drm/sun4i/sun8i_layer.c
new file mode 100644
index ..48f33d8e013b
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun8i_layer.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) Icenowy Zheng <icen...@aosc.io>
+ *
+ * Based on sun4i_layer.h, which is:
+ *   Copyright (C) 2015 Free Electrons
+ *   Copyright (C) 2015 NextThing Co
+ *
+ *   Maxime Ripard <maxime.rip...@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+
+#include "sun8i_layer.h"
+#include "sun8i_mixer.h"
+
+struct sun8i_plane_desc {
+  enum drm_plane_type type;
+  const uint32_t  *formats;
+  uint32_tnformats;
+};
+
+static int sun8i_mixer_layer_atomic_check(struct drm_plane *plane,
+   struct drm_plane_state *state)
+{
+   return 0;
+}
+
+static void sun8i_mixer_layer_atomic_disable(struct drm_plane *plane,
+  struct drm_plane_state 
*old_state)
+{
+   struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+   struct sun8i_mixer *mixer = layer->mixer;
+
+   sun8i_mixer_layer_enable(mixer, layer->id, false);
+}
+
+static void sun8i_mixer_layer_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+   struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+   struct sun8i_mixer *mixer = layer->mixer;
+
+   sun8i_mixer_update_layer_coord(mixer, layer->id, plane);
+   sun8i_mixer_update_layer_formats(mixer, layer->id, plane);
+   sun8i_mixer_update_layer_buffer(mixer, layer->id, plane);
+   sun8i_mixer_layer_enable(mixer, layer->id, true);
+}
+
+static struct drm_plane_helper_funcs sun8i_mixer_layer_helper_funcs = {
+   .atomic_check   = sun8i_mixer_layer_atomic_check,
+   .atomic_disable = sun8i_mixer_

[PATCH v6 10/13] drm/sun4i: tcon: add support for V3s TCON

2017-05-04 Thread Icenowy Zheng

Allwinner V3s SoC features a TCON without channel 1.

Add support for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_drv.c  | 3 ++-
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index dcfb241f817d..367e4e8e9656 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -188,7 +188,8 @@ static bool sun4i_drv_node_is_tcon(struct device_node *node)
return of_device_is_compatible(node, "allwinner,sun5i-a13-tcon") ||
of_device_is_compatible(node, "allwinner,sun6i-a31-tcon") ||
of_device_is_compatible(node, "allwinner,sun6i-a31s-tcon") ||
-   of_device_is_compatible(node, "allwinner,sun8i-a33-tcon");
+   of_device_is_compatible(node, "allwinner,sun8i-a33-tcon") ||
+   of_device_is_compatible(node, "allwinner,sun8i-v3s-tcon");
 }
 
 static int compare_of(struct device *dev, void *data)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index c48135a10fda..e76acf06e91b 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -681,11 +681,16 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
/* nothing is supported */
 };
 
+static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
+   /* nothing is supported */
+};
+
 static const struct of_device_id sun4i_tcon_of_table[] = {
{ .compatible = "allwinner,sun5i-a13-tcon", .data = _a13_quirks },
{ .compatible = "allwinner,sun6i-a31-tcon", .data = _a31_quirks },
{ .compatible = "allwinner,sun6i-a31s-tcon", .data = _a31s_quirks 
},
{ .compatible = "allwinner,sun8i-a33-tcon", .data = _a33_quirks },
+   { .compatible = "allwinner,sun8i-v3s-tcon", .data = _v3s_quirks },
{ }
 };
 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
-- 
2.12.2

Re: [linux-sunxi] Re: [PATCH v6 05/21] net-next: stmmac: Add dwmac-sun8i

2017-06-27 Thread Icenowy Zheng



于 2017年6月27日 GMT+08:00 下午6:11:47, Chen-Yu Tsai  写到:
>On Tue, Jun 27, 2017 at 5:41 PM, Maxime Ripard
> wrote:
>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
>>> Hi,
>>>
>>> (CC:ing some people from that Rockchip dmwac series)
>>>
>>> On 27/06/17 09:21, Corentin Labbe wrote:
>>> > On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote:
>>> >> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe
>>> >>  wrote:
>>> >>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote:
>>>  On 31/05/17 08:18, Corentin Labbe wrote:
>>> > The dwmac-sun8i is a heavy hacked version of stmmac hardware
>by
>>> > allwinner.
>>> > In fact the only common part is the descriptor management and
>the first
>>> > register function.
>>> 
>>>  Hi,
>>> 
>>>  I know I am a bit late with this, but while adapting the U-Boot
>driver
>>>  to the new binding I was wondering about the internal PHY
>detection:
>>> 
>>> 
>>>  So here you seem to deduce the usage of the internal PHY by the
>PHY
>>>  interface specified in the DT (MII = internal, RGMII =
>external).
>>>  I think I raised this question before, but isn't it perfectly
>legal for
>>>  a board to use MII with an external PHY even on those SoCs that
>feature
>>>  an internal PHY?
>>>  On the first glance that does not make too much sense, but
>apart from
>>>  not being the correct binding to describe all of the SoCs
>features I see
>>>  two scenarios:
>>>  1) A board vendor might choose to not use the internal PHY
>because it
>>>  has bugs, lacks features (configurability) or has other issues.
>For
>>>  instance I have heard reports that the internal PHY makes the
>SoC go
>>>  rather hot, possibly limiting the CPU frequency. By using an
>external
>>>  MII PHY (which are still cheaper than RGMII PHYs) this can be
>avoided.
>>>  2) A PHY does not necessarily need to be directly connected to
>>>  magnetics. Indeed quite some boards use (RG)MII to connect to a
>switch
>>>  IC or some other network circuitry, for instance fibre
>connectors.
>>> 
>>>  So I was wondering if we would need an explicit:
>>>    allwinner,use-internal-phy;
>>>  boolean DT property to signal the usage of the internal PHY?
>>>  Alternatively we could go with the negative version:
>>>    allwinner,disable-internal-phy;
>>> 
>>>  Or what about introducing a new "allwinner,internal-mii-phy"
>compatible
>>>  string for the *PHY* node and use that?
>>> 
>>>  I just want to avoid that we introduce a binding that causes us
>>>  headaches later. I think we can still fix this with a followup
>patch
>>>  before the driver and its binding hit a release kernel.
>>> 
>>>  Cheers,
>>>  Andre.
>>> 
>>> >>>
>>> >>> I just see some patch, where "phy-mode = internal" is valid.
>>> >>> I will try to find a way to use it
>>> >>
>>> >> Can you provide a link?
>>> >
>>> > https://lkml.org/lkml/2017/6/23/479
>>> >
>>> >>
>>> >> I'm not a fan of using phy-mode for this. There's no guarantee
>what
>>> >> mode the internal PHY uses. That's what phy-mode is for.
>>>
>>> I can understand Chen-Yu's concerns, but ...
>>>
>>> > For each soc the internal PHY mode is know and setted in
>emac_variant/internal_phy
>>> > So its not a problem.
>>>
>>> that is true as well, at least for now.
>>>
>>> So while I agree that having a separate property to indicate the
>usage
>>> of the internal PHY would be nice, I am bit tempted to use this
>easier
>>> approach and piggy back on the existing phy-mode property.
>>
>> We're trying to fix an issue that works for now too.
>>
>> If we want to consider future weird cases, then we must consider all
>> of them. And the phy mode changing is definitely not really far
>> fetched.
>
>I guess the issue is whether it's likely that the vendor puts 2
>internal
>PHYs in one SoC, and they use different modes and can be switched
>around.
>Otherwise it's fixed for a given SoC, and we can just handle that with
>the per-SoC GMAC compatible.
>
>Maybe Florian could tell us if this was one of the intended use cases
>for the "internal" phy mode.
>
>As for Rockchip, AFAIK they have 2 MACs, one is connected to the
>internal
>PHY, while the other is connected to the external interface, and there
>is
>no muxing involved, unlike Allwinner's solution.
>
>> I agree with Chen-Yu, and I really feel like the compatible solution
>> you suggested would cover both your concerns, and ours.
>
>If using a PHY compatible is the solution, we could just use the
>"ethernet-phy-id." style one, and put in the bogus ID that
>Allwinner used.
>
>Care must be taken to put this at the board level for boards using
>the internal PHY, or we'd have to delete or override the property
>in all other boards.
>
>Ideally I think the internal PHY device node should _not_ be

Re: [PATCH v6 05/21] net-next: stmmac: Add dwmac-sun8i

2017-06-27 Thread Icenowy Zheng



于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara  写到:
>Hi,
>
>On 27/06/17 10:41, Maxime Ripard wrote:
>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
>>> Hi,
>>>
>>> (CC:ing some people from that Rockchip dmwac series)
>>>
>>> On 27/06/17 09:21, Corentin Labbe wrote:
 On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote:
> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe
>  wrote:
>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote:
>>> On 31/05/17 08:18, Corentin Labbe wrote:
 The dwmac-sun8i is a heavy hacked version of stmmac hardware by
 allwinner.
 In fact the only common part is the descriptor management and
>the first
 register function.
>>>
>>> Hi,
>>>
>>> I know I am a bit late with this, but while adapting the U-Boot
>driver
>>> to the new binding I was wondering about the internal PHY
>detection:
>>>
>>>
>>> So here you seem to deduce the usage of the internal PHY by the
>PHY
>>> interface specified in the DT (MII = internal, RGMII =
>external).
>>> I think I raised this question before, but isn't it perfectly
>legal for
>>> a board to use MII with an external PHY even on those SoCs that
>feature
>>> an internal PHY?
>>> On the first glance that does not make too much sense, but apart
>from
>>> not being the correct binding to describe all of the SoCs
>features I see
>>> two scenarios:
>>> 1) A board vendor might choose to not use the internal PHY
>because it
>>> has bugs, lacks features (configurability) or has other issues.
>For
>>> instance I have heard reports that the internal PHY makes the
>SoC go
>>> rather hot, possibly limiting the CPU frequency. By using an
>external
>>> MII PHY (which are still cheaper than RGMII PHYs) this can be
>avoided.
>>> 2) A PHY does not necessarily need to be directly connected to
>>> magnetics. Indeed quite some boards use (RG)MII to connect to a
>switch
>>> IC or some other network circuitry, for instance fibre
>connectors.
>>>
>>> So I was wondering if we would need an explicit:
>>>   allwinner,use-internal-phy;
>>> boolean DT property to signal the usage of the internal PHY?
>>> Alternatively we could go with the negative version:
>>>   allwinner,disable-internal-phy;
>>>
>>> Or what about introducing a new "allwinner,internal-mii-phy"
>compatible
>>> string for the *PHY* node and use that?
>>>
>>> I just want to avoid that we introduce a binding that causes us
>>> headaches later. I think we can still fix this with a followup
>patch
>>> before the driver and its binding hit a release kernel.
>>>
>>> Cheers,
>>> Andre.
>>>
>>
>> I just see some patch, where "phy-mode = internal" is valid.
>> I will try to find a way to use it
>
> Can you provide a link?

 https://lkml.org/lkml/2017/6/23/479

>
> I'm not a fan of using phy-mode for this. There's no guarantee
>what
> mode the internal PHY uses. That's what phy-mode is for.
>>>
>>> I can understand Chen-Yu's concerns, but ...
>>>
 For each soc the internal PHY mode is know and setted in
>emac_variant/internal_phy
 So its not a problem.
>>>
>>> that is true as well, at least for now.
>>>
>>> So while I agree that having a separate property to indicate the
>usage
>>> of the internal PHY would be nice, I am bit tempted to use this
>easier
>>> approach and piggy back on the existing phy-mode property.
>> 
>> We're trying to fix an issue that works for now too.
>> 
>> If we want to consider future weird cases, then we must consider all
>> of them. And the phy mode changing is definitely not really far
>> fetched.
>> 
>> I agree with Chen-Yu, and I really feel like the compatible solution
>> you suggested would cover both your concerns, and ours.
>
>So something like this?
>   emac: emac@1c3 {
>   compatible = "allwinner,sun8i-h3-emac";
>   ...
>   phy-mode = "mii";
>   phy-handle = <_mii_phy>;
>   ...
>
>   mdio: mdio {
>#address-cells = <1>;
>#size-cells = <0>;
>int_mii_phy: ethernet-phy@1 {
>compatible = "allwinner,sun8i-h3-ephy";
>syscon = <>;

The MAC still needs to set some bits of syscon register.

>reg = <1>;
>clocks = < CLK_BUS_EPHY>;
>resets = < RST_BUS_EPHY>;
>};
>};
>};
>
>And then move the internal-PHY setup code into a separate PHY driver?
>
>That looks like the architecturally best solution to me, but is
>probably
>also a bit involved since it would require a separate PHY driver.
>Or can we make it simpler, but still use this binding?
>
>Cheers,
>Andre.

[PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device tree binding for H3

2017-09-14 Thread Icenowy Zheng

Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.

Update the binding document to cover H3.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v4:
- Add nvmem calibration data (not yet used by the driver)
Changes in v3:
- Clock name changes.
- Example node name changes.
- Add interupts (not yet used by the driver).

 .../devicetree/bindings/mfd/sun4i-gpadc.txt| 30 --
 1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt 
b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
index badff3611a98..6c470d584bf9 100644
--- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
+++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
@@ -4,12 +4,26 @@ The Allwinner SoCs all have an ADC that can also act as a 
thermal sensor
 and sometimes as a touchscreen controller.
 
 Required properties:
-  - compatible: "allwinner,sun8i-a33-ths",
+  - compatible: must contain one of the following compatibles:
+   - "allwinner,sun8i-a33-ths"
+   - "allwinner,sun8i-h3-ths"
   - reg: mmio address range of the chip,
   - #thermal-sensor-cells: shall be 0,
   - #io-channel-cells: shall be 0,
 
-Example:
+Optional properties:
+  - nvmem-cells: A phandle to the calibration data provided by a nvmem device.
+ If unspecified default values shall be used.
+  - nvmem-cell-names: Should be "calibration-data"
+
+Required properties for the following compatibles:
+   - "allwinner,sun8i-h3-ths"
+  - clocks: the bus clock and the input clock of the ADC,
+  - clock-names: should be "bus" and "mod",
+  - resets: the bus reset of the ADC,
+  - interrupts: the sampling interrupt of the ADC,
+
+Example for A33:
ths: ths@01c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
@@ -17,6 +31,18 @@ Example:
#io-channel-cells = <0>;
};
 
+Example for H3:
+   ths: thermal-sensor@1c25000 {
+   compatible = "allwinner,sun8i-h3-ths";
+   reg = <0x01c25000 0x400>;
+   clocks = < CLK_BUS_THS>, < CLK_THS>;
+   clock-names = "bus", "mod";
+   resets = < RST_BUS_THS>;
+   interrupts = ;
+   #thermal-sensor-cells = <0>;
+   #io-channel-cells = <0>;
+   };
+
 sun4i, sun5i and sun6i SoCs are also supported via the older binding:
 
 sun4i resistive touchscreen controller
-- 
2.13.5

[PATCH v4 2/6] iio: adc: sun4i-gpadc-iio: rename A33-specified registers to contain A33

2017-09-14 Thread Icenowy Zheng

As the H3 SoC, which is also in sun8i line, has totally different
register map for the thermal sensor (a cut down version of GPADC), we
should rename A23/A33-specified registers to contain A33, in order to
prevent obfuscation with H3 registers. Currently these registers are
only prefixed "SUN8I", not "SUN8I_A33".

Add "_A33" after "SUN8I" on the register names.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v4:
- Change A23 to A33, as the driver never supports A23.

 drivers/iio/adc/sun4i-gpadc-iio.c | 2 +-
 include/linux/mfd/sun4i-gpadc.h   | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 137f577d9432..68926b986cd0 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -88,7 +88,7 @@ static const struct gpadc_data sun6i_gpadc_data = {
 static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_offset = -1662,
.temp_scale = 162,
-   .tp_mode_en = SUN8I_GPADC_CTRL1_CHOP_TEMP_EN,
+   .tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
 };
 
 struct sun4i_gpadc_iio {
diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h
index 139872c2e0fe..78d31984a222 100644
--- a/include/linux/mfd/sun4i-gpadc.h
+++ b/include/linux/mfd/sun4i-gpadc.h
@@ -38,9 +38,9 @@
 #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x)   (GENMASK(3, 0) & BIT(x))
 #define SUN6I_GPADC_CTRL1_ADC_CHAN_MASKGENMASK(3, 0)
 
-/* TP_CTRL1 bits for sun8i SoCs */
-#define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
-#define SUN8I_GPADC_CTRL1_GPADC_CALI_ENBIT(7)
+/* TP_CTRL1 bits for A33 */
+#define SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
+#define SUN8I_A33_GPADC_CTRL1_GPADC_CALI_ENBIT(7)
 
 #define SUN4I_GPADC_CTRL2  0x08
 
-- 
2.13.5

[PATCH v4 0/6] IIO-based thermal sensor driver for Allwinner H3 SoC

2017-09-14 Thread Icenowy Zheng

Allwiner H3 SoC has a thermal sensor, which is a large refactored version of
the old Allwinner "GPADC" (although it have already only thermal part left
in A33).

This patch tried to add support for the sensor in H3 based on the A33 thermal
sensor driver by Quentin Schulz, which is already merged.

Icenowy Zheng (6):
  dt-bindings: update the Allwinner GPADC device tree binding for H3
  iio: adc: sun4i-gpadc-iio: rename A33-specified registers to contain
A33
  iio: adc: sun4i-gpadc-iio: rework code for supporting newer THS
variants
  iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
  ARM: sun8i: h3: add support for the thermal sensor in H3
  ARM: sun8i: h3: add partial CPU thermal zone

 .../devicetree/bindings/mfd/sun4i-gpadc.txt|  30 +++-
 arch/arm/boot/dts/sun8i-h3.dtsi|  26 
 drivers/iio/adc/sun4i-gpadc-iio.c  | 173 -
 include/linux/mfd/sun4i-gpadc.h|  33 +++-
 4 files changed, 249 insertions(+), 13 deletions(-)

-- 
2.13.5

[PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

2017-09-14 Thread Icenowy Zheng

This adds support for the Allwinner H3 thermal sensor.

Allwinner H3 has a thermal sensor like the one in A33, but have its
registers nearly all re-arranged, sample clock moved to CCU and a pair
of bus clock and reset added. It's also the base of newer SoCs' thermal
sensors.

The thermal sensors on A64 and H5 is like the one on H3, but with of
course different formula factors.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Splitted out some code refactors.
- Code sequence changed back. (The gpadc_data went back to the start of
  the source file)

 drivers/iio/adc/sun4i-gpadc-iio.c | 48 +++
 include/linux/mfd/sun4i-gpadc.h   | 27 ++
 2 files changed, 75 insertions(+)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 97845982d050..f7e4df6bd17a 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -59,6 +59,8 @@ struct sun4i_gpadc_iio;
  */
 static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info);
 static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info);
+static int sun8i_h3_gpadc_sample_start(struct sun4i_gpadc_iio *info);
+static int sun8i_h3_gpadc_sample_end(struct sun4i_gpadc_iio *info);
 
 struct gpadc_data {
int temp_offset;
@@ -120,6 +122,24 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
.sample_end = sun4i_gpadc_sample_end,
 };
 
+static const struct gpadc_data sun8i_h3_gpadc_data = {
+   /*
+* The original formula on the datasheet seems to be wrong.
+* These factors are calculated based on the formula in the BSP
+* kernel, which is originally Tem = 217 - (T / 8.253), in which Tem
+* is the temperature in Celsius degree and T is the raw value
+* from the sensor.
+*/
+   .temp_offset = -1791,
+   .temp_scale = -121,
+   .temp_data = SUN8I_H3_GPADC_TEMP_DATA,
+   .sample_start = sun8i_h3_gpadc_sample_start,
+   .sample_end = sun8i_h3_gpadc_sample_end,
+   .has_bus_clk = true,
+   .has_bus_rst = true,
+   .has_mod_clk = true,
+};
+
 struct sun4i_gpadc_iio {
struct iio_dev  *indio_dev;
struct completion   completion;
@@ -425,6 +445,14 @@ static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio 
*info)
return 0;
 }
 
+static int sun8i_h3_gpadc_sample_end(struct sun4i_gpadc_iio *info)
+{
+   /* Disable temperature sensor */
+   regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL2, 0);
+
+   return 0;
+}
+
 static int sun4i_gpadc_runtime_suspend(struct device *dev)
 {
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
@@ -451,6 +479,22 @@ static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio 
*info)
return 0;
 }
 
+static int sun8i_h3_gpadc_sample_start(struct sun4i_gpadc_iio *info)
+{
+   regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL2,
+SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN |
+SUN8I_H3_GPADC_CTRL2_T_ACQ1(31));
+   regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
+SUN4I_GPADC_CTRL0_T_ACQ(31));
+   regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL3,
+SUN4I_GPADC_CTRL3_FILTER_EN |
+SUN4I_GPADC_CTRL3_FILTER_TYPE(1));
+   regmap_write(info->regmap, SUN8I_H3_GPADC_INTC,
+SUN8I_H3_GPADC_INTC_TEMP_PERIOD(800));
+
+   return 0;
+}
+
 static int sun4i_gpadc_runtime_resume(struct device *dev)
 {
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
@@ -537,6 +581,10 @@ static const struct of_device_id sun4i_gpadc_of_id[] = {
.compatible = "allwinner,sun8i-a33-ths",
.data = _a33_gpadc_data,
},
+   {
+   .compatible = "allwinner,sun8i-h3-ths",
+   .data = _h3_gpadc_data,
+   },
{ /* sentinel */ }
 };
 
diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h
index 78d31984a222..5c2a12101052 100644
--- a/include/linux/mfd/sun4i-gpadc.h
+++ b/include/linux/mfd/sun4i-gpadc.h
@@ -42,6 +42,9 @@
 #define SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
 #define SUN8I_A33_GPADC_CTRL1_GPADC_CALI_ENBIT(7)
 
+/* TP_CTRL1 bits for SoCs after H3 */
+#define SUN8I_H3_GPADC_CTRL1_GPADC_CALI_EN BIT(17)
+
 #define SUN4I_GPADC_CTRL2  0x08
 
 #define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x)   ((GENMASK(3, 0) & (x)) 
<< 28)
@@ -49,7 +52,17 @@
 #define SUN4I_GPADC_CTRL2_PRE_MEA_EN   BIT(24)
 #define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x)  (GENMASK(23, 0) & (x))
 
+#define SUN8I_H3_GPADC_CTRL2   0x40
+
+#define SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN BIT(0)
+#define SUN8I_H3_GPADC_CTRL2_T_ACQ1(x) ((GEN

[PATCH v4 5/6] ARM: sun8i: h3: add support for the thermal sensor in H3

2017-09-14 Thread Icenowy Zheng

As we have gained the support for the thermal sensor in H3, we can now
add its device nodes to the device tree.

Add them to the H3 device tree.

The calibration data of the thermal sensor is still not added, as
it's currently not used, and the SID node is not added yet.

The H5 thermal sensor has some differences, and will be added furtherly.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v4:
- Mention calibration data in commit message.
Changes in v3:
- Clock name changes.
- Splited out thermal zone addition.

 arch/arm/boot/dts/sun8i-h3.dtsi | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..3220da3ad790 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -72,6 +72,23 @@
};
};
 
+   iio-hwmon {
+   compatible = "iio-hwmon";
+   io-channels = <>;
+   };
+
+   soc {
+   ths: thermal-sensor@1c25000 {
+   compatible = "allwinner,sun8i-h3-ths";
+   reg = <0x01c25000 0x100>;
+   clocks = < CLK_BUS_THS>, < CLK_THS>;
+   clock-names = "bus", "mod";
+   resets = < RST_BUS_THS>;
+   #thermal-sensor-cells = <0>;
+   #io-channel-cells = <0>;
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
-- 
2.13.5

[PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone

2017-09-14 Thread Icenowy Zheng

Because of the restriction of the OF thermal framework, the thermal
sensor will fail to probe if the thermal zone doesn't exist.

Add a partial thermal zone which claims the H3 THS as the thermal sensor.

The cooling device (CPU DVFS) is still not added as it's not ready, and
the trip points are also not added yet.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 3220da3ad790..687c6457d214 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -89,6 +89,15 @@
};
};
 
+   thermal-zones {
+   cpu-thermal {
+   /* milliseconds */
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = <>;
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
-- 
2.13.5

[PATCH v4 3/6] iio: adc: sun4i-gpadc-iio: rework code for supporting newer THS variants

2017-09-14 Thread Icenowy Zheng

The SoCs after H3 has newer thermal sensor ADCs, which have two clock
inputs (bus clock and sampling clock) and a reset. The registers are
also re-arranged.

This commit reworks the code, adds the process of the clocks and
resets, and allows the sampling start/end code and the position of value
readout register to be altered.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 123 +++---
 1 file changed, 116 insertions(+), 7 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 68926b986cd0..97845982d050 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -22,6 +22,7 @@
  * shutdown for not being used.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -31,6 +32,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -49,6 +51,15 @@ static unsigned int sun6i_gpadc_chan_select(unsigned int 
chan)
return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
 }
 
+struct sun4i_gpadc_iio;
+
+/*
+ * Prototypes for these functions, which enable these functions to be
+ * referenced in gpadc_data structures.
+ */
+static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info);
+static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info);
+
 struct gpadc_data {
int temp_offset;
int temp_scale;
@@ -56,6 +67,12 @@ struct gpadc_data {
unsigned inttp_adc_select;
unsigned int(*adc_chan_select)(unsigned int chan);
unsigned intadc_chan_mask;
+   unsigned inttemp_data;
+   int (*sample_start)(struct sun4i_gpadc_iio *info);
+   int (*sample_end)(struct sun4i_gpadc_iio *info);
+   boolhas_bus_clk;
+   boolhas_bus_rst;
+   boolhas_mod_clk;
 };
 
 static const struct gpadc_data sun4i_gpadc_data = {
@@ -65,6 +82,9 @@ static const struct gpadc_data sun4i_gpadc_data = {
.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = _gpadc_chan_select,
.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
+   .temp_data = SUN4I_GPADC_TEMP_DATA,
+   .sample_start = sun4i_gpadc_sample_start,
+   .sample_end = sun4i_gpadc_sample_end,
 };
 
 static const struct gpadc_data sun5i_gpadc_data = {
@@ -74,6 +94,9 @@ static const struct gpadc_data sun5i_gpadc_data = {
.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = _gpadc_chan_select,
.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
+   .temp_data = SUN4I_GPADC_TEMP_DATA,
+   .sample_start = sun4i_gpadc_sample_start,
+   .sample_end = sun4i_gpadc_sample_end,
 };
 
 static const struct gpadc_data sun6i_gpadc_data = {
@@ -83,12 +106,18 @@ static const struct gpadc_data sun6i_gpadc_data = {
.tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = _gpadc_chan_select,
.adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
+   .temp_data = SUN4I_GPADC_TEMP_DATA,
+   .sample_start = sun4i_gpadc_sample_start,
+   .sample_end = sun4i_gpadc_sample_end,
 };
 
 static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_offset = -1662,
.temp_scale = 162,
.tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
+   .temp_data = SUN4I_GPADC_TEMP_DATA,
+   .sample_start = sun4i_gpadc_sample_start,
+   .sample_end = sun4i_gpadc_sample_end,
 };
 
 struct sun4i_gpadc_iio {
@@ -103,6 +132,9 @@ struct sun4i_gpadc_iio {
atomic_tignore_temp_data_irq;
const struct gpadc_data *data;
boolno_irq;
+   struct clk  *bus_clk;
+   struct clk  *mod_clk;
+   struct reset_control*reset;
/* prevents concurrent reads of temperature and ADC */
struct mutexmutex;
struct thermal_zone_device  *tzd;
@@ -277,7 +309,7 @@ static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, 
int *val)
if (info->no_irq) {
pm_runtime_get_sync(indio_dev->dev.parent);
 
-   regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
+   regmap_read(info->regmap, info->data->temp_data, val);
 
pm_runtime_mark_last_busy(indio_dev->dev.parent);
pm_runtime_put_autosuspend(indio_dev->dev.parent);
@@ -383,10 +415,8 @@ static irqreturn_t sun4i_gpadc_fifo_data_irq_handler(int 
irq, void *dev_id)
return IRQ_HANDLED;
 }
 
-static int sun4i_gpadc_runtime_suspend(struct device *dev)
+static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info)
 {
-   struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
-
/* Disable the ADC on IP */
regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0);
/* Disable temperature s

[PATCH] nvmem: sunxi-sid: add support for A64/H5's SID controller

2017-09-18 Thread Icenowy Zheng

Allwinner A64/H5 SoCs come with a SID controller like the one in H3, but
without the silicon bug that makes the initial value at 0x200 wrong, so
the value at 0x200 can be directly read.

Add support for this kind of SID controller.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt | 1 +
 drivers/nvmem/sunxi_sid.c   | 6 ++
 2 files changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt 
b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt
index ef06d061913c..6ea0836939ee 100644
--- a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt
+++ b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt
@@ -5,6 +5,7 @@ Required properties:
   "allwinner,sun4i-a10-sid"
   "allwinner,sun7i-a20-sid"
   "allwinner,sun8i-h3-sid"
+  "allwinner,sun50i-a64-sid"
 
 - reg: Should contain registers location and length
 
diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
index 0d6648be93b8..3c9fd4fb9207 100644
--- a/drivers/nvmem/sunxi_sid.c
+++ b/drivers/nvmem/sunxi_sid.c
@@ -199,10 +199,16 @@ static const struct sunxi_sid_cfg sun8i_h3_cfg = {
.need_register_readout = true,
 };
 
+static const struct sunxi_sid_cfg sun50i_a64_cfg = {
+   .value_offset = 0x200,
+   .size = 0x100,
+};
+
 static const struct of_device_id sunxi_sid_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-sid", .data = _a10_cfg },
{ .compatible = "allwinner,sun7i-a20-sid", .data = _a20_cfg },
{ .compatible = "allwinner,sun8i-h3-sid", .data = _h3_cfg },
+   { .compatible = "allwinner,sun50i-a64-sid", .data = _a64_cfg },
{/* sentinel */},
 };
 MODULE_DEVICE_TABLE(of, sunxi_sid_of_match);
-- 
2.13.5

Re: [linux-sunxi] Re: [PATCH] nvmem: sunxi-sid: add support for A64/H5's SID controller

2017-09-19 Thread Icenowy Zheng



于 2017年9月19日 GMT+08:00 下午4:20:19, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Mon, Sep 18, 2017 at 11:42:04PM +0800, Icenowy Zheng wrote:
>> Allwinner A64/H5 SoCs come with a SID controller like the one in H3,
>but
>> without the silicon bug that makes the initial value at 0x200 wrong,
>so
>> the value at 0x200 can be directly read.
>> 
>> Add support for this kind of SID controller.
>> 
>> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>> ---
>>  Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt | 1
>+
>>  drivers/nvmem/sunxi_sid.c   | 6
>++
>>  2 files changed, 7 insertions(+)
>> 
>> diff --git
>a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt
>b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt
>> index ef06d061913c..6ea0836939ee 100644
>> --- a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt
>> +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt
>> @@ -5,6 +5,7 @@ Required properties:
>>"allwinner,sun4i-a10-sid"
>>"allwinner,sun7i-a20-sid"
>>"allwinner,sun8i-h3-sid"
>> +  "allwinner,sun50i-a64-sid"
>>  
>>  - reg: Should contain registers location and length
>>  
>> diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
>> index 0d6648be93b8..3c9fd4fb9207 100644
>> --- a/drivers/nvmem/sunxi_sid.c
>> +++ b/drivers/nvmem/sunxi_sid.c
>> @@ -199,10 +199,16 @@ static const struct sunxi_sid_cfg sun8i_h3_cfg
>= {
>>  .need_register_readout = true,
>>  };
>>  
>> +static const struct sunxi_sid_cfg sun50i_a64_cfg = {
>> +.value_offset = 0x200,
>> +.size = 0x100,
>> +};
>> +
>
>How did you get those values?

In the BSP U-Boot headers.

>
>Also, it's reported that the SID can only be accessed in secure mode,
>did you test it?

Yes, however the secure is broken again, and this only
happen if Secure Boot bit is burned.

If it's really burned, we will have no clean way to access SID.

>
>Maxime

Re: [linux-sunxi] Re: [PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device tree binding for H3

2017-09-20 Thread Icenowy Zheng



于 2017年9月20日 GMT+08:00 下午3:52:23, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Mon, Sep 18, 2017 at 03:47:25PM +, icen...@aosc.io wrote:
>> 在 2017-09-18 16:30，Maxime Ripard 写道：
>> > On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:
>> > > 于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard
>> > > <maxime.rip...@free-electrons.com> 写到:
>> > > >On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:
>> > > >> Allwinner H3 features a thermal sensor like the one in A33,
>but has
>> > > >its
>> > > >> register re-arranged, the clock divider moved to CCU
>(originally the
>> > > >> clock divider is in ADC) and added a pair of bus clock and
>reset.
>> > > >>
>> > > >> Update the binding document to cover H3.
>> > > >>
>> > > >> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>> > > >> Reviewed-by: Chen-Yu Tsai <w...@csie.org>
>> > > >> ---
>> > > >> Changes in v4:
>> > > >> - Add nvmem calibration data (not yet used by the driver)
>> > > >> Changes in v3:
>> > > >> - Clock name changes.
>> > > >> - Example node name changes.
>> > > >> - Add interupts (not yet used by the driver).
>> > > >>
>> > > >>  .../devicetree/bindings/mfd/sun4i-gpadc.txt| 30
>> > > >--
>> > > >>  1 file changed, 28 insertions(+), 2 deletions(-)
>> > > >>
>> > > >> diff --git
>a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
>> > > >b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
>> > > >> index badff3611a98..6c470d584bf9 100644
>> > > >> --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
>> > > >> +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
>> > > >> @@ -4,12 +4,26 @@ The Allwinner SoCs all have an ADC that can
>also
>> > > >act as a thermal sensor
>> > > >>  and sometimes as a touchscreen controller.
>> > > >>
>> > > >>  Required properties:
>> > > >> -  - compatible: "allwinner,sun8i-a33-ths",
>> > > >> +  - compatible: must contain one of the following
>compatibles:
>> > > >> + - "allwinner,sun8i-a33-ths"
>> > > >> + - "allwinner,sun8i-h3-ths"
>> > > >>- reg: mmio address range of the chip,
>> > > >>- #thermal-sensor-cells: shall be 0,
>> > > >>- #io-channel-cells: shall be 0,
>> > > >>
>> > > >> -Example:
>> > > >> +Optional properties:
>> > > >> +  - nvmem-cells: A phandle to the calibration data provided
>by a
>> > > >nvmem device.
>> > > >> + If unspecified default values shall be used.
>> > > >> +  - nvmem-cell-names: Should be "calibration-data"
>> > > >
>> > > >I'd prefer to have which sensor it applies to here. It wouldn't
>change
>> > > >anything for the H3, but it definitely does for example for the
>A83t
>> > > >that has two sensors, one for each cluster, and one for the GPU,
>each
>> > > >with calibration data.
>> > > >
>> > > >What about cluster0-calibration?
>> 
>> I prefer sensor0-calibration to sensor3-calibration now.
>> (Theortically the new generation THS can support up to 4 sensors)
>
>The mapping that explains what sensor0 means can change in the
>future. It's better to be explicit here, and just say upfront what
>it's about.

I think for some SoC (e.g. A64) there's no clear explain on
the functions of the sensors.

In addition, in the THS controller the sensors has a
explicit sequence, and when referencing it in the DT
the number is still needed (in thermal zones).

>
>Maxime

[PATCH 2/3] arm64: allwinner: a64: add CPU opp table

2017-09-22 Thread Icenowy Zheng

Add the operating table for the CPU (ARM cores) on Allwinner A64 SoC.

OPPs higher to 816MHz is temporarily dropped, to prevent overheat on
boards with AXP803 support and undervoltage on boards without AXP803
support.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 20aba7b186aa..0532da4939eb 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -52,6 +52,23 @@
#address-cells = <1>;
#size-cells = <1>;
 
+   cpu0_opp_table: opp_table0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp-64800 {
+   opp-hz = /bits/ 64 <64800>;
+   opp-microvolt = <104>;
+   clock-latency-ns = <244144>; /* 8 32k periods */
+   };
+
+   opp-81600 {
+   opp-hz = /bits/ 64 <81600>;
+   opp-microvolt = <110>;
+   clock-latency-ns = <244144>; /* 8 32k periods */
+   };
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -61,6 +78,10 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+   clocks = < CLK_CPUX>;
+   clock-names = "cpu";
+   operating-points-v2 = <_opp_table>;
+   #cooling-cells = <2>;
};
 
cpu1: cpu@1 {
@@ -68,6 +89,7 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+   operating-points-v2 = <_opp_table>;
};
 
cpu2: cpu@2 {
@@ -75,6 +97,7 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+   operating-points-v2 = <_opp_table>;
};
 
cpu3: cpu@3 {
@@ -82,6 +105,7 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+   operating-points-v2 = <_opp_table>;
};
};
 
-- 
2.13.5

[PATCH 0/3] Simple DVFS support for Allwinner A64 SoC

2017-09-22 Thread Icenowy Zheng

This patchset imports simple DVFS support for Allwinner A64 SoC.

As the thermal sensor driver is not yet implemented and some boards
have still no AXP PMIC support, now only two OPPs are present --
648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.

PATCH 1 is a fix to the CCU driver of A64, and the remaining patches
set up the device tree bits of the DVFS on Pine64.

Icenowy Zheng (3):
  clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
  arm64: allwinner: a64: add CPU opp table
  arm64: allwinner: a64: set CPU regulator for Pine64

 .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts |  4 
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi  | 24 +++
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c  | 28 +-
 3 files changed, 55 insertions(+), 1 deletion(-)

-- 
2.13.5

[PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

2017-09-22 Thread Icenowy Zheng

The A64 PLL_CPU clock has the same instability if some factor changed
without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,
H3.

Add the mux and pll notifiers for A64 CPU clock to workaround the
problem.

Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28 +++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c 
b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 2bb4cabf802f..b55fa69dd0c1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
.num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
 };
 
+static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {
+   .common = _cpux_clk.common,
+   /* copy from pll_cpux_clk */
+   .enable = BIT(31),
+   .lock   = BIT(28),
+};
+
+static struct ccu_mux_nb sun50i_a64_cpu_nb = {
+   .common = _clk.common,
+   .cm = _clk.mux,
+   .delay_us   = 1, /* > 8 clock cycles at 24 MHz */
+   .bypass_index   = 1, /* index of 24 MHz oscillator */
+};
+
 static int sun50i_a64_ccu_probe(struct platform_device *pdev)
 {
struct resource *res;
void __iomem *reg;
u32 val;
+   int ret;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
reg = devm_ioremap_resource(>dev, res);
@@ -897,7 +912,18 @@ static int sun50i_a64_ccu_probe(struct platform_device 
*pdev)
 
writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
 
-   return sunxi_ccu_probe(pdev->dev.of_node, reg, _a64_ccu_desc);
+   ret = sunxi_ccu_probe(pdev->dev.of_node, reg, _a64_ccu_desc);
+   if (ret)
+   return ret;
+
+   /* Gate then ungate PLL CPU after any rate changes */
+   ccu_pll_notifier_register(_a64_pll_cpu_nb);
+
+   /* Reparent CPU during PLL CPU rate changes */
+   ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
+ _a64_cpu_nb);
+
+   return 0;
 }
 
 static const struct of_device_id sun50i_a64_ccu_ids[] = {
-- 
2.13.5

[PATCH 3/3] arm64: allwinner: a64: set CPU regulator for Pine64

2017-09-22 Thread Icenowy Zheng

The DCDC2 regulator of the AXP803 PMIC is used for the voltage scaling
of the ARM cores on the A64 SoC.

Add this definition to enable it on Pine64.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index d06e34b5d192..cc77503091f1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -63,6 +63,10 @@
};
 };
 
+ {
+   cpu-supply = <_dcdc2>;
+};
+
  {
status = "okay";
 };
-- 
2.13.5

[RFC PATCH 2/7] iio: adc: axp20x-adc: allow to skip ADC rate setup now

2017-09-20 Thread Icenowy Zheng

The ADC rate setup on AXP803 is more complex than AXP20x/22x.

As it's not a necessary setup, allow it to be skipped, to allow simpler
AXP803 support now.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/iio/adc/axp20x_adc.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
index 11e177180ea0..93dd6b80059e 100644
--- a/drivers/iio/adc/axp20x_adc.c
+++ b/drivers/iio/adc/axp20x_adc.c
@@ -556,8 +556,10 @@ static int axp20x_probe(struct platform_device *pdev)
   AXP20X_ADC_EN2_MASK, AXP20X_ADC_EN2_MASK);
 
/* Configure ADCs rate */
-   regmap_update_bits(info->regmap, AXP20X_ADC_RATE, AXP20X_ADC_RATE_MASK,
-  info->data->adc_rate(100));
+   if (info->data->adc_rate)
+   regmap_update_bits(info->regmap, AXP20X_ADC_RATE,
+  AXP20X_ADC_RATE_MASK,
+  info->data->adc_rate(100));
 
ret = iio_map_array_register(indio_dev, info->data->maps);
if (ret < 0) {
-- 
2.13.5

[RFC PATCH 3/7] iio: adc: axp20x-adc: add support for AXP803

2017-09-20 Thread Icenowy Zheng

AXP803 SoC features an ADC part including these channels: GPADC (GPIO0)
and TS pins, PMIC internal temperature sensor, battery voltage, battery
charge/discharge current.

Add support for the battery-related channels and internal temperature
channel in order to allow battery monitoring. The TS and GPADC channels
are complex and will be support after more investigation.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/iio/adc/axp20x_adc.c | 108 +++
 1 file changed, 108 insertions(+)

diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
index 93dd6b80059e..4f0cd98cf6ea 100644
--- a/drivers/iio/adc/axp20x_adc.c
+++ b/drivers/iio/adc/axp20x_adc.c
@@ -28,6 +28,8 @@
 
 #define AXP20X_ADC_EN2_MASK(GENMASK(3, 2) | BIT(7))
 #define AXP22X_ADC_EN1_MASK(GENMASK(7, 5) | BIT(0))
+/* TODO: Enable TS and GPADC when supporting them */
+#define AXP803_ADC_EN1_MASKGENMASK(7, 5)
 
 #define AXP20X_GPIO10_IN_RANGE_GPIO0   BIT(0)
 #define AXP20X_GPIO10_IN_RANGE_GPIO1   BIT(1)
@@ -95,6 +97,17 @@ enum axp22x_adc_channel_i {
AXP22X_BATT_DISCHRG_I,
 };
 
+enum axp803_adc_channel_v {
+   AXP803_TS_IN = 0,
+   AXP803_GPADC_IN,
+   AXP803_BATT_V,
+};
+
+enum axp803_adc_channel_i {
+   AXP803_BATT_CHRG_I = 2,
+   AXP803_BATT_DISCHRG_I,
+};
+
 static struct iio_map axp20x_maps[] = {
{
.consumer_dev_name = "axp20x-usb-power-supply",
@@ -144,6 +157,11 @@ static struct iio_map axp22x_maps[] = {
 };
 
 /*
+ * AXP803 shares the same consumer map with AXP22x, as it has no ADC for
+ * VBUS and ACIN inputs either.
+ */
+
+/*
  * Channels are mapped by physical system. Their channels share the same index.
  * i.e. acin_i is in_current0_raw and acin_v is in_voltage0_raw.
  * The only exception is for the battery. batt_v will be in_voltage6_raw and
@@ -197,6 +215,23 @@ static const struct iio_chan_spec axp22x_adc_channels[] = {
   AXP20X_BATT_DISCHRG_I_H),
 };
 
+static const struct iio_chan_spec axp803_adc_channels[] = {
+   {
+   .type = IIO_TEMP,
+   .address = AXP288_PMIC_ADC_H,
+   .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_SCALE) |
+ BIT(IIO_CHAN_INFO_OFFSET),
+   .datasheet_name = "pmic_temp",
+   },
+   AXP20X_ADC_CHANNEL(AXP803_BATT_V, "batt_v", IIO_VOLTAGE,
+  AXP20X_BATT_V_H),
+   AXP20X_ADC_CHANNEL(AXP803_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
+  AXP20X_BATT_CHRG_I_H),
+   AXP20X_ADC_CHANNEL(AXP803_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
+  AXP20X_BATT_DISCHRG_I_H),
+};
+
 static int axp20x_adc_raw(struct iio_dev *indio_dev,
  struct iio_chan_spec const *chan, int *val)
 {
@@ -243,6 +278,19 @@ static int axp22x_adc_raw(struct iio_dev *indio_dev,
return IIO_VAL_INT;
 }
 
+static int axp803_adc_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int *val)
+{
+   struct axp20x_adc_iio *info = iio_priv(indio_dev);
+
+   /* All channels on AXP803 are stored on 12 bits. */
+   *val = axp20x_read_variable_width(info->regmap, chan->address, 12);
+   if (*val < 0)
+   return *val;
+
+   return IIO_VAL_INT;
+}
+
 static int axp20x_adc_scale_voltage(int channel, int *val, int *val2)
 {
switch (channel) {
@@ -342,6 +390,31 @@ static int axp22x_adc_scale(struct iio_chan_spec const 
*chan, int *val,
}
 }
 
+static int axp803_adc_scale(struct iio_chan_spec const *chan, int *val,
+   int *val2)
+{
+   switch (chan->type) {
+   case IIO_VOLTAGE:
+   if (chan->channel != AXP803_BATT_V)
+   return -EINVAL;
+
+   *val = 1;
+   *val2 = 10;
+   return IIO_VAL_INT_PLUS_MICRO;
+
+   case IIO_CURRENT:
+   *val = 1;
+   return IIO_VAL_INT;
+
+   case IIO_TEMP:
+   *val = 106;
+   return IIO_VAL_INT;
+
+   default:
+   return -EINVAL;
+   }
+}
+
 static int axp20x_adc_offset_voltage(struct iio_dev *indio_dev, int channel,
 int *val)
 {
@@ -425,6 +498,26 @@ static int axp22x_read_raw(struct iio_dev *indio_dev,
}
 }
 
+static int axp803_read_raw(struct iio_dev *indio_dev,
+  struct iio_chan_spec const *chan, int *val,
+  int *val2, long mask)
+{
+   switch (mask) {
+   case IIO_CHAN_INFO_OFFSET:
+   *val = -2525;
+   return IIO_VAL_INT;
+
+   case IIO_CHAN_INFO_SCALE:
+   return axp803_adc_scale(cha

[RFC PATCH 4/7] power: supply: axp20x-battery: support AXP803

2017-09-20 Thread Icenowy Zheng

The AXP803 PMIC has battery support like other AXP PMICs, but with
different definition of max target charging voltage and constant
charging current.

Add support for AXP803 battery in axp20x-battery driver.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/power/supply/axp20x_battery.c | 88 +++
 1 file changed, 78 insertions(+), 10 deletions(-)

diff --git a/drivers/power/supply/axp20x_battery.c 
b/drivers/power/supply/axp20x_battery.c
index 7494f0f0eadb..c9a9fb320c92 100644
--- a/drivers/power/supply/axp20x_battery.c
+++ b/drivers/power/supply/axp20x_battery.c
@@ -49,6 +49,8 @@
 #define AXP22X_CHRG_CTRL1_TGT_4_22V(1 << 5)
 #define AXP22X_CHRG_CTRL1_TGT_4_24V(3 << 5)
 
+#define AXP803_CHRG_CTRL1_TGT_4_35V(3 << 5)
+
 #define AXP20X_CHRG_CTRL1_TGT_CURR GENMASK(3, 0)
 
 #define AXP20X_V_OFF_MASK  GENMASK(2, 0)
@@ -123,20 +125,71 @@ static int axp22x_battery_get_max_voltage(struct 
axp20x_batt_ps *axp20x_batt,
return 0;
 }
 
+static int axp803_battery_get_max_voltage(struct axp20x_batt_ps *axp20x_batt,
+ int *val)
+{
+   int ret, reg;
+
+   ret = regmap_read(axp20x_batt->regmap, AXP20X_CHRG_CTRL1, );
+   if (ret)
+   return ret;
+
+   switch (reg & AXP20X_CHRG_CTRL1_TGT_VOLT) {
+   case AXP20X_CHRG_CTRL1_TGT_4_1V:
+   *val = 410;
+   break;
+   case AXP20X_CHRG_CTRL1_TGT_4_15V:
+   *val = 415;
+   break;
+   case AXP20X_CHRG_CTRL1_TGT_4_2V:
+   *val = 420;
+   break;
+   case AXP803_CHRG_CTRL1_TGT_4_35V:
+   *val = 435;
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
 static void raw_to_constant_charge_current(struct axp20x_batt_ps *axp, int 
*val)
 {
-   if (axp->axp_id == AXP209_ID)
+   switch (axp->axp_id) {
+   case AXP209_ID:
*val = *val * 10 + 30;
-   else
+   break;
+   case AXP221_ID:
*val = *val * 15 + 30;
+   break;
+   case AXP803_ID:
+   *val = *val * 20 + 20;
+   break;
+   }
 }
 
 static void constant_charge_current_to_raw(struct axp20x_batt_ps *axp, int 
*val)
 {
-   if (axp->axp_id == AXP209_ID)
+   switch (axp->axp_id) {
+   case AXP209_ID:
*val = (*val - 30) / 10;
-   else
+   break;
+   case AXP221_ID:
*val = (*val - 30) / 15;
+   break;
+   case AXP803_ID:
+   *val = (*val - 20) / 20;
+   /*
+* The maximum charge current on AXP803 is 2.8A, and the
+* datasheet says "1110- reserved" in this part.
+* So we return an invalid value -1 in this situation,
+* which will be dealed by the caller of this function,
+*/
+   if (*val > 13)
+   *val = -1;
+   break;
+   }
 }
 
 static int axp20x_get_constant_charge_current(struct axp20x_batt_ps *axp,
@@ -269,9 +322,13 @@ static int axp20x_battery_get_prop(struct power_supply 
*psy,
if (ret)
return ret;
 
-   if (axp20x_batt->axp_id == AXP221_ID &&
-   !(reg & AXP22X_FG_VALID))
-   return -EINVAL;
+   switch (axp20x_batt->axp_id) {
+   case AXP221_ID:
+   case AXP803_ID:
+   if (!(reg & AXP22X_FG_VALID))
+   return -EINVAL;
+   break;
+   };
 
/*
 * Fuel Gauge data takes 7 bits but the stored value seems to be
@@ -281,11 +338,19 @@ static int axp20x_battery_get_prop(struct power_supply 
*psy,
break;
 
case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
-   if (axp20x_batt->axp_id == AXP209_ID)
+   switch (axp20x_batt->axp_id) {
+   case AXP209_ID:
return axp20x_battery_get_max_voltage(axp20x_batt,
  >intval);
-   return axp22x_battery_get_max_voltage(axp20x_batt,
- >intval);
+   case AXP221_ID:
+   return axp22x_battery_get_max_voltage(axp20x_batt,
+ >intval);
+   case AXP803_ID:
+   return axp803_battery_get_max_voltage(axp20x_batt,
+ >intval);
+   default:
+   return -EINVAL;
+   }
 
case POWER_SUP

[RFC PATCH 0/7] AXP803 AC/Battery support

2017-09-20 Thread Icenowy Zheng

The AXP803 PMIC, used by most Allwinner A64 boards, features 3 power inputs:
AC, USB and Battery.

This patchset adds support for the AC and Battery supplies, which is useful
for the boards from Pine64 (Pine64, SoPine w/ baseboard model A, Pinebook).

The USB supply is not yet supported in this patchset because it's not
present on Pine series boards.

In order to enable battery monitoring the ADC for battery is also enabled
for AXs.

In order to enable battery monitoring the ADC for battery is also enabled
for AXP803.

Icenowy Zheng (7):
  dt-bindings: add compatibles for AXP803 Battery/USB power supplies
  iio: adc: axp20x-adc: allow to skip ADC rate setup now
  iio: adc: axp20x-adc: add support for AXP803
  power: supply: axp20x-battery: support AXP803
  mfd: axp20x: add cells for AXP803 ADC/AC Power/Battery
  arm64: allwinner: a64: add power supply nodes in AXP803 DTSI
  arm64: allwinner: a64: enable AC and Battery for Pine64

 .../bindings/power/supply/axp20x_battery.txt   |   1 +
 .../bindings/power/supply/axp20x_usb_power.txt |   1 +
 arch/arm64/boot/dts/allwinner/axp803.dtsi  |  15 +++
 .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts |   8 ++
 drivers/iio/adc/axp20x_adc.c   | 114 -
 drivers/mfd/axp20x.c   |  11 ++
 drivers/power/supply/axp20x_battery.c  |  88 ++--
 7 files changed, 226 insertions(+), 12 deletions(-)

-- 
2.13.5

[RFC PATCH 1/7] dt-bindings: add compatibles for AXP803 Battery/USB power supplies

2017-09-20 Thread Icenowy Zheng

The AXP803 PMIC has different Battery and USB power supplies than the
AXP series PMICs already supported by the kernel, but the AC power
supply is the same as AXP22x (as it can only detect the present/online
state of the AC power supply on both AXP22x and AXP803).

Add compatible strings for the AXP803 Battery/USB power supplies. For AC
power supply the one on AXP803 is compatible with the one on AXP22x.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 Documentation/devicetree/bindings/power/supply/axp20x_battery.txt   | 1 +
 Documentation/devicetree/bindings/power/supply/axp20x_usb_power.txt | 1 +
 2 files changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt 
b/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt
index c24886676a60..091e5471a8c6 100644
--- a/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt
+++ b/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt
@@ -4,6 +4,7 @@ Required Properties:
  - compatible, one of:
"x-powers,axp209-battery-power-supply"
"x-powers,axp221-battery-power-supply"
+   "x-powers,axp803-battery-power-supply"
 
 This node is a subnode of the axp20x/axp22x PMIC.
 
diff --git 
a/Documentation/devicetree/bindings/power/supply/axp20x_usb_power.txt 
b/Documentation/devicetree/bindings/power/supply/axp20x_usb_power.txt
index ba8d35f66cbe..f30e3bf8d23f 100644
--- a/Documentation/devicetree/bindings/power/supply/axp20x_usb_power.txt
+++ b/Documentation/devicetree/bindings/power/supply/axp20x_usb_power.txt
@@ -4,6 +4,7 @@ Required Properties:
 -compatible: One of: "x-powers,axp202-usb-power-supply"
  "x-powers,axp221-usb-power-supply"
  "x-powers,axp223-usb-power-supply"
+ "x-powers,axp803-usb-power-supply"
 
 The AXP223 PMIC shares most of its behaviour with the AXP221 but has slight
 variations such as the former being able to set the VBUS power supply max
-- 
2.13.5

[RFC PATCH 6/7] arm64: allwinner: a64: add power supply nodes in AXP803 DTSI

2017-09-20 Thread Icenowy Zheng

AXP803 PMIC features AC/USB/Battery power supplies.

As we have now the device tree bindings for them, add device tree
nodes for them.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm64/boot/dts/allwinner/axp803.dtsi | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi 
b/arch/arm64/boot/dts/allwinner/axp803.dtsi
index ff8af52743ff..3a8615231b7c 100644
--- a/arch/arm64/boot/dts/allwinner/axp803.dtsi
+++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
@@ -49,6 +49,16 @@
interrupt-controller;
#interrupt-cells = <1>;
 
+   ac_power_supply: ac-power-supply {
+   compatible = "x-powers,axp221-ac-power-supply";
+   status = "disabled";
+   };
+
+   battery_power_supply: battery-power-supply {
+   compatible = "x-powers,axp803-battery-power-supply";
+   status = "disabled";
+   };
+
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>;
@@ -147,4 +157,9 @@
regulator-name = "rtc-ldo";
};
};
+
+   usb_power_supply: usb_power_supply {
+   compatible = "x-powers,axp803-usb-power-supply";
+   status = "disabled";
+   };
 };
-- 
2.13.5

[RFC PATCH 7/7] arm64: allwinner: a64: enable AC and Battery for Pine64

2017-09-20 Thread Icenowy Zheng

The Pine64 boards (including the Plus variant) have a Micro-USB jack
with it's 5V connected to the ACIN of the AXP803 PMIC and a battery
connector connected to the battery pins of the AXP803 PMIC.

Enable AC and Battery power supplies for Pine64, in order to monitor
them in the system.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index d06e34b5d192..955f392af6a2 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -113,6 +113,14 @@
 
 #include "axp803.dtsi"
 
+_power_supply {
+   status = "okay";
+};
+
+_power_supply {
+   status = "okay";
+};
+
 _aldo2 {
regulator-always-on;
regulator-min-microvolt = <180>;
-- 
2.13.5

[RFC PATCH 5/7] mfd: axp20x: add cells for AXP803 ADC/AC Power/Battery

2017-09-20 Thread Icenowy Zheng

As we have now support for AXP803 ADC/Battery, and the AC Power part of
AXP803 is the same as AXP22x, add MFD cells for these drivers.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/mfd/axp20x.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 336de66ca408..91be5fe1c5de 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -850,7 +850,18 @@ static struct mfd_cell axp803_cells[] = {
.num_resources  = ARRAY_SIZE(axp803_pek_resources),
.resources  = axp803_pek_resources,
},
+   {   .name   = "axp803-adc" },
{   .name   = "axp20x-regulator" },
+   {
+   .name   = "axp20x-ac-power-supply",
+   .of_compatible  = "x-powers,axp221-ac-power-supply",
+   .num_resources  = ARRAY_SIZE(axp20x_ac_power_supply_resources),
+   .resources  = axp20x_ac_power_supply_resources,
+   },
+   {
+   .name   = "axp20x-battery-power-supply",
+   .of_compatible  = "x-powers,axp803-battery-power-supply",
+   },
 };
 
 static struct mfd_cell axp806_cells[] = {
-- 
2.13.5

Re: [RFC PATCH 0/7] AXP803 AC/Battery support

2017-09-21 Thread Icenowy Zheng



于 2017年9月21日 GMT+08:00 下午10:46:21, Jonathan Cameron 
<jonathan.came...@huawei.com> 写到:
>On Wed, 20 Sep 2017 23:18:07 +0800
>Icenowy Zheng <icen...@aosc.io> wrote:
>
>> The AXP803 PMIC, used by most Allwinner A64 boards, features 3 power
>inputs:
>> AC, USB and Battery.
>> 
>> This patchset adds support for the AC and Battery supplies, which is
>useful
>> for the boards from Pine64 (Pine64, SoPine w/ baseboard model A,
>Pinebook).
>> 
>> The USB supply is not yet supported in this patchset because it's not
>> present on Pine series boards.
>> 
>> In order to enable battery monitoring the ADC for battery is also
>enabled
>> for AXs.
>> 
>> In order to enable battery monitoring the ADC for battery is also
>enabled
>> for AXP803.
>
>I'll go with the obvious question...
>
>Why an RFC rather than a standard patch submission? I'm not immediately
>seeing what is controversial!

Oh I am just not confident about this patchset,
especially the IIO part.

>
>Jonathan
>
>> 
>> Icenowy Zheng (7):
>>   dt-bindings: add compatibles for AXP803 Battery/USB power supplies
>>   iio: adc: axp20x-adc: allow to skip ADC rate setup now
>>   iio: adc: axp20x-adc: add support for AXP803
>>   power: supply: axp20x-battery: support AXP803
>>   mfd: axp20x: add cells for AXP803 ADC/AC Power/Battery
>>   arm64: allwinner: a64: add power supply nodes in AXP803 DTSI
>>   arm64: allwinner: a64: enable AC and Battery for Pine64
>> 
>>  .../bindings/power/supply/axp20x_battery.txt   |   1 +
>>  .../bindings/power/supply/axp20x_usb_power.txt |   1 +
>>  arch/arm64/boot/dts/allwinner/axp803.dtsi  |  15 +++
>>  .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts |   8 ++
>>  drivers/iio/adc/axp20x_adc.c   | 114
>-
>>  drivers/mfd/axp20x.c   |  11 ++
>>  drivers/power/supply/axp20x_battery.c  |  88
>++--
>>  7 files changed, 226 insertions(+), 12 deletions(-)
>> 
>
>
>___
>linux-arm-kernel mailing list
>linux-arm-ker...@lists.infradead.org
>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device tree binding for H3

2017-09-18 Thread Icenowy Zheng



于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:
>> Allwinner H3 features a thermal sensor like the one in A33, but has
>its
>> register re-arranged, the clock divider moved to CCU (originally the
>> clock divider is in ADC) and added a pair of bus clock and reset.
>> 
>> Update the binding document to cover H3.
>> 
>> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>> Reviewed-by: Chen-Yu Tsai <w...@csie.org>
>> ---
>> Changes in v4:
>> - Add nvmem calibration data (not yet used by the driver)
>> Changes in v3:
>> - Clock name changes.
>> - Example node name changes.
>> - Add interupts (not yet used by the driver).
>> 
>>  .../devicetree/bindings/mfd/sun4i-gpadc.txt| 30
>--
>>  1 file changed, 28 insertions(+), 2 deletions(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
>b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
>> index badff3611a98..6c470d584bf9 100644
>> --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
>> +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
>> @@ -4,12 +4,26 @@ The Allwinner SoCs all have an ADC that can also
>act as a thermal sensor
>>  and sometimes as a touchscreen controller.
>>  
>>  Required properties:
>> -  - compatible: "allwinner,sun8i-a33-ths",
>> +  - compatible: must contain one of the following compatibles:
>> +- "allwinner,sun8i-a33-ths"
>> +- "allwinner,sun8i-h3-ths"
>>- reg: mmio address range of the chip,
>>- #thermal-sensor-cells: shall be 0,
>>- #io-channel-cells: shall be 0,
>>  
>> -Example:
>> +Optional properties:
>> +  - nvmem-cells: A phandle to the calibration data provided by a
>nvmem device.
>> + If unspecified default values shall be used.
>> +  - nvmem-cell-names: Should be "calibration-data"
>
>I'd prefer to have which sensor it applies to here. It wouldn't change
>anything for the H3, but it definitely does for example for the A83t
>that has two sensors, one for each cluster, and one for the GPU, each
>with calibration data.
>
>What about cluster0-calibration?

The calibration data is in fact a 2 word (8 bytes) zone,
which is reserved for 4 sensors on all SoCs, even on H3.
It's half word per sensor.

I prefer to just assume a 2 word cell for every SoC.

>
>> +
>> +Required properties for the following compatibles:
>> +- "allwinner,sun8i-h3-ths"
>> +  - clocks: the bus clock and the input clock of the ADC,
>> +  - clock-names: should be "bus" and "mod",
>> +  - resets: the bus reset of the ADC,
>> +  - interrupts: the sampling interrupt of the ADC,
>
>For resets and interrupts, you should list all of them. If there's
>only one, then there's no point telling which one it is.
>
>
>Thanks,
>Maxime

[PATCH 5/6] ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra

2017-10-07 Thread Icenowy Zheng

From: Icenowy Zheng <icen...@aosc.xyz>

Banana Pi M2 Ultra board features two USB host ports, connected to the
two USB host ports on the SoC.

Add support for them.

Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts 
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 035599d870b9..8c5efe2a9881 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -93,6 +93,14 @@
};
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 
@@ -180,8 +188,22 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pb_pins>;
status = "okay";
 };
+
+ {
+   usb1_vbus-supply = <_vcc5v0>;
+   usb2_vbus-supply = <_vcc5v0>;
+   status = "okay";
+};
-- 
2.13.6

[PATCH 4/6] ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry

2017-10-07 Thread Icenowy Zheng

On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA
and USB) is controlled via a GPIO.

Add regulator node for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts 
b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
index 8a69be2a0842..fe16fc0eb518 100644
--- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -72,6 +72,15 @@
};
};
 
+   reg_vcc5v0: vcc5v0 {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+   enable-active-high;
+   };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
-- 
2.13.6

[PATCH 6/6] ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry

2017-10-07 Thread Icenowy Zheng

Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A
ports, and it's connected to the USB1 port of the SoC.

Enable it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts 
b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
index fe16fc0eb518..45c17c8c5915 100644
--- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -87,6 +87,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 
@@ -98,6 +102,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
 #include "axp22x.dtsi"
 
 _aldo3 {
@@ -171,3 +179,8 @@
pinctrl-0 = <_pb_pins>;
status = "okay";
 };
+
+ {
+   usb1_vbus-supply = <_vcc5v0>;
+   status = "okay";
+};
-- 
2.13.6

[PATCH 2/6] ARM: sun8i: r40: add USB host port nodes for R40

2017-10-07 Thread Icenowy Zheng

From: Icenowy Zheng <icen...@aosc.xyz>

Allwinner R40 SoC features a USB OTG port and two USB HOST ports.

Add support for the host ports in the DTSI file.

The OTG controller still cannot work with existing compatibles, and needs
more investigation. So it's not added yet.

Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
 arch/arm/boot/dts/sun8i-r40.dtsi | 78 
 1 file changed, 78 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index d5a6745409ae..f6c917cbbaac 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -173,6 +173,84 @@
#size-cells = <0>;
};
 
+   usbphy: phy@1c13400 {
+   compatible = "allwinner,sun8i-r40-usb-phy";
+   reg = <0x01c13400 0x14>,
+ <0x01c14800 0x4>,
+ <0x01c19800 0x4>,
+ <0x01c1c800 0x4>;
+   reg-names = "phy_ctrl",
+   "pmu0",
+   "pmu1",
+   "pmu2";
+   clocks = < CLK_USB_PHY0>,
+< CLK_USB_PHY1>,
+< CLK_USB_PHY2>;
+   clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy";
+   resets = < RST_USB_PHY0>,
+< RST_USB_PHY1>,
+< RST_USB_PHY2>;
+   reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+   status = "disabled";
+   #phy-cells = <1>;
+   };
+
+   ehci1: usb@1c19000 {
+   compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
+   reg = <0x01c19000 0x100>;
+   interrupts = ;
+   clocks = < CLK_BUS_OHCI1>,
+< CLK_BUS_EHCI1>,
+< CLK_USB_OHCI1>;
+   resets = < RST_BUS_OHCI1>,
+< RST_BUS_EHCI1>;
+   phys = < 1>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
+   ohci1: usb@1c19400 {
+   compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
+   reg = <0x01c19400 0x100>;
+   interrupts = ;
+   clocks = < CLK_BUS_OHCI1>,
+< CLK_USB_OHCI1>;
+   resets = < RST_BUS_OHCI1>;
+   phys = < 1>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
+   ehci2: usb@1c1c000 {
+   compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
+   reg = <0x01c1c000 0x100>;
+   interrupts = ;
+   clocks = < CLK_BUS_OHCI2>,
+< CLK_BUS_EHCI2>,
+< CLK_USB_OHCI2>;
+   resets = < RST_BUS_OHCI2>,
+< RST_BUS_EHCI2>;
+   phys = < 2>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
+   ohci2: usb@1c1c400 {
+   compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
+   reg = <0x01c1c400 0x100>;
+   interrupts = ;
+   clocks = < CLK_BUS_OHCI2>,
+< CLK_USB_OHCI2>;
+   resets = < RST_BUS_OHCI2>;
+   phys = < 2>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
ccu: clock@1c2 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c2 0x400>;
-- 
2.13.6

[PATCH 3/6] ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra

2017-10-07 Thread Icenowy Zheng

On newer revisions of the Banana Pi M2 Ultra boards, the 5V power output
(used by HDMI, SATA and USB) is controller via a GPIO.

Add the regulator node for it.

Older revisions just have the 5V power output always on, and the GPIO is
reserved on these boards. So it won't affect the older revisions.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts 
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 7b52608cebe6..035599d870b9 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -78,6 +78,15 @@
};
};
 
+   reg_vcc5v0: vcc5v0 {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+   enable-active-high;
+   };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
-- 
2.13.6

[PATCH 0/6] Allwinner R40 USB host support

2017-10-07 Thread Icenowy Zheng

This patchset adds support for the USB host ports on Allwiner R40, and
enable them on Banana Pi M2 Ultra and Berry boards.

The first patch adds R40 support to the USB PHY driver.

The second patch adds USB PHY and EHCI/OHCI nodes to the R40 DTSI.

The thrid and fourth patch adds 5V regulator for the two boards, and
the fifth and sixth patch finally adds USB host ports support.

Icenowy Zheng (6):
  phy: sun4i-usb: add support for R40 USB PHY
  ARM: sun8i: r40: add USB host port nodes for R40
  ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
  ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry
  ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra
  ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry

 .../devicetree/bindings/phy/sun4i-usb-phy.txt  |  1 +
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts  | 31 +
 arch/arm/boot/dts/sun8i-r40.dtsi   | 78 ++
 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts  | 22 ++
 drivers/phy/allwinner/phy-sun4i-usb.c  | 12 
 5 files changed, 144 insertions(+)

-- 
2.13.6

[PATCH 1/6] phy: sun4i-usb: add support for R40 USB PHY

2017-10-07 Thread Icenowy Zheng

Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs.

Add support for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt |  1 +
 drivers/phy/allwinner/phy-sun4i-usb.c   | 12 
 2 files changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt 
b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index cbc7847dbf6c..0f00abd40a50 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -11,6 +11,7 @@ Required properties:
   * allwinner,sun8i-a33-usb-phy
   * allwinner,sun8i-a83t-usb-phy
   * allwinner,sun8i-h3-usb-phy
+  * allwinner,sun8i-r40-usb-phy
   * allwinner,sun8i-v3s-usb-phy
   * allwinner,sun50i-a64-usb-phy
 - reg : a list of offset + length pairs
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c 
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 1161e11fb3cf..9df7a2c9ca75 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -112,6 +112,7 @@ enum sun4i_usb_phy_type {
sun8i_a33_phy,
sun8i_a83t_phy,
sun8i_h3_phy,
+   sun8i_r40_phy,
sun8i_v3s_phy,
sun50i_a64_phy,
 };
@@ -919,6 +920,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.phy0_dual_route = true,
 };
 
+static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
+   .num_phys = 3,
+   .type = sun8i_r40_phy,
+   .disc_thresh = 3,
+   .phyctl_offset = REG_PHYCTL_A33,
+   .dedicated_clocks = true,
+   .enable_pmu_unk1 = true,
+   .phy0_dual_route = true,
+};
+
 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
.num_phys = 1,
.type = sun8i_v3s_phy,
@@ -947,6 +958,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = 
{
{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = _a33_cfg },
{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = _a83t_cfg 
},
{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = _h3_cfg },
+   { .compatible = "allwinner,sun8i-r40-usb-phy", .data = _r40_cfg },
{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = _v3s_cfg },
{ .compatible = "allwinner,sun50i-a64-usb-phy",
  .data = _a64_cfg},
-- 
2.13.6

[PATCH 2/2] ata: ahci_sunxi: add support for R40 SATA controller

2017-10-07 Thread Icenowy Zheng

Allwinner R40 SoC has an AHCI SATA controller like the one in A10/A20,
but with a reset control and two dedicated VDD pins for this controller
(one 1.2v and one 2.5v).

Add support for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/ata/ahci_sunxi.c | 118 +--
 1 file changed, 115 insertions(+), 3 deletions(-)

diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index b26437430163..a650fd6508be 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "ahci.h"
 
 #define DRV_NAME "ahci-sunxi"
@@ -58,6 +59,19 @@ MODULE_PARM_DESC(enable_pmp,
 #define AHCI_P0PHYCR   0x0178
 #define AHCI_P0PHYSR   0x017c
 
+struct ahci_sunxi_quirks {
+   bool has_reset;
+   bool has_vdd1v2;
+   bool has_vdd2v5;
+};
+
+struct ahci_sunxi_data {
+   const struct ahci_sunxi_quirks *quirks;
+   struct reset_control *reset;
+   struct regulator *vdd1v2;
+   struct regulator *vdd2v5;
+};
+
 static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
 {
u32 reg_val;
@@ -179,17 +193,69 @@ static int ahci_sunxi_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
struct ahci_host_priv *hpriv;
+   struct ahci_sunxi_data *data;
int rc;
 
+   data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+   if (!data)
+   return -ENOMEM;
+
+   data->quirks = of_device_get_match_data(dev);
+   if (!data->quirks)
+   return -EINVAL;
+
+   if (data->quirks->has_reset) {
+   data->reset = devm_reset_control_get(dev, NULL);
+   if (IS_ERR(data->reset)) {
+   dev_err(dev, "Failed to get reset\n");
+   return PTR_ERR(data->reset);
+   }
+   }
+
+   if (data->quirks->has_vdd1v2) {
+   data->vdd1v2 = devm_regulator_get(dev, "vdd1v2");
+   if (IS_ERR(data->vdd1v2)) {
+   dev_err(dev, "Failed to get 1.2v VDD regulator\n");
+   return PTR_ERR(data->vdd1v2);
+   }
+   }
+
+   if (data->quirks->has_vdd2v5) {
+   data->vdd2v5 = devm_regulator_get(dev, "vdd2v5");
+   if (IS_ERR(data->vdd2v5)) {
+   dev_err(dev, "Failed to get 2.5v VDD regulator\n");
+   return PTR_ERR(data->vdd2v5);
+   }
+   }
+
hpriv = ahci_platform_get_resources(pdev);
if (IS_ERR(hpriv))
return PTR_ERR(hpriv);
 
+   hpriv->plat_data = data;
hpriv->start_engine = ahci_sunxi_start_engine;
 
+   if (data->quirks->has_vdd1v2) {
+   rc = regulator_enable(data->vdd1v2);
+   if (rc)
+   return rc;
+   }
+
+   if (data->quirks->has_vdd2v5) {
+   rc = regulator_enable(data->vdd2v5);
+   if (rc)
+   goto disable_vdd1v2;
+   }
+
+   if (data->quirks->has_reset) {
+   rc = reset_control_deassert(data->reset);
+   if (rc)
+   goto disable_vdd2v5;
+   }
+
rc = ahci_platform_enable_resources(hpriv);
if (rc)
-   return rc;
+   goto assert_reset;
 
rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
if (rc)
@@ -215,6 +281,35 @@ static int ahci_sunxi_probe(struct platform_device *pdev)
 
 disable_resources:
ahci_platform_disable_resources(hpriv);
+assert_reset:
+   if (data->quirks->has_reset)
+   reset_control_assert(data->reset);
+disable_vdd2v5:
+   if (data->quirks->has_vdd2v5)
+   regulator_disable(data->vdd2v5);
+disable_vdd1v2:
+   if (data->quirks->has_vdd1v2)
+   regulator_disable(data->vdd1v2);
+   return rc;
+}
+
+static int ahci_sunxi_remove(struct platform_device *pdev)
+{
+   struct device *dev = >dev;
+   struct ata_host *host = dev_get_drvdata(dev);
+   struct ahci_host_priv *hpriv = host->private_data;
+   struct ahci_sunxi_data *data = hpriv->plat_data;
+   int rc;
+
+   rc = ata_platform_remove_one(pdev);
+
+   if (data->quirks->has_reset)
+   reset_control_assert(data->reset);
+   if (data->quirks->has_vdd2v5)
+   regulator_disable(data->vdd2v5);
+   if (data->quirks->has_vdd1v2)
+   regulator_disable(data->vdd1v2);
+
return rc;
 }
 
@@ -248,15 +343,32 @@ static int ahci_sunxi_resume(struct device *dev)
 static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
 ahci_sunxi_resume);
 
+static const struct ahci_sunxi_quirks sun4i_a

[PATCH 1/2] dt-bindings: add binding for Allwinner R40 SATA AHCI controller

2017-10-07 Thread Icenowy Zheng

The Allwinner R40 SoC contains a SATA AHCI controller like the one in
A10/A20 SoCs, however a reset control and two power supplies are added
to it.

Add a binding document for it.

As a dedicated binding document is needed now for the A10/A20/R40 AHCI
controller, drop the A10 compatible line from generic platform AHCI
controller binding document.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 .../devicetree/bindings/ata/ahci-platform.txt  |  1 -
 .../bindings/ata/allwinner,sun4i-a10-ahci.txt  | 40 ++
 2 files changed, 40 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt

diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt 
b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index fedc213b5f1a..da6818b2c204 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -9,7 +9,6 @@ PHYs.
 
 Required properties:
 - compatible: compatible string, one of:
-  - "allwinner,sun4i-a10-ahci"
   - "brcm,iproc-ahci"
   - "hisilicon,hisi-ahci"
   - "cavium,octeon-7130-ahci"
diff --git a/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt 
b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt
new file mode 100644
index ..0eea78c14ad3
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt
@@ -0,0 +1,40 @@
+Allwinner A10/A20/R40 SoC SATA AHCI Controller
+
+Required properties:
+- compatible: compatible string, one of:
+  - "allwinner,sun4i-a10-ahci"
+  - "allwinner,sun8i-r40-ahci"
+- interrupts: the SATA IRQ
+- reg   : the register mapping
+- clocks: the clocks needed by SATA controller, usually contains
+ an AHB clock and a mod clock
+
+Optional properties:
+- target-supply : regulator for SATA target power
+
+Required properties for the following compatibles:
+  - "allwinner,sun8i-r40-ahci"
+- resets: the reset control needed by SATA controller
+- vdd1v2-supply : regulator for SATA controller's 1.2V VDD
+- vdd2v5-supply : regulator for SATA controller's 2.5V VDD
+
+
+Examples for A10:
+   ahci: sata@1c18000 {
+   compatible = "allwinner,sun4i-a10-ahci";
+   reg = <0x01c18000 0x1000>;
+   interrupts = <56>;
+   clocks = < 0>, <_gates 25>;
+   target-supply = <_ahci_5v>;
+   };
+
+Examples for R40:
+   ahci: sata@1c18000 {
+   compatible = "allwinner,sun8i-r40-ahci";
+   reg = <0x01c18000 0x1000>;
+   interrupts = ;
+   clocks = < CLK_SATA>, < CLK_BUS_SATA>;
+   resets = < RST_BUS_SATA>;
+   vdd1v2-supply = <_eldo3>;
+   vdd2v5-supply = <_dldo4>;
+   };
-- 
2.13.6

Re: [PATCH review for 4.4 14/24] dmaengine: sun6i: allow build on ARM64 platforms (sun50i)

2017-10-07 Thread Icenowy Zheng



于 2017年10月8日 GMT+08:00 上午6:37:46, "Levin, Alexander (Sasha Levin)" 
<alexander.le...@verizon.com> 写到:
>From: Icenowy Zheng <icen...@aosc.xyz>
>
>[ Upstream commit c429ceb1e18252122ba96b52e689dcf87103c186 ]
>
>As 64-bit Allwinner H5 SoC has the same DMA engine with H3, the DMA
>driver should be allowed to be built for ARM64, in order to make it
>work on H5.

There's no H5 support in 4.4/4.9.

This patch can be ignored.

>
>Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
>Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
>Acked-by: Chen-Yu Tsai <w...@csie.org>
>Signed-off-by: Vinod Koul <vinod.k...@intel.com>
>Signed-off-by: Sasha Levin <alexander.le...@verizon.com>
>---
> drivers/dma/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
>index e6cd1a32025a..27b7b3a9bdd2 100644
>--- a/drivers/dma/Kconfig
>+++ b/drivers/dma/Kconfig
>@@ -158,7 +158,7 @@ config DMA_SUN4I
> 
> config DMA_SUN6I
>   tristate "Allwinner A31 SoCs DMA support"
>-  depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST
>+  depends on MACH_SUN6I || MACH_SUN8I || (ARM64 && ARCH_SUNXI) ||
>COMPILE_TEST
>   depends on RESET_CONTROLLER
>   select DMA_ENGINE
>   select DMA_VIRTUAL_CHANNELS

Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

2017-10-04 Thread Icenowy Zheng



于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo <kv...@codeaurora.org> 写到:
>Icenowy Zheng <icen...@aosc.io> writes:
>
>> Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to
>use
>> an out-of-band interrupt pin instead of SDIO in-band interrupt.
>>
>> Add the device tree binding of this chip, in order to make it
>possible
>> to add this interrupt pin to device trees.
>>
>> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>> Acked-by: Rob Herring <r...@kernel.org>
>> ---
>> Changes in v3:
>> - Renames the node name.
>> - Adds ACK from Rob.
>> Changes in v2:
>> - Removed status property in example.
>> - Added required property reg.
>>
>>  .../bindings/net/wireless/allwinner,xr819.txt  | 38
>++
>>  1 file changed, 38 insertions(+)
>>  create mode 100644
>Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt
>
>Like I asked already last time, AFAICS there is no upstream xr819
>wireless driver in drivers/net/wireless directory. Do we still accept
>bindings like this for out-of-tree drivers?

See esp8089.

There's also no in-tree driver for it.

Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

2017-10-04 Thread Icenowy Zheng



于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote:
>> On 10/4/2017 11:03 AM, Icenowy Zheng wrote:
>> > 
>> > 
>> > 于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo <kv...@codeaurora.org>
>写到:
>> > > Icenowy Zheng <icen...@aosc.io> writes:
>> > > 
>> > > > Allwinner XR819 is a SDIO Wi-Fi chip, which has the
>functionality to
>> > > use
>> > > > an out-of-band interrupt pin instead of SDIO in-band interrupt.
>> > > > 
>> > > > Add the device tree binding of this chip, in order to make it
>> > > possible
>> > > > to add this interrupt pin to device trees.
>> > > > 
>> > > > Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>> > > > Acked-by: Rob Herring <r...@kernel.org>
>> > > > ---
>> > > > Changes in v3:
>> > > > - Renames the node name.
>> > > > - Adds ACK from Rob.
>> > > > Changes in v2:
>> > > > - Removed status property in example.
>> > > > - Added required property reg.
>> > > > 
>> > > >   .../bindings/net/wireless/allwinner,xr819.txt  | 38
>> > > ++
>> > > >   1 file changed, 38 insertions(+)
>> > > >   create mode 100644
>> > >
>Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt
>> > > 
>> > > Like I asked already last time, AFAICS there is no upstream xr819
>> > > wireless driver in drivers/net/wireless directory. Do we still
>accept
>> > > bindings like this for out-of-tree drivers?
>> > 
>> > See esp8089.
>> > 
>> > There's also no in-tree driver for it.
>> 
>> The question is whether we should. The above might be a precedent,
>but it
>> may not necessarily be the way to go. The commit message for esp8089
>seems
>> to hint that there is intent to have an in-tree driver:
>> 
>> """
>> Note that at this point there only is an out of tree driver for
>this
>> hardware, there is no clear timeline / path for merging this.
>Still
>> I believe it would be good to specify the binding for this in
>tree
>> now, so that any future migration to an in tree driver will not
>cause
>> compatiblity issues.
>> 
>> Cc: Icenowy Zheng <icen...@aosc.xyz>
>> Signed-off-by: Hans de Goede <hdego...@redhat.com>
>> Signed-off-by: Rob Herring <r...@kernel.org>
>> """
>> 
>> Regardless the bindings are in principle independent of the kernel
>and just
>> describing hardware. I think there have been discussions to move the
>> bindings to their own repository, but apparently it was decided
>otherwise.
>
>Yeah, I guess especially how it could be merged with the cw1200 driver
>would be very relevant to that commit log.

The cw1200 driver seems to still have some legacy platform
data. Maybe they should also be convert to DT.
(Or maybe compatible = "allwinner,xr819" is enough, as
xr819 is a specified variant of cw1200 family)

>
>Maxime

[PATCH] staging: rtl8723bs: hide "nolinked power save" info when not debugging

2017-10-13 Thread Icenowy Zheng

Currently the rtl8723bs driver will print "nolinked power save enter"
and "nolinked power save leave" per minute if it's not connected to any
network.

These messages are meaningless and annoying to regular users.

Hide them when it's not debugging.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/staging/rtl8723bs/core/rtw_pwrctrl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c 
b/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c
index 820a061506cc..80cf5a8b1557 100644
--- a/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c
+++ b/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c
@@ -34,7 +34,7 @@ void _ips_enter(struct adapter *padapter)
 
if (rf_off == pwrpriv->change_rfpwrstate) {
pwrpriv->bpower_saving = true;
-   DBG_871X_LEVEL(_drv_always_, "nolinked power save enter\n");
+   DBG_871X("nolinked power save enter\n");
 
if (pwrpriv->ips_mode == IPS_LEVEL_2)
pwrpriv->bkeepfwalive = true;
@@ -73,7 +73,7 @@ int _ips_leave(struct adapter *padapter)
if (result == _SUCCESS) {
pwrpriv->rf_pwrstate = rf_on;
}
-   DBG_871X_LEVEL(_drv_always_, "nolinked power save leave\n");
+   DBG_871X("nolinked power save leave\n");
 
DBG_871X("==> ips_leave.LED(0x%08x)...\n", 
rtw_read32(padapter, 0x4c));
pwrpriv->bips_processing = false;
-- 
2.13.6

[PATCH] ARM: sun8i: r40: add watchdog device node

2017-10-13 Thread Icenowy Zheng

The R40 SoC has a watchdog like the one on A20, in the timer memory zone
(which is also the same on A20).

Add the device tree node for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-r40.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index d5a6745409ae..ddcb3fff4cd4 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -229,6 +229,11 @@
};
};
 
+   wdt: watchdog@1c20c90 {
+   compatible = "allwinner,sun4i-a10-wdt";
+   reg = <0x01c20c90 0x10>;
+   };
+
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
-- 
2.13.6

[PATCH 1/2] clk: sunxi-ng: r40: rewrite init code to a platform driver

2017-10-06 Thread Icenowy Zheng

As we need to register a regmap on the R40 CCU, there needs to be a
device structure bound to the CCU device node.

Rewrite the R40 CCU driver initial code to make it a proper platform
driver, thus we will have a platform device bound to it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 37 ++--
 1 file changed, 27 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 933f2e68f42a..bb94e2c44e86 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -12,6 +12,7 @@
  */
 
 #include 
+#include 
 #include 
 
 #include "ccu_common.h"
@@ -1250,17 +1251,17 @@ static struct ccu_mux_nb sun8i_r40_cpu_nb = {
.bypass_index   = 1, /* index of 24 MHz oscillator */
 };
 
-static void __init sun8i_r40_ccu_setup(struct device_node *node)
+static int sun8i_r40_ccu_probe(struct platform_device *pdev)
 {
+   struct resource *res;
void __iomem *reg;
u32 val;
+   int ret;
 
-   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
-   if (IS_ERR(reg)) {
-   pr_err("%s: Could not map the clock registers\n",
-  of_node_full_name(node));
-   return;
-   }
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   reg = devm_ioremap_resource(>dev, res);
+   if (IS_ERR(reg))
+   return PTR_ERR(reg);
 
/* Force the PLL-Audio-1x divider to 4 */
val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
@@ -1277,7 +1278,9 @@ static void __init sun8i_r40_ccu_setup(struct device_node 
*node)
val &= ~GENMASK(25, 20);
writel(val, reg + SUN8I_R40_USB_CLK_REG);
 
-   sunxi_ccu_probe(node, reg, _r40_ccu_desc);
+   ret = sunxi_ccu_probe(pdev->dev.of_node, reg, _r40_ccu_desc);
+   if (ret)
+   return ret;
 
/* Gate then ungate PLL CPU after any rate changes */
ccu_pll_notifier_register(_r40_pll_cpu_nb);
@@ -1285,6 +1288,20 @@ static void __init sun8i_r40_ccu_setup(struct 
device_node *node)
/* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
  _r40_cpu_nb);
+
+   return 0;
 }
-CLK_OF_DECLARE(sun8i_r40_ccu, "allwinner,sun8i-r40-ccu",
-  sun8i_r40_ccu_setup);
+
+static const struct of_device_id sun8i_r40_ccu_ids[] = {
+   { .compatible = "allwinner,sun8i-r40-ccu" },
+   { }
+};
+
+static struct platform_driver sun8i_r40_ccu_driver = {
+   .probe  = sun8i_r40_ccu_probe,
+   .driver = {
+   .name   = "sun8i-r40-ccu",
+   .of_match_table = sun8i_r40_ccu_ids,
+   },
+};
+builtin_platform_driver(sun8i_r40_ccu_driver);
-- 
2.13.6

[PATCH 2/2] clk: sunxi-ng: r40: export a regmap to access the GMAC register

2017-10-06 Thread Icenowy Zheng

There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in
the syscon part, in the CCU of R40 SoC.

Export a regmap of the CCU.

Read access is not restricted to all registers, but only the GMAC
register is allowed to be written.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 32 
 1 file changed, 32 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index bb94e2c44e86..df752bf77ff1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "ccu_common.h"
 #include "ccu_reset.h"
@@ -1251,9 +1252,35 @@ static struct ccu_mux_nb sun8i_r40_cpu_nb = {
.bypass_index   = 1, /* index of 24 MHz oscillator */
 };
 
+/*
+ * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
+ * GMAC configuration register.
+ * Only this register is allowed to be written, in order to
+ * prevent overriding critical clock configuration.
+ */
+
+#define SUN8I_R40_GMAC_CFG_REG 0x164
+static bool sun8i_r40_ccu_regmap_writeable_reg(struct device *dev,
+  unsigned int reg)
+{
+   if (reg == SUN8I_R40_GMAC_CFG_REG)
+   return true;
+   return false;
+}
+
+static struct regmap_config sun8i_r40_ccu_regmap_config = {
+   .reg_bits   = 32,
+   .val_bits   = 32,
+   .reg_stride = 4,
+   .max_register   = 0x320, /* PLL_LOCK_CTRL_REG */
+
+   .writeable_reg  = sun8i_r40_ccu_regmap_writeable_reg,
+};
+
 static int sun8i_r40_ccu_probe(struct platform_device *pdev)
 {
struct resource *res;
+   struct regmap *regmap;
void __iomem *reg;
u32 val;
int ret;
@@ -1278,6 +1305,11 @@ static int sun8i_r40_ccu_probe(struct platform_device 
*pdev)
val &= ~GENMASK(25, 20);
writel(val, reg + SUN8I_R40_USB_CLK_REG);
 
+   regmap = devm_regmap_init_mmio(>dev, reg,
+  _r40_ccu_regmap_config);
+   if (IS_ERR(regmap))
+   return PTR_ERR(regmap);
+
ret = sunxi_ccu_probe(pdev->dev.of_node, reg, _r40_ccu_desc);
if (ret)
return ret;
-- 
2.13.6

[PATCH 0/2] Add a regmap to Allwinner R40 CCU to export GMAC register

2017-10-06 Thread Icenowy Zheng

In the CCU of the Allwinner R40 SoC, there's a GMAC configuration register,
which is intended to be accessed by the dwmac-sun8i driver. On SoCs already
supported by the driver the register is placed in the syscon rather than
the CCU.

As CCU is a critical part of the SoC, so write to it should be strictly
limited. A regmap with restricted write permission is created by the R40
CCU driver, and can be get with dev_get_regmap. In order to tie the regmap
to the CCU device, the R40 CCU is now a platform driver, so a platform
device is created for it (and then tied with the regmap).

The first patch does the conversion of the driver to a platform driver,
and the second patch adds the regmap.

Icenowy Zheng (2):
  clk: sunxi-ng: r40: rewrite init code to a platform driver
  clk: sunxi-ng: r40: export a regmap to access the GMAC register

 drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 69 ++--
 1 file changed, 59 insertions(+), 10 deletions(-)

-- 
2.13.6

[PATCH v3 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

2017-10-06 Thread Icenowy Zheng

From: Chen-Yu Tsai <w...@csie.org>

The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
form factor and position of various connectors, leds and buttons is
similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
as the latest Banana Pi M64.

It features:

  - X-Powers AXP221s PMIC connected to i2c0
  - 2 GB DDR3 DRAM
  - 8 GB eMMC
  - micro SD card slot
  - DC power jack
  - HDMI output
  - MIPI DSI connector
  - 2x USB 2.0 hosts
  - 1x USB 2.0 OTG
  - gigabit ethernet with Realtek RTL8211E transceiver
  - WiFi/Bluetooth with AP6212 chip, with external antenna connector
  - SATA and power connectors for native SATA support
  - camera sensor connector
  - consumer IR receiver
  - audio out headphone jack
  - onboard microphone
  - red, green, and blue LEDs
  - debug UART pins
  - Li-Po battery connector
  - Raspberry Pi B+ compatible GPIO header
  - power, reset, and boot control buttons

This patch adds a dts file that enables UART, MMC and PMIC support.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Added 3.3V vqmmc regulator for mmc2 (eMMC).
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.

 arch/arm/boot/dts/Makefile|   1 +
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 178 ++
 2 files changed, 179 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9cf688d404b8..93b1e63a52af 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -939,6 +939,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-parrot.dtb \
+   sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts 
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
new file mode 100644
index ..7b52608cebe6
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <w...@csie.org>
+ * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+
+#include 
+
+/ {
+   model = "Banana Pi BPI-M2-Ultra";
+   compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   pwr-led {
+   label = "bananapi:red:pwr";
+   gpios = < 7 20 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+

[PATCH v3 0/3] Basical device tree parts for Allwinner R40 SoC

2017-10-06 Thread Icenowy Zheng

This patchset adds basical device tree parts for the Allwinner R40 SoC
and two boards feature this SoC -- Banana Pi M2 Ultra and Berry (The
BPi M2 Berry board uses V40 SoC, which is just a renamed R40).

Chen-Yu Tsai (2):
  ARM: dts: sun8i: Add basic dtsi file for Allwinner R40
  ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

Icenowy Zheng (1):
  ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

 arch/arm/boot/dts/Makefile|   4 +-
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 178 ++
 arch/arm/boot/dts/sun8i-r40.dtsi  | 396 ++
 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 164 +
 4 files changed, 741 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
 create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
 create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts

-- 
2.13.6

[PATCH v3 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-10-06 Thread Icenowy Zheng

From: Chen-Yu Tsai <w...@csie.org>

The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Dropped all max-frequency properties in MMC nodes.
Changes in v2:
- Change the MMC frequencies to conservative verified values.
- Add fallback R40 compatible for MMC.

 arch/arm/boot/dts/sun8i-r40.dtsi | 396 +++
 1 file changed, 396 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
new file mode 100644
index ..d5a6745409ae
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,396 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai <w...@csie.org>
+ * Copyright 2017 Icenowy Zheng <icen...@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   osc24M: osc24M {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   clock-output-names = "osc24M";
+   };
+
+   osc32k: osc32k {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "osc32k";
+   };
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <1>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <2>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+

[PATCH v3 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

2017-10-06 Thread Icenowy Zheng

The Banana Pi M2 Ultra is an SBC based on the Allwinner V40 SoC (same as
the R40 SoC). The form factor is similar to the Raspberry Pi series.

It features:

- X-Powers AXP221s PMIC connected to i2c0
- 1GiB DDR3 DRAM
- microSD slot
- MicroUSB Type-B port for power and connected to usb0
- HDMI output
- MIPI DSI connector
- 4 USB Type-A ports (connected to the usb1 controller via a hub)
- gigabit ethernet with Realtek RTL8211E transceiver
- WiFi/Bluetooth with AP6212 module, with external antenna connector
- SATA and power connectors for native SATA support
- camera sensor connector
- audio out headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons

This patch adds a dts file that enables UART, MMC and PMIC support.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.

 arch/arm/boot/dts/Makefile|   3 +-
 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 164 ++
 2 files changed, 166 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 93b1e63a52af..da3f87b35059 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -941,7 +941,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v3s-licheepi-zero.dtb \
-   sun8i-v3s-licheepi-zero-dock.dtb
+   sun8i-v3s-licheepi-zero-dock.dtb \
+   sun8i-v40-bananapi-m2-berry.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts 
b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
new file mode 100644
index ..8a69be2a0842
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+
+#include 
+
+/ {
+   model = "Banana Pi M2 Berry";
+   compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   pwr-led {
+   label = "bananapi:red:pwr";
+   gpios = < 7 20 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   user-led {
+   label = "bananapi:green:user";
+   gpios = < 7 21 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   wifi_pwrseq: wifi_pwrseq {
+   compatible = "mmc-pwrseq-simple";
+

[PATCH 2/2] clk: sunxi-ng: add support for Allwinner A64 DE2 CCU

2017-10-14 Thread Icenowy Zheng

Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.

Add support for it.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32 
 1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 5cdaf52669e4..2e3a3ca087f7 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "ccu_common.h"
 #include "ccu_div.h"
@@ -148,6 +149,11 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc 
= {
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
 };
 
+static bool sunxi_de2_clk_has_sram(const struct device_node *node)
+{
+   return of_device_is_compatible(node, "allwinner,sun50i-a64-de2-clk");
+}
+
 static int sunxi_de2_clk_probe(struct platform_device *pdev)
 {
struct resource *res;
@@ -191,11 +197,20 @@ static int sunxi_de2_clk_probe(struct platform_device 
*pdev)
return ret;
}
 
+   if (sunxi_de2_clk_has_sram(pdev->dev.of_node)) {
+   ret = sunxi_sram_claim(>dev);
+   if (ret) {
+   dev_err(>dev,
+   "Error couldn't map SRAM to device\n");
+   return ret;
+   }
+   }
+
/* The clocks need to be enabled for us to access the registers */
ret = clk_prepare_enable(bus_clk);
if (ret) {
dev_err(>dev, "Couldn't enable bus clk: %d\n", ret);
-   return ret;
+   goto err_release_sram;
}
 
ret = clk_prepare_enable(mod_clk);
@@ -224,6 +239,10 @@ static int sunxi_de2_clk_probe(struct platform_device 
*pdev)
clk_disable_unprepare(mod_clk);
 err_disable_bus_clk:
clk_disable_unprepare(bus_clk);
+err_release_sram:
+   if (sunxi_de2_clk_has_sram(pdev->dev.of_node))
+   sunxi_sram_release(>dev);
+
return ret;
 }
 
@@ -237,16 +256,13 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
.data = _v3s_de2_clk_desc,
},
{
+   .compatible = "allwinner,sun50i-a64-de2-clk",
+   .data = _a64_de2_clk_desc,
+   },
+   {
.compatible = "allwinner,sun50i-h5-de2-clk",
.data = _a64_de2_clk_desc,
},
-   /*
-* The Allwinner A64 SoC needs some bit to be poke in syscon to make
-* DE2 really working.
-* So there's currently no A64 compatible here.
-* H5 shares the same reset line with A64, so here H5 is using the
-* clock description of A64.
-*/
{ }
 };
 
-- 
2.13.6

[PATCH 1/2] dt-bindings: add binding for A64 DE2 CCU with SRAM section

2017-10-14 Thread Icenowy Zheng

A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed.

Add binding for this.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt 
b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index 631d27cd89d6..8b1f86080d3d 100644
--- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -5,6 +5,7 @@ Required properties :
 - compatible: must contain one of the following compatibles:
- "allwinner,sun8i-a83t-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
+   - "allwinner,sun50i-a64-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
 
 - reg: Must contain the registers base address and length
@@ -17,6 +18,10 @@ Required properties :
 - #clock-cells : must contain 1
 - #reset-cells : must contain 1
 
+Additional required properties for "allwinner,sun50i-a64-de2-clk" :
+- allwinner,sram: See Documentation/devicetree/bindings/sram/sunxi-sram.txt,
+ should be the SRAM C section on A64 SoC.
+
 Example:
 de2_clocks: clock@100 {
compatible = "allwinner,sun8i-a83t-de2-clk";
-- 
2.13.6

[PATCH 0/4] Add SimpleFB support for Allwinner H3 SoC

2017-09-11 Thread Icenowy Zheng

This patchset adds devicetree-side support of SimpleFB on Allwinner H3
SoC.

The DE2 CCU is initialized and used by the SimpleFB node, in order to
furtherly coexist with the DRM code.

The first patch adds pipelines for DE2 displays in simplefb-sunxi
device tree binding.

The second patch adds DE2 CCU device node for H3 SoC, and the skeleton
of the node enters the H3/H5 common DTSI; the H5 support is splited
into the third patch, as they will enter different tree.

The fourth patch finally adds simplefb nodes, using the
pipeline strings introduced in the first patch.

Icenowy Zheng (4):
  dt-bindings: simplefb-sunxi: add pipelines for DE2
  ARM: sun8i: h3/h5: add DE2 CCU device node for H3
  arm64: allwinner: h5: add compatible string for DE2 CCU
  ARM: sunxi: h3/h5: add simplefb nodes

 .../bindings/display/simple-framebuffer-sunxi.txt  |  4 ++
 arch/arm/boot/dts/sun8i-h3.dtsi|  4 ++
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 43 ++
 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi   |  4 ++
 4 files changed, 55 insertions(+)

-- 
2.13.5

[PATCH 4/4] ARM: sunxi: h3/h5: add simplefb nodes

2017-09-11 Thread Icenowy Zheng

The H3/H5 SoCs have a HDMI output and a TV Composite output.

Add simplefb nodes for these outputs.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 +
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 76a4cbc99bdb..13850752dfda 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -53,6 +53,35 @@
#address-cells = <1>;
#size-cells = <1>;
 
+   chosen {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   framebuffer-hdmi {
+   compatible = "allwinner,simple-framebuffer",
+"simple-framebuffer";
+   allwinner,pipeline = "mixer0-lcd0-hdmi";
+   clocks = <_clocks CLK_BUS_MIXER0>,
+< CLK_BUS_TCON0>, < CLK_BUS_HDMI>,
+<_clocks CLK_MIXER0>,
+< CLK_TCON0>, < CLK_HDMI>,
+< CLK_HDMI_DDC>;
+   status = "disabled";
+   };
+
+   framebuffer-tve {
+   compatible = "allwinner,simple-framebuffer",
+"simple-framebuffer";
+   allwinner,pipeline = "mixer1-lcd1-tve";
+   clocks = <_clocks CLK_BUS_MIXER1>,
+< CLK_BUS_TCON1>, < CLK_BUS_TVE>,
+<_clocks CLK_MIXER1>,
+< CLK_TVE>;
+   status = "disabled";
+   };
+   };
+
clocks {
#address-cells = <1>;
#size-cells = <1>;
-- 
2.13.5

[PATCH 3/4] arm64: allwinner: h5: add compatible string for DE2 CCU

2017-09-11 Thread Icenowy Zheng

The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than
the one on H3, so the compatible string is not set in the common DTSI
file.

Add the compatible string of H5 DE2 CCU in H5 DTSI file.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index d9a720bff05d..e237c05cfdb4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -98,6 +98,10 @@
compatible = "allwinner,sun50i-h5-ccu";
 };
 
+_clocks {
+   compatible = "allwinner,sun50i-h5-de2-clk";
+};
+
  {
compatible = "allwinner,sun50i-h5-mmc",
 "allwinner,sun50i-a64-mmc";
-- 
2.13.5

[PATCH 2/4] ARM: sun8i: h3/h5: add DE2 CCU device node for H3

2017-09-11 Thread Icenowy Zheng

The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.

Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.

The compatible string of H5 DE2 CCU will be added in a separated patch.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun8i-h3.dtsi|  4 
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 14 ++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..a8a1db79f362 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -85,6 +85,10 @@
compatible = "allwinner,sun8i-h3-ccu";
 };
 
+_clocks {
+   compatible = "allwinner,sun8i-a83t-de2-clk";
+};
+
  {
compatible = "allwinner,sun7i-a20-mmc";
clocks = < CLK_BUS_MMC0>,
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 11240a8313c2..76a4cbc99bdb 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -40,9 +40,11 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -85,6 +87,18 @@
#size-cells = <1>;
ranges;
 
+   display_clocks: clock@100 {
+   /* compatible is in per SoC .dtsi file */
+   reg = <0x0100 0x10>;
+   clocks = < CLK_DE>,
+< CLK_BUS_DE>;
+   clock-names = "mod",
+ "bus";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-h3-system-controller",
"syscon";
-- 
2.13.5

[PATCH 1/4] dt-bindings: simplefb-sunxi: add pipelines for DE2

2017-09-11 Thread Icenowy Zheng

As we're going to add simplefb support for Allwinner SoCs with DE2, add
suitable pipeline strings in the device tree binding.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 .../devicetree/bindings/display/simple-framebuffer-sunxi.txt  | 4 
 1 file changed, 4 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt 
b/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt
index a9168ae6946c..d693b8dc9a62 100644
--- a/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt
+++ b/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt
@@ -15,6 +15,10 @@ Required properties:
   "de_be1-lcd1"
   "de_be0-lcd0-hdmi"
   "de_be1-lcd1-hdmi"
+  "mixer0-lcd0"
+  "mixer0-lcd0-hdmi"
+  "mixer1-lcd1-hdmi"
+  "mixer1-lcd1-tve"
 
 Example:
 
-- 
2.13.5

[PATCH] ARM: sun7i: a20: enable ac/battery power supplies for Lamobo R1 board

2017-09-13 Thread Icenowy Zheng

The Lamobo R1 board connected the ACIN of the AXP209 PMIC to a MicroUSB
port, and the battery input is connected to a generic connector.

Enable these two power supplies in the device tree.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts 
b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
index 004b6ddac813..6ab2a6649eb1 100644
--- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
@@ -241,6 +241,14 @@
 
 #include "axp209.dtsi"
 
+_power_supply {
+   status = "okay";
+};
+
+_power_supply {
+   status = "okay";
+};
+
 _ahci_5v {
gpio = < 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
status = "okay";
-- 
2.13.5

[PATCH 2/2] clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock

2017-09-10 Thread Icenowy Zheng

The GPU clock on H3 has only one parent, PLL-GPU, and the PLL is only
the parent of the GPU clock. The GPU clock can be tweaked by tweaking
the PLL-GPU clock.

Add CLK_SET_RATE_PARENT flag to allow tweaking the GPU clock via
tweaking PLL-CPU.

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 7a81c4885836..543c46d0e045 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -484,7 +484,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", 
mbus_parents,
 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
 
 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
-0x1a0, 0, 3, BIT(31), 0);
+0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
 
 static struct ccu_common *sun8i_h3_ccu_clks[] = {
_cpux_clk.common,
-- 
2.13.5

[PATCH 1/2] clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs

2017-09-10 Thread Icenowy Zheng

The PLLs on H3 have a lock bit, which will only be set to 1 when the PLL
is really working.

Add CLK_SET_RATE_UNGATE to the PLLs, otherwise it will timeout when
trying to set PLL clock frequency without enabling it.

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 1729ff6a5aae..7a81c4885836 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -37,7 +37,7 @@ static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
 16, 2, /* P */
 BIT(31),   /* gate */
 BIT(28),   /* lock */
-0);
+CLK_SET_RATE_UNGATE);
 
 /*
  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
@@ -55,7 +55,7 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, 
"pll-audio-base",
   0, 5,/* M */
   BIT(31), /* gate */
   BIT(28), /* lock */
-  0);
+  CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
"osc24M", 0x0010,
@@ -67,7 +67,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, 
"pll-video",
29700,  /* frac rate 1 */
BIT(31),/* gate */
BIT(28),/* lock */
-   0);
+   CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x0018,
@@ -79,7 +79,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
29700,  /* frac rate 1 */
BIT(31),/* gate */
BIT(28),/* lock */
-   0);
+   CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
"osc24M", 0x020,
@@ -88,7 +88,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
0, 2,   /* M */
BIT(31),/* gate */
BIT(28),/* lock */
-   0);
+   CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
   "osc24M", 0x028,
@@ -97,7 +97,7 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, 
"pll-periph0",
   BIT(31), /* gate */
   BIT(28), /* lock */
   2,   /* post-div */
-  0);
+  CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x0038,
@@ -109,7 +109,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, 
"pll-gpu",
29700,  /* frac rate 1 */
BIT(31),/* gate */
BIT(28),/* lock */
-   0);
+   CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
   "osc24M", 0x044,
@@ -118,7 +118,7 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, 
"pll-periph1",
   BIT(31), /* gate */
   BIT(28), /* lock */
   2,   /* post-div */
-  0);
+  CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
"osc24M", 0x0048,
@@ -130,7 +130,7 @@ static SUNXI_CCU_NM_WITH_FRAC_G

[PATCH 0/2] clk: sunxi-ng: Add several flags to H3 CCU

2017-09-10 Thread Icenowy Zheng

The H3 CCU is the earliest driver that uses sunxi-ng clk framework, and
some problems show when doing further development.

This patchset fixes some issues by add several clock flags.

The first patch solves the problem that setting some PLL before ungating
them will trigger timeout for waiting for lock by adds CLK_SET_RATE_UNGATE
flag.

The second patch solves the problem that H3 GPU clock is not really tweaked
by add CLK_SET_RATE_PARENT flag to it.

Icenowy Zheng (2):
  clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs
  clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock

 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

-- 
2.13.5

Re: [linux-sunxi] Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC

2017-09-25 Thread Icenowy Zheng



于 2017年9月25日 GMT+08:00 下午6:27:44, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Mon, Sep 25, 2017 at 10:12:09AM +, Icenowy Zheng wrote:
>> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard
><maxime.rip...@free-electrons.com> 写到:
>> >Hi,
>> >
>> >On Sat, Sep 23, 2017 at 12:15:28AM +, Icenowy Zheng wrote:
>> >> This patchset imports simple DVFS support for Allwinner A64 SoC.
>> >> 
>> >> As the thermal sensor driver is not yet implemented and some
>boards
>> >> have still no AXP PMIC support, now only two OPPs are present --
>> >> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.
>> >> 
>> >> PATCH 1 is a fix to the CCU driver of A64, and the remaining
>patches
>> >> set up the device tree bits of the DVFS on Pine64.
>> >
>> >How has this been tested?
>> >
>> >What tasks did you run, with what governor, etc...
>> 
>> I only tested manual frequency switching between 648MHz and
>> 816MHz, and tested the PLL stuck issue by change the OPPs to
>> some random value.
>
>Ideally, we should test that it's actually reliable. Poorly chosen
>OPPs might lead to corrupt data that you might not get before a while.

These are OPPs from the official sys_config.fex .

>
>Please test using:
>https://linux-sunxi.org/Hardware_Reliability_Tests#Reliability_of_cpufreq_voltage.2Ffrequency_settings
>
>And post the report.
>
>Maxime

Re: [PATCH v2 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

2017-09-28 Thread Icenowy Zheng



于 2017年9月28日 GMT+08:00 下午11:12:25, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>On Thu, Sep 28, 2017 at 09:25:42AM +, Icenowy Zheng wrote:
>> + {
>> +vmmc-supply = <_dcdc1>;
>> +bus-width = <8>;
>> +non-removable;
>> +status = "okay";
>> +};
>
>I guess it's an emmc, it doesn't have a vqmmmc regulator?

vqmmc is also 3v3.

>
>Looks good otherwise, thanks!
>Maxime

Re: [PATCH v2 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-09-29 Thread Icenowy Zheng



于 2017年9月28日 GMT+08:00 下午11:11:03, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>Hi,
>
>On Thu, Sep 28, 2017 at 09:25:41AM +, Icenowy Zheng wrote:
>> +/*
>> + * The max-frequency properties in all MMC controller nodes
>> + * are conservative values proven to work on Banana Pi M2
>> + * Ultra (the first community available R40 board).
>> + * As the board doesn't wire MMC3 out, the property is not
>> + * set in MMC3.
>> + * TODO: measure the accurate max frequency of the controllers.
>> + */
>> +mmc0: mmc@1c0f000 {
>> +compatible = "allwinner,sun8i-r40-mmc",
>> + "allwinner,sun50i-a64-mmc";
>> +reg = <0x01c0f000 0x1000>;
>> +clocks = < CLK_BUS_MMC0>, < CLK_MMC0>;
>> +clock-names = "ahb", "mmc";
>> +resets = < RST_BUS_MMC0>;
>> +reset-names = "ahb";
>> +pinctrl-0 = <_pins>;
>> +pinctrl-names = "default";
>> +interrupts = ;
>> +max-frequency = <2500>;
>> +status = "disabled";
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +};
>
>Sorry if it wasn't really clear, but my point was more than you should
>just drop the max-frequency property

Then set it in the boards' DTS?

>
>Maxime

[PATCH v2 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

2017-09-28 Thread Icenowy Zheng

From: Chen-Yu Tsai <w...@csie.org>

The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
form factor and position of various connectors, leds and buttons is
similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
as the latest Banana Pi M64.

It features:

  - X-Powers AXP221s PMIC connected to i2c0
  - 2 GB DDR3 DRAM
  - 8 GB eMMC
  - micro SD card slot
  - DC power jack
  - HDMI output
  - MIPI DSI connector
  - 2x USB 2.0 hosts
  - 1x USB 2.0 OTG
  - gigabit ethernet with Realtek RTL8211E transceiver
  - WiFi/Bluetooth with AP6212 chip, with external antenna connector
  - SATA and power connectors for native SATA support
  - camera sensor connector
  - consumer IR receiver
  - audio out headphone jack
  - onboard microphone
  - red, green, and blue LEDs
  - debug UART pins
  - Li-Po battery connector
  - Raspberry Pi B+ compatible GPIO header
  - power, reset, and boot control buttons

This patch adds a dts file that enables UART, MMC and PMIC support.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.

 arch/arm/boot/dts/Makefile|   1 +
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 177 ++
 2 files changed, 178 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9cf688d404b8..93b1e63a52af 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -939,6 +939,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-parrot.dtb \
+   sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts 
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
new file mode 100644
index ..148427517819
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <w...@csie.org>
+ * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+
+#include 
+
+/ {
+   model = "Banana Pi BPI-M2-Ultra";
+   compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   pwr-led {
+   label = "bananapi:red:pwr";
+   gpios = < 7 20 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   user-led-green {
+

[PATCH v2 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

2017-09-28 Thread Icenowy Zheng

The Banana Pi M2 Ultra is an SBC based on the Allwinner V40 SoC (same as
the R40 SoC). The form factor is similar to the Raspberry Pi series.

It features:

- X-Powers AXP221s PMIC connected to i2c0
- 1GiB DDR3 DRAM
- microSD slot
- MicroUSB Type-B port for power and connected to usb0
- HDMI output
- MIPI DSI connector
- 4 USB Type-A ports (connected to the usb1 controller via a hub)
- gigabit ethernet with Realtek RTL8211E transceiver
- WiFi/Bluetooth with AP6212 module, with external antenna connector
- SATA and power connectors for native SATA support
- camera sensor connector
- audio out headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons

This patch adds a dts file that enables UART, MMC and PMIC support.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.

 arch/arm/boot/dts/Makefile|   3 +-
 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 164 ++
 2 files changed, 166 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 93b1e63a52af..da3f87b35059 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -941,7 +941,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v3s-licheepi-zero.dtb \
-   sun8i-v3s-licheepi-zero-dock.dtb
+   sun8i-v3s-licheepi-zero-dock.dtb \
+   sun8i-v40-bananapi-m2-berry.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts 
b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
new file mode 100644
index ..8a69be2a0842
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+
+#include 
+
+/ {
+   model = "Banana Pi M2 Berry";
+   compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   pwr-led {
+   label = "bananapi:red:pwr";
+   gpios = < 7 20 GPIO_ACTIVE_HIGH>;
+   default-state = "on";
+   };
+
+   user-led {
+   label = "bananapi:green:user";
+   gpios = < 7 21 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   wifi_pwrseq: wifi_pwrseq {
+   compatible = "mmc-pwrseq-simple";
+

[PATCH v2 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-09-28 Thread Icenowy Zheng

From: Chen-Yu Tsai <w...@csie.org>

The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.

Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Change the MMC frequencies to conservative verified values.
- Add fallback R40 compatible for MMC.

 arch/arm/boot/dts/sun8i-r40.dtsi | 407 +++
 1 file changed, 407 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
new file mode 100644
index ..5d365b72b893
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,407 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai <w...@csie.org>
+ * Copyright 2017 Icenowy Zheng <icen...@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   osc24M: osc24M {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   clock-output-names = "osc24M";
+   };
+
+   osc32k: osc32k {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "osc32k";
+   };
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <1>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <2>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <3>;
+   };
+   };
+
+   soc {
+

[PATCH v2 0/3] Basical device tree parts for Allwinner R40 SoC

2017-09-28 Thread Icenowy Zheng

This patchset adds basical device tree parts for the Allwinner R40 SoC
and two boards feature this SoC -- Banana Pi M2 Ultra and Berry (The
BPi M2 Berry board uses V40 SoC, which is just a renamed R40).

Chen-Yu Tsai (2):
  ARM: dts: sun8i: Add basic dtsi file for Allwinner R40
  ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

Icenowy Zheng (1):
  ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

 arch/arm/boot/dts/Makefile|   4 +-
 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 177 ++
 arch/arm/boot/dts/sun8i-r40.dtsi  | 407 ++
 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 164 +
 4 files changed, 751 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
 create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
 create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts

-- 
2.13.5

[PATCH v3 0/2] Allwinner XR819 SDIO Wi-Fi DT binding and OPi Zero XR819 IRQ

2017-10-03 Thread Icenowy Zheng

The Allwinner XR819 SDIO Wi-Fi chip supports an out-of-band interrupt line,
and the in-band interrupt is also supported.

However the current out-of-tree driver uses the out-of-band interrupt by
default.

This patchset adds the device tree binding for the chip as well as the
out-of-band interrupt, then adds the interrupt to the device tree of
Orange Pi Zero.

Icenowy Zheng (1):
  dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

Sergey Matyukevich (1):
  ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero

 .../bindings/net/wireless/allwinner,xr819.txt  | 38 ++
 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts  |  3 ++
 2 files changed, 41 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt

-- 
2.13.5

[PATCH v3 2/2] ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero

2017-10-03 Thread Icenowy Zheng

From: Sergey Matyukevich <geoma...@gmail.com>

The Orange Pi Zero board has Allwinner XR819 SDIO wifi chip. The board
dts file provides a node enabling mmc1 controller, and a out-of-band
interrupt line of the chip is also connected, although the chip also
supports in-band interrupt.

The current out-of-tree driver is hardcoded to use out-of-band interrupt
as default, and it needs to be modified to use the in-band interrupt.

This commit adds the out-of-band interrupt line into the device tree.

Signed-off-by: Sergey Matyukevich <geoma...@gmail.com>
[Icenowy: Changed vendor prefix to allwinner and modify commit message]
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3 by Icenowy:
- Change the compatible string vendor prefix to "allwinner".
- Modify the commit message.
Changes in v2 by Sergey:
- Adds the compatible string.

 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts 
b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index b1502df7b509..6595617204b3 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -127,6 +127,9 @@
 */
xr819: sdio_wifi@1 {
reg = <1>;
+   compatible = "allwinner,xr819";
+   interrupt-parent = <>;
+   interrupts = <6 10 IRQ_TYPE_EDGE_RISING>;
};
 };
 
-- 
2.13.5

[PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

2017-10-03 Thread Icenowy Zheng

Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
an out-of-band interrupt pin instead of SDIO in-band interrupt.

Add the device tree binding of this chip, in order to make it possible
to add this interrupt pin to device trees.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v3:
- Renames the node name.
- Adds ACK from Rob.
Changes in v2:
- Removed status property in example.
- Added required property reg.

 .../bindings/net/wireless/allwinner,xr819.txt  | 38 ++
 1 file changed, 38 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt

diff --git a/Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt 
b/Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt
new file mode 100644
index ..7ae40441e343
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt
@@ -0,0 +1,38 @@
+Allwinner XRadio wireless SDIO devices
+
+This node provides properties for controlling the XRadio wireless device. The
+node is expected to be specified as a child node to the SDIO controller that
+connects the device to the system.
+
+Required properties:
+
+ - reg : The SDIO function number, see "Use of function subnodes" in
+   ../../mmc/mmc.txt.
+ - compatible : Should be "allwinner,xr819".
+
+Optional properties:
+ - interrupt-parent : the phandle for the interrupt controller to which the
+   device interrupts are connected.
+ - interrupts : specifies attributes for the out-of-band interrupt (host-wake).
+   When not specified the device will use in-band SDIO interrupts.
+
+Example:
+
+mmc1: mmc@01c1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   vmmc-supply = <_vcc_wifi>;
+   mmc-pwrseq = <_pwrseq>;
+   bus-width = <4>;
+   non-removable;
+
+   xr819: wifi@1 {
+   reg = <1>;
+   compatible = "allwinner,xr819";
+   interrupt-parent = <>;
+   interrupts = <6 10 IRQ_TYPE_EDGE_RISING>;
+   };
+};
-- 
2.13.5

Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC

2017-09-25 Thread Icenowy Zheng



于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard 
<maxime.rip...@free-electrons.com> 写到:
>Hi,
>
>On Sat, Sep 23, 2017 at 12:15:28AM +, Icenowy Zheng wrote:
>> This patchset imports simple DVFS support for Allwinner A64 SoC.
>> 
>> As the thermal sensor driver is not yet implemented and some boards
>> have still no AXP PMIC support, now only two OPPs are present --
>> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.
>> 
>> PATCH 1 is a fix to the CCU driver of A64, and the remaining patches
>> set up the device tree bits of the DVFS on Pine64.
>
>How has this been tested?
>
>What tasks did you run, with what governor, etc...

I only tested manual frequency switching between 648MHz and
816MHz, and tested the PLL stuck issue by change the OPPs to
some random value.

>
>Thanks!
>Maxime

Re: [RFC PATCH 6/7] arm64: allwinner: a64: add power supply nodes in AXP803 DTSI

2017-09-25 Thread Icenowy Zheng



于 2017年9月25日 GMT+08:00 下午5:11:57, Quentin Schulz 
<quentin.sch...@free-electrons.com> 写到:
>Hi Icenowy,
>
>On 20/09/2017 17:18, Icenowy Zheng wrote:
>> AXP803 PMIC features AC/USB/Battery power supplies.
>> 
>> As we have now the device tree bindings for them, add device tree
>> nodes for them.
>> 
>> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>> ---
>>  arch/arm64/boot/dts/allwinner/axp803.dtsi | 15 +++
>>  1 file changed, 15 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi
>b/arch/arm64/boot/dts/allwinner/axp803.dtsi
>> index ff8af52743ff..3a8615231b7c 100644
>> --- a/arch/arm64/boot/dts/allwinner/axp803.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
>> @@ -49,6 +49,16 @@
>>  interrupt-controller;
>>  #interrupt-cells = <1>;
>>  
>> +ac_power_supply: ac-power-supply {
>> +compatible = "x-powers,axp221-ac-power-supply";
>> +status = "disabled";
>> +};
>> +
>> +battery_power_supply: battery-power-supply {
>> +compatible = "x-powers,axp803-battery-power-supply";
>> +status = "disabled";
>> +};
>> +
>>  regulators {
>>  /* Default work frequency for buck regulators */
>>  x-powers,dcdc-freq = <3000>;
>> @@ -147,4 +157,9 @@
>>  regulator-name = "rtc-ldo";
>>  };
>>  };
>> +
>> +usb_power_supply: usb_power_supply {
>> +compatible = "x-powers,axp803-usb-power-supply";
>> +status = "disabled";
>> +};
>
>No. You have added support for the AC and battery power supply drivers
>in this patchset, not for USB.

But I added its device tree binding.

>
>Quentin

[PATCH v2 2/4] net: phy: realtek: change macro name for page select register

2017-08-21 Thread Icenowy Zheng

From: Icenowy Zheng <icen...@aosc.xyz>

The page select register also exists on RTL8211E PHY (although it
behaves slightly differently).

Change the register macro name to remove the F.

Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
 drivers/net/phy/realtek.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 9cbe645e3d89..d820d00addf6 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -22,11 +22,13 @@
 #define RTL821x_INER   0x12
 #define RTL821x_INER_INIT  0x6400
 #define RTL821x_INSR   0x13
+
+#define RTL8211_PAGE_SELECT0x1f
+
 #define RTL8211E_INER_LINK_STATUS 0x400
 
 #define RTL8211F_INER_LINK_STATUS 0x0010
 #define RTL8211F_INSR  0x1d
-#define RTL8211F_PAGE_SELECT   0x1f
 #define RTL8211F_TX_DELAY  0x100
 
 MODULE_DESCRIPTION("Realtek PHY driver");
@@ -46,10 +48,10 @@ static int rtl8211f_ack_interrupt(struct phy_device *phydev)
 {
int err;
 
-   phy_write(phydev, RTL8211F_PAGE_SELECT, 0xa43);
+   phy_write(phydev, RTL8211_PAGE_SELECT, 0xa43);
err = phy_read(phydev, RTL8211F_INSR);
/* restore to default page 0 */
-   phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
+   phy_write(phydev, RTL8211_PAGE_SELECT, 0x0);
 
return (err < 0) ? err : 0;
 }
@@ -102,7 +104,7 @@ static int rtl8211f_config_init(struct phy_device *phydev)
if (ret < 0)
return ret;
 
-   phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
+   phy_write(phydev, RTL8211_PAGE_SELECT, 0xd08);
reg = phy_read(phydev, 0x11);
 
/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
@@ -114,7 +116,7 @@ static int rtl8211f_config_init(struct phy_device *phydev)
 
phy_write(phydev, 0x11, reg);
/* restore to default page 0 */
-   phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
+   phy_write(phydev, RTL8211_PAGE_SELECT, 0x0);
 
return 0;
 }
-- 
2.13.5

< 1 2 3 4 5 6 7 8 9 10 >

401 - 500 of 1684 matches

Mail list logo