[PATCH] x86/acpi/cstate: Delete some unuseful operations for centaur
For Centaur CPU, the ucode will make sure that each cpu core can keep cache
coherency with each other when the CPU core entering to any C State. So the
cache
flush operations when enter C3 is not necessary and will cause large C3
enter/exit
latency.
And the bus master disable operation when CPU core entering C3 state is not
needed
too. Because the chipset will automatically do this operation.
Signed-off-by: davidwang
---
arch/x86/kernel/acpi/cstate.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index dde437f..1cd357b 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -51,6 +51,18 @@ void acpi_processor_power_init_bm_check(struct
acpi_processor_flags *flags,
if (c->x86_vendor == X86_VENDOR_INTEL &&
(c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
flags->bm_control = 0;
+
+if (c->x86_vendor == X86_VENDOR_CENTAUR) {
+ /*
+* on all centaur CPUs, sw need not execute cache flush
operation
+* when entering C3 type State.
+*
+* On all Centaur platforms, sw need not execute ARB_DISABLE
while
+* entering C3 type state.
+*/
+ flags->bm_check = 1;
+ flags->bm_control = 0;
+ }
}
EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
--
1.9.1
[PATCH] x86/centaur: Mark TSC invariant
Centaur CPU has a constant frequency TSC and that TSC does not stop in
C-States. But because the flags are not set for that CPU, the TSC is
treated as not constant frequency and assumed to stop in C-States, which
makes it an unreliable and unusable clock source. Setting those flags
tells the kernel that the TSC is usable, so it will select it over HPET.
The effect of this is that reading time stamps (from kernel or user space)
will be faster and more efficent.
Signed-off-by: davidwang
---
arch/x86/kernel/cpu/centaur.c | 4
drivers/acpi/processor_idle.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 68bc6d9..c578cd2 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -106,6 +106,10 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#endif
+ if (c->x86_power & (1 << 8)) {
+ set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+ set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
+ }
}
static void init_centaur(struct cpuinfo_x86 *c)
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index d50a7b6..5f0071c 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -207,6 +207,7 @@ static void tsc_check_state(int state)
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD:
case X86_VENDOR_INTEL:
+ case X86_VENDOR_CENTAUR:
/*
* AMD Fam10h TSC will tick in all
* C/P/S0/S1 states when this bit is set.
--
1.9.1
[tip:x86/timers] x86/centaur: Mark TSC invariant
Commit-ID: fe6daab1ee9dfe7f89974ee6c486cccb0f18a61d
Gitweb: https://git.kernel.org/tip/fe6daab1ee9dfe7f89974ee6c486cccb0f18a61d
Author: davidwang
AuthorDate: Mon, 22 Jan 2018 18:14:17 +0800
Committer: Thomas Gleixner
CommitDate: Wed, 24 Jan 2018 13:38:10 +0100
x86/centaur: Mark TSC invariant
Centaur CPU has a constant frequency TSC and that TSC does not stop in
C-States. But because the corresponding TSC feature flags are not set for
that CPU, the TSC is treated as not constant frequency and assumed to stop
in C-States, which makes it an unreliable and unusable clock source.
Setting those flags tells the kernel that the TSC is usable, so it will
select it over HPET. The effect of this is that reading time stamps (from
kernel or user space) will be faster and more efficent.
Signed-off-by: davidwang
Signed-off-by: Thomas Gleixner
Cc: qiyuanw...@zhaoxin.com
Cc: linux...@vger.kernel.org
Cc: brucech...@via-alliance.com
Cc: cooper...@zhaoxin.com
Cc: benjamin...@viatech.com
Link:
https://lkml.kernel.org/r/1516616057-5158-1-git-send-email-davidw...@zhaoxin.com
---
arch/x86/kernel/cpu/centaur.c | 4
drivers/acpi/processor_idle.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 68bc6d9..c578cd2 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -106,6 +106,10 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#endif
+ if (c->x86_power & (1 << 8)) {
+ set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+ set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
+ }
}
static void init_centaur(struct cpuinfo_x86 *c)
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index d50a7b6..5f0071c 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -207,6 +207,7 @@ static void tsc_check_state(int state)
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD:
case X86_VENDOR_INTEL:
+ case X86_VENDOR_CENTAUR:
/*
* AMD Fam10h TSC will tick in all
* C/P/S0/S1 states when this bit is set.
