Re: [RFC] libusb / in-kernel usb driver criteria (was: USB driver for talking to the Microchip PIC18 boot loader)
On Wed, Jan 02, 2008 at 07:59:15PM +, Paulo Marques wrote: > Xiaofan Chen wrote: >> On Dec 30, 2007 11:53 AM, mgross <[EMAIL PROTECTED]> wrote: >>> [...] >>> What is the linux-usb policies on new drivers that could be >>> implemented in user space? When does a kernel driver make sense over >>> a libusb one? >> That would be interesting to know. > > I myself have been faced with this question before, and I think we should > try to clarify this by adding a document with some guidelines to > Documentation/usb. > > So, to get the ball rolling, here are some factors that IMHO help decide in > which side to implement a driver: > > - if the driver ties a hardware device to an existing in-kernel interface > (network, block, serial, bluetooth, video4linux, etc.), it should probably > be implemented in-kernel. Agreed, I think this is clear. > > - on the other hand, if the driver doesn't use an existing kernel > interface and creates a new user-visible interface that is going to be used > by a single userspace application, it should probably be done in userspace. > To me this is still grey, and comes down to opinions of style. I happen to like the way code looks when things are split up into drivers (that know a lot about the hardware and protects it from data that will turn it into a brick) and application code that talks to the interface defined by the driver. The libusb based applications I've seen tend to be quite convoluted and do a poor job of separating the USB protocol from the application protocol for talking to the device. I don't think there is a clear way to define when to do a kernel driver vrs just use a libusb thing, other than if no one does a kernel driver for a device then users are stuck with the libusb applications. If someone steps up and does one and is willing to support it, then to me its like, "whatever" add the driver. BTW I don't know if its worth to code bloat for my driver as I ponder this issue now. I like the way non-libusb applications look more but I guess I could create a lib of api-wrappers to the libusb interface and use that, but I really think its less code to create a simple kernel driver. If it where up to me, I would say if the LOC is smaller to have a kernel driver and application then a kernel driver is justified otherwise its not. --mgross > - if it is going to be used by several applications it could still be > implemented as a library, but it starts moving into the gray area. > > - performance might be a reason to move to kernel space, but I don't think > it matters for transfer rates below 10Mbytes/sec or so. > > Anyway, this is just MHO, so feel free to discuss this further. I'm simply > volunteering to sum up this thread into a patch to add a > Documentation/usb/userspace_drivers.txt (or something like that), so that > we can help future developers decide where to write their drivers. > > -- > Paulo Marques - www.grupopie.com > > "Very funny Scotty. Now beam up my clothes." -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC] USB driver for talking to the Microchip PIC18 boot loader
I'm playing around with a PIC based project at home (not an Intel
activity) and found I needed a usb driver to talk to the boot loader
so I can program my USB Bitwhacker with new custom firmware. The
following adds the pic18bl driver to the kernel. Its pretty simple
and is somewhat based on bits of a libusb driver that does some of
what this driver does.
What do you think?
--mgross
Singed-off-by: Mark Gross <[EMAIL PROTECTED]>
---
Index: linux-2.6.24-rc6/drivers/usb/misc/pic18bl.c
===
--- /dev/null 1970-01-01 00:00:00.0 +
+++ linux-2.6.24-rc6/drivers/usb/misc/pic18bl.c 2007-12-29 11:21:14.0
-0800
@@ -0,0 +1,627 @@
+/*
+ * PIC18 usb boot loader driver based on the MicroChip firmware, and a user
+ * mode libusb driver that does some of the same operations only different.
+ * Based on the skeleton driver
+ *
+ * --mgross
+ *
+ * USB Skeleton driver - 2.2
+ *
+ * Copyright (C) 2001-2004 Greg Kroah-Hartman ([EMAIL PROTECTED])
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation, version 2.
+ *
+ * This driver is based on the 2.6.3 version of drivers/usb/usb-pic18bleton.c
+ * but has been rewritten to be easier to read and use.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Define these values to match your devices */
+#define USB_PIC18BL_VENDOR_ID 0x04d8
+#define USB_PIC18BL_PRODUCT_ID 0x000b
+
+/* table of devices that work with this driver */
+static struct usb_device_id pic18bl_table [] = {
+ { USB_DEVICE(USB_PIC18BL_VENDOR_ID, USB_PIC18BL_PRODUCT_ID) },
+ { } /* Terminating entry */
+};
+MODULE_DEVICE_TABLE(usb, pic18bl_table);
+
+
+/* Get a minor range for your devices from the usb maintainer */
+#define USB_PIC18BL_MINOR_BASE 192
+
+/* our private defines. if this grows any larger, use your own .h file */
+#define MAX_TRANSFER (PAGE_SIZE - 512)
+/* MAX_TRANSFER is chosen so that the VM is not stressed by
+ allocations > PAGE_SIZE and the number of packets in a page
+ is an integer 512 is the largest possible packet on EHCI */
+#define WRITES_IN_FLIGHT 8
+/* arbitrarily chosen */
+
+/* structs and information based on boot loader firmware */
+#define BOOT_EP_SIZE 64
+#define OVER_HEAD 5 /*Overhead: */
+#define DATA_SIZE (BOOT_EP_SIZE - OVER_HEAD)
+
+#defineREAD_VERSION 0x00
+#defineREAD_FLASH 0x01
+#defineWRITE_FLASH 0x02
+#defineERASE_FLASH 0x03
+#defineREAD_EEDATA 0x04
+#defineWRITE_EEDATA 0x05
+#defineREAD_CONFIG 0x06
+#defineWRITE_CONFIG 0x07
+#defineUPDATE_LED 0x32
+#defineRESET0xFF
+
+struct address {
+ u8 low;
+ u8 high;
+ u8 upper;
+} __attribute__ ((packed));
+
+union boot_data_buffer {
+ u8 buffer[BOOT_EP_SIZE];
+ struct {
+ u8 cmd;
+ u8 len;
+ struct address addr;
+ u8 data[DATA_SIZE];
+ } __attribute__ ((packed)) data;
+ struct {
+ u8 cmd; /* should always == 32 */
+ u8 led_num; /* should only be 3 or 4 */
+ u8 led_status;
+ } __attribute__ ((packed)) led;
+};
+
+
+/* Structure to hold all of our device specific stuff */
+struct usb_pic18bl {
+ struct usb_device *udev;
+ struct usb_interface*interface;
+ struct semaphorelimit_sem;
+ struct usb_anchor submitted;
+ unsigned char *bulk_in_buffer;
+ size_t bulk_in_size;
+ __u8bulk_in_endpointAddr;
+ __u8bulk_out_endpointAddr;
+ int errors;
+ int open_count;
+ spinlock_t err_lock;
+ struct kref kref;
+ struct mutexio_mutex;
+};
+#define to_pic18bl_dev(d) container_of(d, struct usb_pic18bl, kref)
+
+static struct usb_driver pic18bl_driver;
+static void pic18bl_draw_down(struct usb_pic18bl *dev);
+
+static void pic18bl_delete(struct kref *kref)
+{
+ struct usb_pic18bl *dev = to_pic18bl_dev(kref);
+
+ usb_put_dev(dev->udev);
+ kfree(dev->bulk_in_buffer);
+ kfree(dev);
+}
+
+static int pic18bl_open(struct inode *inode, struct file *file)
+{
+ struct usb_pic18bl *dev;
+ struct usb_interface *interface;
+ int subminor;
+ int retval = 0;
+
+ subminor = iminor(inode);
+
+ interface = usb_find_interface(&pic18bl_driver, subminor);
+ if (!interface) {
+ err("%s - error, can't find device for minor %d",
+__FUNCTION__, subm
Re: [RFC] USB driver for talking to the Microchip PIC18 boot loader
On Sat, Dec 29, 2007 at 05:15:30PM -0500, Alan Stern wrote: > On Sat, 29 Dec 2007, mgross wrote: > > > I'm playing around with a PIC based project at home (not an Intel > > activity) and found I needed a usb driver to talk to the boot loader > > so I can program my USB Bitwhacker with new custom firmware. The > > following adds the pic18bl driver to the kernel. Its pretty simple > > and is somewhat based on bits of a libusb driver that does some of > > what this driver does. > > > > What do you think? > > Not to detract from your driver, but would it be possible to do the > whole thing in userspace using libusb? Maybe by extending the driver > you mentioned? > Yeah, it has been done from user space using a libusb based application. (that didn't work with a usb-hub in the loop) and had code that was just too nasty for words, so I made a kernel driver that looks nicer to me and enables a nice python FW loader program to work. What is the linux-usb policies on new drivers that could be implemented in user space? When does a kernel driver make sense over a libusb one? --mgross -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC] USB driver for talking to the Microchip PIC18 boot loader
On Sun, Dec 30, 2007 at 10:40:45AM +0800, Xiaofan Chen wrote: > On Dec 30, 2007 6:15 AM, Alan Stern <[EMAIL PROTECTED]> wrote: > > On Sat, 29 Dec 2007, mgross wrote: > > > > > I'm playing around with a PIC based project at home (not an Intel > > > activity) and found I needed a usb driver to talk to the boot loader > > > so I can program my USB Bitwhacker with new custom firmware. The > > > following adds the pic18bl driver to the kernel. Its pretty simple > > > and is somewhat based on bits of a libusb driver that does some of > > > what this driver does. > > > > > > What do you think? > > > > Not to detract from your driver, but would it be possible to do the > > whole thing in userspace using libusb? Maybe by extending the driver > > you mentioned? > > > > The existing libusb based application works fine for PICDEM FS USB > or those based on it (like the Bitwhacker the OP is using). The device ID's are different 0x000C in ldusb.c vrs 0x000b in the driver I just posted. Have you read my patch yet? > > Please do not add it to the kernel. There are libusb based application > for both the bootloader and the demo application and both are working > fine under Linux (along with Windows and I am trying to get FreeBSD > working). The libusb based FW loader http://www.internetking.org/fsusb/ program is nasty and didn't work on one of my systems, so I refactored it into a kernel driver and python program. > > Last time the demo application has been added to the ldusb and > I think it is not a good idea. But since then I've added patches to > the existing libusb application. > > Relevant discussion in thread > '[PATCH 70/78] USB: add picdem device to ldusb' > http://marc.info/?t=11777007643&r=1&w=2 > > So please do not do this again. It is not a problem for the libusb > based applications after the patches but it is really not necessary. Why not? There are a lot of redundant things in the world. Linux is not necessary if you really want to take this argument to its extreme. > > Original libusb based application for the bootloader: > http://www.internetking.org/fsusb/ Yup thats the code. I found it way complex to read and felt a simple kernel driver and simple python program much nicer to my sensibilities. We are getting quickly getting into a fuzzy/ opinion, area on this thread. Is there a technical angle we can discuss? My LOC count of the kernel driver and boot loader is smaller than the fsusb thing. Also, with a kernel driver and a python lib, a GUI based boot loader utility can be had with little effort. > Original libusb based application for the Demo which > also includes my patch for libusb-win32. > http://www.varxec.net/picdem_fs_usb/ > > Updated Patches to detach the kernel driver for both > the bootloader and Demo application. > http://forum.microchip.com/tm.aspx?m=106426 > > Xiaofan Chen > http://mcuee.blogspot.com You blogging about me already? I wont comment on that. --mgross -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6 08/34] misc: xlink-pcie: Add documentation for XLink PCIe driver
From: Srikanth Thokala
Provide overview of XLink PCIe driver implementation
Cc: Jonathan Corbet
Cc: linux-...@vger.kernel.org
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
Documentation/vpu/index.rst | 1 +
Documentation/vpu/xlink-pcie.rst | 90
2 files changed, 91 insertions(+)
create mode 100644 Documentation/vpu/xlink-pcie.rst
diff --git a/Documentation/vpu/index.rst b/Documentation/vpu/index.rst
index 7e290e048910..661cc700ee45 100644
--- a/Documentation/vpu/index.rst
+++ b/Documentation/vpu/index.rst
@@ -14,3 +14,4 @@ This documentation contains information for the Intel VPU
stack.
:maxdepth: 2
vpu-stack-overview
+ xlink-pcie
diff --git a/Documentation/vpu/xlink-pcie.rst b/Documentation/vpu/xlink-pcie.rst
new file mode 100644
index ..85a70990e9c9
--- /dev/null
+++ b/Documentation/vpu/xlink-pcie.rst
@@ -0,0 +1,90 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+
+Kernel driver: Xlink-pcie driver
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+Suffix: Bay
+Slave address: 6240
+Datasheet: Publicly available at Intel
+
+Author: Srikanth Thokala srikanth.thok...@intel.com
+
+Introduction
+
+The Xlink-pcie driver provides transport layer implementation for
+the data transfers to support Xlink protocol subsystem communication with the
+peer device, i.e., between remote host system and Keem Bay device.
+
+The Keem Bay device is an ARM-based SOC that includes a vision processing
+unit (VPU) and deep learning, neural network core in the hardware.
+The Xlink-pcie driver exports a functional device endpoint to the Keem Bay
+device and supports two-way communication with the peer device.
+
+High-level architecture
+===
+Remote Host: IA CPU
+Local Host: ARM CPU (Keem Bay)::
+
+
++
+| Remote Host IA CPU | | Local Host ARM CPU (Keem Bay) |
|
+
+==+=+===+===+
+| User App| | User App |
|
+
+--+-+---+---+
+| XLink UAPI | | XLink UAPI|
|
+
+--+-+---+---+
+| XLink Core | | XLink Core|
|
+
+--+-+---+---+
+| XLink PCIe | | XLink PCIe|
|
+
+--+-+---+---+
+| XLink-PCIe Remote Host driver | | XLink-PCIe Local Host driver |
|
+
+--+-+---+---+
+
|-:-:-:-:-:-:-:-:-:-:-:-:-:-:-:-:-:|:|:-:-:-:-:-:-:-:-:-:-:-:-:-:-:-:-:-:|
+
+--+-+---+---+
+| PCIe Host Controller | | PCIe Device Controller|
HW|
+
+--+-+---+---+
+ ^ ^
+ | |
+ |- PCIe x2 Link -|
+
+This XLink PCIe driver comprises of two variants:
+* Local Host driver
+
+ * Intended for ARM CPU
+ * It is based on PCI Endpoint Framework
+ * Driver path: {tree}/drivers/misc/Xlink-pcie/local_host
+
+* Remote Host driver
+
+ * Intended for IA CPU
+ * It is a PCIe endpoint driver
+ * Driver path: {tree}/drivers/misc/Xlink-pcie/remote_host
+
+XLink PCIe communication between local host and remote host is achieved through
+ring buffer management and MSI/Doorbell interrupts.
+
+The Xlink-pcie driver subsystem registers the Keem Bay device as an endpoint
+driver and provides standard Linux PCIe sysfs interface:
+'/sys/bus/pci/devices/:xx:xx.0/'
+
+
+XLink protocol subsystem
+
+Xlink is an abstracted control and communication subsystem based on channel
+identification. It is intended to support VPU technology both at SoC level as
+well as at IP level, over multiple interfaces.
+
+- The Xlink subsystem abstracts several types of communication channels
+ underneath, allowing the usage of different interfaces with the
+ same function call interface.
+- The Communication channels are full-duplex protocol channels allowing
+ concurrent bidirectional communication.
+- The Xlink subsystem also supports control operations to VPU either
+ from standalone local system or from remote system based on communication
+ interface underneath.
+- The Xlink subsyste
[PATCH v6 06/34] dt-bindings: Add bindings for Keem Bay VPU IPC driver
From: Paul Murphy
Add DT bindings documentation for the Keem Bay VPU IPC driver.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Reviewed-by: Mark Gross
Co-developed-by: Daniele Alessandrelli
Signed-off-by: Paul Murphy
Signed-off-by: Daniele Alessandrelli
Signed-off-by: Mark Gross
---
.../soc/intel/intel,keembay-vpu-ipc.yaml | 143 ++
1 file changed, 143 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
diff --git
a/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
new file mode 100644
index ..9dae8ab4c723
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) Intel Corporation. All rights reserved.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-vpu-ipc.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel Keem Bay VPU IPC
+
+maintainers:
+ - Paul Murphy
+ - Daniele Alessandrelli
+
+description:
+ This binding provides support for the Vision Processing Unit (VPU) found on
+ the Intel Keem Bay SoC.
+
+ The VPU is started and controlled by SoC CPU, which is in charge of loading
+ the VPU firmware. The SoC CPU can communicate with the VPU firmware using an
+ Inter-Processor Communication (IPC) mechanism.
+
+properties:
+ compatible:
+oneOf:
+ - items:
+ - const: intel,keembay-vpu-ipc
+
+ reg:
+items:
+ - description: NCE WDT registers
+ - description: NCE TIM_GEN_CONFIG registers
+ - description: MSS WDT registers
+ - description: MSS TIM_GEN_CONFIG registers
+
+ reg-names:
+items:
+ - const: nce_wdt
+ - const: nce_tim_cfg
+ - const: mss_wdt
+ - const: mss_tim_cfg
+
+ memory-region:
+items:
+ - description: reference to the VPU reserved memory region
+ - description: reference to the X509 reserved memory region
+ - description: reference to the MSS IPC area
+
+ clocks:
+items:
+ - description: cpu clock
+ - description: pll 0 out 0 rate
+ - description: pll 0 out 1 rate
+ - description: pll 0 out 2 rate
+ - description: pll 0 out 3 rate
+ - description: pll 1 out 0 rate
+ - description: pll 1 out 1 rate
+ - description: pll 1 out 2 rate
+ - description: pll 1 out 3 rate
+ - description: pll 2 out 0 rate
+ - description: pll 2 out 1 rate
+ - description: pll 2 out 2 rate
+ - description: pll 2 out 3 rate
+
+ clock-names:
+items:
+ - const: cpu_clock
+ - const: pll_0_out_0
+ - const: pll_0_out_1
+ - const: pll_0_out_2
+ - const: pll_0_out_3
+ - const: pll_1_out_0
+ - const: pll_1_out_1
+ - const: pll_1_out_2
+ - const: pll_1_out_3
+ - const: pll_2_out_0
+ - const: pll_2_out_1
+ - const: pll_2_out_2
+ - const: pll_2_out_3
+
+ interrupts:
+items:
+ - description: number of NCE sub-system WDT timeout IRQ
+ - description: number of MSS sub-system WDT timeout IRQ
+
+ interrupt-names:
+items:
+ - const: nce_wdt
+ - const: mss_wdt
+
+ intel,keembay-vpu-ipc-imr:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description:
+ Isolated Memory Region (IMR) number that the runtime service must use to
+ protect the VPU memory region before authentication.
+
+ intel,keembay-vpu-ipc-id:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description: The VPU ID to be passed to the VPU firmware.
+
+additionalProperties: False
+
+examples:
+ - |
+#include
+vpu-ipc@3f00209c {
+compatible = "intel,keembay-vpu-ipc";
+reg = <0x3f00209c 0x10>,
+ <0x3f003008 0x4>,
+ <0x2082009c 0x10>,
+ <0x20821008 0x4>;
+reg-names = "nce_wdt",
+"nce_tim_cfg",
+"mss_wdt",
+"mss_tim_cfg";
+memory-region = <&vpu_reserved>,
+<&vpu_x509_reserved>,
+<&mss_ipc_reserved>;
+clocks = <&scmi_clk 0>,
+ <&scmi_clk 0>,
+ <&scmi_clk 1>,
+ <&scmi_clk 2>,
+ <&scmi_clk 3>,
+ <&scmi_clk 4>,
+ <&scmi_clk 5>,
+ <&scmi_clk 6>,
+ <&scmi_clk 7>,
+ <&scmi_clk 8>,
+ <&scmi_clk 9>,
+ <&scmi_clk 10>,
+ <&scmi_clk 11>;
+clock-names = "cpu_clock",
+ "pll_0_out_0", "pll_0_out_1",
+ "pll_0_out_2", "pll_0_out_3",
+ "pll_1_out_0", "pll_1_out_1",
+ "pll_1_out_2", "pll_1_out_3",
+ "pll_2_out_0", "pll_2_out_1",
+
[PATCH v6 01/34] Add Vision Processing Unit (VPU) documentation.
From: mark gross The Intel VPU needs a complicated SW stack to make it work. Add a directory to hold VPU related documentation including an architectural overview of the SW stack that the patches implement. Cc: Jonathan Corbet Signed-off-by: Mark Gross --- Documentation/index.rst | 1 + Documentation/vpu/index.rst | 16 ++ Documentation/vpu/vpu-stack-overview.rst | 270 +++ 3 files changed, 287 insertions(+) create mode 100644 Documentation/vpu/index.rst create mode 100644 Documentation/vpu/vpu-stack-overview.rst diff --git a/Documentation/index.rst b/Documentation/index.rst index 5888e8a7272f..81a02f2af939 100644 --- a/Documentation/index.rst +++ b/Documentation/index.rst @@ -137,6 +137,7 @@ needed). misc-devices/index scheduler/index mhi/index + vpu/index Architecture-agnostic documentation --- diff --git a/Documentation/vpu/index.rst b/Documentation/vpu/index.rst new file mode 100644 index ..7e290e048910 --- /dev/null +++ b/Documentation/vpu/index.rst @@ -0,0 +1,16 @@ +.. SPDX-License-Identifier: GPL-2.0-only + + +Vision Processor Unit Documentation + + +This documentation contains information for the Intel VPU stack. + +.. class:: toc-title + + Table of contents + +.. toctree:: + :maxdepth: 2 + + vpu-stack-overview diff --git a/Documentation/vpu/vpu-stack-overview.rst b/Documentation/vpu/vpu-stack-overview.rst new file mode 100644 index ..1fe9ce423177 --- /dev/null +++ b/Documentation/vpu/vpu-stack-overview.rst @@ -0,0 +1,270 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== +Intel VPU architecture +== + +Overview + + +The Intel Movidius acquisition has developed a Vision Processing Unit (VPU) +roadmap of products starting with Keem Bay (KMB). The hardware configurations +the VPU can support include: + +1. Standalone smart camera that does local Computer Vision (CV) processing in + camera +2. Standalone appliance or signel board computer connected to a network and + tethered cameras doing local CV processing +3. Embedded in a USB dongle or M.2 as an CV accelerator. +4. Multiple VPU enabled SOC's on a PCIe card as a CV accelerator in a larger IA + box or server. + +Keem Bay is the first instance of this family of products. This document +provides an architectural overview of the software stack supporting the VPU +enabled products. + +Keem Bay (KMB) is a Computer Vision AI processing SoC based on ARM A53 CPU that +provides Edge neural network acceleration (inference) and includes a Vision +Processing Unit (VPU) hardware. The ARM CPU SubSystem (CPUSS) interfaces +locally to the VPU and enables integration/interfacing with a remote host over +PCIe or USB or Ethernet interfaces. The interface between the CPUSS and the VPU +is implemented with hardware FIFOs (Control) and coherent memory mapping (Data) +such that zero copy processing can happen within the VPU. + +The KMB can be used in all 4 of the above classes of designs. + +We refer to the 'local host' as being the ARM part of the SoC, while the +'remote host' as the IA system hosting the KMB device(s). The KMB SoC boots +from an eMMC via uBoot and ARM Linux compatible device tree interface with an +expectation to fully boot within hundreds of milliseconds. There is also +support for downloading the kernel and root file system image from a remote +host. + +The eMMC can be updated with standard Mender update process. +See https://github.com/mendersoftware/mender + +The VPU is started and controlled from the A53 local host. Its firmware image +is loaded using the drive firware helper KAPI's. + +The VPU IP firware payload consists of a SPARC ISA RTEMS bootloader and/or +application binary. + +The interface allowing (remote or local) host clients to access VPU IP +capabilities is realized through an abstracted programming model, which +provides Remote Proxy APIs for a host CPU application to dynamically create and +execute CV and NN workloads on the VPU. All frameworks exposed through +programming model’s APIs are contained in the pre-compiled standard firmware +image. + +There is a significant software stack built up to support KMB and the use +cases. The rest of this documentation provides an overview of the components +of the stack. + +Keem Bay IPC + + +Directly interfaces with the KMB hardware FIFOs to provide zero copy processing +from the VPU. It implements the lowest level protocol for interacting with the +VPU. + +The Keem Bay IPC mechanism is based on shared memory and hardware FIFOs. +Specifically there are: + +* Two 128-entry hardware FIFOs, one for the CPU and one for the VPU. +* Two shared memory regions, used as memory pool for allocating IPC buffers. + +An IPC channel is a software abstraction allowing communication multiplexing, +so that multiple a
[PATCH v6 04/34] dt-bindings: Add bindings for Keem Bay IPC driver
From: Daniele Alessandrelli
Add DT binding documentation for the Intel Keem Bay IPC driver, which
enables communication between the Computing Sub-System (CSS) and the
Multimedia Sub-System (MSS) of the Intel Movidius SoC code named Keem
Bay.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Reviewed-by: Mark Gross
Signed-off-by: Daniele Alessandrelli
Signed-off-by: Mark Gross
---
.../bindings/soc/intel/intel,keembay-ipc.yaml | 45 +++
1 file changed, 45 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml
diff --git a/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml
b/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml
new file mode 100644
index ..586fe73f4cd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Intel Corporation
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-ipc.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Keem Bay IPC
+
+maintainers:
+ - Daniele Alessandrelli
+
+description:
+ The Keem Bay IPC driver enables Inter-Processor Communication (IPC) with the
+ Visual Processor Unit (VPU) embedded in the Intel Movidius SoC code named
+ Keem Bay.
+
+properties:
+ compatible:
+const: intel,keembay-ipc
+
+ memory-region:
+items:
+ - description:
+ Reserved memory region used by the CPU to allocate IPC packets.
+ - description:
+ Reserved memory region used by the VPU to allocate IPC packets.
+
+ mboxes:
+description: VPU IPC Mailbox.
+
+required:
+ - compatible
+ - memory-region
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ipc {
+ compatible = "intel,keembay-ipc";
+ memory-region = <&ipc_cpu_reserved>, <&ipc_vpu_reserved>;
+ mboxes = <&vpu_ipc_mbox 0>;
+};
--
2.17.1
[PATCH v6 02/34] dt-bindings: mailbox: Add Intel VPU IPC mailbox bindings
From: Daniele Alessandrelli
Add bindings for the Intel VPU IPC mailbox driver.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Daniele Alessandrelli
Signed-off-by: Mark Gross
---
.../mailbox/intel,vpu-ipc-mailbox.yaml| 69 +++
MAINTAINERS | 6 ++
2 files changed, 75 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
diff --git
a/Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
b/Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
new file mode 100644
index ..923a6d619a64
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 Intel Corporation
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mailbox/intel,vpu-ipc-mailbox.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel VPU IPC mailbox
+
+maintainers:
+ - Daniele Alessandrelli
+
+description: |
+ Intel VPU SoCs like Keem Bay have hardware FIFOs to enable Inter-Processor
+ Communication (IPC) between the CPU and the VPU.
+
+ Specifically, there is one HW FIFO for the CPU (aka Application Processor -
+ AP) and one for the VPU. Each FIFO can hold 128 entries of 32 bits each. A
+ "FIFO-not-empty" interrupt is raised every time there is at least a message
+ in the FIFO. The CPU FIFO raises interrupts to the CPU, while the VPU FIFO
+ raises interrupts to VPU. When the CPU wants to send a message to the VPU it
+ writes to the VPU FIFO, similarly, when the VPU want to send a message to the
+ CPU, it writes to the CPU FIFO.
+
+ Refer to ./mailbox.txt for generic information about mailbox device-tree
+ bindings.
+
+properties:
+ compatible:
+const: intel,vpu-ipc-mailbox
+
+ reg:
+items:
+ - description: The CPU FIFO registers
+ - description: The VPU FIFO registers
+
+ reg-names:
+items:
+ - const: cpu_fifo
+ - const: vpu_fifo
+
+ interrupts:
+items:
+ - description: CPU FIFO-not-empty interrupt
+
+ "#mbox-cells":
+const: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+vpu_ipc_mailbox@203300f0 {
+compatible = "intel,vpu-ipc-mailbox";
+#mbox-cells = <1>;
+reg = <0x203300f0 0x310>,
+ <0x208200f0 0x310>;
+reg-names = "cpu_fifo", "vpu_fifo";
+interrupts = ;
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 667d03852191..68e6af3e5650 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9179,6 +9179,12 @@ L: platform-driver-...@vger.kernel.org
S: Maintained
F: drivers/platform/x86/intel-vbtn.c
+INTEL VPU IPC MAILBOX
+M: Daniele Alessandrelli
+M: Mark Gross
+S: Supported
+F: Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
+
INTEL WIRELESS 3945ABG/BG, 4965AGN (iwlegacy)
M: Stanislaw Gruszka
L: linux-wirel...@vger.kernel.org
--
2.17.1
[PATCH v6 12/34] misc: xlink-pcie: lh: Prepare changes for adding remote host driver
From: Srikanth Thokala
Move logic that can be reused between local host and remote host to
common/ folder
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/{local_host => common}/core.h | 8 +++-
drivers/misc/xlink-pcie/{local_host => common}/util.c | 8 +++-
drivers/misc/xlink-pcie/{local_host => common}/util.h | 8 +++-
drivers/misc/xlink-pcie/{local_host => common}/xpcie.h | 8 +++-
drivers/misc/xlink-pcie/local_host/Makefile| 2 +-
drivers/misc/xlink-pcie/local_host/core.c | 4 ++--
drivers/misc/xlink-pcie/local_host/epf.h | 4 ++--
7 files changed, 17 insertions(+), 25 deletions(-)
rename drivers/misc/xlink-pcie/{local_host => common}/core.h (96%)
rename drivers/misc/xlink-pcie/{local_host => common}/util.c (97%)
rename drivers/misc/xlink-pcie/{local_host => common}/util.h (91%)
rename drivers/misc/xlink-pcie/{local_host => common}/xpcie.h (92%)
diff --git a/drivers/misc/xlink-pcie/local_host/core.h
b/drivers/misc/xlink-pcie/common/core.h
similarity index 96%
rename from drivers/misc/xlink-pcie/local_host/core.h
rename to drivers/misc/xlink-pcie/common/core.h
index 84985ef41a64..656b5e2dbfae 100644
--- a/drivers/misc/xlink-pcie/local_host/core.h
+++ b/drivers/misc/xlink-pcie/common/core.h
@@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- *
+/*
* Intel Keem Bay XLink PCIe Driver
*
- * Copyright (C) 2020 Intel Corporation
- *
- /
+ * Copyright (C) 2021 Intel Corporation
+ */
#ifndef XPCIE_CORE_HEADER_
#define XPCIE_CORE_HEADER_
diff --git a/drivers/misc/xlink-pcie/local_host/util.c
b/drivers/misc/xlink-pcie/common/util.c
similarity index 97%
rename from drivers/misc/xlink-pcie/local_host/util.c
rename to drivers/misc/xlink-pcie/common/util.c
index ec808b0cd72b..d99125f61ba0 100644
--- a/drivers/misc/xlink-pcie/local_host/util.c
+++ b/drivers/misc/xlink-pcie/common/util.c
@@ -1,11 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-only
-/*
- *
+/*
* Intel Keem Bay XLink PCIe Driver
*
- * Copyright (C) 2020 Intel Corporation
- *
- /
+ * Copyright (C) 2021 Intel Corporation
+ */
#include "util.h"
diff --git a/drivers/misc/xlink-pcie/local_host/util.h
b/drivers/misc/xlink-pcie/common/util.h
similarity index 91%
rename from drivers/misc/xlink-pcie/local_host/util.h
rename to drivers/misc/xlink-pcie/common/util.h
index 908be897a61d..5295783b0437 100644
--- a/drivers/misc/xlink-pcie/local_host/util.h
+++ b/drivers/misc/xlink-pcie/common/util.h
@@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- *
+/*
* Intel Keem Bay XLink PCIe Driver
*
- * Copyright (C) 2020 Intel Corporation
- *
- /
+ * Copyright (C) 2021 Intel Corporation
+ */
#ifndef XPCIE_UTIL_HEADER_
#define XPCIE_UTIL_HEADER_
diff --git a/drivers/misc/xlink-pcie/local_host/xpcie.h
b/drivers/misc/xlink-pcie/common/xpcie.h
similarity index 92%
rename from drivers/misc/xlink-pcie/local_host/xpcie.h
rename to drivers/misc/xlink-pcie/common/xpcie.h
index 8a559617daba..48529eb49be0 100644
--- a/drivers/misc/xlink-pcie/local_host/xpcie.h
+++ b/drivers/misc/xlink-pcie/common/xpcie.h
@@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- *
+/*
* Intel Keem Bay XLink PCIe Driver
*
- * Copyright (C) 2020 Intel Corporation
- *
- /
+ * Copyright (C) 2021 Intel Corporation
+ */
#ifndef XPCIE_HEADER_
#define XPCIE_HEADER_
diff --git a/drivers/misc/xlink-pcie/local_host/Makefile
b/drivers/misc/xlink-pcie/local_host/Makefile
index 28761751d43b..65df94c7e860 100644
--- a/drivers/misc/xlink-pcie/local_host/Makefile
+++ b/drivers/misc/xlink-pcie/local_host/Makefile
@@ -2,4 +2,4 @@ obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o
mxlk_ep-objs := epf.o
mxlk_ep-objs += dma.o
mxlk_ep-objs += core.o
-mxlk_ep-objs += util.o
+mxlk_ep-objs += ../common/util.o
diff --git a/drivers/misc/xlink-pcie/local_host/core.c
b/drivers/misc/xlink-pcie/local_host/core.c
index c67ce2c3067d..2c4e29bce7f7 100644
--- a/drivers/misc/xlink-pcie/local_host/core.c
+++ b/drivers/misc/xlink-pcie/local_host/core.c
@@ -8,8 +8,8 @@
#include
#include "epf.h"
-#include "core.h"
-#include "util.h"
+#include "../common/core.h"
+#include "../common/util.h"
static struct xpcie *global_xpcie;
diff --git a/drivers/misc/xlink-pcie/local_host/epf.h
b/drivers/m
[PATCH v6 14/34] misc: xlink-pcie: rh: Add core communication logic
From: Srikanth Thokala
Add logic to establish communication with the local host which is through
ring buffer management and MSI/Doorbell interrupts
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/common/core.h| 11 +-
drivers/misc/xlink-pcie/remote_host/Makefile | 2 +
drivers/misc/xlink-pcie/remote_host/core.c | 621 +++
drivers/misc/xlink-pcie/remote_host/pci.c| 48 +-
4 files changed, 670 insertions(+), 12 deletions(-)
create mode 100644 drivers/misc/xlink-pcie/remote_host/core.c
diff --git a/drivers/misc/xlink-pcie/common/core.h
b/drivers/misc/xlink-pcie/common/core.h
index 656b5e2dbfae..f43c175b7a48 100644
--- a/drivers/misc/xlink-pcie/common/core.h
+++ b/drivers/misc/xlink-pcie/common/core.h
@@ -8,15 +8,11 @@
#ifndef XPCIE_CORE_HEADER_
#define XPCIE_CORE_HEADER_
-#include
-#include
-#include
-#include
-#include
-#include
#include
-#include
+#include
+#include
#include
+#include
#include
@@ -62,6 +58,7 @@ struct xpcie_buf_desc {
struct xpcie_stream {
size_t frag;
struct xpcie_pipe pipe;
+ struct xpcie_buf_desc **ddr;
};
struct xpcie_list {
diff --git a/drivers/misc/xlink-pcie/remote_host/Makefile
b/drivers/misc/xlink-pcie/remote_host/Makefile
index 96374a43023e..e8074dbb1161 100644
--- a/drivers/misc/xlink-pcie/remote_host/Makefile
+++ b/drivers/misc/xlink-pcie/remote_host/Makefile
@@ -1,3 +1,5 @@
obj-$(CONFIG_XLINK_PCIE_RH_DRIVER) += mxlk.o
mxlk-objs := main.o
mxlk-objs += pci.o
+mxlk-objs += core.o
+mxlk-objs += ../common/util.o
diff --git a/drivers/misc/xlink-pcie/remote_host/core.c
b/drivers/misc/xlink-pcie/remote_host/core.c
new file mode 100644
index ..3be0492aa57c
--- /dev/null
+++ b/drivers/misc/xlink-pcie/remote_host/core.c
@@ -0,0 +1,621 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include "pci.h"
+
+#include "../common/core.h"
+#include "../common/util.h"
+
+static int intel_xpcie_map_dma(struct xpcie *xpcie, struct xpcie_buf_desc *bd,
+ int direction)
+{
+ struct xpcie_dev *xdev = container_of(xpcie, struct xpcie_dev, xpcie);
+ struct device *dev = &xdev->pci->dev;
+
+ bd->phys = dma_map_single(dev, bd->data, bd->length, direction);
+
+ return dma_mapping_error(dev, bd->phys);
+}
+
+static void intel_xpcie_unmap_dma(struct xpcie *xpcie,
+ struct xpcie_buf_desc *bd,
+ int direction)
+{
+ struct xpcie_dev *xdev = container_of(xpcie, struct xpcie_dev, xpcie);
+ struct device *dev = &xdev->pci->dev;
+
+ dma_unmap_single(dev, bd->phys, bd->length, direction);
+}
+
+static void intel_xpcie_txrx_cleanup(struct xpcie *xpcie)
+{
+ struct xpcie_interface *inf = &xpcie->interfaces[0];
+ struct xpcie_stream *tx = &xpcie->tx;
+ struct xpcie_stream *rx = &xpcie->rx;
+ struct xpcie_buf_desc *bd;
+ int index;
+
+ xpcie->stop_flag = true;
+ xpcie->no_tx_buffer = false;
+ inf->data_avail = true;
+ wake_up_interruptible(&xpcie->tx_waitq);
+ wake_up_interruptible(&inf->rx_waitq);
+ mutex_lock(&xpcie->wlock);
+ mutex_lock(&inf->rlock);
+
+ if (tx->ddr) {
+ for (index = 0; index < tx->pipe.ndesc; index++) {
+ struct xpcie_transfer_desc *td = tx->pipe.tdr + index;
+
+ bd = tx->ddr[index];
+ if (bd) {
+ intel_xpcie_unmap_dma(xpcie, bd, DMA_TO_DEVICE);
+ intel_xpcie_free_tx_bd(xpcie, bd);
+ intel_xpcie_set_td_address(td, 0);
+ intel_xpcie_set_td_length(td, 0);
+ }
+ }
+ kfree(tx->ddr);
+ }
+
+ if (rx->ddr) {
+ for (index = 0; index < rx->pipe.ndesc; index++) {
+ struct xpcie_transfer_desc *td = rx->pipe.tdr + index;
+
+ bd = rx->ddr[index];
+ if (bd) {
+ intel_xpcie_unmap_dma(xpcie,
+ bd, DMA_FROM_DEVICE);
+ intel_xpcie_free_rx_bd(xpcie, bd);
+ intel_xpcie_set_td_address(td, 0);
+ intel_xpcie_set_td_length(td, 0);
+ }
+ }
+ kfree(rx->ddr);
+ }
+
+ intel_xpcie_list_cleanup(&xpcie->tx_pool);
+ intel_xpcie_list_cleanup(&xpcie->rx_pool);
+
+ mutex_unlock(&inf->rlock);
+ mutex_unlock(&xpcie->wlock);
+}
+
+static int intel_xpcie_txrx_init(struct xpcie *xpcie,
+struct xpcie_cap_txrx *cap)
+{
[PATCH v6 07/34] keembay-vpu-ipc: Add Keem Bay VPU IPC module
From: Paul Murphy Intel Keem Bay SoC contains a Vision Processing Unit (VPU) to enable machine vision and other applications. Enable Linux to control the VPU processor and provides an interface to the Keem Bay IPC for communicating with the VPU firmware. Specifically the driver provides the following functionality to other kernel components: - Starting (including loading the VPU firmware) / Stopping / Rebooting the VPU. - Getting notifications of VPU events (e.g., WDT events). - Communicating with the VPU via the Keem Bay IPC mechanism. In addition to the above, the driver also exposes SoC information (like stepping, device ID, etc.) to user-space via sysfs. Specifically, the following sysfs files are provided: - /sys/firmware/keembay-vpu-ipc/device_id - /sys/firmware/keembay-vpu-ipc/feature_exclusion - /sys/firmware/keembay-vpu-ipc/hardware_id - /sys/firmware/keembay-vpu-ipc/sku - /sys/firmware/keembay-vpu-ipc/stepping Co-developed-by: Daniele Alessandrelli Signed-off-by: Daniele Alessandrelli Signed-off-by: Mark Gross Signed-off-by: Paul Murphy --- MAINTAINERS |9 + drivers/soc/intel/Kconfig | 15 + drivers/soc/intel/Makefile|3 +- drivers/soc/intel/keembay-vpu-ipc.c | 2026 + include/linux/soc/intel/keembay-vpu-ipc.h | 62 + 5 files changed, 2114 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/intel/keembay-vpu-ipc.c create mode 100644 include/linux/soc/intel/keembay-vpu-ipc.h diff --git a/MAINTAINERS b/MAINTAINERS index bb39711065a4..c18640ae6955 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9066,6 +9066,15 @@ F: Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml F: drivers/soc/intel/keembay-ipc.c F: include/linux/soc/intel/keembay-ipc.h +INTEL KEEM BAY VPU IPC DRIVER +M: Paul J Murphy +M: Daniele Alessandrelli +M: Mark Gross +S: Supported +F: Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml +F: drivers/soc/intel/keembay-vpu-ipc.c +F: include/linux/soc/intel/keembay-vpu-ipc.h + INTEL MANAGEMENT ENGINE (mei) M: Tomas Winkler L: linux-kernel@vger.kernel.org diff --git a/drivers/soc/intel/Kconfig b/drivers/soc/intel/Kconfig index a575e31e47b4..ebd23ea57d04 100644 --- a/drivers/soc/intel/Kconfig +++ b/drivers/soc/intel/Kconfig @@ -15,4 +15,19 @@ config KEEMBAY_IPC Select this if you are compiling the Kernel for an Intel SoC that includes the Intel Vision Processing Unit (VPU) such as Keem Bay. + +config KEEMBAY_VPU_IPC + tristate "Intel Keem Bay VPU IPC Driver" + depends on KEEMBAY_IPC + depends on HAVE_ARM_SMCCC + help + This option enables support for loading and communicating with + the firmware on the Vision Processing Unit (VPU) of the Keem Bay + SoC. The driver depends on the Keem Bay IPC driver to do + communication, and it depends on secure world monitor software to + do the control of the VPU state. + + Select this if you are compiling the Kernel for an Intel SoC that + includes the Intel Vision Processing Unit (VPU) such as Keem Bay. + endmenu diff --git a/drivers/soc/intel/Makefile b/drivers/soc/intel/Makefile index ecf0246e7822..363a81848843 100644 --- a/drivers/soc/intel/Makefile +++ b/drivers/soc/intel/Makefile @@ -1,4 +1,5 @@ # # Makefile for Keem Bay IPC Linux driver # -obj-$(CONFIG_KEEMBAY_IPC) += keembay-ipc.o +obj-$(CONFIG_KEEMBAY_IPC) += keembay-ipc.o +obj-$(CONFIG_KEEMBAY_VPU_IPC) += keembay-vpu-ipc.o diff --git a/drivers/soc/intel/keembay-vpu-ipc.c b/drivers/soc/intel/keembay-vpu-ipc.c new file mode 100644 index ..8f3d6a466629 --- /dev/null +++ b/drivers/soc/intel/keembay-vpu-ipc.c @@ -0,0 +1,2026 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Keem Bay VPU IPC Driver. + * + * Copyright (c) 2018-2020 Intel Corporation. + * + * The purpose of this driver is to facilitate booting, control and + * communication with the VPU IP on the Keem Bay SoC. + * + * Specifically the driver provides the following functionality to other kernel + * components: + * - Loading the VPU firmware into DDR for the VPU to execute. + * - Starting / Stopping / Rebooting the VPU. + * - Getting notifications of VPU events (e.g., WDT events). + * - Communicating with the VPU using the Keem Bay IPC mechanism. + * + * In addition to the above, the driver also exposes SoC information (like + * stepping, device ID, etc.) to user-space via sysfs. + * + * + * VPU Firmware loading + * + * + * The VPU Firmware consists of both the RTOS and the application code meant to + * be run by the VPU. + * + * The VPU Firmware is loaded into DDR using the Linux Firmware API. The + * firmware is loaded into a specific reserved memory region in DDR and + * executed by the VPU directly from there. + * + * The VPU Firmware binary is expected to have the followin
[PATCH v6 05/34] keembay-ipc: Add Keem Bay IPC module
From: Daniele Alessandrelli On the Intel Movidius SoC code named Keem Bay, communication between the Application Processor(AP) and the VPU is enabled by the Keem Bay Inter-Processor Communication (IPC) mechanism. Add the driver for using Keem Bay IPC from within the Linux Kernel. The IPC uses the following terminology: - Node:A processing entity that can use the IPC to communicate (currently, we just have two nodes, the AP and the VPU). - Link:Two nodes that can communicate over IPC form an IPC link (currently, we just have one link, the one formed by the AP and the VPU). - Channel: An IPC link can provide multiple IPC channels. IPC channels allow communication multiplexing, i.e., the same IPC link can be used by different applications for different communications. Each channel is identified by a channel ID, which must be unique within a single IPC link. Channels are divided in two categories, High-Speed (HS) channels and General-Purpose (GP) channels. HS channels have higher priority over GP channels. The Keem Bay IPC mechanism is built on top of the VPU IPC mailbox, which allows the AP and the VPU to exchange 32-bit messages. Specifically, the IPC uses shared memory (shared between the AP and the VPU) to allocate IPC packets and then exchanges them using the VPU IPC mailbox (the 32-bit physical address of the packet is passed as a message to the VPU IPC mailbox). IPC packets have a fixed structure containing the (VPU) physical address of the payload (which must be located in shared memory too) as well as other information (payload size, IPC channel ID, etc.). Each IPC node (i.e., both the AP and the VPU) has its own reserved memory region (in shared memory) from which it instantiates its own pool of IPC packets. When instantiated, IPC packets are marked as free. When the node needs to send an IPC message, it gets the first free packet it finds (from its own pool), marks it as allocated (used), and transfer its physical address to the destination node using the VPU IPC mailbox. The destination node uses the received physical address to access the IPC packet, process the packet, and, once done with it, marks it as free (so that the sender can reuse it). Cc: Paul Walmsley Cc: Palmer Dabbelt Cc: Borislav Petkov Cc: Damien Le Moal Cc: Peng Fan Cc: Shawn Guo Reviewed-by: Mark Gross Signed-off-by: Daniele Alessandrelli Signed-off-by: Mark Gross --- MAINTAINERS |8 + drivers/soc/Kconfig |1 + drivers/soc/Makefile |1 + drivers/soc/intel/Kconfig | 18 + drivers/soc/intel/Makefile|4 + drivers/soc/intel/keembay-ipc.c | 1364 + include/linux/soc/intel/keembay-ipc.h | 30 + 7 files changed, 1426 insertions(+) create mode 100644 drivers/soc/intel/Kconfig create mode 100644 drivers/soc/intel/Makefile create mode 100644 drivers/soc/intel/keembay-ipc.c create mode 100644 include/linux/soc/intel/keembay-ipc.h diff --git a/MAINTAINERS b/MAINTAINERS index a88f5eb35e39..bb39711065a4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9058,6 +9058,14 @@ F: drivers/crypto/keembay/keembay-ocs-aes-core.c F: drivers/crypto/keembay/ocs-aes.c F: drivers/crypto/keembay/ocs-aes.h +INTEL KEEM BAY IPC DRIVER +M: Daniele Alessandrelli +M: Mark Gross +S: Supported +F: Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml +F: drivers/soc/intel/keembay-ipc.c +F: include/linux/soc/intel/keembay-ipc.h + INTEL MANAGEMENT ENGINE (mei) M: Tomas Winkler L: linux-kernel@vger.kernel.org diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index d097d070f579..b9d69a1eedc7 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -8,6 +8,7 @@ source "drivers/soc/atmel/Kconfig" source "drivers/soc/bcm/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/imx/Kconfig" +source "drivers/soc/intel/Kconfig" source "drivers/soc/ixp4xx/Kconfig" source "drivers/soc/litex/Kconfig" source "drivers/soc/mediatek/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 699b758d28e4..1a6c00d2e32e 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_MACH_DOVE) += dove/ obj-y += fsl/ obj-$(CONFIG_ARCH_GEMINI) += gemini/ obj-y += imx/ +obj-y += intel/ obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/ diff --git a/drivers/soc/intel/Kconfig b/drivers/soc/intel/Kconfig new file mode 100644 index ..a575e31e47b4 --- /dev/null +++ b/drivers/soc/intel/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Keem Bay SoC drivers +# + +menu "Intel SoC drivers" +
[PATCH v6 17/34] xlink-ipc: Add xlink ipc device tree bindings
From: Seamus Kelly
Add device tree bindings for the xLink IPC driver which enables xLink to
control and communicate with the VPU IP present on the Intel Keem Bay
SoC.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Seamus Kelly
---
.../misc/intel,keembay-xlink-ipc.yaml | 51 +++
1 file changed, 51 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/intel,keembay-xlink-ipc.yaml
diff --git
a/Documentation/devicetree/bindings/misc/intel,keembay-xlink-ipc.yaml
b/Documentation/devicetree/bindings/misc/intel,keembay-xlink-ipc.yaml
new file mode 100644
index ..70a3061d024d
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,keembay-xlink-ipc.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) Intel Corporation. All rights reserved.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/intel,keembay-xlink-ipc.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel Keem Bay xlink IPC
+
+maintainers:
+ - Kelly Seamus
+
+description: |
+ The Keem Bay xlink IPC driver enables the communication/control sub-system
+ for internal IPC communications within the Intel Keem Bay SoC.
+
+properties:
+ compatible:
+oneOf:
+ - items:
+ - const: intel,keembay-xlink-ipc
+
+ memory-region:
+items:
+ - description: reference to the CSS xlink IPC reserved memory region.
+ - description: reference to the MSS xlink IPC reserved memory region.
+
+ intel,keembay-vpu-ipc-id:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description: The numeric ID identifying the VPU within the xLink stack.
+
+ intel,keembay-vpu-ipc-name:
+$ref: "/schemas/types.yaml#/definitions/string"
+description: User-friendly name for the VPU within the xLink stack.
+
+ intel,keembay-vpu-ipc:
+$ref: "/schemas/types.yaml#/definitions/phandle"
+description: reference to the corresponding intel,keembay-vpu-ipc node.
+
+additionalProperties: False
+
+examples:
+ - |
+xlink-ipc {
+compatible = "intel,keembay-xlink-ipc";
+memory-region = <&css_xlink_reserved>,
+<&mss_xlink_reserved>;
+intel,keembay-vpu-ipc-id = <0x0>;
+intel,keembay-vpu-ipc-name = "vpu-slice-0";
+intel,keembay-vpu-ipc = <&vpuipc>;
+};
--
2.17.1
[PATCH v6 32/34] dt-bindings: misc: hddl_dev: Add hddl device management documentation
From: "C, Udhayakumar"
Add hddl device management documentation
The HDDL client driver acts as an software RTC to sync with network time.
It abstracts xlink protocol to communicate with remote IA host.
This driver exports the details about sensors available in the platform
to remote IA host as xlink packets.
This driver also handles device connect/disconnect events and identifies
board id and soc id using gpio's based on platform configuration.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
.../bindings/misc/intel,hddl-client.yaml | 117 ++
1 file changed, 117 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/intel,hddl-client.yaml
diff --git a/Documentation/devicetree/bindings/misc/intel,hddl-client.yaml
b/Documentation/devicetree/bindings/misc/intel,hddl-client.yaml
new file mode 100644
index ..522b461663b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,hddl-client.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/intel,hddl-client.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel hddl client device to handle platform management in Bay series
+
+maintainers:
+ - Udhayakumar C
+
+description: |
+ The HDDL client driver acts as an software RTC to sync with network time.
+ It abstracts xlink protocol to communicate with remote host. This driver
+ exports the details about sensors available in the platform to remote
+ host as xlink packets.
+ This driver also handles device connect/disconnect events and identifies
+ board id and soc id using gpio's based on platform configuration.
+
+select: false
+
+properties:
+ compatible:
+items:
+ - const: intel,hddl-client
+
+ reg:
+minItems: 4
+maxItems: 4
+
+ xlink_chan:
+minItems: 1
+maxItems: 1
+description: xlink channel number used for communication
+ with remote host for time sync and sharing sensor
+ details available in platform.
+
+ i2c_xlink_chan:
+minItems: 1
+maxItems: 1
+description: xlink channel number used for communication
+ with remote host for xlink i2c smbus.
+
+ sensor_name:
+type: object
+description:
+ Details about sensors and its configuration on local host and remote
+ host.
+
+properties:
+ compatible:
+items:
+ - const: intel_tsens
+
+ reg:
+description: i2c slave address for sensor.
+
+ local-host:
+minItems: 1
+maxItems: 1
+description: enable bit 0 to register sensor as i2c slave
+ in local host (normal i2c client)
+ enable bit 1 to mimic sensor as i2c slave
+ in local host (onchip sensors as i2c slave)
+ enable bit 2 to register i2c slave as xlink smbus slave
+ in local host.
+ remote-host:
+minItems: 1
+maxItems: 1
+description: enable bit 0 to register sensor as i2c slave
+ in remote host (normal i2c client)
+ enable bit 1 to mimic sensor as i2c slave
+ in remote host (onchip sensors as i2c slave)
+ enable bit 2 to register i2c slave as xlink smbus slave
+ in remote host.
+
+ bus:
+minItems: 1
+maxItems: 1
+description: i2c bus number for the i2c client device.
+
+required:
+ - compatible
+ - reg
+ - local-host
+ - remote-host
+ - bus
+
+required:
+ - compatible
+ - reg
+ - xlink_chan
+ - i2c_xlink_chan
+
+additionalProperties: false
+
+examples:
+ - |
+hddl_dev{
+#address-cells = <2>;
+#size-cells = <2>;
+
+hddl@2032 {
+compatible = "intel,hddl-client";
+status = "disabled";
+reg = <0x0 0x2032 0x0 0x800>;
+xlink_chan = <1080>;
+i2c_xlink_chan = <1081>;
+kmb_xlink_tj {
+ status = "okay";
+ compatible = "intel_tsens";
+ local-host = <0x3>;
+ remote-host = <0x3>;
+ bus = <0x1>;
+};
+};
+};
--
2.17.1
[PATCH v6 13/34] misc: xlink-pcie: rh: Add PCIe EP driver for Remote Host
From: Srikanth Thokala
Add PCIe Endpoint driver that configures PCIe BARs and MSIs on the
Remote Host
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
MAINTAINERS | 2 +-
drivers/misc/xlink-pcie/Kconfig | 11 +
drivers/misc/xlink-pcie/Makefile | 1 +
drivers/misc/xlink-pcie/common/xpcie.h | 1 +
drivers/misc/xlink-pcie/remote_host/Makefile | 3 +
drivers/misc/xlink-pcie/remote_host/main.c | 90
drivers/misc/xlink-pcie/remote_host/pci.c| 449 +++
drivers/misc/xlink-pcie/remote_host/pci.h| 62 +++
8 files changed, 618 insertions(+), 1 deletion(-)
create mode 100644 drivers/misc/xlink-pcie/remote_host/Makefile
create mode 100644 drivers/misc/xlink-pcie/remote_host/main.c
create mode 100644 drivers/misc/xlink-pcie/remote_host/pci.c
create mode 100644 drivers/misc/xlink-pcie/remote_host/pci.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3a7fe50f17a9..b42a432dc667 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1961,7 +1961,7 @@ F:
Documentation/devicetree/bindings/arm/intel,keembay.yaml
F: arch/arm64/boot/dts/intel/keembay-evm.dts
F: arch/arm64/boot/dts/intel/keembay-soc.dtsi
-ARM KEEM BAY XLINK PCIE SUPPORT
+ARM/INTEL KEEM BAY XLINK PCIE SUPPORT
M: Srikanth Thokala
M: Mark Gross
S: Supported
diff --git a/drivers/misc/xlink-pcie/Kconfig b/drivers/misc/xlink-pcie/Kconfig
index 46aa401d79b7..448b9bfbdfa2 100644
--- a/drivers/misc/xlink-pcie/Kconfig
+++ b/drivers/misc/xlink-pcie/Kconfig
@@ -1,3 +1,14 @@
+config XLINK_PCIE_RH_DRIVER
+ tristate "XLink PCIe Remote Host driver"
+ depends on PCI && X86_64
+ help
+ This option enables XLink PCIe Remote Host driver.
+
+ Choose M here to compile this driver as a module, name is mxlk.
+ This driver is used for XLink communication over PCIe,
+ and is to be loaded on the IA host which is connected to
+ the Intel Keem Bay.
+
config XLINK_PCIE_LH_DRIVER
tristate "XLink PCIe Local Host driver"
depends on PCI_ENDPOINT && ARCH_KEEMBAY
diff --git a/drivers/misc/xlink-pcie/Makefile b/drivers/misc/xlink-pcie/Makefile
index d693d382e9c6..1dd984d8d88c 100644
--- a/drivers/misc/xlink-pcie/Makefile
+++ b/drivers/misc/xlink-pcie/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_XLINK_PCIE_RH_DRIVER) += remote_host/
obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += local_host/
diff --git a/drivers/misc/xlink-pcie/common/xpcie.h
b/drivers/misc/xlink-pcie/common/xpcie.h
index 48529eb49be0..b5cf9242a59a 100644
--- a/drivers/misc/xlink-pcie/common/xpcie.h
+++ b/drivers/misc/xlink-pcie/common/xpcie.h
@@ -69,6 +69,7 @@ struct xpcie_mmio {
struct xpcie {
u32 status;
bool legacy_a0;
+ void *bar0;
void *mmio;
void *bar4;
diff --git a/drivers/misc/xlink-pcie/remote_host/Makefile
b/drivers/misc/xlink-pcie/remote_host/Makefile
new file mode 100644
index ..96374a43023e
--- /dev/null
+++ b/drivers/misc/xlink-pcie/remote_host/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_XLINK_PCIE_RH_DRIVER) += mxlk.o
+mxlk-objs := main.o
+mxlk-objs += pci.o
diff --git a/drivers/misc/xlink-pcie/remote_host/main.c
b/drivers/misc/xlink-pcie/remote_host/main.c
new file mode 100644
index ..ed1a431ed5d4
--- /dev/null
+++ b/drivers/misc/xlink-pcie/remote_host/main.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include "pci.h"
+#include "../common/core.h"
+
+#define HW_ID_LO_MASK GENMASK(7, 0)
+#define HW_ID_HI_MASK GENMASK(15, 8)
+
+static const struct pci_device_id xpcie_pci_table[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KEEMBAY), 0 },
+ { 0 }
+};
+
+static int intel_xpcie_probe(struct pci_dev *pdev,
+const struct pci_device_id *ent)
+{
+ bool new_device = false;
+ struct xpcie_dev *xdev;
+ u32 sw_devid;
+ u16 hw_id;
+ int ret;
+
+ hw_id = FIELD_PREP(HW_ID_HI_MASK, pdev->bus->number) |
+ FIELD_PREP(HW_ID_LO_MASK, PCI_SLOT(pdev->devfn));
+
+ sw_devid = FIELD_PREP(XLINK_DEV_INF_TYPE_MASK,
+ XLINK_DEV_INF_PCIE) |
+ FIELD_PREP(XLINK_DEV_PHYS_ID_MASK, hw_id) |
+ FIELD_PREP(XLINK_DEV_TYPE_MASK, XLINK_DEV_TYPE_KMB) |
+ FIELD_PREP(XLINK_DEV_PCIE_ID_MASK, XLINK_DEV_PCIE_0) |
+ FIELD_PREP(XLINK_DEV_FUNC_MASK, XLINK_DEV_FUNC_VPU);
+
+ xdev = intel_xpcie_get_device_by_id(sw_devid);
+ if (!xdev) {
+ xdev = intel_xpcie_create_device(sw_devid, pdev);
+ if (!xdev)
+ return -ENOMEM;
+
+ new_device = true;
+ }
+
+ ret = intel_xpcie_pci_init(xdev, pdev);
+ if (ret) {
+ intel_xpci
[PATCH v6 34/34] misc: HDDL device management for IA host
From: "C, Udhayakumar"
Add IA host hddl device management driver for Intel Edge.AI Computer Vision
platforms.
About Intel Edge.AI Computer Vision platforms:
-
The Intel Edge.AI Computer Vision platforms are vision processing systems
targeting machine vision applications for connected devices.
They are based on ARM A53 CPU running Linux and acts as a PCIe
endpoint device.
High-level architecture:
Remote Host IA CPU Local Host ARM CPU
---
| * Send time as xlink packet | |* Sync time with IA host |
| * receive sensor details| |* Prepare and share sensor|
| and register as i2c or| | details to IA host as |
| xlink smbus slaves| | xlink packets |
---
| hddl server | <=> | hddl client |
--- xlink
hddl device module:
---
The HDDL client driver acts as an software RTC to sync with network
time. It abstracts xlink protocol to communicate with remote host.
This driver exports the details about sensors available in the
platform to remote host as xlink packets.
This driver also handles device connect/disconnect events and
identifies board id and soc id using gpio's, based on platform
configuration.
- Remote Host driver
* Intended for IA CPU
* It is based on xlink Framework
* Driver path:
{tree}/drivers/misc/hddl_device/hddl_device_server.c
Local arm host and Remote IA host drivers communicates using
XLINK protocol.
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
.../misc-devices/hddl_device_server.rst | 205 +
Documentation/misc-devices/index.rst | 1 +
drivers/misc/hddl_device/Kconfig | 12 +
drivers/misc/hddl_device/Makefile | 2 +
drivers/misc/hddl_device/hddl_device_rh.c | 837 ++
5 files changed, 1057 insertions(+)
create mode 100644 Documentation/misc-devices/hddl_device_server.rst
create mode 100644 drivers/misc/hddl_device/hddl_device_rh.c
diff --git a/Documentation/misc-devices/hddl_device_server.rst
b/Documentation/misc-devices/hddl_device_server.rst
new file mode 100644
index ..0be37973d1fe
--- /dev/null
+++ b/Documentation/misc-devices/hddl_device_server.rst
@@ -0,0 +1,205 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Kernel driver: hddl_device_server
+=
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+
+Authors:
+- Thalaiappan, Rathina
+- Udhayakumar C
+
+High-level architecture
+===
+::
+
+Remote Host IA CPU Local Host ARM CPU
+---
+| * Send time as xlink packet | |* Sync time with IA host |
+| * receive sensor details| |* Prepare and share sensor|
+| and register as i2c or| | details to IA host as |
+| xlink smbus slaves| | xlink packets |
+---
+| hddl server | <=> | hddl client |
+--- xlink
+
+Overview
+
+
+This driver supports hddl device management for Intel Edge.AI Computer Vision
+platforms. This driver runs in IA host
+
+This driver supports the following features:
+
+ - Receives deatils of temperature sensor, current sensor and fan controller
+present in Intel Edge.AI Computer Vision platforms.
+ - Send Time sync data to Intel Edge.AI Computer Vision platform.
+ - Handles device connect and disconnect events.
+ - Get free slave address for memory mapped thermal sensors present in SoC
+(Documentation/hwmon/intel_tsens_sensors.rst) and share it with Intel
+Edge.AI Computer Vision platform.
+ - Registers i2c slave device for slaves present in Intel Edge.AI Computer
+Vision platform
+
+Keem Bay platform has
+Onchip sensors:
+
+ - Media Subsystem (mss) temperature sensor
+ - NN subsystem (nce) temperature sensor
+ - Compute subsystem (cse) temperature sensor
+ - SOC(Maximum of mss, nce and cse).
+
+Onboard sensors:
+
+ - two lm75 temperature sensors
+ - emc2103 fan controller
+ - ina3221 current sensor
+
+Driver Structure
+
+
+The driver provides a platform device where the ``probe`` and ``remove``
+operations are provided.
+
+ - probe: spawn kernel thread to monitor new PCIE devices.
+
+ - init task: Poll for new PCIE device with time interval of 5 seconds and
+creates connect task to setup new device.
+
+ - connect task: Connect task is the main entity which connects to hd
[PATCH v6 09/34] misc: xlink-pcie: lh: Add PCIe EPF driver for Local Host
From: Srikanth Thokala
Add PCIe EPF driver for local host (lh) to configure BAR's and other
HW resources. Underlying PCIe HW controller is a Synopsys DWC PCIe core.
Cc: Derek Kiernan
Cc: Dragan Cvetic
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
MAINTAINERS | 6 +
drivers/misc/Kconfig| 1 +
drivers/misc/Makefile | 1 +
drivers/misc/xlink-pcie/Kconfig | 9 +
drivers/misc/xlink-pcie/Makefile| 1 +
drivers/misc/xlink-pcie/local_host/Makefile | 2 +
drivers/misc/xlink-pcie/local_host/epf.c| 373
drivers/misc/xlink-pcie/local_host/epf.h| 37 ++
drivers/misc/xlink-pcie/local_host/xpcie.h | 38 ++
9 files changed, 468 insertions(+)
create mode 100644 drivers/misc/xlink-pcie/Kconfig
create mode 100644 drivers/misc/xlink-pcie/Makefile
create mode 100644 drivers/misc/xlink-pcie/local_host/Makefile
create mode 100644 drivers/misc/xlink-pcie/local_host/epf.c
create mode 100644 drivers/misc/xlink-pcie/local_host/epf.h
create mode 100644 drivers/misc/xlink-pcie/local_host/xpcie.h
diff --git a/MAINTAINERS b/MAINTAINERS
index c18640ae6955..3a7fe50f17a9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1961,6 +1961,12 @@ F:
Documentation/devicetree/bindings/arm/intel,keembay.yaml
F: arch/arm64/boot/dts/intel/keembay-evm.dts
F: arch/arm64/boot/dts/intel/keembay-soc.dtsi
+ARM KEEM BAY XLINK PCIE SUPPORT
+M: Srikanth Thokala
+M: Mark Gross
+S: Supported
+F: drivers/misc/xlink-pcie/
+
ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
M: Jonathan Cameron
L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index fafa8b0d8099..dfb98e444c6e 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -481,4 +481,5 @@ source "drivers/misc/ocxl/Kconfig"
source "drivers/misc/cardreader/Kconfig"
source "drivers/misc/habanalabs/Kconfig"
source "drivers/misc/uacce/Kconfig"
+source "drivers/misc/xlink-pcie/Kconfig"
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index d23231e73330..d17621fc43d5 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/
obj-$(CONFIG_UACCE)+= uacce/
obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
+obj-y += xlink-pcie/
diff --git a/drivers/misc/xlink-pcie/Kconfig b/drivers/misc/xlink-pcie/Kconfig
new file mode 100644
index ..46aa401d79b7
--- /dev/null
+++ b/drivers/misc/xlink-pcie/Kconfig
@@ -0,0 +1,9 @@
+config XLINK_PCIE_LH_DRIVER
+ tristate "XLink PCIe Local Host driver"
+ depends on PCI_ENDPOINT && ARCH_KEEMBAY
+ help
+ This option enables XLink PCIe Local Host driver.
+
+ Choose M here to compile this driver as a module, name is mxlk_ep.
+ This driver is used for XLink communication over PCIe and is to be
+ loaded on the Intel Keem Bay platform.
diff --git a/drivers/misc/xlink-pcie/Makefile b/drivers/misc/xlink-pcie/Makefile
new file mode 100644
index ..d693d382e9c6
--- /dev/null
+++ b/drivers/misc/xlink-pcie/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += local_host/
diff --git a/drivers/misc/xlink-pcie/local_host/Makefile
b/drivers/misc/xlink-pcie/local_host/Makefile
new file mode 100644
index ..514d3f0c91bc
--- /dev/null
+++ b/drivers/misc/xlink-pcie/local_host/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o
+mxlk_ep-objs := epf.o
diff --git a/drivers/misc/xlink-pcie/local_host/epf.c
b/drivers/misc/xlink-pcie/local_host/epf.c
new file mode 100644
index ..0234756e89ae
--- /dev/null
+++ b/drivers/misc/xlink-pcie/local_host/epf.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include
+#include
+
+#include "epf.h"
+
+#define BAR2_MIN_SIZE SZ_16K
+#define BAR4_MIN_SIZE SZ_16K
+
+#define PCIE_REGS_PCIE_INTR_ENABLE 0x18
+#define PCIE_REGS_PCIE_INTR_FLAGS 0x1C
+#define LBC_CII_EVENT_FLAG BIT(18)
+#define PCIE_REGS_PCIE_ERR_INTR_FLAGS 0x24
+#define LINK_REQ_RST_FLG BIT(15)
+
+static struct pci_epf_header xpcie_header = {
+ .vendorid = PCI_VENDOR_ID_INTEL,
+ .deviceid = PCI_DEVICE_ID_INTEL_KEEMBAY,
+ .baseclass_code = PCI_BASE_CLASS_MULTIMEDIA,
+ .subclass_code = 0x0,
+ .subsys_vendor_id = 0x0,
+ .subsys_id = 0x0,
+};
+
+static const struct pci_epf_device_id xpcie_epf_ids[] = {
+ {
+ .name = "mxlk_pcie_epf",
+ },
+ {},
+};
+
+static irqreturn_t intel_xpcie_err_interrupt(int
[PATCH v6 10/34] misc: xlink-pcie: lh: Add PCIe EP DMA functionality
From: Srikanth Thokala Add Synopsys PCIe DWC core embedded-DMA functionality for local host Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Reviewed-by: Mark Gross Signed-off-by: Mark Gross Signed-off-by: Srikanth Thokala --- drivers/misc/xlink-pcie/local_host/Makefile | 1 + drivers/misc/xlink-pcie/local_host/dma.c| 575 drivers/misc/xlink-pcie/local_host/epf.c| 15 +- drivers/misc/xlink-pcie/local_host/epf.h| 41 ++ 4 files changed, 629 insertions(+), 3 deletions(-) create mode 100644 drivers/misc/xlink-pcie/local_host/dma.c diff --git a/drivers/misc/xlink-pcie/local_host/Makefile b/drivers/misc/xlink-pcie/local_host/Makefile index 514d3f0c91bc..54fc118e2dd1 100644 --- a/drivers/misc/xlink-pcie/local_host/Makefile +++ b/drivers/misc/xlink-pcie/local_host/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o mxlk_ep-objs := epf.o +mxlk_ep-objs += dma.o diff --git a/drivers/misc/xlink-pcie/local_host/dma.c b/drivers/misc/xlink-pcie/local_host/dma.c new file mode 100644 index ..42978fb0db49 --- /dev/null +++ b/drivers/misc/xlink-pcie/local_host/dma.c @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Keem Bay XLink PCIe Driver + * + * Copyright (C) 2021 Intel Corporation + */ +#include +#include +#include + +#include "epf.h" + +#define DMA_DBI_OFFSET (0x38) + +/* PCIe DMA control 1 register definitions. */ +#define DMA_CH_CONTROL1_CB_SHIFT (0) +#define DMA_CH_CONTROL1_TCB_SHIFT (1) +#define DMA_CH_CONTROL1_LLP_SHIFT (2) +#define DMA_CH_CONTROL1_LIE_SHIFT (3) +#define DMA_CH_CONTROL1_CS_SHIFT (5) +#define DMA_CH_CONTROL1_CCS_SHIFT (8) +#define DMA_CH_CONTROL1_LLE_SHIFT (9) +#define DMA_CH_CONTROL1_CB_MASK(BIT(DMA_CH_CONTROL1_CB_SHIFT)) +#define DMA_CH_CONTROL1_TCB_MASK (BIT(DMA_CH_CONTROL1_TCB_SHIFT)) +#define DMA_CH_CONTROL1_LLP_MASK (BIT(DMA_CH_CONTROL1_LLP_SHIFT)) +#define DMA_CH_CONTROL1_LIE_MASK (BIT(DMA_CH_CONTROL1_LIE_SHIFT)) +#define DMA_CH_CONTROL1_CS_MASK(0x3 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CCS_MASK (BIT(DMA_CH_CONTROL1_CCS_SHIFT)) +#define DMA_CH_CONTROL1_LLE_MASK (BIT(DMA_CH_CONTROL1_LLE_SHIFT)) + +/* DMA control 1 register Channel Status */ +#define DMA_CH_CONTROL1_CS_RUNNING (0x1 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CS_HALTED (0x2 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CS_STOPPED (0x3 << DMA_CH_CONTROL1_CS_SHIFT) + +/* PCIe DMA Engine enable register definitions. */ +#define DMA_ENGINE_EN_SHIFT(0) +#define DMA_ENGINE_EN_MASK (BIT(DMA_ENGINE_EN_SHIFT)) + +/* PCIe DMA interrupt registers definitions. */ +#define DMA_ABORT_INTERRUPT_SHIFT (16) +#define DMA_ABORT_INTERRUPT_MASK (0xFF << DMA_ABORT_INTERRUPT_SHIFT) +#define DMA_ABORT_INTERRUPT_CH_MASK(_c) (BIT(_c) << DMA_ABORT_INTERRUPT_SHIFT) +#define DMA_DONE_INTERRUPT_MASK(0xFF) +#define DMA_DONE_INTERRUPT_CH_MASK(_c) (BIT(_c)) +#define DMA_ALL_INTERRUPT_MASK \ + (DMA_ABORT_INTERRUPT_MASK | DMA_DONE_INTERRUPT_MASK) + +#define DMA_LL_ERROR_SHIFT (16) +#define DMA_CPL_ABORT_SHIFT(8) +#define DMA_CPL_TIMEOUT_SHIFT (16) +#define DMA_DATA_POI_SHIFT (24) +#define DMA_AR_ERROR_CH_MASK(_c) (BIT(_c)) +#define DMA_LL_ERROR_CH_MASK(_c) (BIT(_c) << DMA_LL_ERROR_SHIFT) +#define DMA_UNREQ_ERROR_CH_MASK(_c)(BIT(_c)) +#define DMA_CPL_ABORT_ERROR_CH_MASK(_c)(BIT(_c) << DMA_CPL_ABORT_SHIFT) +#define DMA_CPL_TIMEOUT_ERROR_CH_MASK(_c) (BIT(_c) << DMA_CPL_TIMEOUT_SHIFT) +#define DMA_DATA_POI_ERROR_CH_MASK(_c) (BIT(_c) << DMA_DATA_POI_SHIFT) + +#define DMA_LLLAIE_SHIFT (16) +#define DMA_LLLAIE_MASK(0xF << DMA_LLLAIE_SHIFT) + +#define DMA_CHAN_WRITE_MAX_WEIGHT (0x7) +#define DMA_CHAN_READ_MAX_WEIGHT (0x3) +#define DMA_CHAN0_WEIGHT_OFFSET(0) +#define DMA_CHAN1_WEIGHT_OFFSET(5) +#define DMA_CHAN2_WEIGHT_OFFSET(10) +#define DMA_CHAN3_WEIGHT_OFFSET(15) +#define DMA_CHAN_WRITE_ALL_MAX_WEIGHT \ + ((DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN0_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN1_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN2_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN3_WEIGHT_OFFSET)) +#define DMA_CHAN_READ_ALL_MAX_WEIGHT \ + ((DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN0_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN1_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN2_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN3_WEIGHT_OFFSET)) + +#define PCIE_REGS_PCIE_APP_CNTRL 0x8 +#define APP_XFER_PENDING BIT(6) +#def
[PATCH v6 15/34] misc: xlink-pcie: Add XLink API interface
From: Srikanth Thokala
Provide interface for XLink layer to interact with XLink PCIe transport
layer on both local host and remote host.
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/common/interface.c | 107 +++
drivers/misc/xlink-pcie/local_host/Makefile | 1 +
drivers/misc/xlink-pcie/remote_host/Makefile | 1 +
3 files changed, 109 insertions(+)
create mode 100644 drivers/misc/xlink-pcie/common/interface.c
diff --git a/drivers/misc/xlink-pcie/common/interface.c
b/drivers/misc/xlink-pcie/common/interface.c
new file mode 100644
index ..fcc69a940a4c
--- /dev/null
+++ b/drivers/misc/xlink-pcie/common/interface.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include
+
+#include "core.h"
+#include "xpcie.h"
+
+/* Define xpcie driver interface API */
+int xlink_pcie_get_device_list(u32 *sw_device_id_list, u32 *num_devices)
+{
+ if (!sw_device_id_list || !num_devices)
+ return -EINVAL;
+
+ *num_devices = intel_xpcie_get_device_num(sw_device_id_list);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_list);
+
+int xlink_pcie_get_device_name(u32 sw_device_id, char *device_name,
+ size_t name_size)
+{
+ if (!device_name)
+ return -EINVAL;
+
+ return intel_xpcie_get_device_name_by_id(sw_device_id,
+device_name, name_size);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_name);
+
+int xlink_pcie_get_device_status(u32 sw_device_id, u32 *device_status)
+{
+ u32 status;
+ int rc;
+
+ if (!device_status)
+ return -EINVAL;
+
+ rc = intel_xpcie_get_device_status_by_id(sw_device_id, &status);
+ if (rc)
+ return rc;
+
+ switch (status) {
+ case XPCIE_STATUS_READY:
+ case XPCIE_STATUS_RUN:
+ *device_status = _XLINK_DEV_READY;
+ break;
+ case XPCIE_STATUS_ERROR:
+ *device_status = _XLINK_DEV_ERROR;
+ break;
+ case XPCIE_STATUS_RECOVERY:
+ *device_status = _XLINK_DEV_RECOVERY;
+ break;
+ case XPCIE_STATUS_OFF:
+ *device_status = _XLINK_DEV_OFF;
+ break;
+ default:
+ *device_status = _XLINK_DEV_BUSY;
+ break;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_status);
+
+int xlink_pcie_boot_device(u32 sw_device_id, const char *binary_name)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_boot_device);
+
+int xlink_pcie_connect(u32 sw_device_id)
+{
+ return intel_xpcie_pci_connect_device(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_connect);
+
+int xlink_pcie_read(u32 sw_device_id, void *data, size_t *const size,
+ u32 timeout)
+{
+ if (!data || !size)
+ return -EINVAL;
+
+ return intel_xpcie_pci_read(sw_device_id, data, size, timeout);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_read);
+
+int xlink_pcie_write(u32 sw_device_id, void *data, size_t *const size,
+u32 timeout)
+{
+ if (!data || !size)
+ return -EINVAL;
+
+ return intel_xpcie_pci_write(sw_device_id, data, size, timeout);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_write);
+
+int xlink_pcie_reset_device(u32 sw_device_id)
+{
+ return intel_xpcie_pci_reset_device(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_reset_device);
diff --git a/drivers/misc/xlink-pcie/local_host/Makefile
b/drivers/misc/xlink-pcie/local_host/Makefile
index 65df94c7e860..16bb1e7345ac 100644
--- a/drivers/misc/xlink-pcie/local_host/Makefile
+++ b/drivers/misc/xlink-pcie/local_host/Makefile
@@ -3,3 +3,4 @@ mxlk_ep-objs := epf.o
mxlk_ep-objs += dma.o
mxlk_ep-objs += core.o
mxlk_ep-objs += ../common/util.o
+mxlk_ep-objs += ../common/interface.o
diff --git a/drivers/misc/xlink-pcie/remote_host/Makefile
b/drivers/misc/xlink-pcie/remote_host/Makefile
index e8074dbb1161..088e121ad46e 100644
--- a/drivers/misc/xlink-pcie/remote_host/Makefile
+++ b/drivers/misc/xlink-pcie/remote_host/Makefile
@@ -3,3 +3,4 @@ mxlk-objs := main.o
mxlk-objs += pci.o
mxlk-objs += core.o
mxlk-objs += ../common/util.o
+mxlk-objs += ../common/interface.o
--
2.17.1
[PATCH v6 00/34] Intel Vision Processing base enabling
From: Mark Gross The Intel Vision Processing Unit (VPU) is an IP block that is showing up for the first time as part of the Keem Bay SOC. Keem Bay is a quad core A53 Arm SOC. It is designed to be used as a stand alone SOC as well as in an PCIe Vision Processing accelerator add in card. This 6th version of this patch set includes more updates to the xlink SMBUS patch correction some language in its Kconfig file. At the bottom of this cover letter is the delta between v5 and this version for easy review of the modifications. Thanks for looking at these and providing feedback. C, Udhayakumar (8): dt-bindings: misc: intel_tsens: Add tsens thermal bindings documentation misc: Tsens ARM host thermal driver. misc: Intel tsens IA host driver. Intel tsens i2c slave driver. misc:intel_tsens: Intel Keem Bay tsens driver. dt-bindings: misc: hddl_dev: Add hddl device management documentation misc: Hddl device management for local host misc: HDDL device management for IA host Daniele Alessandrelli (4): dt-bindings: mailbox: Add Intel VPU IPC mailbox bindings mailbox: vpu-ipc-mailbox: Add support for Intel VPU IPC mailbox dt-bindings: Add bindings for Keem Bay IPC driver keembay-ipc: Add Keem Bay IPC module Li, Tingqian (2): dt-bindings: misc: Add Keem Bay vpumgr misc: Add Keem Bay VPU manager Paul Murphy (2): dt-bindings: Add bindings for Keem Bay VPU IPC driver keembay-vpu-ipc: Add Keem Bay VPU IPC module Ramya P Karanth (1): Intel Keembay XLink SMBus driver Seamus Kelly (7): xlink-ipc: Add xlink ipc device tree bindings xlink-ipc: Add xlink ipc driver xlink-core: Add xlink core device tree bindings xlink-core: Add xlink core driver xLink xlink-core: Enable xlink protocol over pcie xlink-core: Enable VPU IP management and runtime control xlink-core: add async channel and events Srikanth Thokala (9): misc: xlink-pcie: Add documentation for XLink PCIe driver misc: xlink-pcie: lh: Add PCIe EPF driver for Local Host misc: xlink-pcie: lh: Add PCIe EP DMA functionality misc: xlink-pcie: lh: Add core communication logic misc: xlink-pcie: lh: Prepare changes for adding remote host driver misc: xlink-pcie: rh: Add PCIe EP driver for Remote Host misc: xlink-pcie: rh: Add core communication logic misc: xlink-pcie: Add XLink API interface misc: xlink-pcie: Add asynchronous event notification support for XLink mark gross (1): Add Vision Processing Unit (VPU) documentation. .../mailbox/intel,vpu-ipc-mailbox.yaml| 69 + .../bindings/misc/intel,hddl-client.yaml | 117 + .../bindings/misc/intel,intel-tsens.yaml | 122 + .../bindings/misc/intel,keembay-vpu-mgr.yaml | 48 + .../misc/intel,keembay-xlink-ipc.yaml | 51 + .../bindings/misc/intel,keembay-xlink.yaml| 29 + .../bindings/soc/intel/intel,keembay-ipc.yaml | 45 + .../soc/intel/intel,keembay-vpu-ipc.yaml | 143 ++ Documentation/hwmon/index.rst |2 + Documentation/hwmon/intel_tsens_host.rst | 71 + Documentation/hwmon/intel_tsens_sensor.rst| 67 + Documentation/i2c/busses/index.rst|1 + .../i2c/busses/intel-xlink-smbus.rst | 71 + Documentation/index.rst |1 + .../misc-devices/hddl_device_client.rst | 212 ++ .../misc-devices/hddl_device_server.rst | 205 ++ Documentation/misc-devices/index.rst |2 + Documentation/vpu/index.rst | 20 + Documentation/vpu/vpu-stack-overview.rst | 270 +++ Documentation/vpu/xlink-core.rst | 81 + Documentation/vpu/xlink-ipc.rst | 51 + Documentation/vpu/xlink-pcie.rst | 90 + MAINTAINERS | 54 + drivers/mailbox/Kconfig | 11 + drivers/mailbox/Makefile |2 + drivers/mailbox/vpu-ipc-mailbox.c | 297 +++ drivers/misc/Kconfig |7 + drivers/misc/Makefile |7 + drivers/misc/hddl_device/Kconfig | 26 + drivers/misc/hddl_device/Makefile |7 + drivers/misc/hddl_device/hddl_device.c| 565 + drivers/misc/hddl_device/hddl_device_lh.c | 764 +++ drivers/misc/hddl_device/hddl_device_rh.c | 837 +++ drivers/misc/hddl_device/hddl_device_util.h | 52 + drivers/misc/intel_tsens/Kconfig | 54 + drivers/misc/intel_tsens/Makefile | 10 + drivers/misc/intel_tsens/intel_tsens_host.c | 352 +++ drivers/misc/intel_tsens/intel_tsens_i2c.c| 119 + .../misc/intel_tsens/intel_tsens_thermal.c| 651 ++ .../misc/intel_tsens/intel_tsens_thermal.h| 38 + drivers/misc/intel_tsens/keembay_thermal.c| 169 ++ drivers/misc/intel_tsens/keembay_tsens.h | 366 +++ drivers/misc/vpumgr/Kconfig |9 + drivers/misc/vpumgr/Makefile |3 + drivers/misc/vpumg
[PATCH v6 24/34] dt-bindings: misc: Add Keem Bay vpumgr
From: "Li, Tingqian"
Add DT binding schema for VPU on Keem Bay ASoC platform
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Li Tingqian
Signed-off-by: Mark Gross
---
.../bindings/misc/intel,keembay-vpu-mgr.yaml | 48 +++
1 file changed, 48 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/intel,keembay-vpu-mgr.yaml
diff --git a/Documentation/devicetree/bindings/misc/intel,keembay-vpu-mgr.yaml
b/Documentation/devicetree/bindings/misc/intel,keembay-vpu-mgr.yaml
new file mode 100644
index ..a44f492277ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,keembay-vpu-mgr.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright (C) 2020 Intel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/intel,keembay-vpu-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel VPU manager bindings
+
+maintainers:
+ - Li, Tingqian
+ - Zhou, Luwei
+
+description: |
+ The Intel VPU manager provides shared memory and process
+ depedent context management for Intel VPU hardware IP.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - intel,keembay-vpu-mgr
+ - intel,keembay-vpusmm
+
+ memory-region:
+description:
+ phandle to a node describing reserved memory (System RAM memory)
+ used by VPU (see bindings/reserved-memory/reserved-memory.txt)
+maxItems: 1
+
+ intel,keembay-vpu-ipc-id:
+$ref: /schemas/types.yaml#/definitions/uint32
+description:
+ the index of the VPU slice to be managed. Default is 0.
+
+required:
+ - compatible
+ - memory-region
+
+additionalProperties: false
+
+examples:
+ - |
+vpumgr0 {
+compatible = "intel,keembay-vpu-mgr";
+memory-region = <&vpu_reserved>;
+intel,keembay-vpu-ipc-id = <0x0>;
+};
--
2.17.1
[PATCH v6 22/34] xlink-core: Enable VPU IP management and runtime control
From: Seamus Kelly
Enable VPU management including, enumeration, boot and runtime control.
Add APIs:
write control data:
used to transmit small, local data
start vpu:
calls boot_device API ( soon to be deprecated )
stop vpu
calls reset_device API ( soon to be deprecated )
reset vpu
calls reset_device API ( soon to be deprecated )
get device name:
Returns the device name for the input device id
This could be a char device path, for example "/dev/ttyUSB0"
for a serial device; or it could be a device string
description, for example, for PCIE "00:00.0 Host bridge: Intel
Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 01)"
get device list:
Returns the list of software device IDs for all connected
physical devices
get device status:
returns the current state of the input device
OFF - The device is off (D3cold/Slot power removed).
BUSY - device is busy and not available (device is
booting)
READY - device is available for use
ERROR - device HW failure is detected
RECOVERY - device is in recovery mode, waiting for
recovery operations
boot device:
When used on the remote host - starts the SOC device by calling
corresponding function from VPU Driver.
Takes firmware's 'binary_name' as input.
For Linux, the firmware image is expected to be located in
'/lib/firmware' folder or its subfolders.
For Linux, 'binary_name' is not a path but an image name that
will be searched in the default Linux search paths
('/lib/firmware').
When used on the local host - triggers the booting of VPUIP
device.
reset device:
When used on the remote host - resets the device by calling
corresponding VPU Driver function.
When used on the local host - resets the VPUIP device
get device mode:
query and returns the current device power mode
set device mode:
used for device throttling or entering various power modes
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Seamus Kelly
---
drivers/misc/xlink-core/xlink-core.c| 235
drivers/misc/xlink-core/xlink-defs.h| 2 +
drivers/misc/xlink-core/xlink-ioctl.c | 214 ++
drivers/misc/xlink-core/xlink-ioctl.h | 9 +
drivers/misc/xlink-core/xlink-multiplexer.c | 56 +
drivers/misc/xlink-core/xlink-platform.c| 86 +++
include/linux/xlink.h | 27 +++
7 files changed, 629 insertions(+)
diff --git a/drivers/misc/xlink-core/xlink-core.c
b/drivers/misc/xlink-core/xlink-core.c
index bdbf8c6a99ca..d0a3f98d16af 100644
--- a/drivers/misc/xlink-core/xlink-core.c
+++ b/drivers/misc/xlink-core/xlink-core.c
@@ -73,6 +73,8 @@ struct keembay_xlink_dev {
struct mutex lock; // protect access to xlink_dev
};
+static u8 volbuf[XLINK_MAX_BUF_SIZE]; // buffer for volatile transactions
+
/*
* global variable pointing to our xlink device.
*
@@ -264,6 +266,9 @@ static long xlink_ioctl(struct file *file, unsigned int
cmd, unsigned long arg)
case XL_READ_DATA:
rc = ioctl_read_data(arg);
break;
+ case XL_READ_TO_BUFFER:
+ rc = ioctl_read_to_buffer(arg);
+ break;
case XL_WRITE_DATA:
rc = ioctl_write_data(arg);
break;
@@ -276,9 +281,39 @@ static long xlink_ioctl(struct file *file, unsigned int
cmd, unsigned long arg)
case XL_CLOSE_CHANNEL:
rc = ioctl_close_channel(arg);
break;
+ case XL_START_VPU:
+ rc = ioctl_start_vpu(arg);
+ break;
+ case XL_STOP_VPU:
+ rc = xlink_stop_vpu();
+ break;
+ case XL_RESET_VPU:
+ rc = xlink_stop_vpu();
+ break;
case XL_DISCONNECT:
rc = ioctl_disconnect(arg);
break;
+ case XL_GET_DEVICE_NAME:
+ rc = ioctl_get_device_name(arg);
+ break;
+ case XL_GET_DEVICE_LIST:
+ rc = ioctl_get_device_list(arg);
+ break;
+ case XL_GET_DEVICE_STATUS:
+ rc = ioctl_get_device_status(arg);
+ break;
+ case XL_BOOT_DEVICE:
+ rc = ioctl_boot_device(arg);
+ break;
+ case XL_RESET_DEVICE:
+ rc = ioctl_reset_device(arg);
+ break;
+ case XL_GET_DEVIC
[PATCH v6 21/34] xlink-core: Enable xlink protocol over pcie
From: Seamus Kelly
Enable host system access to the VPU over the xlink protocol over PCIe by
enabling channel multiplexing and dispatching. This allows for remote host
communication channels across pcie links.
add dispatcher
update multiplexer to utilise dispatcher
xlink-core: Patch set 2
Add xlink-dispatcher
creates tx and rx threads
enables queueing of messages for transmission and on reception
Update multiplexer to utilise dispatcher:
handle multiplexing channels over single interface link e.g.
PCIe
process messages received by dispatcher
pass messages created by API calls to dispatcher for
transmission
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Seamus Kelly
---
drivers/misc/xlink-core/Makefile| 2 +-
drivers/misc/xlink-core/xlink-core.c| 35 +-
drivers/misc/xlink-core/xlink-dispatcher.c | 441 +
drivers/misc/xlink-core/xlink-dispatcher.h | 26 +
drivers/misc/xlink-core/xlink-multiplexer.c | 498 +++-
5 files changed, 999 insertions(+), 3 deletions(-)
create mode 100644 drivers/misc/xlink-core/xlink-dispatcher.c
create mode 100644 drivers/misc/xlink-core/xlink-dispatcher.h
diff --git a/drivers/misc/xlink-core/Makefile b/drivers/misc/xlink-core/Makefile
index e82b7c72b6b9..ee81f9d05f2b 100644
--- a/drivers/misc/xlink-core/Makefile
+++ b/drivers/misc/xlink-core/Makefile
@@ -2,4 +2,4 @@
# Makefile for Keem Bay xlink Linux driver
#
obj-$(CONFIG_XLINK_CORE) += xlink.o
-xlink-objs += xlink-core.o xlink-multiplexer.o xlink-platform.o xlink-ioctl.o
+xlink-objs += xlink-core.o xlink-multiplexer.o xlink-dispatcher.o
xlink-platform.o xlink-ioctl.o
diff --git a/drivers/misc/xlink-core/xlink-core.c
b/drivers/misc/xlink-core/xlink-core.c
index dd8db834c184..bdbf8c6a99ca 100644
--- a/drivers/misc/xlink-core/xlink-core.c
+++ b/drivers/misc/xlink-core/xlink-core.c
@@ -21,6 +21,7 @@
#include "xlink-core.h"
#include "xlink-defs.h"
+#include "xlink-dispatcher.h"
#include "xlink-ioctl.h"
#include "xlink-multiplexer.h"
#include "xlink-platform.h"
@@ -151,6 +152,12 @@ static int kmb_xlink_probe(struct platform_device *pdev)
goto r_multiplexer;
}
+ // initialize dispatcher
+ rc = xlink_dispatcher_init(xlink_dev->pdev);
+ if (rc != X_LINK_SUCCESS) {
+ pr_err("Dispatcher initialization failed\n");
+ goto r_dispatcher;
+ }
// initialize xlink data structure
xlink_dev->nmb_connected_links = 0;
mutex_init(&xlink_dev->lock);
@@ -168,7 +175,7 @@ static int kmb_xlink_probe(struct platform_device *pdev)
/*Allocating Major number*/
if ((alloc_chrdev_region(&xdev, 0, 1, "xlinkdev")) < 0) {
dev_info(&pdev->dev, "Cannot allocate major number\n");
- goto r_multiplexer;
+ goto r_dispatcher;
}
dev_info(&pdev->dev, "Major = %d Minor = %d\n", MAJOR(xdev),
MINOR(xdev));
@@ -205,6 +212,8 @@ static int kmb_xlink_probe(struct platform_device *pdev)
class_destroy(dev_class);
r_class:
unregister_chrdev_region(xdev, 1);
+r_dispatcher:
+ xlink_dispatcher_destroy();
r_multiplexer:
xlink_multiplexer_destroy();
return -1;
@@ -220,6 +229,10 @@ static int kmb_xlink_remove(struct platform_device *pdev)
rc = xlink_multiplexer_destroy();
if (rc != X_LINK_SUCCESS)
pr_err("Multiplexer destroy failed\n");
+ // stop dispatchers and destroy
+ rc = xlink_dispatcher_destroy();
+ if (rc != X_LINK_SUCCESS)
+ pr_err("Dispatcher destroy failed\n");
mutex_unlock(&xlink->lock);
mutex_destroy(&xlink->lock);
@@ -314,6 +327,14 @@ enum xlink_error xlink_connect(struct xlink_handle *handle)
link->handle = *handle;
xlink->nmb_connected_links++;
kref_init(&link->refcount);
+ if (interface != IPC_INTERFACE) {
+ // start dispatcher
+ rc = xlink_dispatcher_start(link->id, &link->handle);
+ if (rc) {
+ pr_err("dispatcher start failed\n");
+ goto r_cleanup;
+ }
+ }
// initialize multiplexer connection
rc = xlink_multiplexer_connect(link->id);
if (rc) {
@@ -649,6 +670,7 @@ EXPORT_SYMBOL_GPL(xlink_release_data);
enum xlink_error xlink_disconnect(struct xlink_handle *handle)
{
struct xlink_link *link;
+ int interface = NULL_INTERFACE;
enum xlink_error rc = X_LINK_ERROR;
if (!xlink || !handle)
@@ -661,6 +683,17 @@ enum xlink_error xlink_disconnect(struct xlink_handle
*handle)
// decrement refcount, if count i
[PATCH v6 23/34] xlink-core: add async channel and events
From: Seamus Kelly
Enable asynchronous channel and event communication.
Add APIs:
data ready callback:
The xLink Data Ready Callback function is used to
register a callback function that is invoked when data
is ready to be read from a channel
data consumed callback:
The xLink Data Consumed Callback function is used to
register a callback function that is invoked when data
is consumed by the peer node on a channel
Add event notification handling including APIs:
register device event:
The xLink Register Device Event function is used to
register a callback for notification of certain system
events. Currently XLink supports 4 such events [0-3]
whose meaning is system dependent. Registering for an
event means that the callback will be called when the
event occurs with 2 parameters the sw_device_id of the
device that triggered the event and the event number
[0-3]
unregister device event
The xLink Unregister Device Event function is used to
unregister events that have previously been registered
by register device event API
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Seamus Kelly
---
drivers/misc/xlink-core/xlink-core.c| 497
drivers/misc/xlink-core/xlink-core.h| 11 +-
drivers/misc/xlink-core/xlink-defs.h| 6 +-
drivers/misc/xlink-core/xlink-dispatcher.c | 53 +--
drivers/misc/xlink-core/xlink-ioctl.c | 146 +-
drivers/misc/xlink-core/xlink-ioctl.h | 6 +
drivers/misc/xlink-core/xlink-multiplexer.c | 176 +--
drivers/misc/xlink-core/xlink-platform.c| 27 ++
include/linux/xlink.h | 15 +-
9 files changed, 757 insertions(+), 180 deletions(-)
diff --git a/drivers/misc/xlink-core/xlink-core.c
b/drivers/misc/xlink-core/xlink-core.c
index d0a3f98d16af..23c0025f6f0d 100644
--- a/drivers/misc/xlink-core/xlink-core.c
+++ b/drivers/misc/xlink-core/xlink-core.c
@@ -55,6 +55,8 @@ static struct cdev xlink_cdev;
static long xlink_ioctl(struct file *file, unsigned int cmd, unsigned long
arg);
+static struct mutex dev_event_lock;
+
static const struct file_operations fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = xlink_ioctl,
@@ -66,14 +68,75 @@ struct xlink_link {
struct kref refcount;
};
+struct xlink_attr {
+ unsigned long value;
+ u32 sw_dev_id;
+};
+
struct keembay_xlink_dev {
struct platform_device *pdev;
struct xlink_link links[XLINK_MAX_CONNECTIONS];
u32 nmb_connected_links;
struct mutex lock; // protect access to xlink_dev
+ struct xlink_attr eventx[4];
+};
+
+struct event_info {
+ struct list_head list;
+ u32 sw_device_id;
+ u32 event_type;
+ u32 user_flag;
+ xlink_device_event_cb event_notif_fn;
};
-static u8 volbuf[XLINK_MAX_BUF_SIZE]; // buffer for volatile transactions
+// sysfs attribute functions
+
+static ssize_t eventx_show(struct device *dev, struct device_attribute *attr,
+ int index, char *buf)
+{
+ struct keembay_xlink_dev *xlink_dev = dev_get_drvdata(dev);
+ struct xlink_attr *a = &xlink_dev->eventx[index];
+
+ return sysfs_emit(buf, "0x%x 0x%lx\n", a->sw_dev_id, a->value);
+}
+
+static ssize_t event0_show(struct device *dev, struct device_attribute *attr,
char *buf)
+{
+ return eventx_show(dev, attr, 0, buf);
+}
+
+static ssize_t event1_show(struct device *dev, struct device_attribute *attr,
char *buf)
+{
+ return eventx_show(dev, attr, 1, buf);
+}
+
+static ssize_t event2_show(struct device *dev, struct device_attribute *attr,
char *buf)
+{
+ return eventx_show(dev, attr, 2, buf);
+}
+
+static ssize_t event3_show(struct device *dev, struct device_attribute *attr,
char *buf)
+{
+ return eventx_show(dev, attr, 3, buf);
+}
+
+static DEVICE_ATTR_RO(event0);
+static DEVICE_ATTR_RO(event1);
+static DEVICE_ATTR_RO(event2);
+static DEVICE_ATTR_RO(event3);
+static struct attribute *xlink_sysfs_entries[] = {
+ &dev_attr_event0.attr,
+ &dev_attr_event1.attr,
+ &dev_attr_event2.attr,
+ &dev_attr_event3.attr,
+ NULL,
+};
+
+static const struct attribute_group xlink_sysfs_group = {
+ .attrs = xlink_sysfs_entries,
+};
+
+static struct event_info ev_info;
/*
* global variable pointing to our xlink device.
@@ -207,7 +270,14 @@ static int kmb_xlink_probe(struct platform_device *pdev)
dev_info(&pdev->dev, "Cannot add the device to the system\n");
[PATCH v6 30/34] misc:intel_tsens: Intel Keem Bay tsens driver.
From: "C, Udhayakumar"
Add keembey_thermal driver to expose on chip temperature
sensors, and register call back functions for periodic sampling.
This driver does following:
* Reads temperature data from on chip sensors present in Keem Bay
platform.
* Registers callback function to intel tsens driver for sampling
temperature values periodically.
* Decode the raw values from registers to Celsius.
Acked-by: mark gross
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
drivers/misc/intel_tsens/Kconfig | 12 +
drivers/misc/intel_tsens/Makefile | 1 +
drivers/misc/intel_tsens/keembay_thermal.c | 169 ++
drivers/misc/intel_tsens/keembay_tsens.h | 366 +
4 files changed, 548 insertions(+)
create mode 100644 drivers/misc/intel_tsens/keembay_thermal.c
create mode 100644 drivers/misc/intel_tsens/keembay_tsens.h
diff --git a/drivers/misc/intel_tsens/Kconfig b/drivers/misc/intel_tsens/Kconfig
index be8d27e81864..5cfe6b4004e5 100644
--- a/drivers/misc/intel_tsens/Kconfig
+++ b/drivers/misc/intel_tsens/Kconfig
@@ -28,6 +28,18 @@ config INTEL_TSENS_I2C_SLAVE
Say Y if using a processor that includes the Intel VPU such as
Keem Bay. If unsure, say N.
+config KEEMBAY_THERMAL
+ tristate "Temperature sensor driver for intel Keem Bay"
+ depends on INTEL_TSENS_LOCAL_HOST && ARCH_KEEMBAY
+ help
+ Enable this option if you want to have support for Keem Bay
+ thermal management sensors.
+
+ This driver is used for reading onchip temperature sensor
+ values from Keem Bay SoC.
+ Say Y if using a processor that includes the Intel VPU such as
+ Keem Bay. If unsure, say N.
+
config INTEL_TSENS_IA_HOST
tristate "Temperature sensor driver for intel tsens remote host"
depends on I2C && THERMAL
diff --git a/drivers/misc/intel_tsens/Makefile
b/drivers/misc/intel_tsens/Makefile
index f6f41bbca80c..00f63c2d5b2f 100644
--- a/drivers/misc/intel_tsens/Makefile
+++ b/drivers/misc/intel_tsens/Makefile
@@ -7,3 +7,4 @@
obj-$(CONFIG_INTEL_TSENS_LOCAL_HOST) += intel_tsens_thermal.o
obj-$(CONFIG_INTEL_TSENS_I2C_SLAVE)+= intel_tsens_i2c.o
obj-$(CONFIG_INTEL_TSENS_IA_HOST) += intel_tsens_host.o
+obj-$(CONFIG_KEEMBAY_THERMAL) += keembay_thermal.o
diff --git a/drivers/misc/intel_tsens/keembay_thermal.c
b/drivers/misc/intel_tsens/keembay_thermal.c
new file mode 100644
index ..d6c8fa8fc3aa
--- /dev/null
+++ b/drivers/misc/intel_tsens/keembay_thermal.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *
+ * Intel Keem Bay thermal Driver
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "intel_tsens_thermal.h"
+#include "keembay_tsens.h"
+
+struct keembay_thermal_priv {
+ const char *name;
+ void __iomem *base_addr;
+ /* sensor lock*/
+ spinlock_t lock;
+ int current_temp[KEEMBAY_SENSOR_MAX];
+ struct intel_tsens_plat_data *plat_data;
+};
+
+static void kmb_sensor_read_temp(void __iomem *regs_val,
+int offset,
+int sample_valid_mask,
+int sample_value,
+int bit_shift,
+int *temp)
+{
+ int reg_val, kmb_raw_index;
+
+ /* clear the bit of TSENS_EN and re-enable again */
+ iowrite32(0x00, regs_val + AON_TSENS_CFG);
+ iowrite32(CFG_MASK_MANUAL, regs_val + AON_TSENS_CFG);
+ reg_val = ioread32(regs_val + offset);
+ if (reg_val & sample_valid_mask) {
+ reg_val = (reg_val >> bit_shift) & sample_value;
+ kmb_raw_index = reg_val - KEEMBAY_SENSOR_BASE_TEMP;
+ if (kmb_raw_index < 0)
+ reg_val = raw_kmb[0];
+ else if (kmb_raw_index > (raw_kmb_size - 1))
+ reg_val = raw_kmb[raw_kmb_size - 1];
+ else
+ reg_val = raw_kmb[kmb_raw_index];
+ *temp = reg_val;
+ } else {
+ *temp = -255;
+ }
+}
+
+/*The lock is assumed to be held by the caller.*/
+static int keembay_get_temp(struct platform_device *pdev, int type, int *temp)
+{
+ struct keembay_thermal_priv *priv = platform_get_drvdata(pdev);
+
+ spin_lock(&priv->lock);
+ switch (type) {
+ case KEEMBAY_SENSOR_MSS:
+ kmb_sensor_read_temp(priv->base_addr,
+AON_TSENS_DATA0,
+MSS_T_SAMPLE_VALID,
+MSS_T_SAMPLE,
+MSS_BIT_SHIFT,
+temp);
+ priv->current_temp[KEEMBAY_SENSOR_MSS] = *temp;
+ break;
+
+ case KEEMBAY_SENSOR_CSS:
+
[PATCH v6 27/34] misc: Tsens ARM host thermal driver.
From: "C, Udhayakumar"
Add tsens ARM host thermal driver for Intel Edge.AI Computer Vision
platforms.
About Intel Edge.AI Computer Vision platforms:
-
The Intel Edge.AI Computer Vision platforms are vision processing systems
targeting machine vision applications for connected devices.
They are based on ARM A53 CPU running Linux and acts as a PCIe
endpoint device.
High-level architecture:
Remote Host IA CPULocal Host ARM CPU
--
| Platform| | Thermal Daemon|
| Management SW| ||
--
| Intel tsens | | intel tsens i2c slave |
| i2c client | | and thermal driver|
--
| XLINK I2C | | XLINK I2C Slave |
| controller | <=> | controller |
smbus--
intel tsens module:
---
The tsens module enables reading of on chip sensors present
in the Intel Edge.AI Computer Vision platforms. In the tsens module
various junction and SoC temperatures are reported using thermal
subsystem and i2c subsystem.
Temperature data reported using thermal subsystem will be used for
various cooling agents such as DVFS, fan control and shutdown the
system in case of critical temperature.
Temperature data reported using i2c subsystem will be used by
platform manageability software running in IA host.
- Local Host driver
* Intended for ARM CPU
* It is based on Thermal and I2C slave Framework
* Driver path:
{tree}/drivers/misc/intel_tsens/intel_tsens_thermal.c
Local host and Remote host drivers communicates using
XLINK I2C SMBUS protocol.
Acked-by: Mark Gross
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/intel_tsens_sensor.rst| 67 ++
MAINTAINERS | 5 +
drivers/misc/Kconfig | 1 +
drivers/misc/Makefile | 1 +
drivers/misc/intel_tsens/Kconfig | 15 +
drivers/misc/intel_tsens/Makefile | 7 +
.../misc/intel_tsens/intel_tsens_thermal.c| 651 ++
.../misc/intel_tsens/intel_tsens_thermal.h| 38 +
include/linux/hddl_device.h | 153
10 files changed, 939 insertions(+)
create mode 100644 Documentation/hwmon/intel_tsens_sensor.rst
create mode 100644 drivers/misc/intel_tsens/Kconfig
create mode 100644 drivers/misc/intel_tsens/Makefile
create mode 100644 drivers/misc/intel_tsens/intel_tsens_thermal.c
create mode 100644 drivers/misc/intel_tsens/intel_tsens_thermal.h
create mode 100644 include/linux/hddl_device.h
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index fcb870ce6286..fc29100bef73 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -80,6 +80,7 @@ Hardware Monitoring Kernel Drivers
ir38064
isl68137
it87
+ intel_tsens_sensor.rst
jc42
k10temp
k8temp
diff --git a/Documentation/hwmon/intel_tsens_sensor.rst
b/Documentation/hwmon/intel_tsens_sensor.rst
new file mode 100644
index ..0f53dfca477e
--- /dev/null
+++ b/Documentation/hwmon/intel_tsens_sensor.rst
@@ -0,0 +1,67 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+==
+Kernel driver: intel_tsens_thermal
+==
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+
+Slave address: The address is assigned by the hddl device management
+ driver.
+
+Authors:
+- Thalaiappan, Rathina
+- Udhayakumar C
+
+Description
+===
+The Intel Edge.AI Computer Vision platforms have memory mapped thermal sensors
+which are accessible locally. The intel_tsens_thermal driver handles these
+thermal sensor and exposes the temperature to
+
+* the external host similar to the standard SMBUS based thermal sensor
+(like LM73) to the host by registering to the I2C subsystem as
+slave interface (Documentation/i2c/slave-interface.rst).
+* the local CPU as a standard thermal device.
+
+In Keem Bay, the four thermal junction temperature points are,
+Media Subsystem (mss), NN subsystem (nce), Compute subsystem (cse) and
+SOC(Maximum of mss, nce and cse).
+
+Similarity: /drivers/thermal/qcom
+
+Example
+===
+Local Thermal Interface:
+
+Temperature reported in Keem Bay on the Linux Thermal sysfs interface.
+
+# cat /sys/class/thermal/thermal_zone*/type
+mss
+css
+nce
+soc
+
+# cat /sys/class/thermal/thermal_zone*/temp
+0
+29210
+28478
+29210
+
+Remote Thermal Interface:
+
+tsens i2c slave driver reports temperature of v
[PATCH v6 19/34] xlink-core: Add xlink core device tree bindings
From: Seamus Kelly
Add device tree bindings for keembay-xlink.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Seamus Kelly
---
.../bindings/misc/intel,keembay-xlink.yaml| 29 +++
1 file changed, 29 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/intel,keembay-xlink.yaml
diff --git a/Documentation/devicetree/bindings/misc/intel,keembay-xlink.yaml
b/Documentation/devicetree/bindings/misc/intel,keembay-xlink.yaml
new file mode 100644
index ..5ac2e7fa5b5e
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,keembay-xlink.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) Intel Corporation. All rights reserved.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/intel,keembay-xlink.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel Keem Bay xlink
+
+maintainers:
+ - Seamus Kelly
+
+description: |
+ The Keem Bay xlink driver enables the communication/control sub-system
+ for internal and external communications to the Intel Keem Bay SoC.
+
+properties:
+ compatible:
+oneOf:
+ - items:
+ - const: intel,keembay-xlink
+
+additionalProperties: False
+
+examples:
+ - |
+xlink {
+compatible = "intel,keembay-xlink";
+};
--
2.17.1
[PATCH v6 25/34] misc: Add Keem Bay VPU manager
From: "Li, Tingqian"
VPU IP on Keem Bay SOC is a vision acceleration IP complex
under the control of a RTOS-based firmware (running on RISC
MCU inside the VPU IP) serving user-space application
running on CPU side for HW accelerated computer vision tasks.
This module is kernel counterpart of the VPUAL(VPU abstraction
layer) which bridges firmware on VPU side and applications on
CPU user-space, it assists firmware on VPU side serving multiple
user space application processes on CPU side concurrently while
also performing necessary data buffer management on behave of
VPU IP.
objmgr provides basic infrastructure for create/destroy VPU side
software object concurrently on demand of user-space application
and also automatically release leaked objects during handling of
application termination. Note this module only cares about the
life-cycle of such objects, it's up to the application and firmware
to define the behavior/operations of each object.
objmgr does it's job by communicating with firmware through a fixed
reserved xlink channel, using a very simple message protocol.
smm provides DMABuf allocation/import facilities to allow user-space
app pass data to/from VPU in zero-copy fashion. it also provided a
convenient ioctl function for converting virtual pointer of a mem-mapped
and imported DMABuf into it's corresponding dma address, to allow
user-space app to specify the sub-regions of a bigger DMABuf to be
processed by VPU.
Signed-off-by: Li Tingqian
Signed-off-by: Zhou Luwei
Signed-off-by: Wang jue
Signed-off-by: Mark Gross
---
drivers/misc/Kconfig | 1 +
drivers/misc/Makefile| 1 +
drivers/misc/vpumgr/Kconfig | 9 +
drivers/misc/vpumgr/Makefile | 3 +
drivers/misc/vpumgr/vpu_common.h | 31 ++
drivers/misc/vpumgr/vpu_mgr.c| 370
drivers/misc/vpumgr/vpu_smm.c| 554 +
drivers/misc/vpumgr/vpu_smm.h| 30 ++
drivers/misc/vpumgr/vpu_vcm.c| 584 +++
drivers/misc/vpumgr/vpu_vcm.h| 84 +
include/uapi/misc/vpumgr.h | 64
11 files changed, 1731 insertions(+)
create mode 100644 drivers/misc/vpumgr/Kconfig
create mode 100644 drivers/misc/vpumgr/Makefile
create mode 100644 drivers/misc/vpumgr/vpu_common.h
create mode 100644 drivers/misc/vpumgr/vpu_mgr.c
create mode 100644 drivers/misc/vpumgr/vpu_smm.c
create mode 100644 drivers/misc/vpumgr/vpu_smm.h
create mode 100644 drivers/misc/vpumgr/vpu_vcm.c
create mode 100644 drivers/misc/vpumgr/vpu_vcm.h
create mode 100644 include/uapi/misc/vpumgr.h
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 09ae65e98681..2d1f7b165cc8 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -484,4 +484,5 @@ source "drivers/misc/uacce/Kconfig"
source "drivers/misc/xlink-pcie/Kconfig"
source "drivers/misc/xlink-ipc/Kconfig"
source "drivers/misc/xlink-core/Kconfig"
+source "drivers/misc/vpumgr/Kconfig"
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f3a6eb03bae9..2936930f3edc 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
obj-y += xlink-pcie/
obj-$(CONFIG_XLINK_IPC)+= xlink-ipc/
obj-$(CONFIG_XLINK_CORE) += xlink-core/
+obj-$(CONFIG_VPUMGR) += vpumgr/
diff --git a/drivers/misc/vpumgr/Kconfig b/drivers/misc/vpumgr/Kconfig
new file mode 100644
index ..bb82ff83afd3
--- /dev/null
+++ b/drivers/misc/vpumgr/Kconfig
@@ -0,0 +1,9 @@
+config VPUMGR
+ tristate "VPU Manager"
+ depends on ARM64 && XLINK_CORE
+ help
+ VPUMGR manages life-cycle of VPU related resources which were
+ dynamically allocated on demands of user-space application
+
+ Select y or m if you have a processor including the Intel
+ Vision Processor (VPU) on it.
diff --git a/drivers/misc/vpumgr/Makefile b/drivers/misc/vpumgr/Makefile
new file mode 100644
index ..51441dc8a930
--- /dev/null
+++ b/drivers/misc/vpumgr/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_VPUMGR) += vpumgr.o
+vpumgr-objs := vpu_mgr.o vpu_smm.o vpu_vcm.o
diff --git a/drivers/misc/vpumgr/vpu_common.h b/drivers/misc/vpumgr/vpu_common.h
new file mode 100644
index ..cd474ffc05f3
--- /dev/null
+++ b/drivers/misc/vpumgr/vpu_common.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ * VPUMGR Kernel module - common definition
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+#ifndef _VPU_COMMON_H
+#define _VPU_COMMON_H
+#include
+#include
+
+#include
+
+#include "vpu_vcm.h"
+
+/* there will be one such device for each HW instance */
+struct vpumgr_device {
+ struct device *sdev;
+ struct device *dev;
+ dev_t devnum;
+ struct cdev cdev;
+ struct platform_device *pdev;
+
+ struct vcm_dev vcm;
+ struct dentry *debugfs_root;
+
+ stru
[PATCH v6 03/34] mailbox: vpu-ipc-mailbox: Add support for Intel VPU IPC mailbox
From: Daniele Alessandrelli Add mailbox controller enabling inter-processor communication (IPC) between the CPU (aka, the Application Processor - AP) and the VPU on Intel Movidius SoCs like Keem Bay. The controller uses HW FIFOs to enable such communication. Specifically, there are two FIFOs, one for the CPU and one for VPU. Each FIFO can hold 128 entries (messages) of 32-bit each (but only 26 bits are actually usable, since the 6 least-significant bits are reserved for the overflow detection mechanism, more info below). When the Linux kernel on the AP needs to send messages to the VPU firmware, it writes them to the VPU FIFO; similarly, when the VPU firmware needs to send messages to the AP, it writes them to the CPU FIFO. It's important to note that the AP is not the only one that can write to the VPU FIFO: other components within the SoC can write to it too. Each of these components (including the AP) has a unique 6-bit processor ID associated to it. The VPU HW FIFO expects the last 6 bits of each 32-bit FIFO entry to contain the processor ID of the sender. Therefore, sending a message from the AP to the VPU works as follows: 1. The message must be a 32-bit value with the last 6-bit set to 0 (in practice, the message is meant to be a 32-bit address value, aligned to 64 bytes; but this is not really relevant for this mailbox controller). 2. The AP adds its processor ID to the 32-bit message being sent: M = m | AP_ProcID 3. The sender writes the message (M) to the TIM_IPC_FIFO register of the VPU FIFO. 4. The HW atomically checks if the FIFO is full and if not it writes it to the actual FIFO; if the FIFO is full, the HW reads the ProcID from M and then sets the corresponding bit of TIM_IPC_FIFO_OF_FLAG0, to signal that the write failed, because the FIFO was full. 5. The AP reads the TIM_IPC_FIFO_OF_FLAG0 register and checks if the bit corresponding to its ProcID has been set (in order to know if the TX succeeded or failed); if the bit is set, the AP clears it. Note: as briefly mentioned above, the 32-bit value is meant to be a 32- bit physical address (64-byte aligned). This address points to a predefined struct (i.e., the IPC packet) in shared memory. However, since this struct is not HW dependent (it's just the struct the VPU firmware expects and in theory it could change if a different VPU FW is used), it's not defined here, but in the Keem Bay IPC driver, which is the mailbox client for this controller. The AP is notified of pending messages in the CPU FIFO by means of the 'FIFO-not-empty' interrupt, which is generated by the CPU FIFO while not empty. This interrupt is cleared automatically once all messages have been read from the FIFO (i.e., the FIFO has been emptied). The hardware doesn't provide an TX done IRQ (i.e., an IRQ that allows the VPU firmware to notify the AP that the message put into the VPU FIFO has been received); however the AP can ensure that the message has been successfully put into the VPU FIFO (and therefore transmitted) by checking the VPU FIFO status register (TIM_IPC_FIFO_OF_FLAG0) to ensure that writing the message didn't cause the FIFO to overflow (as described above). Therefore, the mailbox controller is configured as capable of tx_done IRQs and a tasklet is used to simulate the tx_done IRQ. The tasklet is activated by send_data() right after the message has been put into the VPU FIFO and the VPU FIFO status registers has been checked. If an overflow is reported by the status register, the tasklet passes -EBUSY to mbox_chan_txdone(), to notify the mailbox client of the failed TX. The client should therefore register a tx_done() callback to properly handle failed transmissions. Note: the 'txdone_poll' mechanism cannot be used because it doesn't provide a way to report a failed transmission. Reviewed-by: Mark Gross Signed-off-by: Daniele Alessandrelli Signed-off-by: Mark Gross --- MAINTAINERS | 1 + drivers/mailbox/Kconfig | 11 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/vpu-ipc-mailbox.c | 297 ++ 4 files changed, 311 insertions(+) create mode 100644 drivers/mailbox/vpu-ipc-mailbox.c diff --git a/MAINTAINERS b/MAINTAINERS index 68e6af3e5650..a88f5eb35e39 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9184,6 +9184,7 @@ M:Daniele Alessandrelli M: Mark Gross S: Supported F: Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml +F: drivers/mailbox/vpu-ipc-mailbox.c INTEL WIRELESS 3945ABG/BG, 4965AGN (iwlegacy) M: Stanislaw Gruszka diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index f4abe3529acd..cb50b541a5c6 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -29,6 +29,17 @@ config IMX_MBOX help Mailbox implementation for i.MX Messaging Unit (MU). +config INTEL_VPU_IPC_MBOX + tristate "Intel VPU IPC Mailbox" + depends on HAS_
[PATCH v6 11/34] misc: xlink-pcie: lh: Add core communication logic
From: Srikanth Thokala
Add logic to establish communication with the remote host which is through
ring buffer management and MSI/Doorbell interrupts
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/local_host/Makefile | 2 +
drivers/misc/xlink-pcie/local_host/core.c | 806
drivers/misc/xlink-pcie/local_host/core.h | 247 ++
drivers/misc/xlink-pcie/local_host/epf.c| 116 ++-
drivers/misc/xlink-pcie/local_host/epf.h| 23 +
drivers/misc/xlink-pcie/local_host/util.c | 375 +
drivers/misc/xlink-pcie/local_host/util.h | 70 ++
drivers/misc/xlink-pcie/local_host/xpcie.h | 63 ++
include/linux/xlink_drv_inf.h | 58 ++
9 files changed, 1752 insertions(+), 8 deletions(-)
create mode 100644 drivers/misc/xlink-pcie/local_host/core.c
create mode 100644 drivers/misc/xlink-pcie/local_host/core.h
create mode 100644 drivers/misc/xlink-pcie/local_host/util.c
create mode 100644 drivers/misc/xlink-pcie/local_host/util.h
create mode 100644 include/linux/xlink_drv_inf.h
diff --git a/drivers/misc/xlink-pcie/local_host/Makefile
b/drivers/misc/xlink-pcie/local_host/Makefile
index 54fc118e2dd1..28761751d43b 100644
--- a/drivers/misc/xlink-pcie/local_host/Makefile
+++ b/drivers/misc/xlink-pcie/local_host/Makefile
@@ -1,3 +1,5 @@
obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o
mxlk_ep-objs := epf.o
mxlk_ep-objs += dma.o
+mxlk_ep-objs += core.o
+mxlk_ep-objs += util.o
diff --git a/drivers/misc/xlink-pcie/local_host/core.c
b/drivers/misc/xlink-pcie/local_host/core.c
new file mode 100644
index ..c67ce2c3067d
--- /dev/null
+++ b/drivers/misc/xlink-pcie/local_host/core.c
@@ -0,0 +1,806 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include
+
+#include "epf.h"
+#include "core.h"
+#include "util.h"
+
+static struct xpcie *global_xpcie;
+
+static struct xpcie *intel_xpcie_core_get_by_id(u32 sw_device_id)
+{
+ return (sw_device_id == xlink_sw_id) ? global_xpcie : NULL;
+}
+
+static int intel_xpcie_map_dma(struct xpcie *xpcie, struct xpcie_buf_desc *bd,
+ int direction)
+{
+ struct xpcie_epf *xpcie_epf = container_of(xpcie,
+ struct xpcie_epf, xpcie);
+ struct pci_epf *epf = xpcie_epf->epf;
+ struct device *dma_dev = epf->epc->dev.parent;
+
+ bd->phys = dma_map_single(dma_dev, bd->data, bd->length, direction);
+
+ return dma_mapping_error(dma_dev, bd->phys);
+}
+
+static void intel_xpcie_unmap_dma(struct xpcie *xpcie,
+ struct xpcie_buf_desc *bd, int direction)
+{
+ struct xpcie_epf *xpcie_epf = container_of(xpcie,
+ struct xpcie_epf, xpcie);
+ struct pci_epf *epf = xpcie_epf->epf;
+ struct device *dma_dev = epf->epc->dev.parent;
+
+ dma_unmap_single(dma_dev, bd->phys, bd->length, direction);
+}
+
+static void intel_xpcie_set_cap_txrx(struct xpcie *xpcie)
+{
+ size_t tx_len = sizeof(struct xpcie_transfer_desc) *
+ XPCIE_NUM_TX_DESCS;
+ size_t rx_len = sizeof(struct xpcie_transfer_desc) *
+ XPCIE_NUM_RX_DESCS;
+ size_t hdr_len = sizeof(struct xpcie_cap_txrx);
+ u32 start = sizeof(struct xpcie_mmio);
+ struct xpcie_cap_txrx *cap;
+ struct xpcie_cap_hdr *hdr;
+ u16 next;
+
+ next = (u16)(start + hdr_len + tx_len + rx_len);
+ intel_xpcie_iowrite32(start, xpcie->mmio + XPCIE_MMIO_CAP_OFF);
+ cap = (void *)xpcie->mmio + start;
+ memset(cap, 0, sizeof(struct xpcie_cap_txrx));
+ cap->hdr.id = XPCIE_CAP_TXRX;
+ cap->hdr.next = next;
+ cap->fragment_size = XPCIE_FRAGMENT_SIZE;
+ cap->tx.ring = start + hdr_len;
+ cap->tx.ndesc = XPCIE_NUM_TX_DESCS;
+ cap->rx.ring = start + hdr_len + tx_len;
+ cap->rx.ndesc = XPCIE_NUM_RX_DESCS;
+
+ hdr = (struct xpcie_cap_hdr *)((void *)xpcie->mmio + next);
+ hdr->id = XPCIE_CAP_NULL;
+}
+
+static void intel_xpcie_txrx_cleanup(struct xpcie *xpcie)
+{
+ struct xpcie_epf *xpcie_epf = container_of(xpcie,
+ struct xpcie_epf, xpcie);
+ struct device *dma_dev = xpcie_epf->epf->epc->dev.parent;
+ struct xpcie_interface *inf = &xpcie->interfaces[0];
+ struct xpcie_stream *tx = &xpcie->tx;
+ struct xpcie_stream *rx = &xpcie->rx;
+ struct xpcie_transfer_desc *td;
+ int index;
+
+ xpcie->stop_flag = true;
+ xpcie->no_tx_buffer = false;
+ inf->data_avail = true;
+ wake_up_interruptible(&xpcie->tx_waitq);
+ wake_up_interruptible(&inf->rx_waitq);
+ mutex_lock(&xpcie->wlock);
+ mutex_lock(&inf->rlock);
+
+ for (inde
[PATCH v6 29/34] Intel tsens i2c slave driver.
From: "C, Udhayakumar"
Add Intel tsens i2c slave driver for Intel Edge.AI Computer Vision
platforms.
The tsens i2c slave driver enables reading of on chip sensors present
in the Intel Edge.AI Computer Vision platforms. In the tsens i2c module
various junction and SoC temperatures are reported using i2c slave
protocol.
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
drivers/misc/intel_tsens/Kconfig | 14 +++
drivers/misc/intel_tsens/Makefile | 1 +
drivers/misc/intel_tsens/intel_tsens_i2c.c | 119 +
3 files changed, 134 insertions(+)
create mode 100644 drivers/misc/intel_tsens/intel_tsens_i2c.c
diff --git a/drivers/misc/intel_tsens/Kconfig b/drivers/misc/intel_tsens/Kconfig
index 8b263fdd80c3..be8d27e81864 100644
--- a/drivers/misc/intel_tsens/Kconfig
+++ b/drivers/misc/intel_tsens/Kconfig
@@ -14,6 +14,20 @@ config INTEL_TSENS_LOCAL_HOST
Say Y if using a processor that includes the Intel VPU such as
Keem Bay. If unsure, say N.
+config INTEL_TSENS_I2C_SLAVE
+ bool "I2C slave driver for intel tsens"
+ depends on INTEL_TSENS_LOCAL_HOST
+ depends on I2C=y && I2C_SLAVE
+ help
+ This option enables tsens I2C slave driver.
+
+ This driver is used for reporting thermal data via I2C
+ SMBUS to remote host.
+ Enable this option if you want to have support for thermal
+ management controller.
+ Say Y if using a processor that includes the Intel VPU such as
+ Keem Bay. If unsure, say N.
+
config INTEL_TSENS_IA_HOST
tristate "Temperature sensor driver for intel tsens remote host"
depends on I2C && THERMAL
diff --git a/drivers/misc/intel_tsens/Makefile
b/drivers/misc/intel_tsens/Makefile
index 250dc484fb49..f6f41bbca80c 100644
--- a/drivers/misc/intel_tsens/Makefile
+++ b/drivers/misc/intel_tsens/Makefile
@@ -5,4 +5,5 @@
#
obj-$(CONFIG_INTEL_TSENS_LOCAL_HOST) += intel_tsens_thermal.o
+obj-$(CONFIG_INTEL_TSENS_I2C_SLAVE)+= intel_tsens_i2c.o
obj-$(CONFIG_INTEL_TSENS_IA_HOST) += intel_tsens_host.o
diff --git a/drivers/misc/intel_tsens/intel_tsens_i2c.c
b/drivers/misc/intel_tsens/intel_tsens_i2c.c
new file mode 100644
index ..520c3f4bf392
--- /dev/null
+++ b/drivers/misc/intel_tsens/intel_tsens_i2c.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *
+ * Intel tsens I2C thermal Driver
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include "intel_tsens_thermal.h"
+
+#define TSENS_BYTE_INDEX_SHIFT 0x6
+#define TSENS_BYTE_INDEX_MASK 0x3
+#define TSENS_SENSOR_TYPE_MASK 0x3F
+
+struct intel_tsens_i2c {
+ int sensor_type;
+ u16 buffer_idx;
+ bool read_only;
+ u8 idx_write_cnt;
+ struct intel_tsens_i2c_plat_data *plat_data;
+};
+
+static int intel_i2c_tsens_slave_cb(struct i2c_client *client,
+ enum i2c_slave_event event, u8 *val)
+{
+ struct intel_tsens_i2c *tsens_i2c = i2c_get_clientdata(client);
+ struct intel_tsens_i2c_plat_data *plat_data = tsens_i2c->plat_data;
+ int ret = 0;
+
+ switch (event) {
+ case I2C_SLAVE_WRITE_RECEIVED:
+ tsens_i2c->sensor_type = *val;
+ break;
+
+ case I2C_SLAVE_READ_PROCESSED:
+ case I2C_SLAVE_READ_REQUESTED:
+ if (plat_data->get_temp) {
+ int temp;
+ int sensor_type = tsens_i2c->sensor_type &
+ TSENS_SENSOR_TYPE_MASK;
+
+ if (!plat_data->get_temp(sensor_type, &temp,
+plat_data->pdata)) {
+ u8 offset = (tsens_i2c->sensor_type >>
+ TSENS_BYTE_INDEX_SHIFT) &
+ TSENS_BYTE_INDEX_MASK;
+ u8 *ptr_temp = (u8 *)&temp;
+
+ *val = ptr_temp[offset];
+ tsens_i2c->buffer_idx++;
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+ } else {
+ ret = -EINVAL;
+ }
+ break;
+
+ case I2C_SLAVE_STOP:
+ case I2C_SLAVE_WRITE_REQUESTED:
+ tsens_i2c->idx_write_cnt = 0;
+ tsens_i2c->buffer_idx = 0;
+ break;
+
+ default:
+ break;
+ }
+ return ret;
+}
+
+static int intel_i2c_tsens_slave_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{ struct intel_tsens_i2c *priv;
+ int ret;
+
+ if (!id->driver_data) {
+ dev_err(&client->dev, "No platform data");
+ return -EINVAL;
+ }
+ priv = devm
[PATCH v6 28/34] misc: Intel tsens IA host driver.
From: "C, Udhayakumar"
Add Intel tsens IA host driver for Intel Edge.AI Computer Vision
platforms.
About Intel Edge.AI Computer Vision platforms:
-
The Intel Edge.AI Computer Vision platforms are vision processing systems
targeting machine vision applications for connected devices.
They are based on ARM A53 CPU running Linux and acts as a PCIe
endpoint device.
High-level architecture:
Remote Host IA CPU Local Host ARM CPU
--
| Platform| | Thermal Daemon|
| Management SW| ||
--
| Intel tsens | | intel tsens i2c slave |
| i2c client | | and thermal driver|
--
| XLINK I2C | | XLINK I2C Slave |
| controller | <=> | controller |
xlink smbus --
intel tsens module:
---
The tsens module enables reading of on chip sensors present
in the Intel Edge.AI Computer Vision platforms.In the tsens module
various junction and SoC temperatures are reported using thermal
subsystem and i2c subsystem.
Temperature data reported using thermal subsystem will be used for
various cooling agents such as DVFS, fan control and shutdown the
system in case of critical temperature.
Temperature data reported using i2c subsystem will be used by
platform manageability software running in IA host.
- Remote Host driver
* Intended for IA CPU
* It is a I2C client driver
* Driver path:
{tree}/drivers/misc/intel_tsens/intel_tsens_host.c
Local host and Remote host drivers communicates using
I2C SMBUS protocol.
Acked-by: Mark Mross
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/intel_tsens_host.rst| 71
drivers/misc/intel_tsens/Kconfig| 13 +
drivers/misc/intel_tsens/Makefile | 1 +
drivers/misc/intel_tsens/intel_tsens_host.c | 352
include/linux/intel_tsens_host.h| 34 ++
6 files changed, 472 insertions(+)
create mode 100644 Documentation/hwmon/intel_tsens_host.rst
create mode 100644 drivers/misc/intel_tsens/intel_tsens_host.c
create mode 100644 include/linux/intel_tsens_host.h
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index fc29100bef73..7a9eaddd1ab3 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -81,6 +81,7 @@ Hardware Monitoring Kernel Drivers
isl68137
it87
intel_tsens_sensor.rst
+ intel_tsens_host.rst
jc42
k10temp
k8temp
diff --git a/Documentation/hwmon/intel_tsens_host.rst
b/Documentation/hwmon/intel_tsens_host.rst
new file mode 100644
index ..012c593f969f
--- /dev/null
+++ b/Documentation/hwmon/intel_tsens_host.rst
@@ -0,0 +1,71 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+==
+Kernel driver: intel_tsens
+==
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+
+Slave address: The address is assigned by the hddl device management
+ driver.
+
+Datasheet:
+ Documentation/hwmon/intel_tsens_sensor.rst#Remote Thermal Interface
+
+Authors:
+- Thalaiappan, Rathina
+
+Description
+===
+The intel_tsens is a temperature sensor driver receiving the junction
temperature
+from different heating points inside the SOC. The driver will receive the
+temperature on SMBUS connection. The reported temperature is in degrees
Celsius.
+
+In Keem Bay, the four thermal junction temperature points are,
+Media Subsystem (mss), NN subsystem (nce), Compute subsystem (cse) and
+SOC(Maximum of mss, nce and cse).
+
+Example
+===
+Temperature reported by a Keem Bay on the Linux Thermal sysfs interface.
+
+# cat /sys/class/thermal/thermal_zone*/type
+mss
+css
+nce
+soc
+
+# cat /sys/class/thermal/thermal_zone*/temp
+0
+29210
+28478
+29210
+
++---+-+
+| offset| Sensor|
++---+-+
+| 0 | mss |
++---+-+
+| 1 | css |
++---+-+
+| 2 | nce |
++---+-+
+| 3 | soc |
++---+-+
+
+#sudo i2cdetect -l
+i2c-8 smbus SMBus I801 adapter at efa0 SMBus adapte
r
+
+To read mss junction temperature:
+#i2cget -y 8 0x0 w
+
+To read cse junction temperature:
+#i2cget -y 8 0x1 w
+
+To read nce junction temperature:
+#i2cget -y 8 0x2 w
+
+To read overall SoC temperature:
+#i2cget -y 8 0x3 w
diff --git a/drivers/misc/intel_tsens/Kconfig b/drivers/misc/intel_tsens/Kconfig
[PATCH v6 18/34] xlink-ipc: Add xlink ipc driver
From: Seamus Kelly Add xLink driver, which interfaces the xLink Core driver with the Keem Bay VPU IPC driver, thus enabling xLink to control and communicate with the VPU IP present on the Intel Keem Bay SoC. Specifically the driver enables xLink Core to: * Boot / Reset the VPU IP * Register to VPU IP event notifications (device connected, device disconnected, WDT event) * Query the status of the VPU IP (OFF, BUSY, READY, ERROR, RECOVERY) * Exchange data with the VPU IP, using the Keem Bay IPC mechanism - Including the ability to send 'volatile' data (i.e., small amount of data, up to 128-bytes that was not allocated in the CPU/VPU shared memory region) Cc: Jonathan Corbet Cc: Cc: Derek Kiernan Cc: Dragan Cvetic Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Cc: linux-...@vger.kernel.org Reviewed-by: Mark Gross Signed-off-by: Mark Gross Signed-off-by: Seamus Kelly --- Documentation/vpu/index.rst| 1 + Documentation/vpu/xlink-ipc.rst| 51 ++ MAINTAINERS| 6 + drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/xlink-ipc/Kconfig | 7 + drivers/misc/xlink-ipc/Makefile| 4 + drivers/misc/xlink-ipc/xlink-ipc.c | 878 + include/linux/xlink-ipc.h | 48 ++ 9 files changed, 997 insertions(+) create mode 100644 Documentation/vpu/xlink-ipc.rst create mode 100644 drivers/misc/xlink-ipc/Kconfig create mode 100644 drivers/misc/xlink-ipc/Makefile create mode 100644 drivers/misc/xlink-ipc/xlink-ipc.c create mode 100644 include/linux/xlink-ipc.h diff --git a/Documentation/vpu/index.rst b/Documentation/vpu/index.rst index 661cc700ee45..49c78bb65b83 100644 --- a/Documentation/vpu/index.rst +++ b/Documentation/vpu/index.rst @@ -15,3 +15,4 @@ This documentation contains information for the Intel VPU stack. vpu-stack-overview xlink-pcie + xlink-ipc diff --git a/Documentation/vpu/xlink-ipc.rst b/Documentation/vpu/xlink-ipc.rst new file mode 100644 index ..97ee62b10e93 --- /dev/null +++ b/Documentation/vpu/xlink-ipc.rst @@ -0,0 +1,51 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=== +Kernel driver: xLink IPC driver +=== + +Supported chips: + +* | Intel Edge.AI Computer Vision platforms: Keem Bay + | Suffix: Bay + | Datasheet: (not yet publicly available) + +Introduction + + +The xLink IPC driver interfaces the xLink Core driver with the Keem Bay VPU IPC +driver, thus enabling xLink to control and communicate with the VPU IP present +on the Intel Keem Bay SoC. + +Specifically the driver enables xLink Core to: + +* Boot / Reset the VPU IP +* Register to VPU IP event notifications (device connected, device disconnected, + WDT event) +* Query the status of the VPU IP (OFF, BUSY, READY, ERROR, RECOVERY) +* Exchange data with the VPU IP, using the Keem Bay IPC mechanism + + * Including the ability to send 'volatile' data (i.e. small amounts of data, +up to 128-bytes that was not allocated in the CPU/VPU shared memory region) + +Sending / Receiving 'volatile' data +=== + +Data to be exchanged with Keem Bay IPC needs to be allocated in the portion of +DDR shared between the CPU and VPU. + +This can be impractical for small amounts of data that user code can allocate +on the stack. + +To reduce the burden on user code, xLink Core provides special send / receive +functions to send up to 128 bytes of 'volatile data', i.e., data that is not +allocated in the shared memory and that might also disappear after the xLink +API is called (e.g., because allocated on the stack). + +The xLink IPC driver implements support for transferring such 'volatile data' +to the VPU using Keem Bay IPC. To this end, the driver reserves some memory in +the shared memory region. + +When volatile data is to be sent, xLink IPC allocates a buffer from the +reserved memory region and copies the volatile data to the buffer. The buffer +is then transferred to the VPU using Keem Bay IPC. diff --git a/MAINTAINERS b/MAINTAINERS index b42a432dc667..aff4d8dd53a4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1961,6 +1961,12 @@ F: Documentation/devicetree/bindings/arm/intel,keembay.yaml F: arch/arm64/boot/dts/intel/keembay-evm.dts F: arch/arm64/boot/dts/intel/keembay-soc.dtsi +ARM/INTEL XLINK IPC SUPPORT +M: Seamus Kelly +M: Mark Gross +S: Supported +F: drivers/misc/xlink-ipc/ + ARM/INTEL KEEM BAY XLINK PCIE SUPPORT M: Srikanth Thokala M: Mark Gross diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index dfb98e444c6e..1f81ea915b95 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -482,4 +482,5 @@ source "drivers/misc/cardreader/Kconfig" source "drivers/misc/habanalabs/Kconfig" source "drivers/misc/uacce/Kconfig" source "drivers/misc/xlink-pcie/Kconfig" +source "drivers/misc/xlink-ipc/Kconfig" endmenu diff --git a
[PATCH v6 31/34] Intel Keembay XLink SMBus driver
From: Ramya P Karanth Adds XLink SMBus driver for Intel Keem Bay SoC. Xlink-smbus driver is a logical SMBus adapter which uses Xlink (xlink-pcie) protocol as an interface. Keem Bay(s) vision accelerators are connected to the server via PCI interface. The Server needs to know the temperature of the SoC and the source to get the temperature can be either on board sensors or on chip sensors. The sensors are ideally connected over i2c bus of the SoC and the server does not have access to sensors present in the PCB. With this xlink-smbus interfaces, server access the on board/on chip sensors via xlink smbus adapter. Signed-off-by: Ramya P Karanth Signed-off-by: Mark Gross --- Documentation/i2c/busses/index.rst| 1 + .../i2c/busses/intel-xlink-smbus.rst | 71 +++ drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/xlink-smbus/Kconfig | 25 + drivers/misc/xlink-smbus/Makefile | 5 + drivers/misc/xlink-smbus/xlink-smbus.c| 467 ++ 7 files changed, 571 insertions(+) create mode 100644 Documentation/i2c/busses/intel-xlink-smbus.rst create mode 100644 drivers/misc/xlink-smbus/Kconfig create mode 100644 drivers/misc/xlink-smbus/Makefile create mode 100644 drivers/misc/xlink-smbus/xlink-smbus.c diff --git a/Documentation/i2c/busses/index.rst b/Documentation/i2c/busses/index.rst index 5e4077b08d86..6ce4a740f616 100644 --- a/Documentation/i2c/busses/index.rst +++ b/Documentation/i2c/busses/index.rst @@ -29,4 +29,5 @@ I2C Bus Drivers i2c-taos-evm i2c-viapro i2c-via + intel-xlink-smbus.rst scx200_acb diff --git a/Documentation/i2c/busses/intel-xlink-smbus.rst b/Documentation/i2c/busses/intel-xlink-smbus.rst new file mode 100644 index ..ab87d18051b4 --- /dev/null +++ b/Documentation/i2c/busses/intel-xlink-smbus.rst @@ -0,0 +1,71 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== +Kernel driver: xlink_smbus +== + +Supported chips: + * Intel Edge.AI Computer Vision platforms: Keem Bay + + Sufix: Bay + + Slave address: The address is selectable by device-tree. (TBD) + +Authors: +- Raja Subramanian, Lakshmi Bai +- Thalaiappan, Rathina +- Karanth, Ramya P + +Description +=== +The Intel Edge.AI Computer Vision platforms have to be monitored using platform +devices like sensors, fan controller, IO expander etc. Some of these devices +are memory mapped and some are i2c based. Either of these devices are not +directly accessible to the host. + +The host here refers to the server to which the vision accelerators are +connected over PCIe Interface. The Host needs to do a consolidated action based +on the parameters of platform devices. In general, most of the standard devices +(includes sensors, fan controller, IO expander etc) are I2C/SMBus based and are +used to provide the status of the accelerator. Standard drivers for these +devices are available based on i2c/smbus APIs. + +Instead of changing the sensor drivers to adapt to PCIe interface, a generic +i2c adapter "xlink-smbus" which underneath uses xlink as physical medium is +used. With xlink-smbus, the drivers for the platform devices doesn't need to +undergo any interface change. + +High-level architecture +=== + +Accessing Onchip devices:: + +--- --- +| Remote Host | | Local Host| +| IA CPU| | Vision platforms| +--- --- +| Onchip | |i2c slave| ==> Access the device +| sensor driver | |handler | ==> which is mmio based +--- --- +|Intel XLINK_SMBUS| |Intel XLINK_SMBUS| +| adpater | | adapter | +|(Master) | | (I2C_SLAVE) | +--- --- +| XLINK |<==> | XLINK | +---PCIE --- + +Accessing Onboard devices:: + +--- -- +| Remote Host | | Local Host | +| IA CPU| | Vision platforms | +--- -- +|On board | | i2c smbus | ==> Access the device +| sensor driver | | xfer [synopsys] | ==> which is on i2c bus +--- -- +|Intel XLINK_SMBUS| | Intel XLI
[PATCH v6 26/34] dt-bindings: misc: intel_tsens: Add tsens thermal bindings documentation
From: "C, Udhayakumar"
Add device tree bindings for local host thermal sensors
Intel Edge.AI Computer Vision platforms.
The tsens module enables reading of on chip sensors present
in the Intel Bay series SoC. In the tsens module various junction
temperature and SoC temperature are reported using thermal subsystem
and i2c subsystem.
Temperature data reported using thermal subsystem will be used for
various cooling agents such as DVFS, fan control and shutdown the
system in case of critical temperature.
Temperature data reported using i2c subsytem will be used by
platform manageability software running in remote host.
Acked-by: mark gross
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
.../bindings/misc/intel,intel-tsens.yaml | 122 ++
1 file changed, 122 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/intel,intel-tsens.yaml
diff --git a/Documentation/devicetree/bindings/misc/intel,intel-tsens.yaml
b/Documentation/devicetree/bindings/misc/intel,intel-tsens.yaml
new file mode 100644
index ..f307dc6d2012
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,intel-tsens.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/intel,intel-tsens.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel Temperature sensors in Bay series
+
+maintainers:
+ - Udhayakumar C
+
+description: |
+ The tsens driver enables reading of onchip sensors present
+ in the Intel Bay SoC.
+ Each subnode of the tsens represents sensors available
+ on the soc.
+
+select: false
+
+properties:
+ compatible:
+items:
+ - const: intel,intel-tsens
+
+ plat_name:
+contains:
+ enum:
+- intel,keembay_thermal
+
+ reg:
+minItems: 1
+maxItems: 2
+
+ clocks:
+items:
+ - description: thermal sensor clock
+
+ clk-rate:
+items:
+ - description: thermal sensor clock freq
+
+ sensor_name:
+type: object
+description:
+ Details to configure sensor trip points and its types.
+
+properties:
+ passive_delay:
+minItems: 1
+maxItems: 1
+description: number of milliseconds to wait between polls when
+ performing passive cooling
+
+ polling_delay:
+minItems: 1
+maxItems: 1
+description: number of milliseconds to wait between polls when checking
+ whether trip points have been crossed (0 for interrupt
+ driven systems)
+
+ trip_temp:
+minItems: 1
+description: temperature for trip points
+
+ trip_type:
+minItems: 1
+description: trip type list for trip points
+
+required:
+ - passive_delay
+ - polling_delay
+ - trip_temp
+ - trip_type
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+tsens {
+#address-cells = <2>;
+#size-cells = <2>;
+
+tsens@2026 {
+compatible = "intel,intel-tsens";
+status = "disabled";
+plat_name = "intel,keembay_thermal";
+reg = <0x0 0x2026 0x0 0x100>;
+clocks = <&scmi_clk>;
+clk-rate = <125>;
+
+mss {
+passive_delay = <1000>;
+polling_delay = <2000>;
+trip_temp = <4 8 100>;
+trip_type = "passive", "passive", "critical";
+};
+
+css {
+passive_delay = <1000>;
+polling_delay = <2000>;
+trip_temp = <4 8 100>;
+trip_type = "passive", "passive", "critical";
+};
+
+nce {
+passive_delay = <1000>;
+polling_delay = <2000>;
+trip_temp = <4 8 100>;
+trip_type = "passive", "passive", "critical";
+};
+
+soc {
+passive_delay = <1000>;
+polling_delay = <2000>;
+trip_temp = <4 8 100>;
+trip_type = "passive", "passive", "critical";
+};
+};
+};
--
2.17.1
[PATCH v6 33/34] misc: Hddl device management for local host
From: "C, Udhayakumar"
Add local host hddl device management for Intel Edge.AI Computer Vision
platforms.
About Intel Edge.AI Computer Vision platforms:
-
The Intel Edge.AI Computer Vision platforms are vision processing systems
targeting machine vision applications for connected devices.
They are based on ARM A53 CPU running Linux and acts as a PCIe
endpoint device.
High-level architecture:
Remote Host IA CPU Local Host ARM CPU
---
| * Send time as xlink packet | |* Sync time with IA host |
| * receive sensor details| |* Prepare and share sensor|
| and register as i2c or| | details to IA host as |
| xlink smbus slaves| | xlink packets |
---
| hddl server | <=> | hddl client |
--- xlink
hddl device module:
---
The HDDL client driver acts as an software RTC to sync with network
time. It abstracts xlink protocol to communicate with remote host.
This driver exports the details about sensors available in the
platform to remote host as xlink packets.
This driver also handles device connect/disconnect events and
identifies board id and soc id using gpio's, based on platform
configuration.
- Local Host driver
* Intended for ARM CPU
* It is based on xlink Framework
* Driver path:
{tree}/drivers/misc/hddl_device/hddl_device_client.c
Local arm host and Remote IA host drivers communicates using
XLINK protocol.
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
.../misc-devices/hddl_device_client.rst | 212 +
Documentation/misc-devices/index.rst | 1 +
Documentation/vpu/index.rst | 1 +
MAINTAINERS | 1 +
drivers/misc/Kconfig | 1 +
drivers/misc/Makefile | 1 +
drivers/misc/hddl_device/Kconfig | 14 +
drivers/misc/hddl_device/Makefile | 5 +
drivers/misc/hddl_device/hddl_device.c| 565 +
drivers/misc/hddl_device/hddl_device_lh.c | 764 ++
drivers/misc/hddl_device/hddl_device_util.h | 52 ++
11 files changed, 1617 insertions(+)
create mode 100644 Documentation/misc-devices/hddl_device_client.rst
create mode 100644 drivers/misc/hddl_device/Kconfig
create mode 100644 drivers/misc/hddl_device/Makefile
create mode 100644 drivers/misc/hddl_device/hddl_device.c
create mode 100644 drivers/misc/hddl_device/hddl_device_lh.c
create mode 100644 drivers/misc/hddl_device/hddl_device_util.h
diff --git a/Documentation/misc-devices/hddl_device_client.rst
b/Documentation/misc-devices/hddl_device_client.rst
new file mode 100644
index ..413643b6b500
--- /dev/null
+++ b/Documentation/misc-devices/hddl_device_client.rst
@@ -0,0 +1,212 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=
+Kernel driver: hddl_device_client
+=
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+
+Authors:
+- Thalaiappan, Rathina
+- Udhayakumar C
+
+
+Overview
+
+
+This driver supports hddl device management for Intel Edge.AI Computer Vision
+platforms.
+
+This driver supports the following features:
+
+ - Exports deatils of temperature sensor, current sensor and fan controller
+present in Intel Edge.AI Computer Vision platforms to IA host.
+ - Enable Time sync of Intel Edge.AI Computer Vision platform with IA host.
+ - Handles device connect and disconnect events.
+ - Receives slave address from the IA host for memory mapped thermal sensors
+present in SoC (Documentation/hwmon/intel_tsens_sensors.rst).
+ - Registers i2c slave device for slaves present in Intel Edge.AI Computer
+Vision platform
+
+Keem Bay platform has
+Onchip sensors:
+
+ - Media Subsystem (mss) temperature sensor
+ - NN subsystem (nce) temperature sensor
+ - Compute subsystem (cse) temperature sensor
+ - SOC(Maximum of mss, nce and cse).
+
+Onboard sensors:
+
+ - two lm75 temperature sensors
+ - emc2103 fan controller
+ - ina3221 current sensor
+
+High-level architecture
+===
+::
+
+Remote Host IA CPU Local Host ARM CPU
+---
+| * Send time as xlink packet | |* Sync time with IA host |
+| * receive sensor details| |* Prepare and share sensor|
+| and register as i2c or| | details to IA host as |
+| xlink smbus slaves| | xlink packets |
+---
+
[PATCH v6 20/34] xlink-core: Add xlink core driver xLink
From: Seamus Kelly Add xLink driver, which provides an abstracted control and communication subsystem based on channel identification. It is intended to support VPU technology both at SoC level as well as at IP level, over multiple interfaces. This initial patch enables local host user mode to open/close/read/write via IOCTLs. Specifically the driver enables application/process to: * Access a common xLink API across all interfaces from both kernel and user space. * Call typical APIs types (open, close, read, write) that you would associate with a communication interface. * Call other APIs that are related to other functions that the device can perform e.g. boot, reset get/set device mode. Device mode refers to the power load of the VPU and an API can be used to read and control it. * Use multiple commnication channels that the driver manages from one interface to another, providing routing of data through these multiple channels across a single physical interface. xLink: Add xLink Core device tree bindings Add device tree bindings for the xLink Core driver which enables xLink to control and communicate with the VPU IP present on the Intel Keem Bay SoC. Cc: Jonathan Corbet Cc: Derek Kiernan Cc: Dragan Cvetic Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Cc: linux-...@vger.kernel.org Reviewed-by: Mark Gross Signed-off-by: Mark Gross Signed-off-by: Seamus Kelly --- Documentation/vpu/index.rst | 1 + Documentation/vpu/xlink-core.rst| 81 +++ MAINTAINERS | 12 + drivers/misc/Kconfig| 1 + drivers/misc/Makefile | 1 + drivers/misc/xlink-core/Kconfig | 33 + drivers/misc/xlink-core/Makefile| 5 + drivers/misc/xlink-core/xlink-core.c| 738 drivers/misc/xlink-core/xlink-core.h| 22 + drivers/misc/xlink-core/xlink-defs.h| 175 + drivers/misc/xlink-core/xlink-ioctl.c | 212 ++ drivers/misc/xlink-core/xlink-ioctl.h | 21 + drivers/misc/xlink-core/xlink-multiplexer.c | 534 ++ drivers/misc/xlink-core/xlink-multiplexer.h | 35 + drivers/misc/xlink-core/xlink-platform.c| 160 + drivers/misc/xlink-core/xlink-platform.h| 65 ++ include/linux/xlink.h | 108 +++ include/uapi/misc/xlink_uapi.h | 145 18 files changed, 2349 insertions(+) create mode 100644 Documentation/vpu/xlink-core.rst create mode 100644 drivers/misc/xlink-core/Kconfig create mode 100644 drivers/misc/xlink-core/Makefile create mode 100644 drivers/misc/xlink-core/xlink-core.c create mode 100644 drivers/misc/xlink-core/xlink-core.h create mode 100644 drivers/misc/xlink-core/xlink-defs.h create mode 100644 drivers/misc/xlink-core/xlink-ioctl.c create mode 100644 drivers/misc/xlink-core/xlink-ioctl.h create mode 100644 drivers/misc/xlink-core/xlink-multiplexer.c create mode 100644 drivers/misc/xlink-core/xlink-multiplexer.h create mode 100644 drivers/misc/xlink-core/xlink-platform.c create mode 100644 drivers/misc/xlink-core/xlink-platform.h create mode 100644 include/linux/xlink.h create mode 100644 include/uapi/misc/xlink_uapi.h diff --git a/Documentation/vpu/index.rst b/Documentation/vpu/index.rst index 49c78bb65b83..cd4272e089ec 100644 --- a/Documentation/vpu/index.rst +++ b/Documentation/vpu/index.rst @@ -16,3 +16,4 @@ This documentation contains information for the Intel VPU stack. vpu-stack-overview xlink-pcie xlink-ipc + xlink-core diff --git a/Documentation/vpu/xlink-core.rst b/Documentation/vpu/xlink-core.rst new file mode 100644 index ..441c18230491 --- /dev/null +++ b/Documentation/vpu/xlink-core.rst @@ -0,0 +1,81 @@ +.. SPDX-License-Identifier: GPL-2.0 + += +xLink-core software subsystem += + +The purpose of the xLink software subsystem is to facilitate communication +between multiple users on multiple nodes in the system. + +There are three types of xLink nodes: + +1. Remote Host: this is an external IA/x86 host system that is only capable of + communicating directly to the Local Host node on VPU 2.x products. +2. Local Host: this is the ARM core within the VPU 2.x SoC. The Local Host can + communicate upstream to the Remote Host node, and downstream to the VPU IP + node. +3. VPU IP: this is the Leon RT core within the VPU 2.x SoC. The VPU IP can only + communicate upstream to the Local Host node. + +xLink provides a common API across all interfaces for users to access xLink +functions and provides user space APIs via an IOCTL interface implemented in +the xLink core. + +xLink manages communications from one interface to another and provides routing +of data through multiple channels across a single physical interface. + +It exposes a common API across all interfac
[PATCH v6 16/34] misc: xlink-pcie: Add asynchronous event notification support for XLink
From: Srikanth Thokala
Add support to notify XLink layer upon PCIe link UP/DOWN events
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/common/core.h | 3 ++
drivers/misc/xlink-pcie/common/interface.c | 17 ++
drivers/misc/xlink-pcie/local_host/core.c | 11 +++
drivers/misc/xlink-pcie/remote_host/main.c | 3 ++
drivers/misc/xlink-pcie/remote_host/pci.c | 36 ++
drivers/misc/xlink-pcie/remote_host/pci.h | 3 ++
include/linux/xlink_drv_inf.h | 12
7 files changed, 85 insertions(+)
diff --git a/drivers/misc/xlink-pcie/common/core.h
b/drivers/misc/xlink-pcie/common/core.h
index f43c175b7a48..87b302f87cfd 100644
--- a/drivers/misc/xlink-pcie/common/core.h
+++ b/drivers/misc/xlink-pcie/common/core.h
@@ -239,4 +239,7 @@ int intel_xpcie_pci_connect_device(u32 id);
int intel_xpcie_pci_read(u32 id, void *data, size_t *size, u32 timeout);
int intel_xpcie_pci_write(u32 id, void *data, size_t *size, u32 timeout);
int intel_xpcie_pci_reset_device(u32 id);
+int intel_xpcie_pci_register_device_event(u32 sw_device_id,
+ xlink_device_event event_notif_fn);
+int intel_xpcie_pci_unregister_device_event(u32 sw_device_id);
#endif /* XPCIE_CORE_HEADER_ */
diff --git a/drivers/misc/xlink-pcie/common/interface.c
b/drivers/misc/xlink-pcie/common/interface.c
index fcc69a940a4c..5d30c27dd18d 100644
--- a/drivers/misc/xlink-pcie/common/interface.c
+++ b/drivers/misc/xlink-pcie/common/interface.c
@@ -105,3 +105,20 @@ int xlink_pcie_reset_device(u32 sw_device_id)
return intel_xpcie_pci_reset_device(sw_device_id);
}
EXPORT_SYMBOL_GPL(xlink_pcie_reset_device);
+
+int xlink_pcie_register_device_event(u32 sw_device_id,
+xlink_device_event event_notif_fn)
+{
+ if (!event_notif_fn)
+ return -EINVAL;
+
+ return intel_xpcie_pci_register_device_event(sw_device_id,
+event_notif_fn);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_register_device_event);
+
+int xlink_pcie_unregister_device_event(u32 sw_device_id)
+{
+ return intel_xpcie_pci_unregister_device_event(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_unregister_device_event);
diff --git a/drivers/misc/xlink-pcie/local_host/core.c
b/drivers/misc/xlink-pcie/local_host/core.c
index 2c4e29bce7f7..bfb14c18c24c 100644
--- a/drivers/misc/xlink-pcie/local_host/core.c
+++ b/drivers/misc/xlink-pcie/local_host/core.c
@@ -804,3 +804,14 @@ int intel_xpcie_pci_reset_device(u32 id)
{
return 0;
}
+
+int intel_xpcie_pci_register_device_event(u32 sw_device_id,
+ xlink_device_event event_notif_fn)
+{
+ return 0;
+}
+
+int intel_xpcie_pci_unregister_device_event(u32 sw_device_id)
+{
+ return 0;
+}
diff --git a/drivers/misc/xlink-pcie/remote_host/main.c
b/drivers/misc/xlink-pcie/remote_host/main.c
index ed1a431ed5d4..efc9143a2fac 100644
--- a/drivers/misc/xlink-pcie/remote_host/main.c
+++ b/drivers/misc/xlink-pcie/remote_host/main.c
@@ -53,6 +53,8 @@ static int intel_xpcie_probe(struct pci_dev *pdev,
if (new_device)
intel_xpcie_list_add_device(xdev);
+ intel_xpcie_pci_notify_event(xdev, NOTIFY_DEVICE_CONNECTED);
+
return ret;
}
@@ -62,6 +64,7 @@ static void intel_xpcie_remove(struct pci_dev *pdev)
if (xdev) {
intel_xpcie_pci_cleanup(xdev);
+ intel_xpcie_pci_notify_event(xdev, NOTIFY_DEVICE_DISCONNECTED);
intel_xpcie_remove_device(xdev);
}
}
diff --git a/drivers/misc/xlink-pcie/remote_host/pci.c
b/drivers/misc/xlink-pcie/remote_host/pci.c
index 71cbe779d1bc..6a79782b983e 100644
--- a/drivers/misc/xlink-pcie/remote_host/pci.c
+++ b/drivers/misc/xlink-pcie/remote_host/pci.c
@@ -6,6 +6,7 @@
*/
#include
+#include
#include
#include
#include
@@ -485,3 +486,38 @@ int intel_xpcie_pci_reset_device(u32 id)
return intel_xpcie_pci_prepare_dev_reset(xdev, true);
}
+
+int intel_xpcie_pci_register_device_event(u32 sw_device_id,
+ xlink_device_event event_notif_fn)
+{
+ struct xpcie_dev *xdev = intel_xpcie_get_device_by_id(sw_device_id);
+
+ if (!xdev)
+ return -ENOMEM;
+
+ xdev->event_fn = event_notif_fn;
+
+ return 0;
+}
+
+int intel_xpcie_pci_unregister_device_event(u32 sw_device_id)
+{
+ struct xpcie_dev *xdev = intel_xpcie_get_device_by_id(sw_device_id);
+
+ if (!xdev)
+ return -ENOMEM;
+
+ xdev->event_fn = NULL;
+
+ return 0;
+}
+
+void intel_xpcie_pci_notify_event(struct xpcie_dev *xdev,
+ enum xlink_device_event_type event_type)
+{
+ if (event_type >= NUM_EVENT_TYPE)
+ return;
+
+ if (xdev->event_fn)
+ xdev
[PATCH v3 01/34] Add Vision Processing Unit (VPU) documentation.
From: mark gross The Intel VPU needs a complicated SW stack to make it work. Add a directory to hold VPU related documentation including an architectural overview of the SW stack that the patches implement. Cc: Jonathan Corbet Signed-off-by: Mark Gross --- Documentation/index.rst | 1 + Documentation/vpu/index.rst | 16 ++ Documentation/vpu/vpu-stack-overview.rst | 270 +++ 3 files changed, 287 insertions(+) create mode 100644 Documentation/vpu/index.rst create mode 100644 Documentation/vpu/vpu-stack-overview.rst diff --git a/Documentation/index.rst b/Documentation/index.rst index 5888e8a7272f..81a02f2af939 100644 --- a/Documentation/index.rst +++ b/Documentation/index.rst @@ -137,6 +137,7 @@ needed). misc-devices/index scheduler/index mhi/index + vpu/index Architecture-agnostic documentation --- diff --git a/Documentation/vpu/index.rst b/Documentation/vpu/index.rst new file mode 100644 index ..7e290e048910 --- /dev/null +++ b/Documentation/vpu/index.rst @@ -0,0 +1,16 @@ +.. SPDX-License-Identifier: GPL-2.0-only + + +Vision Processor Unit Documentation + + +This documentation contains information for the Intel VPU stack. + +.. class:: toc-title + + Table of contents + +.. toctree:: + :maxdepth: 2 + + vpu-stack-overview diff --git a/Documentation/vpu/vpu-stack-overview.rst b/Documentation/vpu/vpu-stack-overview.rst new file mode 100644 index ..1fe9ce423177 --- /dev/null +++ b/Documentation/vpu/vpu-stack-overview.rst @@ -0,0 +1,270 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== +Intel VPU architecture +== + +Overview + + +The Intel Movidius acquisition has developed a Vision Processing Unit (VPU) +roadmap of products starting with Keem Bay (KMB). The hardware configurations +the VPU can support include: + +1. Standalone smart camera that does local Computer Vision (CV) processing in + camera +2. Standalone appliance or signel board computer connected to a network and + tethered cameras doing local CV processing +3. Embedded in a USB dongle or M.2 as an CV accelerator. +4. Multiple VPU enabled SOC's on a PCIe card as a CV accelerator in a larger IA + box or server. + +Keem Bay is the first instance of this family of products. This document +provides an architectural overview of the software stack supporting the VPU +enabled products. + +Keem Bay (KMB) is a Computer Vision AI processing SoC based on ARM A53 CPU that +provides Edge neural network acceleration (inference) and includes a Vision +Processing Unit (VPU) hardware. The ARM CPU SubSystem (CPUSS) interfaces +locally to the VPU and enables integration/interfacing with a remote host over +PCIe or USB or Ethernet interfaces. The interface between the CPUSS and the VPU +is implemented with hardware FIFOs (Control) and coherent memory mapping (Data) +such that zero copy processing can happen within the VPU. + +The KMB can be used in all 4 of the above classes of designs. + +We refer to the 'local host' as being the ARM part of the SoC, while the +'remote host' as the IA system hosting the KMB device(s). The KMB SoC boots +from an eMMC via uBoot and ARM Linux compatible device tree interface with an +expectation to fully boot within hundreds of milliseconds. There is also +support for downloading the kernel and root file system image from a remote +host. + +The eMMC can be updated with standard Mender update process. +See https://github.com/mendersoftware/mender + +The VPU is started and controlled from the A53 local host. Its firmware image +is loaded using the drive firware helper KAPI's. + +The VPU IP firware payload consists of a SPARC ISA RTEMS bootloader and/or +application binary. + +The interface allowing (remote or local) host clients to access VPU IP +capabilities is realized through an abstracted programming model, which +provides Remote Proxy APIs for a host CPU application to dynamically create and +execute CV and NN workloads on the VPU. All frameworks exposed through +programming model’s APIs are contained in the pre-compiled standard firmware +image. + +There is a significant software stack built up to support KMB and the use +cases. The rest of this documentation provides an overview of the components +of the stack. + +Keem Bay IPC + + +Directly interfaces with the KMB hardware FIFOs to provide zero copy processing +from the VPU. It implements the lowest level protocol for interacting with the +VPU. + +The Keem Bay IPC mechanism is based on shared memory and hardware FIFOs. +Specifically there are: + +* Two 128-entry hardware FIFOs, one for the CPU and one for the VPU. +* Two shared memory regions, used as memory pool for allocating IPC buffers. + +An IPC channel is a software abstraction allowing communication multiplexing, +so that multiple a
[PATCH v4 28/34] misc: Intel tsens IA host driver.
From: "C, Udhayakumar"
Add Intel tsens IA host driver for Intel Edge.AI Computer Vision
platforms.
About Intel Edge.AI Computer Vision platforms:
-
The Intel Edge.AI Computer Vision platforms are vision processing systems
targeting machine vision applications for connected devices.
They are based on ARM A53 CPU running Linux and acts as a PCIe
endpoint device.
High-level architecture:
Remote Host IA CPU Local Host ARM CPU
--
| Platform| | Thermal Daemon|
| Management SW| ||
--
| Intel tsens | | intel tsens i2c slave |
| i2c client | | and thermal driver|
--
| XLINK I2C | | XLINK I2C Slave |
| controller | <=> | controller |
xlink smbus --
intel tsens module:
---
The tsens module enables reading of on chip sensors present
in the Intel Edge.AI Computer Vision platforms.In the tsens module
various junction and SoC temperatures are reported using thermal
subsystem and i2c subsystem.
Temperature data reported using thermal subsystem will be used for
various cooling agents such as DVFS, fan control and shutdown the
system in case of critical temperature.
Temperature data reported using i2c subsystem will be used by
platform manageability software running in IA host.
- Remote Host driver
* Intended for IA CPU
* It is a I2C client driver
* Driver path:
{tree}/drivers/misc/intel_tsens/intel_tsens_host.c
Local host and Remote host drivers communicates using
I2C SMBUS protocol.
Acked-by: Mark Mross
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/intel_tsens_host.rst| 71
drivers/misc/intel_tsens/Kconfig| 13 +
drivers/misc/intel_tsens/Makefile | 1 +
drivers/misc/intel_tsens/intel_tsens_host.c | 351
include/linux/intel_tsens_host.h| 34 ++
6 files changed, 471 insertions(+)
create mode 100644 Documentation/hwmon/intel_tsens_host.rst
create mode 100644 drivers/misc/intel_tsens/intel_tsens_host.c
create mode 100644 include/linux/intel_tsens_host.h
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index fc29100bef73..7a9eaddd1ab3 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -81,6 +81,7 @@ Hardware Monitoring Kernel Drivers
isl68137
it87
intel_tsens_sensor.rst
+ intel_tsens_host.rst
jc42
k10temp
k8temp
diff --git a/Documentation/hwmon/intel_tsens_host.rst
b/Documentation/hwmon/intel_tsens_host.rst
new file mode 100644
index ..012c593f969f
--- /dev/null
+++ b/Documentation/hwmon/intel_tsens_host.rst
@@ -0,0 +1,71 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+==
+Kernel driver: intel_tsens
+==
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+
+Slave address: The address is assigned by the hddl device management
+ driver.
+
+Datasheet:
+ Documentation/hwmon/intel_tsens_sensor.rst#Remote Thermal Interface
+
+Authors:
+- Thalaiappan, Rathina
+
+Description
+===
+The intel_tsens is a temperature sensor driver receiving the junction
temperature
+from different heating points inside the SOC. The driver will receive the
+temperature on SMBUS connection. The reported temperature is in degrees
Celsius.
+
+In Keem Bay, the four thermal junction temperature points are,
+Media Subsystem (mss), NN subsystem (nce), Compute subsystem (cse) and
+SOC(Maximum of mss, nce and cse).
+
+Example
+===
+Temperature reported by a Keem Bay on the Linux Thermal sysfs interface.
+
+# cat /sys/class/thermal/thermal_zone*/type
+mss
+css
+nce
+soc
+
+# cat /sys/class/thermal/thermal_zone*/temp
+0
+29210
+28478
+29210
+
++---+-+
+| offset| Sensor|
++---+-+
+| 0 | mss |
++---+-+
+| 1 | css |
++---+-+
+| 2 | nce |
++---+-+
+| 3 | soc |
++---+-+
+
+#sudo i2cdetect -l
+i2c-8 smbus SMBus I801 adapter at efa0 SMBus adapte
r
+
+To read mss junction temperature:
+#i2cget -y 8 0x0 w
+
+To read cse junction temperature:
+#i2cget -y 8 0x1 w
+
+To read nce junction temperature:
+#i2cget -y 8 0x2 w
+
+To read overall SoC temperature:
+#i2cget -y 8 0x3 w
diff --git a/drivers/misc/intel_tsens/Kconfig b/drivers/misc/intel_tsens/Kconfig
[PATCH v3 25/34] misc: Add Keem Bay VPU manager
From: "Li, Tingqian"
VPU IP on Keem Bay SOC is a vision acceleration IP complex
under the control of a RTOS-based firmware (running on RISC
MCU inside the VPU IP) serving user-space application
running on CPU side for HW accelerated computer vision tasks.
This module is kernel counterpart of the VPUAL(VPU abstraction
layer) which bridges firmware on VPU side and applications on
CPU user-space, it assists firmware on VPU side serving multiple
user space application processes on CPU side concurrently while
also performing necessary data buffer management on behave of
VPU IP.
objmgr provides basic infrastructure for create/destroy VPU side
software object concurrently on demand of user-space application
and also automatically release leaked objects during handling of
application termination. Note this module only cares about the
life-cycle of such objects, it's up to the application and firmware
to define the behavior/operations of each object.
objmgr does it's job by communicating with firmware through a fixed
reserved xlink channel, using a very simple message protocol.
smm provides DMABuf allocation/import facilities to allow user-space
app pass data to/from VPU in zero-copy fashion. it also provided a
convenient ioctl function for converting virtual pointer of a mem-mapped
and imported DMABuf into it's corresponding dma address, to allow
user-space app to specify the sub-regions of a bigger DMABuf to be
processed by VPU.
Signed-off-by: Li, Tingqian
Signed-off-by: Zhou, Luwei
Signed-off-by: Wang, jue
---
drivers/misc/Kconfig | 1 +
drivers/misc/Makefile| 1 +
drivers/misc/vpumgr/Kconfig | 9 +
drivers/misc/vpumgr/Makefile | 3 +
drivers/misc/vpumgr/vpu_common.h | 31 ++
drivers/misc/vpumgr/vpu_mgr.c| 370
drivers/misc/vpumgr/vpu_smm.c| 554 +
drivers/misc/vpumgr/vpu_smm.h| 30 ++
drivers/misc/vpumgr/vpu_vcm.c| 584 +++
drivers/misc/vpumgr/vpu_vcm.h| 84 +
include/uapi/misc/vpumgr.h | 64
11 files changed, 1731 insertions(+)
create mode 100644 drivers/misc/vpumgr/Kconfig
create mode 100644 drivers/misc/vpumgr/Makefile
create mode 100644 drivers/misc/vpumgr/vpu_common.h
create mode 100644 drivers/misc/vpumgr/vpu_mgr.c
create mode 100644 drivers/misc/vpumgr/vpu_smm.c
create mode 100644 drivers/misc/vpumgr/vpu_smm.h
create mode 100644 drivers/misc/vpumgr/vpu_vcm.c
create mode 100644 drivers/misc/vpumgr/vpu_vcm.h
create mode 100644 include/uapi/misc/vpumgr.h
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 09ae65e98681..2d1f7b165cc8 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -484,4 +484,5 @@ source "drivers/misc/uacce/Kconfig"
source "drivers/misc/xlink-pcie/Kconfig"
source "drivers/misc/xlink-ipc/Kconfig"
source "drivers/misc/xlink-core/Kconfig"
+source "drivers/misc/vpumgr/Kconfig"
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f3a6eb03bae9..2936930f3edc 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
obj-y += xlink-pcie/
obj-$(CONFIG_XLINK_IPC)+= xlink-ipc/
obj-$(CONFIG_XLINK_CORE) += xlink-core/
+obj-$(CONFIG_VPUMGR) += vpumgr/
diff --git a/drivers/misc/vpumgr/Kconfig b/drivers/misc/vpumgr/Kconfig
new file mode 100644
index ..bb82ff83afd3
--- /dev/null
+++ b/drivers/misc/vpumgr/Kconfig
@@ -0,0 +1,9 @@
+config VPUMGR
+ tristate "VPU Manager"
+ depends on ARM64 && XLINK_CORE
+ help
+ VPUMGR manages life-cycle of VPU related resources which were
+ dynamically allocated on demands of user-space application
+
+ Select y or m if you have a processor including the Intel
+ Vision Processor (VPU) on it.
diff --git a/drivers/misc/vpumgr/Makefile b/drivers/misc/vpumgr/Makefile
new file mode 100644
index ..51441dc8a930
--- /dev/null
+++ b/drivers/misc/vpumgr/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_VPUMGR) += vpumgr.o
+vpumgr-objs := vpu_mgr.o vpu_smm.o vpu_vcm.o
diff --git a/drivers/misc/vpumgr/vpu_common.h b/drivers/misc/vpumgr/vpu_common.h
new file mode 100644
index ..cd474ffc05f3
--- /dev/null
+++ b/drivers/misc/vpumgr/vpu_common.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ * VPUMGR Kernel module - common definition
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+#ifndef _VPU_COMMON_H
+#define _VPU_COMMON_H
+#include
+#include
+
+#include
+
+#include "vpu_vcm.h"
+
+/* there will be one such device for each HW instance */
+struct vpumgr_device {
+ struct device *sdev;
+ struct device *dev;
+ dev_t devnum;
+ struct cdev cdev;
+ struct platform_device *pdev;
+
+ struct vcm_dev vcm;
+ struct dentry *debugfs_root;
+
+ struct mutex client_mutex; /
[PATCH v3 10/34] misc: xlink-pcie: lh: Add PCIe EP DMA functionality
From: Srikanth Thokala Add Synopsys PCIe DWC core embedded-DMA functionality for local host Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Reviewed-by: Mark Gross Signed-off-by: Srikanth Thokala --- drivers/misc/xlink-pcie/local_host/Makefile | 1 + drivers/misc/xlink-pcie/local_host/dma.c| 575 drivers/misc/xlink-pcie/local_host/epf.c| 15 +- drivers/misc/xlink-pcie/local_host/epf.h| 41 ++ 4 files changed, 629 insertions(+), 3 deletions(-) create mode 100644 drivers/misc/xlink-pcie/local_host/dma.c diff --git a/drivers/misc/xlink-pcie/local_host/Makefile b/drivers/misc/xlink-pcie/local_host/Makefile index 514d3f0c91bc..54fc118e2dd1 100644 --- a/drivers/misc/xlink-pcie/local_host/Makefile +++ b/drivers/misc/xlink-pcie/local_host/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o mxlk_ep-objs := epf.o +mxlk_ep-objs += dma.o diff --git a/drivers/misc/xlink-pcie/local_host/dma.c b/drivers/misc/xlink-pcie/local_host/dma.c new file mode 100644 index ..42978fb0db49 --- /dev/null +++ b/drivers/misc/xlink-pcie/local_host/dma.c @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Keem Bay XLink PCIe Driver + * + * Copyright (C) 2021 Intel Corporation + */ +#include +#include +#include + +#include "epf.h" + +#define DMA_DBI_OFFSET (0x38) + +/* PCIe DMA control 1 register definitions. */ +#define DMA_CH_CONTROL1_CB_SHIFT (0) +#define DMA_CH_CONTROL1_TCB_SHIFT (1) +#define DMA_CH_CONTROL1_LLP_SHIFT (2) +#define DMA_CH_CONTROL1_LIE_SHIFT (3) +#define DMA_CH_CONTROL1_CS_SHIFT (5) +#define DMA_CH_CONTROL1_CCS_SHIFT (8) +#define DMA_CH_CONTROL1_LLE_SHIFT (9) +#define DMA_CH_CONTROL1_CB_MASK(BIT(DMA_CH_CONTROL1_CB_SHIFT)) +#define DMA_CH_CONTROL1_TCB_MASK (BIT(DMA_CH_CONTROL1_TCB_SHIFT)) +#define DMA_CH_CONTROL1_LLP_MASK (BIT(DMA_CH_CONTROL1_LLP_SHIFT)) +#define DMA_CH_CONTROL1_LIE_MASK (BIT(DMA_CH_CONTROL1_LIE_SHIFT)) +#define DMA_CH_CONTROL1_CS_MASK(0x3 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CCS_MASK (BIT(DMA_CH_CONTROL1_CCS_SHIFT)) +#define DMA_CH_CONTROL1_LLE_MASK (BIT(DMA_CH_CONTROL1_LLE_SHIFT)) + +/* DMA control 1 register Channel Status */ +#define DMA_CH_CONTROL1_CS_RUNNING (0x1 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CS_HALTED (0x2 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CS_STOPPED (0x3 << DMA_CH_CONTROL1_CS_SHIFT) + +/* PCIe DMA Engine enable register definitions. */ +#define DMA_ENGINE_EN_SHIFT(0) +#define DMA_ENGINE_EN_MASK (BIT(DMA_ENGINE_EN_SHIFT)) + +/* PCIe DMA interrupt registers definitions. */ +#define DMA_ABORT_INTERRUPT_SHIFT (16) +#define DMA_ABORT_INTERRUPT_MASK (0xFF << DMA_ABORT_INTERRUPT_SHIFT) +#define DMA_ABORT_INTERRUPT_CH_MASK(_c) (BIT(_c) << DMA_ABORT_INTERRUPT_SHIFT) +#define DMA_DONE_INTERRUPT_MASK(0xFF) +#define DMA_DONE_INTERRUPT_CH_MASK(_c) (BIT(_c)) +#define DMA_ALL_INTERRUPT_MASK \ + (DMA_ABORT_INTERRUPT_MASK | DMA_DONE_INTERRUPT_MASK) + +#define DMA_LL_ERROR_SHIFT (16) +#define DMA_CPL_ABORT_SHIFT(8) +#define DMA_CPL_TIMEOUT_SHIFT (16) +#define DMA_DATA_POI_SHIFT (24) +#define DMA_AR_ERROR_CH_MASK(_c) (BIT(_c)) +#define DMA_LL_ERROR_CH_MASK(_c) (BIT(_c) << DMA_LL_ERROR_SHIFT) +#define DMA_UNREQ_ERROR_CH_MASK(_c)(BIT(_c)) +#define DMA_CPL_ABORT_ERROR_CH_MASK(_c)(BIT(_c) << DMA_CPL_ABORT_SHIFT) +#define DMA_CPL_TIMEOUT_ERROR_CH_MASK(_c) (BIT(_c) << DMA_CPL_TIMEOUT_SHIFT) +#define DMA_DATA_POI_ERROR_CH_MASK(_c) (BIT(_c) << DMA_DATA_POI_SHIFT) + +#define DMA_LLLAIE_SHIFT (16) +#define DMA_LLLAIE_MASK(0xF << DMA_LLLAIE_SHIFT) + +#define DMA_CHAN_WRITE_MAX_WEIGHT (0x7) +#define DMA_CHAN_READ_MAX_WEIGHT (0x3) +#define DMA_CHAN0_WEIGHT_OFFSET(0) +#define DMA_CHAN1_WEIGHT_OFFSET(5) +#define DMA_CHAN2_WEIGHT_OFFSET(10) +#define DMA_CHAN3_WEIGHT_OFFSET(15) +#define DMA_CHAN_WRITE_ALL_MAX_WEIGHT \ + ((DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN0_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN1_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN2_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN3_WEIGHT_OFFSET)) +#define DMA_CHAN_READ_ALL_MAX_WEIGHT \ + ((DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN0_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN1_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN2_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN3_WEIGHT_OFFSET)) + +#define PCIE_REGS_PCIE_APP_CNTRL 0x8 +#define APP_XFER_PENDING BIT(6) +#define PCIE_REGS_PCIE_SII_PM_S
[PATCH v4 03/34] mailbox: vpu-ipc-mailbox: Add support for Intel VPU IPC mailbox
From: Daniele Alessandrelli Add mailbox controller enabling inter-processor communication (IPC) between the CPU (aka, the Application Processor - AP) and the VPU on Intel Movidius SoCs like Keem Bay. The controller uses HW FIFOs to enable such communication. Specifically, there are two FIFOs, one for the CPU and one for VPU. Each FIFO can hold 128 entries (messages) of 32-bit each (but only 26 bits are actually usable, since the 6 least-significant bits are reserved). When the Linux kernel on the AP needs to send messages to the VPU firmware, it writes them to the VPU FIFO; similarly, when the VPU firmware needs to send messages to the AP, it writes them to the CPU FIFO. The AP is notified of pending messages in the CPU FIFO by means of the 'FIFO-not-empty' interrupt, which is generated by the CPU FIFO while not empty. This interrupt is cleared automatically once all messages have been read from the FIFO (i.e., the FIFO has been emptied). The hardware doesn't provide an TX done IRQ (i.e., an IRQ that allows the VPU firmware to notify the AP that the message put into the VPU FIFO has been received); however the AP can ensure that the message has been successfully put into the VPU FIFO (and therefore transmitted) by checking the VPU FIFO status register to ensure that writing the message didn't cause the FIFO to overflow. Therefore, the mailbox controller is configured as capable of tx_done IRQs and a tasklet is used to simulate the tx_done IRQ. The tasklet is activated by send_data() right after the message has been put into the VPU FIFO and the VPU FIFO status registers has been checked. If an overflow is reported by the status register, the tasklet passes -EBUSY to mbox_chan_txdone(), to notify the mailbox client of the failed TX. The client should therefore register a tx_done() callback to properly handle failed transmissions. Note: the 'txdone_poll' mechanism cannot be used because it doesn't provide a way to report a failed transmission. Reviewed-by: Mark Gross Signed-off-by: Daniele Alessandrelli Signed-off-by: Mark Gross --- MAINTAINERS | 1 + drivers/mailbox/Kconfig | 11 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/vpu-ipc-mailbox.c | 297 ++ 4 files changed, 311 insertions(+) create mode 100644 drivers/mailbox/vpu-ipc-mailbox.c diff --git a/MAINTAINERS b/MAINTAINERS index 2b82526a00dc..de23f6e5cfce 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9186,6 +9186,7 @@ M:Daniele Alessandrelli M: Mark Gross S: Supported F: Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml +F: drivers/mailbox/vpu-ipc-mailbox.c INTEL WIRELESS 3945ABG/BG, 4965AGN (iwlegacy) M: Stanislaw Gruszka diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index f4abe3529acd..cb50b541a5c6 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -29,6 +29,17 @@ config IMX_MBOX help Mailbox implementation for i.MX Messaging Unit (MU). +config INTEL_VPU_IPC_MBOX + tristate "Intel VPU IPC Mailbox" + depends on HAS_IOMEM + depends on OF || COMPILE_TEST + help + Mailbox implementation for enabling inter-processor communication + between application processors and Intel VPUs. + + Say Y or M here if you are building for an SoC equipped with an Intel + VPU. If M is selected, the module will be called vpu-ipc-mailbox. + config PLATFORM_MHU tristate "Platform MHU Mailbox" depends on OF diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 7194fa92c787..68768bb2ee43 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -56,3 +56,5 @@ obj-$(CONFIG_SUN6I_MSGBOX)+= sun6i-msgbox.o obj-$(CONFIG_SPRD_MBOX)+= sprd-mailbox.o obj-$(CONFIG_QCOM_IPCC)+= qcom-ipcc.o + +obj-$(CONFIG_INTEL_VPU_IPC_MBOX) += vpu-ipc-mailbox.o diff --git a/drivers/mailbox/vpu-ipc-mailbox.c b/drivers/mailbox/vpu-ipc-mailbox.c new file mode 100644 index ..ad161a7bbabb --- /dev/null +++ b/drivers/mailbox/vpu-ipc-mailbox.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel VPU IPC mailbox driver. + * + * Copyright (c) 2020-2021 Intel Corporation. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * The IPC FIFO registers (offsets to the base address defined in device tree). + */ + +/* + * TIM_IPC_FIFO - Write a 32-bit entry to FIFO. + * + * The entry to be put in the FIFO must be written to this register. + * + * NOTE: the 6 least-significant bits are reserved for the writing processor + * to include its processor ID, 0 <= x <= 62, so it can determine if the entry + * was written correctly by checking the appropriate bit of register + * TIM_IPC_FIFO_OF_FLAG[n]. + * + * Internally, the hardware increments FIFO write pointer and fill level. + * + */ +#define IPC_FIF
[PATCH v4 30/34] misc:intel_tsens: Intel Keem Bay tsens driver.
From: "C, Udhayakumar"
Add keembey_thermal driver to expose on chip temperature
sensors, and register call back functions for periodic sampling.
This driver does following:
* Reads temperature data from on chip sensors present in Keem Bay
platform.
* Registers callback function to intel tsens driver for sampling
temperature values periodically.
* Decode the raw values from registers to Celsius.
Acked-by: mark gross
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
drivers/misc/intel_tsens/Kconfig | 12 +
drivers/misc/intel_tsens/Makefile | 1 +
drivers/misc/intel_tsens/keembay_thermal.c | 169 ++
drivers/misc/intel_tsens/keembay_tsens.h | 366 +
4 files changed, 548 insertions(+)
create mode 100644 drivers/misc/intel_tsens/keembay_thermal.c
create mode 100644 drivers/misc/intel_tsens/keembay_tsens.h
diff --git a/drivers/misc/intel_tsens/Kconfig b/drivers/misc/intel_tsens/Kconfig
index be8d27e81864..5cfe6b4004e5 100644
--- a/drivers/misc/intel_tsens/Kconfig
+++ b/drivers/misc/intel_tsens/Kconfig
@@ -28,6 +28,18 @@ config INTEL_TSENS_I2C_SLAVE
Say Y if using a processor that includes the Intel VPU such as
Keem Bay. If unsure, say N.
+config KEEMBAY_THERMAL
+ tristate "Temperature sensor driver for intel Keem Bay"
+ depends on INTEL_TSENS_LOCAL_HOST && ARCH_KEEMBAY
+ help
+ Enable this option if you want to have support for Keem Bay
+ thermal management sensors.
+
+ This driver is used for reading onchip temperature sensor
+ values from Keem Bay SoC.
+ Say Y if using a processor that includes the Intel VPU such as
+ Keem Bay. If unsure, say N.
+
config INTEL_TSENS_IA_HOST
tristate "Temperature sensor driver for intel tsens remote host"
depends on I2C && THERMAL
diff --git a/drivers/misc/intel_tsens/Makefile
b/drivers/misc/intel_tsens/Makefile
index f6f41bbca80c..00f63c2d5b2f 100644
--- a/drivers/misc/intel_tsens/Makefile
+++ b/drivers/misc/intel_tsens/Makefile
@@ -7,3 +7,4 @@
obj-$(CONFIG_INTEL_TSENS_LOCAL_HOST) += intel_tsens_thermal.o
obj-$(CONFIG_INTEL_TSENS_I2C_SLAVE)+= intel_tsens_i2c.o
obj-$(CONFIG_INTEL_TSENS_IA_HOST) += intel_tsens_host.o
+obj-$(CONFIG_KEEMBAY_THERMAL) += keembay_thermal.o
diff --git a/drivers/misc/intel_tsens/keembay_thermal.c
b/drivers/misc/intel_tsens/keembay_thermal.c
new file mode 100644
index ..d6c8fa8fc3aa
--- /dev/null
+++ b/drivers/misc/intel_tsens/keembay_thermal.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *
+ * Intel Keem Bay thermal Driver
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "intel_tsens_thermal.h"
+#include "keembay_tsens.h"
+
+struct keembay_thermal_priv {
+ const char *name;
+ void __iomem *base_addr;
+ /* sensor lock*/
+ spinlock_t lock;
+ int current_temp[KEEMBAY_SENSOR_MAX];
+ struct intel_tsens_plat_data *plat_data;
+};
+
+static void kmb_sensor_read_temp(void __iomem *regs_val,
+int offset,
+int sample_valid_mask,
+int sample_value,
+int bit_shift,
+int *temp)
+{
+ int reg_val, kmb_raw_index;
+
+ /* clear the bit of TSENS_EN and re-enable again */
+ iowrite32(0x00, regs_val + AON_TSENS_CFG);
+ iowrite32(CFG_MASK_MANUAL, regs_val + AON_TSENS_CFG);
+ reg_val = ioread32(regs_val + offset);
+ if (reg_val & sample_valid_mask) {
+ reg_val = (reg_val >> bit_shift) & sample_value;
+ kmb_raw_index = reg_val - KEEMBAY_SENSOR_BASE_TEMP;
+ if (kmb_raw_index < 0)
+ reg_val = raw_kmb[0];
+ else if (kmb_raw_index > (raw_kmb_size - 1))
+ reg_val = raw_kmb[raw_kmb_size - 1];
+ else
+ reg_val = raw_kmb[kmb_raw_index];
+ *temp = reg_val;
+ } else {
+ *temp = -255;
+ }
+}
+
+/*The lock is assumed to be held by the caller.*/
+static int keembay_get_temp(struct platform_device *pdev, int type, int *temp)
+{
+ struct keembay_thermal_priv *priv = platform_get_drvdata(pdev);
+
+ spin_lock(&priv->lock);
+ switch (type) {
+ case KEEMBAY_SENSOR_MSS:
+ kmb_sensor_read_temp(priv->base_addr,
+AON_TSENS_DATA0,
+MSS_T_SAMPLE_VALID,
+MSS_T_SAMPLE,
+MSS_BIT_SHIFT,
+temp);
+ priv->current_temp[KEEMBAY_SENSOR_MSS] = *temp;
+ break;
+
+ case KEEMBAY_SENSOR_CSS:
+
[PATCH v4 27/34] misc: Tsens ARM host thermal driver.
From: "C, Udhayakumar"
Add tsens ARM host thermal driver for Intel Edge.AI Computer Vision
platforms.
About Intel Edge.AI Computer Vision platforms:
-
The Intel Edge.AI Computer Vision platforms are vision processing systems
targeting machine vision applications for connected devices.
They are based on ARM A53 CPU running Linux and acts as a PCIe
endpoint device.
High-level architecture:
Remote Host IA CPULocal Host ARM CPU
--
| Platform| | Thermal Daemon|
| Management SW| ||
--
| Intel tsens | | intel tsens i2c slave |
| i2c client | | and thermal driver|
--
| XLINK I2C | | XLINK I2C Slave |
| controller | <=> | controller |
smbus--
intel tsens module:
---
The tsens module enables reading of on chip sensors present
in the Intel Edge.AI Computer Vision platforms. In the tsens module
various junction and SoC temperatures are reported using thermal
subsystem and i2c subsystem.
Temperature data reported using thermal subsystem will be used for
various cooling agents such as DVFS, fan control and shutdown the
system in case of critical temperature.
Temperature data reported using i2c subsystem will be used by
platform manageability software running in IA host.
- Local Host driver
* Intended for ARM CPU
* It is based on Thermal and I2C slave Framework
* Driver path:
{tree}/drivers/misc/intel_tsens/intel_tsens_thermal.c
Local host and Remote host drivers communicates using
XLINK I2C SMBUS protocol.
Acked-by: Mark Gross
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/intel_tsens_sensor.rst| 67 ++
MAINTAINERS | 5 +
drivers/misc/Kconfig | 1 +
drivers/misc/Makefile | 1 +
drivers/misc/intel_tsens/Kconfig | 15 +
drivers/misc/intel_tsens/Makefile | 7 +
.../misc/intel_tsens/intel_tsens_thermal.c| 651 ++
.../misc/intel_tsens/intel_tsens_thermal.h| 38 +
include/linux/hddl_device.h | 153
10 files changed, 939 insertions(+)
create mode 100644 Documentation/hwmon/intel_tsens_sensor.rst
create mode 100644 drivers/misc/intel_tsens/Kconfig
create mode 100644 drivers/misc/intel_tsens/Makefile
create mode 100644 drivers/misc/intel_tsens/intel_tsens_thermal.c
create mode 100644 drivers/misc/intel_tsens/intel_tsens_thermal.h
create mode 100644 include/linux/hddl_device.h
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index fcb870ce6286..fc29100bef73 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -80,6 +80,7 @@ Hardware Monitoring Kernel Drivers
ir38064
isl68137
it87
+ intel_tsens_sensor.rst
jc42
k10temp
k8temp
diff --git a/Documentation/hwmon/intel_tsens_sensor.rst
b/Documentation/hwmon/intel_tsens_sensor.rst
new file mode 100644
index ..0f53dfca477e
--- /dev/null
+++ b/Documentation/hwmon/intel_tsens_sensor.rst
@@ -0,0 +1,67 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+==
+Kernel driver: intel_tsens_thermal
+==
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+
+Slave address: The address is assigned by the hddl device management
+ driver.
+
+Authors:
+- Thalaiappan, Rathina
+- Udhayakumar C
+
+Description
+===
+The Intel Edge.AI Computer Vision platforms have memory mapped thermal sensors
+which are accessible locally. The intel_tsens_thermal driver handles these
+thermal sensor and exposes the temperature to
+
+* the external host similar to the standard SMBUS based thermal sensor
+(like LM73) to the host by registering to the I2C subsystem as
+slave interface (Documentation/i2c/slave-interface.rst).
+* the local CPU as a standard thermal device.
+
+In Keem Bay, the four thermal junction temperature points are,
+Media Subsystem (mss), NN subsystem (nce), Compute subsystem (cse) and
+SOC(Maximum of mss, nce and cse).
+
+Similarity: /drivers/thermal/qcom
+
+Example
+===
+Local Thermal Interface:
+
+Temperature reported in Keem Bay on the Linux Thermal sysfs interface.
+
+# cat /sys/class/thermal/thermal_zone*/type
+mss
+css
+nce
+soc
+
+# cat /sys/class/thermal/thermal_zone*/temp
+0
+29210
+28478
+29210
+
+Remote Thermal Interface:
+
+tsens i2c slave driver reports temperature of v
[PATCH v4 13/34] misc: xlink-pcie: rh: Add PCIe EP driver for Remote Host
From: Srikanth Thokala
Add PCIe Endpoint driver that configures PCIe BARs and MSIs on the
Remote Host
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
MAINTAINERS | 2 +-
drivers/misc/xlink-pcie/Kconfig | 11 +
drivers/misc/xlink-pcie/Makefile | 1 +
drivers/misc/xlink-pcie/common/xpcie.h | 1 +
drivers/misc/xlink-pcie/remote_host/Makefile | 3 +
drivers/misc/xlink-pcie/remote_host/main.c | 90
drivers/misc/xlink-pcie/remote_host/pci.c| 449 +++
drivers/misc/xlink-pcie/remote_host/pci.h| 62 +++
8 files changed, 618 insertions(+), 1 deletion(-)
create mode 100644 drivers/misc/xlink-pcie/remote_host/Makefile
create mode 100644 drivers/misc/xlink-pcie/remote_host/main.c
create mode 100644 drivers/misc/xlink-pcie/remote_host/pci.c
create mode 100644 drivers/misc/xlink-pcie/remote_host/pci.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3ca6c8c6341b..e05fa34d72ce 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1961,7 +1961,7 @@ F:
Documentation/devicetree/bindings/arm/intel,keembay.yaml
F: arch/arm64/boot/dts/intel/keembay-evm.dts
F: arch/arm64/boot/dts/intel/keembay-soc.dtsi
-ARM KEEM BAY XLINK PCIE SUPPORT
+ARM/INTEL KEEM BAY XLINK PCIE SUPPORT
M: Srikanth Thokala
M: Mark Gross
S: Supported
diff --git a/drivers/misc/xlink-pcie/Kconfig b/drivers/misc/xlink-pcie/Kconfig
index 46aa401d79b7..448b9bfbdfa2 100644
--- a/drivers/misc/xlink-pcie/Kconfig
+++ b/drivers/misc/xlink-pcie/Kconfig
@@ -1,3 +1,14 @@
+config XLINK_PCIE_RH_DRIVER
+ tristate "XLink PCIe Remote Host driver"
+ depends on PCI && X86_64
+ help
+ This option enables XLink PCIe Remote Host driver.
+
+ Choose M here to compile this driver as a module, name is mxlk.
+ This driver is used for XLink communication over PCIe,
+ and is to be loaded on the IA host which is connected to
+ the Intel Keem Bay.
+
config XLINK_PCIE_LH_DRIVER
tristate "XLink PCIe Local Host driver"
depends on PCI_ENDPOINT && ARCH_KEEMBAY
diff --git a/drivers/misc/xlink-pcie/Makefile b/drivers/misc/xlink-pcie/Makefile
index d693d382e9c6..1dd984d8d88c 100644
--- a/drivers/misc/xlink-pcie/Makefile
+++ b/drivers/misc/xlink-pcie/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_XLINK_PCIE_RH_DRIVER) += remote_host/
obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += local_host/
diff --git a/drivers/misc/xlink-pcie/common/xpcie.h
b/drivers/misc/xlink-pcie/common/xpcie.h
index 48529eb49be0..b5cf9242a59a 100644
--- a/drivers/misc/xlink-pcie/common/xpcie.h
+++ b/drivers/misc/xlink-pcie/common/xpcie.h
@@ -69,6 +69,7 @@ struct xpcie_mmio {
struct xpcie {
u32 status;
bool legacy_a0;
+ void *bar0;
void *mmio;
void *bar4;
diff --git a/drivers/misc/xlink-pcie/remote_host/Makefile
b/drivers/misc/xlink-pcie/remote_host/Makefile
new file mode 100644
index ..96374a43023e
--- /dev/null
+++ b/drivers/misc/xlink-pcie/remote_host/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_XLINK_PCIE_RH_DRIVER) += mxlk.o
+mxlk-objs := main.o
+mxlk-objs += pci.o
diff --git a/drivers/misc/xlink-pcie/remote_host/main.c
b/drivers/misc/xlink-pcie/remote_host/main.c
new file mode 100644
index ..ed1a431ed5d4
--- /dev/null
+++ b/drivers/misc/xlink-pcie/remote_host/main.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include "pci.h"
+#include "../common/core.h"
+
+#define HW_ID_LO_MASK GENMASK(7, 0)
+#define HW_ID_HI_MASK GENMASK(15, 8)
+
+static const struct pci_device_id xpcie_pci_table[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KEEMBAY), 0 },
+ { 0 }
+};
+
+static int intel_xpcie_probe(struct pci_dev *pdev,
+const struct pci_device_id *ent)
+{
+ bool new_device = false;
+ struct xpcie_dev *xdev;
+ u32 sw_devid;
+ u16 hw_id;
+ int ret;
+
+ hw_id = FIELD_PREP(HW_ID_HI_MASK, pdev->bus->number) |
+ FIELD_PREP(HW_ID_LO_MASK, PCI_SLOT(pdev->devfn));
+
+ sw_devid = FIELD_PREP(XLINK_DEV_INF_TYPE_MASK,
+ XLINK_DEV_INF_PCIE) |
+ FIELD_PREP(XLINK_DEV_PHYS_ID_MASK, hw_id) |
+ FIELD_PREP(XLINK_DEV_TYPE_MASK, XLINK_DEV_TYPE_KMB) |
+ FIELD_PREP(XLINK_DEV_PCIE_ID_MASK, XLINK_DEV_PCIE_0) |
+ FIELD_PREP(XLINK_DEV_FUNC_MASK, XLINK_DEV_FUNC_VPU);
+
+ xdev = intel_xpcie_get_device_by_id(sw_devid);
+ if (!xdev) {
+ xdev = intel_xpcie_create_device(sw_devid, pdev);
+ if (!xdev)
+ return -ENOMEM;
+
+ new_device = true;
+ }
+
+ ret = intel_xpcie_pci_init(xdev, pdev);
+ if (ret) {
+ intel_xpci
[PATCH v3 12/34] misc: xlink-pcie: lh: Prepare changes for adding remote host driver
From: Srikanth Thokala
Move logic that can be reused between local host and remote host to
common/ folder
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/{local_host => common}/core.h | 8 +++-
drivers/misc/xlink-pcie/{local_host => common}/util.c | 8 +++-
drivers/misc/xlink-pcie/{local_host => common}/util.h | 8 +++-
drivers/misc/xlink-pcie/{local_host => common}/xpcie.h | 8 +++-
drivers/misc/xlink-pcie/local_host/Makefile| 2 +-
drivers/misc/xlink-pcie/local_host/core.c | 4 ++--
drivers/misc/xlink-pcie/local_host/epf.h | 4 ++--
7 files changed, 17 insertions(+), 25 deletions(-)
rename drivers/misc/xlink-pcie/{local_host => common}/core.h (96%)
rename drivers/misc/xlink-pcie/{local_host => common}/util.c (97%)
rename drivers/misc/xlink-pcie/{local_host => common}/util.h (91%)
rename drivers/misc/xlink-pcie/{local_host => common}/xpcie.h (92%)
diff --git a/drivers/misc/xlink-pcie/local_host/core.h
b/drivers/misc/xlink-pcie/common/core.h
similarity index 96%
rename from drivers/misc/xlink-pcie/local_host/core.h
rename to drivers/misc/xlink-pcie/common/core.h
index 84985ef41a64..656b5e2dbfae 100644
--- a/drivers/misc/xlink-pcie/local_host/core.h
+++ b/drivers/misc/xlink-pcie/common/core.h
@@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- *
+/*
* Intel Keem Bay XLink PCIe Driver
*
- * Copyright (C) 2020 Intel Corporation
- *
- /
+ * Copyright (C) 2021 Intel Corporation
+ */
#ifndef XPCIE_CORE_HEADER_
#define XPCIE_CORE_HEADER_
diff --git a/drivers/misc/xlink-pcie/local_host/util.c
b/drivers/misc/xlink-pcie/common/util.c
similarity index 97%
rename from drivers/misc/xlink-pcie/local_host/util.c
rename to drivers/misc/xlink-pcie/common/util.c
index ec808b0cd72b..d99125f61ba0 100644
--- a/drivers/misc/xlink-pcie/local_host/util.c
+++ b/drivers/misc/xlink-pcie/common/util.c
@@ -1,11 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-only
-/*
- *
+/*
* Intel Keem Bay XLink PCIe Driver
*
- * Copyright (C) 2020 Intel Corporation
- *
- /
+ * Copyright (C) 2021 Intel Corporation
+ */
#include "util.h"
diff --git a/drivers/misc/xlink-pcie/local_host/util.h
b/drivers/misc/xlink-pcie/common/util.h
similarity index 91%
rename from drivers/misc/xlink-pcie/local_host/util.h
rename to drivers/misc/xlink-pcie/common/util.h
index 908be897a61d..5295783b0437 100644
--- a/drivers/misc/xlink-pcie/local_host/util.h
+++ b/drivers/misc/xlink-pcie/common/util.h
@@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- *
+/*
* Intel Keem Bay XLink PCIe Driver
*
- * Copyright (C) 2020 Intel Corporation
- *
- /
+ * Copyright (C) 2021 Intel Corporation
+ */
#ifndef XPCIE_UTIL_HEADER_
#define XPCIE_UTIL_HEADER_
diff --git a/drivers/misc/xlink-pcie/local_host/xpcie.h
b/drivers/misc/xlink-pcie/common/xpcie.h
similarity index 92%
rename from drivers/misc/xlink-pcie/local_host/xpcie.h
rename to drivers/misc/xlink-pcie/common/xpcie.h
index 8a559617daba..48529eb49be0 100644
--- a/drivers/misc/xlink-pcie/local_host/xpcie.h
+++ b/drivers/misc/xlink-pcie/common/xpcie.h
@@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- *
+/*
* Intel Keem Bay XLink PCIe Driver
*
- * Copyright (C) 2020 Intel Corporation
- *
- /
+ * Copyright (C) 2021 Intel Corporation
+ */
#ifndef XPCIE_HEADER_
#define XPCIE_HEADER_
diff --git a/drivers/misc/xlink-pcie/local_host/Makefile
b/drivers/misc/xlink-pcie/local_host/Makefile
index 28761751d43b..65df94c7e860 100644
--- a/drivers/misc/xlink-pcie/local_host/Makefile
+++ b/drivers/misc/xlink-pcie/local_host/Makefile
@@ -2,4 +2,4 @@ obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o
mxlk_ep-objs := epf.o
mxlk_ep-objs += dma.o
mxlk_ep-objs += core.o
-mxlk_ep-objs += util.o
+mxlk_ep-objs += ../common/util.o
diff --git a/drivers/misc/xlink-pcie/local_host/core.c
b/drivers/misc/xlink-pcie/local_host/core.c
index c67ce2c3067d..2c4e29bce7f7 100644
--- a/drivers/misc/xlink-pcie/local_host/core.c
+++ b/drivers/misc/xlink-pcie/local_host/core.c
@@ -8,8 +8,8 @@
#include
#include "epf.h"
-#include "core.h"
-#include "util.h"
+#include "../common/core.h"
+#include "../common/util.h"
static struct xpcie *global_xpcie;
diff --git a/drivers/misc/xlink-pcie/local_host/epf.h
b/drivers/misc/xlink-pcie/local_host/e
[PATCH v4 07/34] keembay-vpu-ipc: Add Keem Bay VPU IPC module
From: Paul Murphy Intel Keem Bay SoC contains a Vision Processing Unit (VPU) to enable machine vision and other applications. Enable Linux to control the VPU processor and provides an interface to the Keem Bay IPC for communicating with the VPU firmware. Specifically the driver provides the following functionality to other kernel components: - Starting (including loading the VPU firmware) / Stopping / Rebooting the VPU. - Getting notifications of VPU events (e.g., WDT events). - Communicating with the VPU via the Keem Bay IPC mechanism. In addition to the above, the driver also exposes SoC information (like stepping, device ID, etc.) to user-space via sysfs. Specifically, the following sysfs files are provided: - /sys/firmware/keembay-vpu-ipc/device_id - /sys/firmware/keembay-vpu-ipc/feature_exclusion - /sys/firmware/keembay-vpu-ipc/hardware_id - /sys/firmware/keembay-vpu-ipc/sku - /sys/firmware/keembay-vpu-ipc/stepping Co-developed-by: Daniele Alessandrelli Signed-off-by: Daniele Alessandrelli Signed-off-by: Mark Gross Signed-off-by: Paul Murphy --- MAINTAINERS |9 + drivers/soc/intel/Kconfig | 15 + drivers/soc/intel/Makefile|3 +- drivers/soc/intel/keembay-vpu-ipc.c | 2026 + include/linux/soc/intel/keembay-vpu-ipc.h | 62 + 5 files changed, 2114 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/intel/keembay-vpu-ipc.c create mode 100644 include/linux/soc/intel/keembay-vpu-ipc.h diff --git a/MAINTAINERS b/MAINTAINERS index 684e64e958a4..6742a1827cd9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9068,6 +9068,15 @@ F: Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml F: drivers/soc/intel/keembay-ipc.c F: include/linux/soc/intel/keembay-ipc.h +INTEL KEEM BAY VPU IPC DRIVER +M: Paul J Murphy +M: Daniele Alessandrelli +M: Mark Gross +S: Supported +F: Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml +F: drivers/soc/intel/keembay-vpu-ipc.c +F: include/linux/soc/intel/keembay-vpu-ipc.h + INTEL MANAGEMENT ENGINE (mei) M: Tomas Winkler L: linux-kernel@vger.kernel.org diff --git a/drivers/soc/intel/Kconfig b/drivers/soc/intel/Kconfig index a575e31e47b4..ebd23ea57d04 100644 --- a/drivers/soc/intel/Kconfig +++ b/drivers/soc/intel/Kconfig @@ -15,4 +15,19 @@ config KEEMBAY_IPC Select this if you are compiling the Kernel for an Intel SoC that includes the Intel Vision Processing Unit (VPU) such as Keem Bay. + +config KEEMBAY_VPU_IPC + tristate "Intel Keem Bay VPU IPC Driver" + depends on KEEMBAY_IPC + depends on HAVE_ARM_SMCCC + help + This option enables support for loading and communicating with + the firmware on the Vision Processing Unit (VPU) of the Keem Bay + SoC. The driver depends on the Keem Bay IPC driver to do + communication, and it depends on secure world monitor software to + do the control of the VPU state. + + Select this if you are compiling the Kernel for an Intel SoC that + includes the Intel Vision Processing Unit (VPU) such as Keem Bay. + endmenu diff --git a/drivers/soc/intel/Makefile b/drivers/soc/intel/Makefile index ecf0246e7822..363a81848843 100644 --- a/drivers/soc/intel/Makefile +++ b/drivers/soc/intel/Makefile @@ -1,4 +1,5 @@ # # Makefile for Keem Bay IPC Linux driver # -obj-$(CONFIG_KEEMBAY_IPC) += keembay-ipc.o +obj-$(CONFIG_KEEMBAY_IPC) += keembay-ipc.o +obj-$(CONFIG_KEEMBAY_VPU_IPC) += keembay-vpu-ipc.o diff --git a/drivers/soc/intel/keembay-vpu-ipc.c b/drivers/soc/intel/keembay-vpu-ipc.c new file mode 100644 index ..8f3d6a466629 --- /dev/null +++ b/drivers/soc/intel/keembay-vpu-ipc.c @@ -0,0 +1,2026 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Keem Bay VPU IPC Driver. + * + * Copyright (c) 2018-2020 Intel Corporation. + * + * The purpose of this driver is to facilitate booting, control and + * communication with the VPU IP on the Keem Bay SoC. + * + * Specifically the driver provides the following functionality to other kernel + * components: + * - Loading the VPU firmware into DDR for the VPU to execute. + * - Starting / Stopping / Rebooting the VPU. + * - Getting notifications of VPU events (e.g., WDT events). + * - Communicating with the VPU using the Keem Bay IPC mechanism. + * + * In addition to the above, the driver also exposes SoC information (like + * stepping, device ID, etc.) to user-space via sysfs. + * + * + * VPU Firmware loading + * + * + * The VPU Firmware consists of both the RTOS and the application code meant to + * be run by the VPU. + * + * The VPU Firmware is loaded into DDR using the Linux Firmware API. The + * firmware is loaded into a specific reserved memory region in DDR and + * executed by the VPU directly from there. + * + * The VPU Firmware binary is expected to have the followin
[PATCH v4 14/34] misc: xlink-pcie: rh: Add core communication logic
From: Srikanth Thokala
Add logic to establish communication with the local host which is through
ring buffer management and MSI/Doorbell interrupts
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/common/core.h| 11 +-
drivers/misc/xlink-pcie/remote_host/Makefile | 2 +
drivers/misc/xlink-pcie/remote_host/core.c | 621 +++
drivers/misc/xlink-pcie/remote_host/pci.c| 48 +-
4 files changed, 670 insertions(+), 12 deletions(-)
create mode 100644 drivers/misc/xlink-pcie/remote_host/core.c
diff --git a/drivers/misc/xlink-pcie/common/core.h
b/drivers/misc/xlink-pcie/common/core.h
index 656b5e2dbfae..f43c175b7a48 100644
--- a/drivers/misc/xlink-pcie/common/core.h
+++ b/drivers/misc/xlink-pcie/common/core.h
@@ -8,15 +8,11 @@
#ifndef XPCIE_CORE_HEADER_
#define XPCIE_CORE_HEADER_
-#include
-#include
-#include
-#include
-#include
-#include
#include
-#include
+#include
+#include
#include
+#include
#include
@@ -62,6 +58,7 @@ struct xpcie_buf_desc {
struct xpcie_stream {
size_t frag;
struct xpcie_pipe pipe;
+ struct xpcie_buf_desc **ddr;
};
struct xpcie_list {
diff --git a/drivers/misc/xlink-pcie/remote_host/Makefile
b/drivers/misc/xlink-pcie/remote_host/Makefile
index 96374a43023e..e8074dbb1161 100644
--- a/drivers/misc/xlink-pcie/remote_host/Makefile
+++ b/drivers/misc/xlink-pcie/remote_host/Makefile
@@ -1,3 +1,5 @@
obj-$(CONFIG_XLINK_PCIE_RH_DRIVER) += mxlk.o
mxlk-objs := main.o
mxlk-objs += pci.o
+mxlk-objs += core.o
+mxlk-objs += ../common/util.o
diff --git a/drivers/misc/xlink-pcie/remote_host/core.c
b/drivers/misc/xlink-pcie/remote_host/core.c
new file mode 100644
index ..3be0492aa57c
--- /dev/null
+++ b/drivers/misc/xlink-pcie/remote_host/core.c
@@ -0,0 +1,621 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include "pci.h"
+
+#include "../common/core.h"
+#include "../common/util.h"
+
+static int intel_xpcie_map_dma(struct xpcie *xpcie, struct xpcie_buf_desc *bd,
+ int direction)
+{
+ struct xpcie_dev *xdev = container_of(xpcie, struct xpcie_dev, xpcie);
+ struct device *dev = &xdev->pci->dev;
+
+ bd->phys = dma_map_single(dev, bd->data, bd->length, direction);
+
+ return dma_mapping_error(dev, bd->phys);
+}
+
+static void intel_xpcie_unmap_dma(struct xpcie *xpcie,
+ struct xpcie_buf_desc *bd,
+ int direction)
+{
+ struct xpcie_dev *xdev = container_of(xpcie, struct xpcie_dev, xpcie);
+ struct device *dev = &xdev->pci->dev;
+
+ dma_unmap_single(dev, bd->phys, bd->length, direction);
+}
+
+static void intel_xpcie_txrx_cleanup(struct xpcie *xpcie)
+{
+ struct xpcie_interface *inf = &xpcie->interfaces[0];
+ struct xpcie_stream *tx = &xpcie->tx;
+ struct xpcie_stream *rx = &xpcie->rx;
+ struct xpcie_buf_desc *bd;
+ int index;
+
+ xpcie->stop_flag = true;
+ xpcie->no_tx_buffer = false;
+ inf->data_avail = true;
+ wake_up_interruptible(&xpcie->tx_waitq);
+ wake_up_interruptible(&inf->rx_waitq);
+ mutex_lock(&xpcie->wlock);
+ mutex_lock(&inf->rlock);
+
+ if (tx->ddr) {
+ for (index = 0; index < tx->pipe.ndesc; index++) {
+ struct xpcie_transfer_desc *td = tx->pipe.tdr + index;
+
+ bd = tx->ddr[index];
+ if (bd) {
+ intel_xpcie_unmap_dma(xpcie, bd, DMA_TO_DEVICE);
+ intel_xpcie_free_tx_bd(xpcie, bd);
+ intel_xpcie_set_td_address(td, 0);
+ intel_xpcie_set_td_length(td, 0);
+ }
+ }
+ kfree(tx->ddr);
+ }
+
+ if (rx->ddr) {
+ for (index = 0; index < rx->pipe.ndesc; index++) {
+ struct xpcie_transfer_desc *td = rx->pipe.tdr + index;
+
+ bd = rx->ddr[index];
+ if (bd) {
+ intel_xpcie_unmap_dma(xpcie,
+ bd, DMA_FROM_DEVICE);
+ intel_xpcie_free_rx_bd(xpcie, bd);
+ intel_xpcie_set_td_address(td, 0);
+ intel_xpcie_set_td_length(td, 0);
+ }
+ }
+ kfree(rx->ddr);
+ }
+
+ intel_xpcie_list_cleanup(&xpcie->tx_pool);
+ intel_xpcie_list_cleanup(&xpcie->rx_pool);
+
+ mutex_unlock(&inf->rlock);
+ mutex_unlock(&xpcie->wlock);
+}
+
+static int intel_xpcie_txrx_init(struct xpcie *xpcie,
+struct xpcie_cap_txrx *cap)
+{
[PATCH v3 24/34] dt-bindings: misc: Add Keem Bay vpumgr
From: "Li, Tingqian"
Add DT binding schema for VPU on Keem Bay ASoC platform
Signed-off-by: Li, Tingqian
---
.../bindings/misc/intel,keembay-vpu-mgr.yaml | 48 +++
1 file changed, 48 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/intel,keembay-vpu-mgr.yaml
diff --git a/Documentation/devicetree/bindings/misc/intel,keembay-vpu-mgr.yaml
b/Documentation/devicetree/bindings/misc/intel,keembay-vpu-mgr.yaml
new file mode 100644
index ..7fad14274ee2
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,keembay-vpu-mgr.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright (C) 2020 Intel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/intel,keembay-vpu-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel VPU manager bindings
+
+maintainers:
+ - Li, Tingqian
+ - Zhou, Luwei
+
+description: |
+ The Intel VPU manager provides shared memory and process
+ depedent context management for Intel VPU hardware IP.
+
+properties:
+ compatible:
+items:
+ - enum:
+- intel,keembay-vpu-mgr
+- intel,keembay-vpusmm
+
+ memory-region:
+description:
+ phandle to a node describing reserved memory (System RAM memory)
+ used by VPU (see bindings/reserved-memory/reserved-memory.txt)
+maxItems: 1
+
+ intel,keembay-vpu-ipc-id:
+$ref: /schemas/types.yaml#/definitions/uint32
+description:
+ the index of the VPU slice to be managed. Default is 0.
+
+required:
+ - compatible
+ - memory-region
+
+additionalProperties: false
+
+examples:
+ - |
+vpumgr0 {
+compatible = "intel,keembay-vpu-mgr";
+memory-region = <&vpu_reserved>;
+intel,keembay-vpu-ipc-id = <0x0>;
+};
--
2.17.1
[PATCH v3 33/34] misc: Hddl device management for local host
From: "C, Udhayakumar"
Add local host hddl device management for Intel Edge.AI Computer Vision
platforms.
About Intel Edge.AI Computer Vision platforms:
-
The Intel Edge.AI Computer Vision platforms are vision processing systems
targeting machine vision applications for connected devices.
They are based on ARM A53 CPU running Linux and acts as a PCIe
endpoint device.
High-level architecture:
Remote Host IA CPU Local Host ARM CPU
---
| * Send time as xlink packet | |* Sync time with IA host |
| * receive sensor details| |* Prepare and share sensor|
| and register as i2c or| | details to IA host as |
| xlink smbus slaves| | xlink packets |
---
| hddl server | <=> | hddl client |
--- xlink
hddl device module:
---
The HDDL client driver acts as an software RTC to sync with network
time. It abstracts xlink protocol to communicate with remote host.
This driver exports the details about sensors available in the
platform to remote host as xlink packets.
This driver also handles device connect/disconnect events and
identifies board id and soc id using gpio's, based on platform
configuration.
- Local Host driver
* Intended for ARM CPU
* It is based on xlink Framework
* Driver path:
{tree}/drivers/misc/hddl_device/hddl_device_client.c
Local arm host and Remote IA host drivers communicates using
XLINK protocol.
Signed-off-by: C, Udhayakumar
---
.../misc-devices/hddl_device_client.rst | 212 +
Documentation/misc-devices/index.rst | 1 +
Documentation/vpu/index.rst | 1 +
MAINTAINERS | 1 +
drivers/misc/Kconfig | 1 +
drivers/misc/Makefile | 1 +
drivers/misc/hddl_device/Kconfig | 14 +
drivers/misc/hddl_device/Makefile | 5 +
drivers/misc/hddl_device/hddl_device.c| 565 +
drivers/misc/hddl_device/hddl_device_lh.c | 764 ++
drivers/misc/hddl_device/hddl_device_util.h | 52 ++
11 files changed, 1617 insertions(+)
create mode 100644 Documentation/misc-devices/hddl_device_client.rst
create mode 100644 drivers/misc/hddl_device/Kconfig
create mode 100644 drivers/misc/hddl_device/Makefile
create mode 100644 drivers/misc/hddl_device/hddl_device.c
create mode 100644 drivers/misc/hddl_device/hddl_device_lh.c
create mode 100644 drivers/misc/hddl_device/hddl_device_util.h
diff --git a/Documentation/misc-devices/hddl_device_client.rst
b/Documentation/misc-devices/hddl_device_client.rst
new file mode 100644
index ..413643b6b500
--- /dev/null
+++ b/Documentation/misc-devices/hddl_device_client.rst
@@ -0,0 +1,212 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=
+Kernel driver: hddl_device_client
+=
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+
+Authors:
+- Thalaiappan, Rathina
+- Udhayakumar C
+
+
+Overview
+
+
+This driver supports hddl device management for Intel Edge.AI Computer Vision
+platforms.
+
+This driver supports the following features:
+
+ - Exports deatils of temperature sensor, current sensor and fan controller
+present in Intel Edge.AI Computer Vision platforms to IA host.
+ - Enable Time sync of Intel Edge.AI Computer Vision platform with IA host.
+ - Handles device connect and disconnect events.
+ - Receives slave address from the IA host for memory mapped thermal sensors
+present in SoC (Documentation/hwmon/intel_tsens_sensors.rst).
+ - Registers i2c slave device for slaves present in Intel Edge.AI Computer
+Vision platform
+
+Keem Bay platform has
+Onchip sensors:
+
+ - Media Subsystem (mss) temperature sensor
+ - NN subsystem (nce) temperature sensor
+ - Compute subsystem (cse) temperature sensor
+ - SOC(Maximum of mss, nce and cse).
+
+Onboard sensors:
+
+ - two lm75 temperature sensors
+ - emc2103 fan controller
+ - ina3221 current sensor
+
+High-level architecture
+===
+::
+
+Remote Host IA CPU Local Host ARM CPU
+---
+| * Send time as xlink packet | |* Sync time with IA host |
+| * receive sensor details| |* Prepare and share sensor|
+| and register as i2c or| | details to IA host as |
+| xlink smbus slaves| | xlink packets |
+---
+| hddl server
[PATCH v4 21/34] xlink-core: Enable xlink protocol over pcie
From: Seamus Kelly
Enable host system access to the VPU over the xlink protocol over PCIe by
enabling channel multiplexing and dispatching. This allows for remote host
communication channels across pcie links.
add dispatcher
update multiplexer to utilise dispatcher
xlink-core: Patch set 2
Add xlink-dispatcher
creates tx and rx threads
enables queueing of messages for transmission and on reception
Update multiplexer to utilise dispatcher:
handle multiplexing channels over single interface link e.g.
PCIe
process messages received by dispatcher
pass messages created by API calls to dispatcher for
transmission
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Seamus Kelly
---
drivers/misc/xlink-core/Makefile| 2 +-
drivers/misc/xlink-core/xlink-core.c| 35 +-
drivers/misc/xlink-core/xlink-dispatcher.c | 441 +
drivers/misc/xlink-core/xlink-dispatcher.h | 26 +
drivers/misc/xlink-core/xlink-multiplexer.c | 498 +++-
5 files changed, 999 insertions(+), 3 deletions(-)
create mode 100644 drivers/misc/xlink-core/xlink-dispatcher.c
create mode 100644 drivers/misc/xlink-core/xlink-dispatcher.h
diff --git a/drivers/misc/xlink-core/Makefile b/drivers/misc/xlink-core/Makefile
index e82b7c72b6b9..ee81f9d05f2b 100644
--- a/drivers/misc/xlink-core/Makefile
+++ b/drivers/misc/xlink-core/Makefile
@@ -2,4 +2,4 @@
# Makefile for Keem Bay xlink Linux driver
#
obj-$(CONFIG_XLINK_CORE) += xlink.o
-xlink-objs += xlink-core.o xlink-multiplexer.o xlink-platform.o xlink-ioctl.o
+xlink-objs += xlink-core.o xlink-multiplexer.o xlink-dispatcher.o
xlink-platform.o xlink-ioctl.o
diff --git a/drivers/misc/xlink-core/xlink-core.c
b/drivers/misc/xlink-core/xlink-core.c
index dd8db834c184..bdbf8c6a99ca 100644
--- a/drivers/misc/xlink-core/xlink-core.c
+++ b/drivers/misc/xlink-core/xlink-core.c
@@ -21,6 +21,7 @@
#include "xlink-core.h"
#include "xlink-defs.h"
+#include "xlink-dispatcher.h"
#include "xlink-ioctl.h"
#include "xlink-multiplexer.h"
#include "xlink-platform.h"
@@ -151,6 +152,12 @@ static int kmb_xlink_probe(struct platform_device *pdev)
goto r_multiplexer;
}
+ // initialize dispatcher
+ rc = xlink_dispatcher_init(xlink_dev->pdev);
+ if (rc != X_LINK_SUCCESS) {
+ pr_err("Dispatcher initialization failed\n");
+ goto r_dispatcher;
+ }
// initialize xlink data structure
xlink_dev->nmb_connected_links = 0;
mutex_init(&xlink_dev->lock);
@@ -168,7 +175,7 @@ static int kmb_xlink_probe(struct platform_device *pdev)
/*Allocating Major number*/
if ((alloc_chrdev_region(&xdev, 0, 1, "xlinkdev")) < 0) {
dev_info(&pdev->dev, "Cannot allocate major number\n");
- goto r_multiplexer;
+ goto r_dispatcher;
}
dev_info(&pdev->dev, "Major = %d Minor = %d\n", MAJOR(xdev),
MINOR(xdev));
@@ -205,6 +212,8 @@ static int kmb_xlink_probe(struct platform_device *pdev)
class_destroy(dev_class);
r_class:
unregister_chrdev_region(xdev, 1);
+r_dispatcher:
+ xlink_dispatcher_destroy();
r_multiplexer:
xlink_multiplexer_destroy();
return -1;
@@ -220,6 +229,10 @@ static int kmb_xlink_remove(struct platform_device *pdev)
rc = xlink_multiplexer_destroy();
if (rc != X_LINK_SUCCESS)
pr_err("Multiplexer destroy failed\n");
+ // stop dispatchers and destroy
+ rc = xlink_dispatcher_destroy();
+ if (rc != X_LINK_SUCCESS)
+ pr_err("Dispatcher destroy failed\n");
mutex_unlock(&xlink->lock);
mutex_destroy(&xlink->lock);
@@ -314,6 +327,14 @@ enum xlink_error xlink_connect(struct xlink_handle *handle)
link->handle = *handle;
xlink->nmb_connected_links++;
kref_init(&link->refcount);
+ if (interface != IPC_INTERFACE) {
+ // start dispatcher
+ rc = xlink_dispatcher_start(link->id, &link->handle);
+ if (rc) {
+ pr_err("dispatcher start failed\n");
+ goto r_cleanup;
+ }
+ }
// initialize multiplexer connection
rc = xlink_multiplexer_connect(link->id);
if (rc) {
@@ -649,6 +670,7 @@ EXPORT_SYMBOL_GPL(xlink_release_data);
enum xlink_error xlink_disconnect(struct xlink_handle *handle)
{
struct xlink_link *link;
+ int interface = NULL_INTERFACE;
enum xlink_error rc = X_LINK_ERROR;
if (!xlink || !handle)
@@ -661,6 +683,17 @@ enum xlink_error xlink_disconnect(struct xlink_handle
*handle)
// decrement refcount, if count i
[PATCH v3 09/34] misc: xlink-pcie: lh: Add PCIe EPF driver for Local Host
From: Srikanth Thokala
Add PCIe EPF driver for local host (lh) to configure BAR's and other
HW resources. Underlying PCIe HW controller is a Synopsys DWC PCIe core.
Cc: Derek Kiernan
Cc: Dragan Cvetic
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
MAINTAINERS | 6 +
drivers/misc/Kconfig| 1 +
drivers/misc/Makefile | 1 +
drivers/misc/xlink-pcie/Kconfig | 9 +
drivers/misc/xlink-pcie/Makefile| 1 +
drivers/misc/xlink-pcie/local_host/Makefile | 2 +
drivers/misc/xlink-pcie/local_host/epf.c| 373
drivers/misc/xlink-pcie/local_host/epf.h| 37 ++
drivers/misc/xlink-pcie/local_host/xpcie.h | 38 ++
9 files changed, 468 insertions(+)
create mode 100644 drivers/misc/xlink-pcie/Kconfig
create mode 100644 drivers/misc/xlink-pcie/Makefile
create mode 100644 drivers/misc/xlink-pcie/local_host/Makefile
create mode 100644 drivers/misc/xlink-pcie/local_host/epf.c
create mode 100644 drivers/misc/xlink-pcie/local_host/epf.h
create mode 100644 drivers/misc/xlink-pcie/local_host/xpcie.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 6742a1827cd9..3ca6c8c6341b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1961,6 +1961,12 @@ F:
Documentation/devicetree/bindings/arm/intel,keembay.yaml
F: arch/arm64/boot/dts/intel/keembay-evm.dts
F: arch/arm64/boot/dts/intel/keembay-soc.dtsi
+ARM KEEM BAY XLINK PCIE SUPPORT
+M: Srikanth Thokala
+M: Mark Gross
+S: Supported
+F: drivers/misc/xlink-pcie/
+
ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
M: Jonathan Cameron
L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index fafa8b0d8099..dfb98e444c6e 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -481,4 +481,5 @@ source "drivers/misc/ocxl/Kconfig"
source "drivers/misc/cardreader/Kconfig"
source "drivers/misc/habanalabs/Kconfig"
source "drivers/misc/uacce/Kconfig"
+source "drivers/misc/xlink-pcie/Kconfig"
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index d23231e73330..d17621fc43d5 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/
obj-$(CONFIG_UACCE)+= uacce/
obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
+obj-y += xlink-pcie/
diff --git a/drivers/misc/xlink-pcie/Kconfig b/drivers/misc/xlink-pcie/Kconfig
new file mode 100644
index ..46aa401d79b7
--- /dev/null
+++ b/drivers/misc/xlink-pcie/Kconfig
@@ -0,0 +1,9 @@
+config XLINK_PCIE_LH_DRIVER
+ tristate "XLink PCIe Local Host driver"
+ depends on PCI_ENDPOINT && ARCH_KEEMBAY
+ help
+ This option enables XLink PCIe Local Host driver.
+
+ Choose M here to compile this driver as a module, name is mxlk_ep.
+ This driver is used for XLink communication over PCIe and is to be
+ loaded on the Intel Keem Bay platform.
diff --git a/drivers/misc/xlink-pcie/Makefile b/drivers/misc/xlink-pcie/Makefile
new file mode 100644
index ..d693d382e9c6
--- /dev/null
+++ b/drivers/misc/xlink-pcie/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += local_host/
diff --git a/drivers/misc/xlink-pcie/local_host/Makefile
b/drivers/misc/xlink-pcie/local_host/Makefile
new file mode 100644
index ..514d3f0c91bc
--- /dev/null
+++ b/drivers/misc/xlink-pcie/local_host/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o
+mxlk_ep-objs := epf.o
diff --git a/drivers/misc/xlink-pcie/local_host/epf.c
b/drivers/misc/xlink-pcie/local_host/epf.c
new file mode 100644
index ..0234756e89ae
--- /dev/null
+++ b/drivers/misc/xlink-pcie/local_host/epf.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include
+#include
+
+#include "epf.h"
+
+#define BAR2_MIN_SIZE SZ_16K
+#define BAR4_MIN_SIZE SZ_16K
+
+#define PCIE_REGS_PCIE_INTR_ENABLE 0x18
+#define PCIE_REGS_PCIE_INTR_FLAGS 0x1C
+#define LBC_CII_EVENT_FLAG BIT(18)
+#define PCIE_REGS_PCIE_ERR_INTR_FLAGS 0x24
+#define LINK_REQ_RST_FLG BIT(15)
+
+static struct pci_epf_header xpcie_header = {
+ .vendorid = PCI_VENDOR_ID_INTEL,
+ .deviceid = PCI_DEVICE_ID_INTEL_KEEMBAY,
+ .baseclass_code = PCI_BASE_CLASS_MULTIMEDIA,
+ .subclass_code = 0x0,
+ .subsys_vendor_id = 0x0,
+ .subsys_id = 0x0,
+};
+
+static const struct pci_epf_device_id xpcie_epf_ids[] = {
+ {
+ .name = "mxlk_pcie_epf",
+ },
+ {},
+};
+
+static irqreturn_t intel_xpcie_err_interrupt(int irq, void *args)
+{
+
[PATCH v3 14/34] misc: xlink-pcie: rh: Add core communication logic
From: Srikanth Thokala
Add logic to establish communication with the local host which is through
ring buffer management and MSI/Doorbell interrupts
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/common/core.h| 11 +-
drivers/misc/xlink-pcie/remote_host/Makefile | 2 +
drivers/misc/xlink-pcie/remote_host/core.c | 621 +++
drivers/misc/xlink-pcie/remote_host/pci.c| 48 +-
4 files changed, 670 insertions(+), 12 deletions(-)
create mode 100644 drivers/misc/xlink-pcie/remote_host/core.c
diff --git a/drivers/misc/xlink-pcie/common/core.h
b/drivers/misc/xlink-pcie/common/core.h
index 656b5e2dbfae..f43c175b7a48 100644
--- a/drivers/misc/xlink-pcie/common/core.h
+++ b/drivers/misc/xlink-pcie/common/core.h
@@ -8,15 +8,11 @@
#ifndef XPCIE_CORE_HEADER_
#define XPCIE_CORE_HEADER_
-#include
-#include
-#include
-#include
-#include
-#include
#include
-#include
+#include
+#include
#include
+#include
#include
@@ -62,6 +58,7 @@ struct xpcie_buf_desc {
struct xpcie_stream {
size_t frag;
struct xpcie_pipe pipe;
+ struct xpcie_buf_desc **ddr;
};
struct xpcie_list {
diff --git a/drivers/misc/xlink-pcie/remote_host/Makefile
b/drivers/misc/xlink-pcie/remote_host/Makefile
index 96374a43023e..e8074dbb1161 100644
--- a/drivers/misc/xlink-pcie/remote_host/Makefile
+++ b/drivers/misc/xlink-pcie/remote_host/Makefile
@@ -1,3 +1,5 @@
obj-$(CONFIG_XLINK_PCIE_RH_DRIVER) += mxlk.o
mxlk-objs := main.o
mxlk-objs += pci.o
+mxlk-objs += core.o
+mxlk-objs += ../common/util.o
diff --git a/drivers/misc/xlink-pcie/remote_host/core.c
b/drivers/misc/xlink-pcie/remote_host/core.c
new file mode 100644
index ..3be0492aa57c
--- /dev/null
+++ b/drivers/misc/xlink-pcie/remote_host/core.c
@@ -0,0 +1,621 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include "pci.h"
+
+#include "../common/core.h"
+#include "../common/util.h"
+
+static int intel_xpcie_map_dma(struct xpcie *xpcie, struct xpcie_buf_desc *bd,
+ int direction)
+{
+ struct xpcie_dev *xdev = container_of(xpcie, struct xpcie_dev, xpcie);
+ struct device *dev = &xdev->pci->dev;
+
+ bd->phys = dma_map_single(dev, bd->data, bd->length, direction);
+
+ return dma_mapping_error(dev, bd->phys);
+}
+
+static void intel_xpcie_unmap_dma(struct xpcie *xpcie,
+ struct xpcie_buf_desc *bd,
+ int direction)
+{
+ struct xpcie_dev *xdev = container_of(xpcie, struct xpcie_dev, xpcie);
+ struct device *dev = &xdev->pci->dev;
+
+ dma_unmap_single(dev, bd->phys, bd->length, direction);
+}
+
+static void intel_xpcie_txrx_cleanup(struct xpcie *xpcie)
+{
+ struct xpcie_interface *inf = &xpcie->interfaces[0];
+ struct xpcie_stream *tx = &xpcie->tx;
+ struct xpcie_stream *rx = &xpcie->rx;
+ struct xpcie_buf_desc *bd;
+ int index;
+
+ xpcie->stop_flag = true;
+ xpcie->no_tx_buffer = false;
+ inf->data_avail = true;
+ wake_up_interruptible(&xpcie->tx_waitq);
+ wake_up_interruptible(&inf->rx_waitq);
+ mutex_lock(&xpcie->wlock);
+ mutex_lock(&inf->rlock);
+
+ if (tx->ddr) {
+ for (index = 0; index < tx->pipe.ndesc; index++) {
+ struct xpcie_transfer_desc *td = tx->pipe.tdr + index;
+
+ bd = tx->ddr[index];
+ if (bd) {
+ intel_xpcie_unmap_dma(xpcie, bd, DMA_TO_DEVICE);
+ intel_xpcie_free_tx_bd(xpcie, bd);
+ intel_xpcie_set_td_address(td, 0);
+ intel_xpcie_set_td_length(td, 0);
+ }
+ }
+ kfree(tx->ddr);
+ }
+
+ if (rx->ddr) {
+ for (index = 0; index < rx->pipe.ndesc; index++) {
+ struct xpcie_transfer_desc *td = rx->pipe.tdr + index;
+
+ bd = rx->ddr[index];
+ if (bd) {
+ intel_xpcie_unmap_dma(xpcie,
+ bd, DMA_FROM_DEVICE);
+ intel_xpcie_free_rx_bd(xpcie, bd);
+ intel_xpcie_set_td_address(td, 0);
+ intel_xpcie_set_td_length(td, 0);
+ }
+ }
+ kfree(rx->ddr);
+ }
+
+ intel_xpcie_list_cleanup(&xpcie->tx_pool);
+ intel_xpcie_list_cleanup(&xpcie->rx_pool);
+
+ mutex_unlock(&inf->rlock);
+ mutex_unlock(&xpcie->wlock);
+}
+
+static int intel_xpcie_txrx_init(struct xpcie *xpcie,
+struct xpcie_cap_txrx *cap)
+{
+ struct xpcie_stream
[PATCH v4 10/34] misc: xlink-pcie: lh: Add PCIe EP DMA functionality
From: Srikanth Thokala Add Synopsys PCIe DWC core embedded-DMA functionality for local host Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Reviewed-by: Mark Gross Signed-off-by: Mark Gross Signed-off-by: Srikanth Thokala --- drivers/misc/xlink-pcie/local_host/Makefile | 1 + drivers/misc/xlink-pcie/local_host/dma.c| 575 drivers/misc/xlink-pcie/local_host/epf.c| 15 +- drivers/misc/xlink-pcie/local_host/epf.h| 41 ++ 4 files changed, 629 insertions(+), 3 deletions(-) create mode 100644 drivers/misc/xlink-pcie/local_host/dma.c diff --git a/drivers/misc/xlink-pcie/local_host/Makefile b/drivers/misc/xlink-pcie/local_host/Makefile index 514d3f0c91bc..54fc118e2dd1 100644 --- a/drivers/misc/xlink-pcie/local_host/Makefile +++ b/drivers/misc/xlink-pcie/local_host/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o mxlk_ep-objs := epf.o +mxlk_ep-objs += dma.o diff --git a/drivers/misc/xlink-pcie/local_host/dma.c b/drivers/misc/xlink-pcie/local_host/dma.c new file mode 100644 index ..42978fb0db49 --- /dev/null +++ b/drivers/misc/xlink-pcie/local_host/dma.c @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Keem Bay XLink PCIe Driver + * + * Copyright (C) 2021 Intel Corporation + */ +#include +#include +#include + +#include "epf.h" + +#define DMA_DBI_OFFSET (0x38) + +/* PCIe DMA control 1 register definitions. */ +#define DMA_CH_CONTROL1_CB_SHIFT (0) +#define DMA_CH_CONTROL1_TCB_SHIFT (1) +#define DMA_CH_CONTROL1_LLP_SHIFT (2) +#define DMA_CH_CONTROL1_LIE_SHIFT (3) +#define DMA_CH_CONTROL1_CS_SHIFT (5) +#define DMA_CH_CONTROL1_CCS_SHIFT (8) +#define DMA_CH_CONTROL1_LLE_SHIFT (9) +#define DMA_CH_CONTROL1_CB_MASK(BIT(DMA_CH_CONTROL1_CB_SHIFT)) +#define DMA_CH_CONTROL1_TCB_MASK (BIT(DMA_CH_CONTROL1_TCB_SHIFT)) +#define DMA_CH_CONTROL1_LLP_MASK (BIT(DMA_CH_CONTROL1_LLP_SHIFT)) +#define DMA_CH_CONTROL1_LIE_MASK (BIT(DMA_CH_CONTROL1_LIE_SHIFT)) +#define DMA_CH_CONTROL1_CS_MASK(0x3 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CCS_MASK (BIT(DMA_CH_CONTROL1_CCS_SHIFT)) +#define DMA_CH_CONTROL1_LLE_MASK (BIT(DMA_CH_CONTROL1_LLE_SHIFT)) + +/* DMA control 1 register Channel Status */ +#define DMA_CH_CONTROL1_CS_RUNNING (0x1 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CS_HALTED (0x2 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CS_STOPPED (0x3 << DMA_CH_CONTROL1_CS_SHIFT) + +/* PCIe DMA Engine enable register definitions. */ +#define DMA_ENGINE_EN_SHIFT(0) +#define DMA_ENGINE_EN_MASK (BIT(DMA_ENGINE_EN_SHIFT)) + +/* PCIe DMA interrupt registers definitions. */ +#define DMA_ABORT_INTERRUPT_SHIFT (16) +#define DMA_ABORT_INTERRUPT_MASK (0xFF << DMA_ABORT_INTERRUPT_SHIFT) +#define DMA_ABORT_INTERRUPT_CH_MASK(_c) (BIT(_c) << DMA_ABORT_INTERRUPT_SHIFT) +#define DMA_DONE_INTERRUPT_MASK(0xFF) +#define DMA_DONE_INTERRUPT_CH_MASK(_c) (BIT(_c)) +#define DMA_ALL_INTERRUPT_MASK \ + (DMA_ABORT_INTERRUPT_MASK | DMA_DONE_INTERRUPT_MASK) + +#define DMA_LL_ERROR_SHIFT (16) +#define DMA_CPL_ABORT_SHIFT(8) +#define DMA_CPL_TIMEOUT_SHIFT (16) +#define DMA_DATA_POI_SHIFT (24) +#define DMA_AR_ERROR_CH_MASK(_c) (BIT(_c)) +#define DMA_LL_ERROR_CH_MASK(_c) (BIT(_c) << DMA_LL_ERROR_SHIFT) +#define DMA_UNREQ_ERROR_CH_MASK(_c)(BIT(_c)) +#define DMA_CPL_ABORT_ERROR_CH_MASK(_c)(BIT(_c) << DMA_CPL_ABORT_SHIFT) +#define DMA_CPL_TIMEOUT_ERROR_CH_MASK(_c) (BIT(_c) << DMA_CPL_TIMEOUT_SHIFT) +#define DMA_DATA_POI_ERROR_CH_MASK(_c) (BIT(_c) << DMA_DATA_POI_SHIFT) + +#define DMA_LLLAIE_SHIFT (16) +#define DMA_LLLAIE_MASK(0xF << DMA_LLLAIE_SHIFT) + +#define DMA_CHAN_WRITE_MAX_WEIGHT (0x7) +#define DMA_CHAN_READ_MAX_WEIGHT (0x3) +#define DMA_CHAN0_WEIGHT_OFFSET(0) +#define DMA_CHAN1_WEIGHT_OFFSET(5) +#define DMA_CHAN2_WEIGHT_OFFSET(10) +#define DMA_CHAN3_WEIGHT_OFFSET(15) +#define DMA_CHAN_WRITE_ALL_MAX_WEIGHT \ + ((DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN0_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN1_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN2_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN3_WEIGHT_OFFSET)) +#define DMA_CHAN_READ_ALL_MAX_WEIGHT \ + ((DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN0_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN1_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN2_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN3_WEIGHT_OFFSET)) + +#define PCIE_REGS_PCIE_APP_CNTRL 0x8 +#define APP_XFER_PENDING BIT(6) +#def
[PATCH v3 11/34] misc: xlink-pcie: lh: Add core communication logic
From: Srikanth Thokala
Add logic to establish communication with the remote host which is through
ring buffer management and MSI/Doorbell interrupts
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/local_host/Makefile | 2 +
drivers/misc/xlink-pcie/local_host/core.c | 806
drivers/misc/xlink-pcie/local_host/core.h | 247 ++
drivers/misc/xlink-pcie/local_host/epf.c| 116 ++-
drivers/misc/xlink-pcie/local_host/epf.h| 23 +
drivers/misc/xlink-pcie/local_host/util.c | 375 +
drivers/misc/xlink-pcie/local_host/util.h | 70 ++
drivers/misc/xlink-pcie/local_host/xpcie.h | 63 ++
include/linux/xlink_drv_inf.h | 58 ++
9 files changed, 1752 insertions(+), 8 deletions(-)
create mode 100644 drivers/misc/xlink-pcie/local_host/core.c
create mode 100644 drivers/misc/xlink-pcie/local_host/core.h
create mode 100644 drivers/misc/xlink-pcie/local_host/util.c
create mode 100644 drivers/misc/xlink-pcie/local_host/util.h
create mode 100644 include/linux/xlink_drv_inf.h
diff --git a/drivers/misc/xlink-pcie/local_host/Makefile
b/drivers/misc/xlink-pcie/local_host/Makefile
index 54fc118e2dd1..28761751d43b 100644
--- a/drivers/misc/xlink-pcie/local_host/Makefile
+++ b/drivers/misc/xlink-pcie/local_host/Makefile
@@ -1,3 +1,5 @@
obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o
mxlk_ep-objs := epf.o
mxlk_ep-objs += dma.o
+mxlk_ep-objs += core.o
+mxlk_ep-objs += util.o
diff --git a/drivers/misc/xlink-pcie/local_host/core.c
b/drivers/misc/xlink-pcie/local_host/core.c
new file mode 100644
index ..c67ce2c3067d
--- /dev/null
+++ b/drivers/misc/xlink-pcie/local_host/core.c
@@ -0,0 +1,806 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include
+
+#include "epf.h"
+#include "core.h"
+#include "util.h"
+
+static struct xpcie *global_xpcie;
+
+static struct xpcie *intel_xpcie_core_get_by_id(u32 sw_device_id)
+{
+ return (sw_device_id == xlink_sw_id) ? global_xpcie : NULL;
+}
+
+static int intel_xpcie_map_dma(struct xpcie *xpcie, struct xpcie_buf_desc *bd,
+ int direction)
+{
+ struct xpcie_epf *xpcie_epf = container_of(xpcie,
+ struct xpcie_epf, xpcie);
+ struct pci_epf *epf = xpcie_epf->epf;
+ struct device *dma_dev = epf->epc->dev.parent;
+
+ bd->phys = dma_map_single(dma_dev, bd->data, bd->length, direction);
+
+ return dma_mapping_error(dma_dev, bd->phys);
+}
+
+static void intel_xpcie_unmap_dma(struct xpcie *xpcie,
+ struct xpcie_buf_desc *bd, int direction)
+{
+ struct xpcie_epf *xpcie_epf = container_of(xpcie,
+ struct xpcie_epf, xpcie);
+ struct pci_epf *epf = xpcie_epf->epf;
+ struct device *dma_dev = epf->epc->dev.parent;
+
+ dma_unmap_single(dma_dev, bd->phys, bd->length, direction);
+}
+
+static void intel_xpcie_set_cap_txrx(struct xpcie *xpcie)
+{
+ size_t tx_len = sizeof(struct xpcie_transfer_desc) *
+ XPCIE_NUM_TX_DESCS;
+ size_t rx_len = sizeof(struct xpcie_transfer_desc) *
+ XPCIE_NUM_RX_DESCS;
+ size_t hdr_len = sizeof(struct xpcie_cap_txrx);
+ u32 start = sizeof(struct xpcie_mmio);
+ struct xpcie_cap_txrx *cap;
+ struct xpcie_cap_hdr *hdr;
+ u16 next;
+
+ next = (u16)(start + hdr_len + tx_len + rx_len);
+ intel_xpcie_iowrite32(start, xpcie->mmio + XPCIE_MMIO_CAP_OFF);
+ cap = (void *)xpcie->mmio + start;
+ memset(cap, 0, sizeof(struct xpcie_cap_txrx));
+ cap->hdr.id = XPCIE_CAP_TXRX;
+ cap->hdr.next = next;
+ cap->fragment_size = XPCIE_FRAGMENT_SIZE;
+ cap->tx.ring = start + hdr_len;
+ cap->tx.ndesc = XPCIE_NUM_TX_DESCS;
+ cap->rx.ring = start + hdr_len + tx_len;
+ cap->rx.ndesc = XPCIE_NUM_RX_DESCS;
+
+ hdr = (struct xpcie_cap_hdr *)((void *)xpcie->mmio + next);
+ hdr->id = XPCIE_CAP_NULL;
+}
+
+static void intel_xpcie_txrx_cleanup(struct xpcie *xpcie)
+{
+ struct xpcie_epf *xpcie_epf = container_of(xpcie,
+ struct xpcie_epf, xpcie);
+ struct device *dma_dev = xpcie_epf->epf->epc->dev.parent;
+ struct xpcie_interface *inf = &xpcie->interfaces[0];
+ struct xpcie_stream *tx = &xpcie->tx;
+ struct xpcie_stream *rx = &xpcie->rx;
+ struct xpcie_transfer_desc *td;
+ int index;
+
+ xpcie->stop_flag = true;
+ xpcie->no_tx_buffer = false;
+ inf->data_avail = true;
+ wake_up_interruptible(&xpcie->tx_waitq);
+ wake_up_interruptible(&inf->rx_waitq);
+ mutex_lock(&xpcie->wlock);
+ mutex_lock(&inf->rlock);
+
+ for (index = 0; index < rx->pipe.nde
[PATCH v3 00/34] Intel Vision Processing base enabling
From: Mark Gross The Intel Vision Processing Unit (VPU) is an IP block that is showing up for the first time as part of the Keem Bay SOC. Keem Bay is a quad core A53 Arm SOC. It is designed to be used as a stand alone SOC as well as in an PCIe Vision Processing accelerator add in card. This thrid version of this patch set includes updates to xling-pci some minor updates to a Kconfig help text and global use of EXPORT_SYMBOL_GPL based on review feedback. At the bottom of this coverletter is the delta between v2 and V3 for easy review of the modifications. Feels like things are converging. :) Thanks for looking at these and providing feedback. --mark C, Udhayakumar (8): dt-bindings: misc: intel_tsens: Add tsens thermal bindings documentation misc: Tsens ARM host thermal driver. misc: Intel tsens IA host driver. Intel tsens i2c slave driver. misc:intel_tsens: Intel Keem Bay tsens driver. dt-bindings: misc: hddl_dev: Add hddl device management documentation misc: Hddl device management for local host misc: HDDL device management for IA host Daniele Alessandrelli (4): dt-bindings: mailbox: Add Intel VPU IPC mailbox bindings mailbox: vpu-ipc-mailbox: Add support for Intel VPU IPC mailbox dt-bindings: Add bindings for Keem Bay IPC driver keembay-ipc: Add Keem Bay IPC module Li, Tingqian (2): dt-bindings: misc: Add Keem Bay vpumgr misc: Add Keem Bay VPU manager Paul Murphy (2): dt-bindings: Add bindings for Keem Bay VPU IPC driver keembay-vpu-ipc: Add Keem Bay VPU IPC module Ramya P Karanth (1): Intel Keem Bay XLink SMBus driver Seamus Kelly (7): xlink-ipc: Add xlink ipc device tree bindings xlink-ipc: Add xlink ipc driver xlink-core: Add xlink core device tree bindings xlink-core: Add xlink core driver xLink xlink-core: Enable xlink protocol over pcie xlink-core: Enable VPU IP management and runtime control xlink-core: add async channel and events Srikanth Thokala (9): misc: xlink-pcie: Add documentation for XLink PCIe driver misc: xlink-pcie: lh: Add PCIe EPF driver for Local Host misc: xlink-pcie: lh: Add PCIe EP DMA functionality misc: xlink-pcie: lh: Add core communication logic misc: xlink-pcie: lh: Prepare changes for adding remote host driver misc: xlink-pcie: rh: Add PCIe EP driver for Remote Host misc: xlink-pcie: rh: Add core communication logic misc: xlink-pcie: Add XLink API interface misc: xlink-pcie: Add asynchronous event notification support for XLink mark gross (1): Add Vision Processing Unit (VPU) documentation. .../mailbox/intel,vpu-ipc-mailbox.yaml| 69 + .../bindings/misc/intel,hddl-client.yaml | 114 + .../bindings/misc/intel,intel-tsens.yaml | 122 + .../bindings/misc/intel,keembay-vpu-mgr.yaml | 48 + .../misc/intel,keembay-xlink-ipc.yaml | 49 + .../bindings/misc/intel,keembay-xlink.yaml| 27 + .../bindings/soc/intel/intel,keembay-ipc.yaml | 45 + .../soc/intel/intel,keembay-vpu-ipc.yaml | 153 ++ Documentation/hwmon/index.rst |2 + Documentation/hwmon/intel_tsens_host.rst | 71 + Documentation/hwmon/intel_tsens_sensor.rst| 67 + Documentation/i2c/busses/index.rst|1 + .../i2c/busses/intel-xlink-smbus.rst | 71 + Documentation/index.rst |1 + .../misc-devices/hddl_device_client.rst | 212 ++ .../misc-devices/hddl_device_server.rst | 205 ++ Documentation/misc-devices/index.rst |2 + Documentation/vpu/index.rst | 20 + Documentation/vpu/vpu-stack-overview.rst | 270 +++ Documentation/vpu/xlink-core.rst | 81 + Documentation/vpu/xlink-ipc.rst | 51 + Documentation/vpu/xlink-pcie.rst | 90 + MAINTAINERS | 54 + drivers/mailbox/Kconfig | 11 + drivers/mailbox/Makefile |2 + drivers/mailbox/vpu-ipc-mailbox.c | 297 +++ drivers/misc/Kconfig |7 + drivers/misc/Makefile |7 + drivers/misc/hddl_device/Kconfig | 26 + drivers/misc/hddl_device/Makefile |7 + drivers/misc/hddl_device/hddl_device.c| 565 + drivers/misc/hddl_device/hddl_device_lh.c | 764 +++ drivers/misc/hddl_device/hddl_device_rh.c | 837 +++ drivers/misc/hddl_device/hddl_device_util.h | 52 + drivers/misc/intel_tsens/Kconfig | 55 + drivers/misc/intel_tsens/Makefile | 10 + drivers/misc/intel_tsens/intel_tsens_host.c | 351 +++ drivers/misc/intel_tsens/intel_tsens_i2c.c| 119 + .../misc/intel_tsens/intel_tsens_thermal.c| 651 ++ .../misc/intel_tsens/intel_tsens_thermal.h| 38 + drivers/misc/intel_tsens/keembay_thermal.c| 169 ++ drivers/misc/intel_tsens/keembay_tsens.h | 366 +++ drivers/misc/vpumgr/Kconfig |
[PATCH v3 28/34] misc: Intel tsens IA host driver.
From: "C, Udhayakumar"
Add Intel tsens IA host driver for Intel Edge.AI Computer Vision
platforms.
About Intel Edge.AI Computer Vision platforms:
-
The Intel Edge.AI Computer Vision platforms are vision processing systems
targeting machine vision applications for connected devices.
They are based on ARM A53 CPU running Linux and acts as a PCIe
endpoint device.
High-level architecture:
Remote Host IA CPU Local Host ARM CPU
--
| Platform| | Thermal Daemon|
| Management SW| ||
--
| Intel tsens | | intel tsens i2c slave |
| i2c client | | and thermal driver|
--
| XLINK I2C | | XLINK I2C Slave |
| controller | <=> | controller |
xlink smbus --
intel tsens module:
---
The tsens module enables reading of on chip sensors present
in the Intel Edge.AI Computer Vision platforms.In the tsens module
various junction and SoC temperatures are reported using thermal
subsystem and i2c subsystem.
Temperature data reported using thermal subsystem will be used for
various cooling agents such as DVFS, fan control and shutdown the
system in case of critical temperature.
Temperature data reported using i2c subsystem will be used by
platform manageability software running in IA host.
- Remote Host driver
* Intended for IA CPU
* It is a I2C client driver
* Driver path:
{tree}/drivers/misc/intel_tsens/intel_tsens_host.c
Local host and Remote host drivers communicates using
I2C SMBUS protocol.
Acked-by: Mark Mross
Signed-off-by: C, Udhayakumar
---
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/intel_tsens_host.rst| 71
drivers/misc/intel_tsens/Kconfig| 13 +
drivers/misc/intel_tsens/Makefile | 1 +
drivers/misc/intel_tsens/intel_tsens_host.c | 351
include/linux/intel_tsens_host.h| 34 ++
6 files changed, 471 insertions(+)
create mode 100644 Documentation/hwmon/intel_tsens_host.rst
create mode 100644 drivers/misc/intel_tsens/intel_tsens_host.c
create mode 100644 include/linux/intel_tsens_host.h
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index fc29100bef73..7a9eaddd1ab3 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -81,6 +81,7 @@ Hardware Monitoring Kernel Drivers
isl68137
it87
intel_tsens_sensor.rst
+ intel_tsens_host.rst
jc42
k10temp
k8temp
diff --git a/Documentation/hwmon/intel_tsens_host.rst
b/Documentation/hwmon/intel_tsens_host.rst
new file mode 100644
index ..012c593f969f
--- /dev/null
+++ b/Documentation/hwmon/intel_tsens_host.rst
@@ -0,0 +1,71 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+==
+Kernel driver: intel_tsens
+==
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+
+Slave address: The address is assigned by the hddl device management
+ driver.
+
+Datasheet:
+ Documentation/hwmon/intel_tsens_sensor.rst#Remote Thermal Interface
+
+Authors:
+- Thalaiappan, Rathina
+
+Description
+===
+The intel_tsens is a temperature sensor driver receiving the junction
temperature
+from different heating points inside the SOC. The driver will receive the
+temperature on SMBUS connection. The reported temperature is in degrees
Celsius.
+
+In Keem Bay, the four thermal junction temperature points are,
+Media Subsystem (mss), NN subsystem (nce), Compute subsystem (cse) and
+SOC(Maximum of mss, nce and cse).
+
+Example
+===
+Temperature reported by a Keem Bay on the Linux Thermal sysfs interface.
+
+# cat /sys/class/thermal/thermal_zone*/type
+mss
+css
+nce
+soc
+
+# cat /sys/class/thermal/thermal_zone*/temp
+0
+29210
+28478
+29210
+
++---+-+
+| offset| Sensor|
++---+-+
+| 0 | mss |
++---+-+
+| 1 | css |
++---+-+
+| 2 | nce |
++---+-+
+| 3 | soc |
++---+-+
+
+#sudo i2cdetect -l
+i2c-8 smbus SMBus I801 adapter at efa0 SMBus adapte
r
+
+To read mss junction temperature:
+#i2cget -y 8 0x0 w
+
+To read cse junction temperature:
+#i2cget -y 8 0x1 w
+
+To read nce junction temperature:
+#i2cget -y 8 0x2 w
+
+To read overall SoC temperature:
+#i2cget -y 8 0x3 w
diff --git a/drivers/misc/intel_tsens/Kconfig b/drivers/misc/intel_tsens/Kconfig
index bfb8fe1997f4..8b263
[PATCH v4 05/34] keembay-ipc: Add Keem Bay IPC module
From: Daniele Alessandrelli On the Intel Movidius SoC code named Keem Bay, communication between the Application Processor(AP) and the VPU is enabled by the Keem Bay Inter-Processor Communication (IPC) mechanism. Add the driver for using Keem Bay IPC from within the Linux Kernel. The IPC uses the following terminology: - Node:A processing entity that can use the IPC to communicate (currently, we just have two nodes, the AP and the VPU). - Link:Two nodes that can communicate over IPC form an IPC link (currently, we just have one link, the one formed by the AP and the VPU). - Channel: An IPC link can provide multiple IPC channels. IPC channels allow communication multiplexing, i.e., the same IPC link can be used by different applications for different communications. Each channel is identified by a channel ID, which must be unique within a single IPC link. Channels are divided in two categories, High-Speed (HS) channels and General-Purpose (GP) channels. HS channels have higher priority over GP channels. The Keem Bay IPC mechanism is built on top of the VPU IPC mailbox, which allows the AP and the VPU to exchange 32-bit messages. Specifically, the IPC uses shared memory (shared between the AP and the VPU) to allocate IPC packets and then exchanges them using the VPU IPC mailbox (the 32-bit physical address of the packet is passed as a message to the VPU IPC mailbox). IPC packets have a fixed structure containing the (VPU) physical address of the payload (which must be located in shared memory too) as well as other information (payload size, IPC channel ID, etc.). Each IPC node (i.e., both the AP and the VPU) has its own reserved memory region (in shared memory) from which it instantiates its own pool of IPC packets. When instantiated, IPC packets are marked as free. When the node needs to send an IPC message, it gets the first free packet it finds (from its own pool), marks it as allocated (used), and transfer its physical address to the destination node using the VPU IPC mailbox. The destination node uses the received physical address to access the IPC packet, process the packet, and, once done with it, marks it as free (so that the sender can reuse it). Cc: Paul Walmsley Cc: Palmer Dabbelt Cc: Borislav Petkov Cc: Damien Le Moal Cc: Peng Fan Cc: Shawn Guo Reviewed-by: Mark Gross Signed-off-by: Daniele Alessandrelli Signed-off-by: Mark Gross --- MAINTAINERS |8 + drivers/soc/Kconfig |1 + drivers/soc/Makefile |1 + drivers/soc/intel/Kconfig | 18 + drivers/soc/intel/Makefile|4 + drivers/soc/intel/keembay-ipc.c | 1364 + include/linux/soc/intel/keembay-ipc.h | 30 + 7 files changed, 1426 insertions(+) create mode 100644 drivers/soc/intel/Kconfig create mode 100644 drivers/soc/intel/Makefile create mode 100644 drivers/soc/intel/keembay-ipc.c create mode 100644 include/linux/soc/intel/keembay-ipc.h diff --git a/MAINTAINERS b/MAINTAINERS index de23f6e5cfce..684e64e958a4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9060,6 +9060,14 @@ F: drivers/crypto/keembay/keembay-ocs-aes-core.c F: drivers/crypto/keembay/ocs-aes.c F: drivers/crypto/keembay/ocs-aes.h +INTEL KEEM BAY IPC DRIVER +M: Daniele Alessandrelli +M: Mark Gross +S: Supported +F: Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml +F: drivers/soc/intel/keembay-ipc.c +F: include/linux/soc/intel/keembay-ipc.h + INTEL MANAGEMENT ENGINE (mei) M: Tomas Winkler L: linux-kernel@vger.kernel.org diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index d097d070f579..b9d69a1eedc7 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -8,6 +8,7 @@ source "drivers/soc/atmel/Kconfig" source "drivers/soc/bcm/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/imx/Kconfig" +source "drivers/soc/intel/Kconfig" source "drivers/soc/ixp4xx/Kconfig" source "drivers/soc/litex/Kconfig" source "drivers/soc/mediatek/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 699b758d28e4..1a6c00d2e32e 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_MACH_DOVE) += dove/ obj-y += fsl/ obj-$(CONFIG_ARCH_GEMINI) += gemini/ obj-y += imx/ +obj-y += intel/ obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/ diff --git a/drivers/soc/intel/Kconfig b/drivers/soc/intel/Kconfig new file mode 100644 index ..a575e31e47b4 --- /dev/null +++ b/drivers/soc/intel/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Keem Bay SoC drivers +# + +menu "Intel SoC drivers" +
[PATCH v4 12/34] misc: xlink-pcie: lh: Prepare changes for adding remote host driver
From: Srikanth Thokala
Move logic that can be reused between local host and remote host to
common/ folder
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/{local_host => common}/core.h | 8 +++-
drivers/misc/xlink-pcie/{local_host => common}/util.c | 8 +++-
drivers/misc/xlink-pcie/{local_host => common}/util.h | 8 +++-
drivers/misc/xlink-pcie/{local_host => common}/xpcie.h | 8 +++-
drivers/misc/xlink-pcie/local_host/Makefile| 2 +-
drivers/misc/xlink-pcie/local_host/core.c | 4 ++--
drivers/misc/xlink-pcie/local_host/epf.h | 4 ++--
7 files changed, 17 insertions(+), 25 deletions(-)
rename drivers/misc/xlink-pcie/{local_host => common}/core.h (96%)
rename drivers/misc/xlink-pcie/{local_host => common}/util.c (97%)
rename drivers/misc/xlink-pcie/{local_host => common}/util.h (91%)
rename drivers/misc/xlink-pcie/{local_host => common}/xpcie.h (92%)
diff --git a/drivers/misc/xlink-pcie/local_host/core.h
b/drivers/misc/xlink-pcie/common/core.h
similarity index 96%
rename from drivers/misc/xlink-pcie/local_host/core.h
rename to drivers/misc/xlink-pcie/common/core.h
index 84985ef41a64..656b5e2dbfae 100644
--- a/drivers/misc/xlink-pcie/local_host/core.h
+++ b/drivers/misc/xlink-pcie/common/core.h
@@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- *
+/*
* Intel Keem Bay XLink PCIe Driver
*
- * Copyright (C) 2020 Intel Corporation
- *
- /
+ * Copyright (C) 2021 Intel Corporation
+ */
#ifndef XPCIE_CORE_HEADER_
#define XPCIE_CORE_HEADER_
diff --git a/drivers/misc/xlink-pcie/local_host/util.c
b/drivers/misc/xlink-pcie/common/util.c
similarity index 97%
rename from drivers/misc/xlink-pcie/local_host/util.c
rename to drivers/misc/xlink-pcie/common/util.c
index ec808b0cd72b..d99125f61ba0 100644
--- a/drivers/misc/xlink-pcie/local_host/util.c
+++ b/drivers/misc/xlink-pcie/common/util.c
@@ -1,11 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-only
-/*
- *
+/*
* Intel Keem Bay XLink PCIe Driver
*
- * Copyright (C) 2020 Intel Corporation
- *
- /
+ * Copyright (C) 2021 Intel Corporation
+ */
#include "util.h"
diff --git a/drivers/misc/xlink-pcie/local_host/util.h
b/drivers/misc/xlink-pcie/common/util.h
similarity index 91%
rename from drivers/misc/xlink-pcie/local_host/util.h
rename to drivers/misc/xlink-pcie/common/util.h
index 908be897a61d..5295783b0437 100644
--- a/drivers/misc/xlink-pcie/local_host/util.h
+++ b/drivers/misc/xlink-pcie/common/util.h
@@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- *
+/*
* Intel Keem Bay XLink PCIe Driver
*
- * Copyright (C) 2020 Intel Corporation
- *
- /
+ * Copyright (C) 2021 Intel Corporation
+ */
#ifndef XPCIE_UTIL_HEADER_
#define XPCIE_UTIL_HEADER_
diff --git a/drivers/misc/xlink-pcie/local_host/xpcie.h
b/drivers/misc/xlink-pcie/common/xpcie.h
similarity index 92%
rename from drivers/misc/xlink-pcie/local_host/xpcie.h
rename to drivers/misc/xlink-pcie/common/xpcie.h
index 8a559617daba..48529eb49be0 100644
--- a/drivers/misc/xlink-pcie/local_host/xpcie.h
+++ b/drivers/misc/xlink-pcie/common/xpcie.h
@@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- *
+/*
* Intel Keem Bay XLink PCIe Driver
*
- * Copyright (C) 2020 Intel Corporation
- *
- /
+ * Copyright (C) 2021 Intel Corporation
+ */
#ifndef XPCIE_HEADER_
#define XPCIE_HEADER_
diff --git a/drivers/misc/xlink-pcie/local_host/Makefile
b/drivers/misc/xlink-pcie/local_host/Makefile
index 28761751d43b..65df94c7e860 100644
--- a/drivers/misc/xlink-pcie/local_host/Makefile
+++ b/drivers/misc/xlink-pcie/local_host/Makefile
@@ -2,4 +2,4 @@ obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o
mxlk_ep-objs := epf.o
mxlk_ep-objs += dma.o
mxlk_ep-objs += core.o
-mxlk_ep-objs += util.o
+mxlk_ep-objs += ../common/util.o
diff --git a/drivers/misc/xlink-pcie/local_host/core.c
b/drivers/misc/xlink-pcie/local_host/core.c
index c67ce2c3067d..2c4e29bce7f7 100644
--- a/drivers/misc/xlink-pcie/local_host/core.c
+++ b/drivers/misc/xlink-pcie/local_host/core.c
@@ -8,8 +8,8 @@
#include
#include "epf.h"
-#include "core.h"
-#include "util.h"
+#include "../common/core.h"
+#include "../common/util.h"
static struct xpcie *global_xpcie;
diff --git a/drivers/misc/xlink-pcie/local_host/epf.h
b/drivers/m
[PATCH v3 22/34] xlink-core: Enable VPU IP management and runtime control
From: Seamus Kelly
Enable VPU management including, enumeration, boot and runtime control.
Add APIs:
write control data:
used to transmit small, local data
start vpu:
calls boot_device API ( soon to be deprecated )
stop vpu
calls reset_device API ( soon to be deprecated )
reset vpu
calls reset_device API ( soon to be deprecated )
get device name:
Returns the device name for the input device id
This could be a char device path, for example "/dev/ttyUSB0"
for a serial device; or it could be a device string
description, for example, for PCIE "00:00.0 Host bridge: Intel
Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 01)"
get device list:
Returns the list of software device IDs for all connected
physical devices
get device status:
returns the current state of the input device
OFF - The device is off (D3cold/Slot power removed).
BUSY - device is busy and not available (device is
booting)
READY - device is available for use
ERROR - device HW failure is detected
RECOVERY - device is in recovery mode, waiting for
recovery operations
boot device:
When used on the remote host - starts the SOC device by calling
corresponding function from VPU Driver.
Takes firmware's 'binary_name' as input.
For Linux, the firmware image is expected to be located in
'/lib/firmware' folder or its subfolders.
For Linux, 'binary_name' is not a path but an image name that
will be searched in the default Linux search paths
('/lib/firmware').
When used on the local host - triggers the booting of VPUIP
device.
reset device:
When used on the remote host - resets the device by calling
corresponding VPU Driver function.
When used on the local host - resets the VPUIP device
get device mode:
query and returns the current device power mode
set device mode:
used for device throttling or entering various power modes
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Seamus Kelly
---
drivers/misc/xlink-core/xlink-core.c| 235
drivers/misc/xlink-core/xlink-defs.h| 2 +
drivers/misc/xlink-core/xlink-ioctl.c | 214 ++
drivers/misc/xlink-core/xlink-ioctl.h | 9 +
drivers/misc/xlink-core/xlink-multiplexer.c | 56 +
drivers/misc/xlink-core/xlink-platform.c| 86 +++
include/linux/xlink.h | 27 +++
7 files changed, 629 insertions(+)
diff --git a/drivers/misc/xlink-core/xlink-core.c
b/drivers/misc/xlink-core/xlink-core.c
index bdbf8c6a99ca..d0a3f98d16af 100644
--- a/drivers/misc/xlink-core/xlink-core.c
+++ b/drivers/misc/xlink-core/xlink-core.c
@@ -73,6 +73,8 @@ struct keembay_xlink_dev {
struct mutex lock; // protect access to xlink_dev
};
+static u8 volbuf[XLINK_MAX_BUF_SIZE]; // buffer for volatile transactions
+
/*
* global variable pointing to our xlink device.
*
@@ -264,6 +266,9 @@ static long xlink_ioctl(struct file *file, unsigned int
cmd, unsigned long arg)
case XL_READ_DATA:
rc = ioctl_read_data(arg);
break;
+ case XL_READ_TO_BUFFER:
+ rc = ioctl_read_to_buffer(arg);
+ break;
case XL_WRITE_DATA:
rc = ioctl_write_data(arg);
break;
@@ -276,9 +281,39 @@ static long xlink_ioctl(struct file *file, unsigned int
cmd, unsigned long arg)
case XL_CLOSE_CHANNEL:
rc = ioctl_close_channel(arg);
break;
+ case XL_START_VPU:
+ rc = ioctl_start_vpu(arg);
+ break;
+ case XL_STOP_VPU:
+ rc = xlink_stop_vpu();
+ break;
+ case XL_RESET_VPU:
+ rc = xlink_stop_vpu();
+ break;
case XL_DISCONNECT:
rc = ioctl_disconnect(arg);
break;
+ case XL_GET_DEVICE_NAME:
+ rc = ioctl_get_device_name(arg);
+ break;
+ case XL_GET_DEVICE_LIST:
+ rc = ioctl_get_device_list(arg);
+ break;
+ case XL_GET_DEVICE_STATUS:
+ rc = ioctl_get_device_status(arg);
+ break;
+ case XL_BOOT_DEVICE:
+ rc = ioctl_boot_device(arg);
+ break;
+ case XL_RESET_DEVICE:
+ rc = ioctl_reset_device(arg);
+ break;
+ case XL_GET_DEVICE_MODE:
+ rc
[PATCH v4 33/34] misc: Hddl device management for local host
From: "C, Udhayakumar"
Add local host hddl device management for Intel Edge.AI Computer Vision
platforms.
About Intel Edge.AI Computer Vision platforms:
-
The Intel Edge.AI Computer Vision platforms are vision processing systems
targeting machine vision applications for connected devices.
They are based on ARM A53 CPU running Linux and acts as a PCIe
endpoint device.
High-level architecture:
Remote Host IA CPU Local Host ARM CPU
---
| * Send time as xlink packet | |* Sync time with IA host |
| * receive sensor details| |* Prepare and share sensor|
| and register as i2c or| | details to IA host as |
| xlink smbus slaves| | xlink packets |
---
| hddl server | <=> | hddl client |
--- xlink
hddl device module:
---
The HDDL client driver acts as an software RTC to sync with network
time. It abstracts xlink protocol to communicate with remote host.
This driver exports the details about sensors available in the
platform to remote host as xlink packets.
This driver also handles device connect/disconnect events and
identifies board id and soc id using gpio's, based on platform
configuration.
- Local Host driver
* Intended for ARM CPU
* It is based on xlink Framework
* Driver path:
{tree}/drivers/misc/hddl_device/hddl_device_client.c
Local arm host and Remote IA host drivers communicates using
XLINK protocol.
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
.../misc-devices/hddl_device_client.rst | 212 +
Documentation/misc-devices/index.rst | 1 +
Documentation/vpu/index.rst | 1 +
MAINTAINERS | 1 +
drivers/misc/Kconfig | 1 +
drivers/misc/Makefile | 1 +
drivers/misc/hddl_device/Kconfig | 14 +
drivers/misc/hddl_device/Makefile | 5 +
drivers/misc/hddl_device/hddl_device.c| 565 +
drivers/misc/hddl_device/hddl_device_lh.c | 764 ++
drivers/misc/hddl_device/hddl_device_util.h | 52 ++
11 files changed, 1617 insertions(+)
create mode 100644 Documentation/misc-devices/hddl_device_client.rst
create mode 100644 drivers/misc/hddl_device/Kconfig
create mode 100644 drivers/misc/hddl_device/Makefile
create mode 100644 drivers/misc/hddl_device/hddl_device.c
create mode 100644 drivers/misc/hddl_device/hddl_device_lh.c
create mode 100644 drivers/misc/hddl_device/hddl_device_util.h
diff --git a/Documentation/misc-devices/hddl_device_client.rst
b/Documentation/misc-devices/hddl_device_client.rst
new file mode 100644
index ..413643b6b500
--- /dev/null
+++ b/Documentation/misc-devices/hddl_device_client.rst
@@ -0,0 +1,212 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=
+Kernel driver: hddl_device_client
+=
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+
+Authors:
+- Thalaiappan, Rathina
+- Udhayakumar C
+
+
+Overview
+
+
+This driver supports hddl device management for Intel Edge.AI Computer Vision
+platforms.
+
+This driver supports the following features:
+
+ - Exports deatils of temperature sensor, current sensor and fan controller
+present in Intel Edge.AI Computer Vision platforms to IA host.
+ - Enable Time sync of Intel Edge.AI Computer Vision platform with IA host.
+ - Handles device connect and disconnect events.
+ - Receives slave address from the IA host for memory mapped thermal sensors
+present in SoC (Documentation/hwmon/intel_tsens_sensors.rst).
+ - Registers i2c slave device for slaves present in Intel Edge.AI Computer
+Vision platform
+
+Keem Bay platform has
+Onchip sensors:
+
+ - Media Subsystem (mss) temperature sensor
+ - NN subsystem (nce) temperature sensor
+ - Compute subsystem (cse) temperature sensor
+ - SOC(Maximum of mss, nce and cse).
+
+Onboard sensors:
+
+ - two lm75 temperature sensors
+ - emc2103 fan controller
+ - ina3221 current sensor
+
+High-level architecture
+===
+::
+
+Remote Host IA CPU Local Host ARM CPU
+---
+| * Send time as xlink packet | |* Sync time with IA host |
+| * receive sensor details| |* Prepare and share sensor|
+| and register as i2c or| | details to IA host as |
+| xlink smbus slaves| | xlink packets |
+---
+
[PATCH v3 34/34] misc: HDDL device management for IA host
From: "C, Udhayakumar"
Add IA host hddl device management driver for Intel Edge.AI Computer Vision
platforms.
About Intel Edge.AI Computer Vision platforms:
-
The Intel Edge.AI Computer Vision platforms are vision processing systems
targeting machine vision applications for connected devices.
They are based on ARM A53 CPU running Linux and acts as a PCIe
endpoint device.
High-level architecture:
Remote Host IA CPU Local Host ARM CPU
---
| * Send time as xlink packet | |* Sync time with IA host |
| * receive sensor details| |* Prepare and share sensor|
| and register as i2c or| | details to IA host as |
| xlink smbus slaves| | xlink packets |
---
| hddl server | <=> | hddl client |
--- xlink
hddl device module:
---
The HDDL client driver acts as an software RTC to sync with network
time. It abstracts xlink protocol to communicate with remote host.
This driver exports the details about sensors available in the
platform to remote host as xlink packets.
This driver also handles device connect/disconnect events and
identifies board id and soc id using gpio's, based on platform
configuration.
- Remote Host driver
* Intended for IA CPU
* It is based on xlink Framework
* Driver path:
{tree}/drivers/misc/hddl_device/hddl_device_server.c
Local arm host and Remote IA host drivers communicates using
XLINK protocol.
Signed-off-by: C, Udhayakumar
---
.../misc-devices/hddl_device_server.rst | 205 +
Documentation/misc-devices/index.rst | 1 +
drivers/misc/hddl_device/Kconfig | 12 +
drivers/misc/hddl_device/Makefile | 2 +
drivers/misc/hddl_device/hddl_device_rh.c | 837 ++
5 files changed, 1057 insertions(+)
create mode 100644 Documentation/misc-devices/hddl_device_server.rst
create mode 100644 drivers/misc/hddl_device/hddl_device_rh.c
diff --git a/Documentation/misc-devices/hddl_device_server.rst
b/Documentation/misc-devices/hddl_device_server.rst
new file mode 100644
index ..0be37973d1fe
--- /dev/null
+++ b/Documentation/misc-devices/hddl_device_server.rst
@@ -0,0 +1,205 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Kernel driver: hddl_device_server
+=
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+
+Authors:
+- Thalaiappan, Rathina
+- Udhayakumar C
+
+High-level architecture
+===
+::
+
+Remote Host IA CPU Local Host ARM CPU
+---
+| * Send time as xlink packet | |* Sync time with IA host |
+| * receive sensor details| |* Prepare and share sensor|
+| and register as i2c or| | details to IA host as |
+| xlink smbus slaves| | xlink packets |
+---
+| hddl server | <=> | hddl client |
+--- xlink
+
+Overview
+
+
+This driver supports hddl device management for Intel Edge.AI Computer Vision
+platforms. This driver runs in IA host
+
+This driver supports the following features:
+
+ - Receives deatils of temperature sensor, current sensor and fan controller
+present in Intel Edge.AI Computer Vision platforms.
+ - Send Time sync data to Intel Edge.AI Computer Vision platform.
+ - Handles device connect and disconnect events.
+ - Get free slave address for memory mapped thermal sensors present in SoC
+(Documentation/hwmon/intel_tsens_sensors.rst) and share it with Intel
+Edge.AI Computer Vision platform.
+ - Registers i2c slave device for slaves present in Intel Edge.AI Computer
+Vision platform
+
+Keem Bay platform has
+Onchip sensors:
+
+ - Media Subsystem (mss) temperature sensor
+ - NN subsystem (nce) temperature sensor
+ - Compute subsystem (cse) temperature sensor
+ - SOC(Maximum of mss, nce and cse).
+
+Onboard sensors:
+
+ - two lm75 temperature sensors
+ - emc2103 fan controller
+ - ina3221 current sensor
+
+Driver Structure
+
+
+The driver provides a platform device where the ``probe`` and ``remove``
+operations are provided.
+
+ - probe: spawn kernel thread to monitor new PCIE devices.
+
+ - init task: Poll for new PCIE device with time interval of 5 seconds and
+creates connect task to setup new device.
+
+ - connect task: Connect task is the main entity which connects to hddl
+device client usin
[PATCH v4 16/34] misc: xlink-pcie: Add asynchronous event notification support for XLink
From: Srikanth Thokala
Add support to notify XLink layer upon PCIe link UP/DOWN events
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/common/core.h | 3 ++
drivers/misc/xlink-pcie/common/interface.c | 17 ++
drivers/misc/xlink-pcie/local_host/core.c | 11 +++
drivers/misc/xlink-pcie/remote_host/main.c | 3 ++
drivers/misc/xlink-pcie/remote_host/pci.c | 36 ++
drivers/misc/xlink-pcie/remote_host/pci.h | 3 ++
include/linux/xlink_drv_inf.h | 12
7 files changed, 85 insertions(+)
diff --git a/drivers/misc/xlink-pcie/common/core.h
b/drivers/misc/xlink-pcie/common/core.h
index f43c175b7a48..87b302f87cfd 100644
--- a/drivers/misc/xlink-pcie/common/core.h
+++ b/drivers/misc/xlink-pcie/common/core.h
@@ -239,4 +239,7 @@ int intel_xpcie_pci_connect_device(u32 id);
int intel_xpcie_pci_read(u32 id, void *data, size_t *size, u32 timeout);
int intel_xpcie_pci_write(u32 id, void *data, size_t *size, u32 timeout);
int intel_xpcie_pci_reset_device(u32 id);
+int intel_xpcie_pci_register_device_event(u32 sw_device_id,
+ xlink_device_event event_notif_fn);
+int intel_xpcie_pci_unregister_device_event(u32 sw_device_id);
#endif /* XPCIE_CORE_HEADER_ */
diff --git a/drivers/misc/xlink-pcie/common/interface.c
b/drivers/misc/xlink-pcie/common/interface.c
index fcc69a940a4c..5d30c27dd18d 100644
--- a/drivers/misc/xlink-pcie/common/interface.c
+++ b/drivers/misc/xlink-pcie/common/interface.c
@@ -105,3 +105,20 @@ int xlink_pcie_reset_device(u32 sw_device_id)
return intel_xpcie_pci_reset_device(sw_device_id);
}
EXPORT_SYMBOL_GPL(xlink_pcie_reset_device);
+
+int xlink_pcie_register_device_event(u32 sw_device_id,
+xlink_device_event event_notif_fn)
+{
+ if (!event_notif_fn)
+ return -EINVAL;
+
+ return intel_xpcie_pci_register_device_event(sw_device_id,
+event_notif_fn);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_register_device_event);
+
+int xlink_pcie_unregister_device_event(u32 sw_device_id)
+{
+ return intel_xpcie_pci_unregister_device_event(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_unregister_device_event);
diff --git a/drivers/misc/xlink-pcie/local_host/core.c
b/drivers/misc/xlink-pcie/local_host/core.c
index 2c4e29bce7f7..bfb14c18c24c 100644
--- a/drivers/misc/xlink-pcie/local_host/core.c
+++ b/drivers/misc/xlink-pcie/local_host/core.c
@@ -804,3 +804,14 @@ int intel_xpcie_pci_reset_device(u32 id)
{
return 0;
}
+
+int intel_xpcie_pci_register_device_event(u32 sw_device_id,
+ xlink_device_event event_notif_fn)
+{
+ return 0;
+}
+
+int intel_xpcie_pci_unregister_device_event(u32 sw_device_id)
+{
+ return 0;
+}
diff --git a/drivers/misc/xlink-pcie/remote_host/main.c
b/drivers/misc/xlink-pcie/remote_host/main.c
index ed1a431ed5d4..efc9143a2fac 100644
--- a/drivers/misc/xlink-pcie/remote_host/main.c
+++ b/drivers/misc/xlink-pcie/remote_host/main.c
@@ -53,6 +53,8 @@ static int intel_xpcie_probe(struct pci_dev *pdev,
if (new_device)
intel_xpcie_list_add_device(xdev);
+ intel_xpcie_pci_notify_event(xdev, NOTIFY_DEVICE_CONNECTED);
+
return ret;
}
@@ -62,6 +64,7 @@ static void intel_xpcie_remove(struct pci_dev *pdev)
if (xdev) {
intel_xpcie_pci_cleanup(xdev);
+ intel_xpcie_pci_notify_event(xdev, NOTIFY_DEVICE_DISCONNECTED);
intel_xpcie_remove_device(xdev);
}
}
diff --git a/drivers/misc/xlink-pcie/remote_host/pci.c
b/drivers/misc/xlink-pcie/remote_host/pci.c
index 71cbe779d1bc..6a79782b983e 100644
--- a/drivers/misc/xlink-pcie/remote_host/pci.c
+++ b/drivers/misc/xlink-pcie/remote_host/pci.c
@@ -6,6 +6,7 @@
*/
#include
+#include
#include
#include
#include
@@ -485,3 +486,38 @@ int intel_xpcie_pci_reset_device(u32 id)
return intel_xpcie_pci_prepare_dev_reset(xdev, true);
}
+
+int intel_xpcie_pci_register_device_event(u32 sw_device_id,
+ xlink_device_event event_notif_fn)
+{
+ struct xpcie_dev *xdev = intel_xpcie_get_device_by_id(sw_device_id);
+
+ if (!xdev)
+ return -ENOMEM;
+
+ xdev->event_fn = event_notif_fn;
+
+ return 0;
+}
+
+int intel_xpcie_pci_unregister_device_event(u32 sw_device_id)
+{
+ struct xpcie_dev *xdev = intel_xpcie_get_device_by_id(sw_device_id);
+
+ if (!xdev)
+ return -ENOMEM;
+
+ xdev->event_fn = NULL;
+
+ return 0;
+}
+
+void intel_xpcie_pci_notify_event(struct xpcie_dev *xdev,
+ enum xlink_device_event_type event_type)
+{
+ if (event_type >= NUM_EVENT_TYPE)
+ return;
+
+ if (xdev->event_fn)
+ xdev
[PATCH v3 04/34] dt-bindings: Add bindings for Keem Bay IPC driver
From: Daniele Alessandrelli
Add DT binding documentation for the Intel Keem Bay IPC driver, which
enables communication between the Computing Sub-System (CSS) and the
Multimedia Sub-System (MSS) of the Intel Movidius SoC code named Keem
Bay.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Reviewed-by: Mark Gross
Signed-off-by: Daniele Alessandrelli
---
.../bindings/soc/intel/intel,keembay-ipc.yaml | 45 +++
1 file changed, 45 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml
diff --git a/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml
b/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml
new file mode 100644
index ..586fe73f4cd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Intel Corporation
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-ipc.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Keem Bay IPC
+
+maintainers:
+ - Daniele Alessandrelli
+
+description:
+ The Keem Bay IPC driver enables Inter-Processor Communication (IPC) with the
+ Visual Processor Unit (VPU) embedded in the Intel Movidius SoC code named
+ Keem Bay.
+
+properties:
+ compatible:
+const: intel,keembay-ipc
+
+ memory-region:
+items:
+ - description:
+ Reserved memory region used by the CPU to allocate IPC packets.
+ - description:
+ Reserved memory region used by the VPU to allocate IPC packets.
+
+ mboxes:
+description: VPU IPC Mailbox.
+
+required:
+ - compatible
+ - memory-region
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ipc {
+ compatible = "intel,keembay-ipc";
+ memory-region = <&ipc_cpu_reserved>, <&ipc_vpu_reserved>;
+ mboxes = <&vpu_ipc_mbox 0>;
+};
--
2.17.1
[PATCH v3 30/34] misc:intel_tsens: Intel Keem Bay tsens driver.
From: "C, Udhayakumar"
Add keembey_thermal driver to expose on chip temperature
sensors, and register call back functions for periodic sampling.
This driver does following:
* Reads temperature data from on chip sensors present in Keem Bay
platform.
* Registers callback function to intel tsens driver for sampling
temperature values periodically.
* Decode the raw values from registers to Celsius.
Acked-by: mark gross
Signed-off-by: C, Udhayakumar
---
drivers/misc/intel_tsens/Kconfig | 12 +
drivers/misc/intel_tsens/Makefile | 1 +
drivers/misc/intel_tsens/keembay_thermal.c | 169 ++
drivers/misc/intel_tsens/keembay_tsens.h | 366 +
4 files changed, 548 insertions(+)
create mode 100644 drivers/misc/intel_tsens/keembay_thermal.c
create mode 100644 drivers/misc/intel_tsens/keembay_tsens.h
diff --git a/drivers/misc/intel_tsens/Kconfig b/drivers/misc/intel_tsens/Kconfig
index 9b2198ab28c3..bd575d99281d 100644
--- a/drivers/misc/intel_tsens/Kconfig
+++ b/drivers/misc/intel_tsens/Kconfig
@@ -29,6 +29,18 @@ config INTEL_TSENS_I2C_SLAVE
Say Y if using a processor that includes the Intel VPU such as
Keem Bay. If unsure, say N.
+config KEEMBAY_THERMAL
+ tristate "Temperature sensor driver for intel Keem Bay"
+ depends on INTEL_TSENS_LOCAL_HOST && ARCH_KEEMBAY
+ help
+ Enable this option if you want to have support for Keem Bay
+ thermal management sensors.
+
+ This driver is used for reading onchip temperature sensor
+ values from Keem Bay SoC.
+ Say Y if using a processor that includes the Intel VPU such as
+ Keem Bay. If unsure, say N.
+
config INTEL_TSENS_IA_HOST
tristate "Temperature sensor driver for intel tsens remote host"
depends on I2C && THERMAL
diff --git a/drivers/misc/intel_tsens/Makefile
b/drivers/misc/intel_tsens/Makefile
index f6f41bbca80c..00f63c2d5b2f 100644
--- a/drivers/misc/intel_tsens/Makefile
+++ b/drivers/misc/intel_tsens/Makefile
@@ -7,3 +7,4 @@
obj-$(CONFIG_INTEL_TSENS_LOCAL_HOST) += intel_tsens_thermal.o
obj-$(CONFIG_INTEL_TSENS_I2C_SLAVE)+= intel_tsens_i2c.o
obj-$(CONFIG_INTEL_TSENS_IA_HOST) += intel_tsens_host.o
+obj-$(CONFIG_KEEMBAY_THERMAL) += keembay_thermal.o
diff --git a/drivers/misc/intel_tsens/keembay_thermal.c
b/drivers/misc/intel_tsens/keembay_thermal.c
new file mode 100644
index ..d6c8fa8fc3aa
--- /dev/null
+++ b/drivers/misc/intel_tsens/keembay_thermal.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *
+ * Intel Keem Bay thermal Driver
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "intel_tsens_thermal.h"
+#include "keembay_tsens.h"
+
+struct keembay_thermal_priv {
+ const char *name;
+ void __iomem *base_addr;
+ /* sensor lock*/
+ spinlock_t lock;
+ int current_temp[KEEMBAY_SENSOR_MAX];
+ struct intel_tsens_plat_data *plat_data;
+};
+
+static void kmb_sensor_read_temp(void __iomem *regs_val,
+int offset,
+int sample_valid_mask,
+int sample_value,
+int bit_shift,
+int *temp)
+{
+ int reg_val, kmb_raw_index;
+
+ /* clear the bit of TSENS_EN and re-enable again */
+ iowrite32(0x00, regs_val + AON_TSENS_CFG);
+ iowrite32(CFG_MASK_MANUAL, regs_val + AON_TSENS_CFG);
+ reg_val = ioread32(regs_val + offset);
+ if (reg_val & sample_valid_mask) {
+ reg_val = (reg_val >> bit_shift) & sample_value;
+ kmb_raw_index = reg_val - KEEMBAY_SENSOR_BASE_TEMP;
+ if (kmb_raw_index < 0)
+ reg_val = raw_kmb[0];
+ else if (kmb_raw_index > (raw_kmb_size - 1))
+ reg_val = raw_kmb[raw_kmb_size - 1];
+ else
+ reg_val = raw_kmb[kmb_raw_index];
+ *temp = reg_val;
+ } else {
+ *temp = -255;
+ }
+}
+
+/*The lock is assumed to be held by the caller.*/
+static int keembay_get_temp(struct platform_device *pdev, int type, int *temp)
+{
+ struct keembay_thermal_priv *priv = platform_get_drvdata(pdev);
+
+ spin_lock(&priv->lock);
+ switch (type) {
+ case KEEMBAY_SENSOR_MSS:
+ kmb_sensor_read_temp(priv->base_addr,
+AON_TSENS_DATA0,
+MSS_T_SAMPLE_VALID,
+MSS_T_SAMPLE,
+MSS_BIT_SHIFT,
+temp);
+ priv->current_temp[KEEMBAY_SENSOR_MSS] = *temp;
+ break;
+
+ case KEEMBAY_SENSOR_CSS:
+ kmb_sensor_read_
[PATCH v3 02/34] dt-bindings: mailbox: Add Intel VPU IPC mailbox bindings
From: Daniele Alessandrelli
Add bindings for the Intel VPU IPC mailbox driver.
Signed-off-by: Daniele Alessandrelli
---
.../mailbox/intel,vpu-ipc-mailbox.yaml| 69 +++
MAINTAINERS | 6 ++
2 files changed, 75 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
diff --git
a/Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
b/Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
new file mode 100644
index ..923a6d619a64
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 Intel Corporation
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mailbox/intel,vpu-ipc-mailbox.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel VPU IPC mailbox
+
+maintainers:
+ - Daniele Alessandrelli
+
+description: |
+ Intel VPU SoCs like Keem Bay have hardware FIFOs to enable Inter-Processor
+ Communication (IPC) between the CPU and the VPU.
+
+ Specifically, there is one HW FIFO for the CPU (aka Application Processor -
+ AP) and one for the VPU. Each FIFO can hold 128 entries of 32 bits each. A
+ "FIFO-not-empty" interrupt is raised every time there is at least a message
+ in the FIFO. The CPU FIFO raises interrupts to the CPU, while the VPU FIFO
+ raises interrupts to VPU. When the CPU wants to send a message to the VPU it
+ writes to the VPU FIFO, similarly, when the VPU want to send a message to the
+ CPU, it writes to the CPU FIFO.
+
+ Refer to ./mailbox.txt for generic information about mailbox device-tree
+ bindings.
+
+properties:
+ compatible:
+const: intel,vpu-ipc-mailbox
+
+ reg:
+items:
+ - description: The CPU FIFO registers
+ - description: The VPU FIFO registers
+
+ reg-names:
+items:
+ - const: cpu_fifo
+ - const: vpu_fifo
+
+ interrupts:
+items:
+ - description: CPU FIFO-not-empty interrupt
+
+ "#mbox-cells":
+const: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+vpu_ipc_mailbox@203300f0 {
+compatible = "intel,vpu-ipc-mailbox";
+#mbox-cells = <1>;
+reg = <0x203300f0 0x310>,
+ <0x208200f0 0x310>;
+reg-names = "cpu_fifo", "vpu_fifo";
+interrupts = ;
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 992fe3b0900a..2b82526a00dc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9181,6 +9181,12 @@ L: platform-driver-...@vger.kernel.org
S: Maintained
F: drivers/platform/x86/intel-vbtn.c
+INTEL VPU IPC MAILBOX
+M: Daniele Alessandrelli
+M: Mark Gross
+S: Supported
+F: Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
+
INTEL WIRELESS 3945ABG/BG, 4965AGN (iwlegacy)
M: Stanislaw Gruszka
L: linux-wirel...@vger.kernel.org
--
2.17.1
[PATCH v3 19/34] xlink-core: Add xlink core device tree bindings
From: Seamus Kelly
Add device tree bindings for keembay-xlink.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Reviewed-by: Mark Gross
Signed-off-by: Seamus Kelly
Signed-off-by: Ryan Carnaghi
---
.../bindings/misc/intel,keembay-xlink.yaml| 27 +++
1 file changed, 27 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/intel,keembay-xlink.yaml
diff --git a/Documentation/devicetree/bindings/misc/intel,keembay-xlink.yaml
b/Documentation/devicetree/bindings/misc/intel,keembay-xlink.yaml
new file mode 100644
index ..89c34018fa04
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,keembay-xlink.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) Intel Corporation. All rights reserved.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/intel,keembay-xlink.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel Keem Bay xlink
+
+maintainers:
+ - Seamus Kelly
+
+description: |
+ The Keem Bay xlink driver enables the communication/control sub-system
+ for internal and external communications to the Intel Keem Bay SoC.
+
+properties:
+ compatible:
+oneOf:
+ - items:
+- const: intel,keembay-xlink
+
+examples:
+ - |
+xlink {
+compatible = "intel,keembay-xlink";
+};
--
2.17.1
[PATCH v4 09/34] misc: xlink-pcie: lh: Add PCIe EPF driver for Local Host
From: Srikanth Thokala
Add PCIe EPF driver for local host (lh) to configure BAR's and other
HW resources. Underlying PCIe HW controller is a Synopsys DWC PCIe core.
Cc: Derek Kiernan
Cc: Dragan Cvetic
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
MAINTAINERS | 6 +
drivers/misc/Kconfig| 1 +
drivers/misc/Makefile | 1 +
drivers/misc/xlink-pcie/Kconfig | 9 +
drivers/misc/xlink-pcie/Makefile| 1 +
drivers/misc/xlink-pcie/local_host/Makefile | 2 +
drivers/misc/xlink-pcie/local_host/epf.c| 373
drivers/misc/xlink-pcie/local_host/epf.h| 37 ++
drivers/misc/xlink-pcie/local_host/xpcie.h | 38 ++
9 files changed, 468 insertions(+)
create mode 100644 drivers/misc/xlink-pcie/Kconfig
create mode 100644 drivers/misc/xlink-pcie/Makefile
create mode 100644 drivers/misc/xlink-pcie/local_host/Makefile
create mode 100644 drivers/misc/xlink-pcie/local_host/epf.c
create mode 100644 drivers/misc/xlink-pcie/local_host/epf.h
create mode 100644 drivers/misc/xlink-pcie/local_host/xpcie.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 6742a1827cd9..3ca6c8c6341b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1961,6 +1961,12 @@ F:
Documentation/devicetree/bindings/arm/intel,keembay.yaml
F: arch/arm64/boot/dts/intel/keembay-evm.dts
F: arch/arm64/boot/dts/intel/keembay-soc.dtsi
+ARM KEEM BAY XLINK PCIE SUPPORT
+M: Srikanth Thokala
+M: Mark Gross
+S: Supported
+F: drivers/misc/xlink-pcie/
+
ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
M: Jonathan Cameron
L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index fafa8b0d8099..dfb98e444c6e 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -481,4 +481,5 @@ source "drivers/misc/ocxl/Kconfig"
source "drivers/misc/cardreader/Kconfig"
source "drivers/misc/habanalabs/Kconfig"
source "drivers/misc/uacce/Kconfig"
+source "drivers/misc/xlink-pcie/Kconfig"
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index d23231e73330..d17621fc43d5 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/
obj-$(CONFIG_UACCE)+= uacce/
obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
+obj-y += xlink-pcie/
diff --git a/drivers/misc/xlink-pcie/Kconfig b/drivers/misc/xlink-pcie/Kconfig
new file mode 100644
index ..46aa401d79b7
--- /dev/null
+++ b/drivers/misc/xlink-pcie/Kconfig
@@ -0,0 +1,9 @@
+config XLINK_PCIE_LH_DRIVER
+ tristate "XLink PCIe Local Host driver"
+ depends on PCI_ENDPOINT && ARCH_KEEMBAY
+ help
+ This option enables XLink PCIe Local Host driver.
+
+ Choose M here to compile this driver as a module, name is mxlk_ep.
+ This driver is used for XLink communication over PCIe and is to be
+ loaded on the Intel Keem Bay platform.
diff --git a/drivers/misc/xlink-pcie/Makefile b/drivers/misc/xlink-pcie/Makefile
new file mode 100644
index ..d693d382e9c6
--- /dev/null
+++ b/drivers/misc/xlink-pcie/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += local_host/
diff --git a/drivers/misc/xlink-pcie/local_host/Makefile
b/drivers/misc/xlink-pcie/local_host/Makefile
new file mode 100644
index ..514d3f0c91bc
--- /dev/null
+++ b/drivers/misc/xlink-pcie/local_host/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o
+mxlk_ep-objs := epf.o
diff --git a/drivers/misc/xlink-pcie/local_host/epf.c
b/drivers/misc/xlink-pcie/local_host/epf.c
new file mode 100644
index ..0234756e89ae
--- /dev/null
+++ b/drivers/misc/xlink-pcie/local_host/epf.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include
+#include
+
+#include "epf.h"
+
+#define BAR2_MIN_SIZE SZ_16K
+#define BAR4_MIN_SIZE SZ_16K
+
+#define PCIE_REGS_PCIE_INTR_ENABLE 0x18
+#define PCIE_REGS_PCIE_INTR_FLAGS 0x1C
+#define LBC_CII_EVENT_FLAG BIT(18)
+#define PCIE_REGS_PCIE_ERR_INTR_FLAGS 0x24
+#define LINK_REQ_RST_FLG BIT(15)
+
+static struct pci_epf_header xpcie_header = {
+ .vendorid = PCI_VENDOR_ID_INTEL,
+ .deviceid = PCI_DEVICE_ID_INTEL_KEEMBAY,
+ .baseclass_code = PCI_BASE_CLASS_MULTIMEDIA,
+ .subclass_code = 0x0,
+ .subsys_vendor_id = 0x0,
+ .subsys_id = 0x0,
+};
+
+static const struct pci_epf_device_id xpcie_epf_ids[] = {
+ {
+ .name = "mxlk_pcie_epf",
+ },
+ {},
+};
+
+static irqreturn_t intel_xpcie_err_interrupt(int
[PATCH v3 23/34] xlink-core: add async channel and events
From: Seamus Kelly
Enable asynchronous channel and event communication.
Add APIs:
data ready callback:
The xLink Data Ready Callback function is used to
register a callback function that is invoked when data
is ready to be read from a channel
data consumed callback:
The xLink Data Consumed Callback function is used to
register a callback function that is invoked when data
is consumed by the peer node on a channel
Add event notification handling including APIs:
register device event:
The xLink Register Device Event function is used to
register a callback for notification of certain system
events. Currently XLink supports 4 such events [0-3]
whose meaning is system dependent. Registering for an
event means that the callback will be called when the
event occurs with 2 parameters the sw_device_id of the
device that triggered the event and the event number
[0-3]
unregister device event
The xLink Unregister Device Event function is used to
unregister events that have previously been registered
by register device event API
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Seamus Kelly
---
drivers/misc/xlink-core/xlink-core.c| 497
drivers/misc/xlink-core/xlink-core.h| 11 +-
drivers/misc/xlink-core/xlink-defs.h| 6 +-
drivers/misc/xlink-core/xlink-dispatcher.c | 53 +--
drivers/misc/xlink-core/xlink-ioctl.c | 146 +-
drivers/misc/xlink-core/xlink-ioctl.h | 6 +
drivers/misc/xlink-core/xlink-multiplexer.c | 176 +--
drivers/misc/xlink-core/xlink-platform.c| 27 ++
include/linux/xlink.h | 15 +-
9 files changed, 757 insertions(+), 180 deletions(-)
diff --git a/drivers/misc/xlink-core/xlink-core.c
b/drivers/misc/xlink-core/xlink-core.c
index d0a3f98d16af..23c0025f6f0d 100644
--- a/drivers/misc/xlink-core/xlink-core.c
+++ b/drivers/misc/xlink-core/xlink-core.c
@@ -55,6 +55,8 @@ static struct cdev xlink_cdev;
static long xlink_ioctl(struct file *file, unsigned int cmd, unsigned long
arg);
+static struct mutex dev_event_lock;
+
static const struct file_operations fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = xlink_ioctl,
@@ -66,14 +68,75 @@ struct xlink_link {
struct kref refcount;
};
+struct xlink_attr {
+ unsigned long value;
+ u32 sw_dev_id;
+};
+
struct keembay_xlink_dev {
struct platform_device *pdev;
struct xlink_link links[XLINK_MAX_CONNECTIONS];
u32 nmb_connected_links;
struct mutex lock; // protect access to xlink_dev
+ struct xlink_attr eventx[4];
+};
+
+struct event_info {
+ struct list_head list;
+ u32 sw_device_id;
+ u32 event_type;
+ u32 user_flag;
+ xlink_device_event_cb event_notif_fn;
};
-static u8 volbuf[XLINK_MAX_BUF_SIZE]; // buffer for volatile transactions
+// sysfs attribute functions
+
+static ssize_t eventx_show(struct device *dev, struct device_attribute *attr,
+ int index, char *buf)
+{
+ struct keembay_xlink_dev *xlink_dev = dev_get_drvdata(dev);
+ struct xlink_attr *a = &xlink_dev->eventx[index];
+
+ return sysfs_emit(buf, "0x%x 0x%lx\n", a->sw_dev_id, a->value);
+}
+
+static ssize_t event0_show(struct device *dev, struct device_attribute *attr,
char *buf)
+{
+ return eventx_show(dev, attr, 0, buf);
+}
+
+static ssize_t event1_show(struct device *dev, struct device_attribute *attr,
char *buf)
+{
+ return eventx_show(dev, attr, 1, buf);
+}
+
+static ssize_t event2_show(struct device *dev, struct device_attribute *attr,
char *buf)
+{
+ return eventx_show(dev, attr, 2, buf);
+}
+
+static ssize_t event3_show(struct device *dev, struct device_attribute *attr,
char *buf)
+{
+ return eventx_show(dev, attr, 3, buf);
+}
+
+static DEVICE_ATTR_RO(event0);
+static DEVICE_ATTR_RO(event1);
+static DEVICE_ATTR_RO(event2);
+static DEVICE_ATTR_RO(event3);
+static struct attribute *xlink_sysfs_entries[] = {
+ &dev_attr_event0.attr,
+ &dev_attr_event1.attr,
+ &dev_attr_event2.attr,
+ &dev_attr_event3.attr,
+ NULL,
+};
+
+static const struct attribute_group xlink_sysfs_group = {
+ .attrs = xlink_sysfs_entries,
+};
+
+static struct event_info ev_info;
/*
* global variable pointing to our xlink device.
@@ -207,7 +270,14 @@ static int kmb_xlink_probe(struct platform_device *pdev)
dev_info(&pdev->dev, "Cannot add the device to the system\n");
goto r_class;
[PATCH v3 15/34] misc: xlink-pcie: Add XLink API interface
From: Srikanth Thokala
Provide interface for XLink layer to interact with XLink PCIe transport
layer on both local host and remote host.
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/common/interface.c | 107 +++
drivers/misc/xlink-pcie/local_host/Makefile | 1 +
drivers/misc/xlink-pcie/remote_host/Makefile | 1 +
3 files changed, 109 insertions(+)
create mode 100644 drivers/misc/xlink-pcie/common/interface.c
diff --git a/drivers/misc/xlink-pcie/common/interface.c
b/drivers/misc/xlink-pcie/common/interface.c
new file mode 100644
index ..fcc69a940a4c
--- /dev/null
+++ b/drivers/misc/xlink-pcie/common/interface.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include
+
+#include "core.h"
+#include "xpcie.h"
+
+/* Define xpcie driver interface API */
+int xlink_pcie_get_device_list(u32 *sw_device_id_list, u32 *num_devices)
+{
+ if (!sw_device_id_list || !num_devices)
+ return -EINVAL;
+
+ *num_devices = intel_xpcie_get_device_num(sw_device_id_list);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_list);
+
+int xlink_pcie_get_device_name(u32 sw_device_id, char *device_name,
+ size_t name_size)
+{
+ if (!device_name)
+ return -EINVAL;
+
+ return intel_xpcie_get_device_name_by_id(sw_device_id,
+device_name, name_size);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_name);
+
+int xlink_pcie_get_device_status(u32 sw_device_id, u32 *device_status)
+{
+ u32 status;
+ int rc;
+
+ if (!device_status)
+ return -EINVAL;
+
+ rc = intel_xpcie_get_device_status_by_id(sw_device_id, &status);
+ if (rc)
+ return rc;
+
+ switch (status) {
+ case XPCIE_STATUS_READY:
+ case XPCIE_STATUS_RUN:
+ *device_status = _XLINK_DEV_READY;
+ break;
+ case XPCIE_STATUS_ERROR:
+ *device_status = _XLINK_DEV_ERROR;
+ break;
+ case XPCIE_STATUS_RECOVERY:
+ *device_status = _XLINK_DEV_RECOVERY;
+ break;
+ case XPCIE_STATUS_OFF:
+ *device_status = _XLINK_DEV_OFF;
+ break;
+ default:
+ *device_status = _XLINK_DEV_BUSY;
+ break;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_status);
+
+int xlink_pcie_boot_device(u32 sw_device_id, const char *binary_name)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_boot_device);
+
+int xlink_pcie_connect(u32 sw_device_id)
+{
+ return intel_xpcie_pci_connect_device(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_connect);
+
+int xlink_pcie_read(u32 sw_device_id, void *data, size_t *const size,
+ u32 timeout)
+{
+ if (!data || !size)
+ return -EINVAL;
+
+ return intel_xpcie_pci_read(sw_device_id, data, size, timeout);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_read);
+
+int xlink_pcie_write(u32 sw_device_id, void *data, size_t *const size,
+u32 timeout)
+{
+ if (!data || !size)
+ return -EINVAL;
+
+ return intel_xpcie_pci_write(sw_device_id, data, size, timeout);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_write);
+
+int xlink_pcie_reset_device(u32 sw_device_id)
+{
+ return intel_xpcie_pci_reset_device(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_reset_device);
diff --git a/drivers/misc/xlink-pcie/local_host/Makefile
b/drivers/misc/xlink-pcie/local_host/Makefile
index 65df94c7e860..16bb1e7345ac 100644
--- a/drivers/misc/xlink-pcie/local_host/Makefile
+++ b/drivers/misc/xlink-pcie/local_host/Makefile
@@ -3,3 +3,4 @@ mxlk_ep-objs := epf.o
mxlk_ep-objs += dma.o
mxlk_ep-objs += core.o
mxlk_ep-objs += ../common/util.o
+mxlk_ep-objs += ../common/interface.o
diff --git a/drivers/misc/xlink-pcie/remote_host/Makefile
b/drivers/misc/xlink-pcie/remote_host/Makefile
index e8074dbb1161..088e121ad46e 100644
--- a/drivers/misc/xlink-pcie/remote_host/Makefile
+++ b/drivers/misc/xlink-pcie/remote_host/Makefile
@@ -3,3 +3,4 @@ mxlk-objs := main.o
mxlk-objs += pci.o
mxlk-objs += core.o
mxlk-objs += ../common/util.o
+mxlk-objs += ../common/interface.o
--
2.17.1
[PATCH v4 20/34] xlink-core: Add xlink core driver xLink
From: Seamus Kelly Add xLink driver, which provides an abstracted control and communication subsystem based on channel identification. It is intended to support VPU technology both at SoC level as well as at IP level, over multiple interfaces. This initial patch enables local host user mode to open/close/read/write via IOCTLs. Specifically the driver enables application/process to: * Access a common xLink API across all interfaces from both kernel and user space. * Call typical APIs types (open, close, read, write) that you would associate with a communication interface. * Call other APIs that are related to other functions that the device can perform e.g. boot, reset get/set device mode. Device mode refers to the power load of the VPU and an API can be used to read and control it. * Use multiple commnication channels that the driver manages from one interface to another, providing routing of data through these multiple channels across a single physical interface. xLink: Add xLink Core device tree bindings Add device tree bindings for the xLink Core driver which enables xLink to control and communicate with the VPU IP present on the Intel Keem Bay SoC. Cc: Jonathan Corbet Cc: Derek Kiernan Cc: Dragan Cvetic Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Cc: linux-...@vger.kernel.org Reviewed-by: Mark Gross Signed-off-by: Mark Gross Signed-off-by: Seamus Kelly --- Documentation/vpu/index.rst | 1 + Documentation/vpu/xlink-core.rst| 81 +++ MAINTAINERS | 12 + drivers/misc/Kconfig| 1 + drivers/misc/Makefile | 1 + drivers/misc/xlink-core/Kconfig | 33 + drivers/misc/xlink-core/Makefile| 5 + drivers/misc/xlink-core/xlink-core.c| 738 drivers/misc/xlink-core/xlink-core.h| 22 + drivers/misc/xlink-core/xlink-defs.h| 175 + drivers/misc/xlink-core/xlink-ioctl.c | 212 ++ drivers/misc/xlink-core/xlink-ioctl.h | 21 + drivers/misc/xlink-core/xlink-multiplexer.c | 534 ++ drivers/misc/xlink-core/xlink-multiplexer.h | 35 + drivers/misc/xlink-core/xlink-platform.c| 160 + drivers/misc/xlink-core/xlink-platform.h| 65 ++ include/linux/xlink.h | 108 +++ include/uapi/misc/xlink_uapi.h | 145 18 files changed, 2349 insertions(+) create mode 100644 Documentation/vpu/xlink-core.rst create mode 100644 drivers/misc/xlink-core/Kconfig create mode 100644 drivers/misc/xlink-core/Makefile create mode 100644 drivers/misc/xlink-core/xlink-core.c create mode 100644 drivers/misc/xlink-core/xlink-core.h create mode 100644 drivers/misc/xlink-core/xlink-defs.h create mode 100644 drivers/misc/xlink-core/xlink-ioctl.c create mode 100644 drivers/misc/xlink-core/xlink-ioctl.h create mode 100644 drivers/misc/xlink-core/xlink-multiplexer.c create mode 100644 drivers/misc/xlink-core/xlink-multiplexer.h create mode 100644 drivers/misc/xlink-core/xlink-platform.c create mode 100644 drivers/misc/xlink-core/xlink-platform.h create mode 100644 include/linux/xlink.h create mode 100644 include/uapi/misc/xlink_uapi.h diff --git a/Documentation/vpu/index.rst b/Documentation/vpu/index.rst index 49c78bb65b83..cd4272e089ec 100644 --- a/Documentation/vpu/index.rst +++ b/Documentation/vpu/index.rst @@ -16,3 +16,4 @@ This documentation contains information for the Intel VPU stack. vpu-stack-overview xlink-pcie xlink-ipc + xlink-core diff --git a/Documentation/vpu/xlink-core.rst b/Documentation/vpu/xlink-core.rst new file mode 100644 index ..441c18230491 --- /dev/null +++ b/Documentation/vpu/xlink-core.rst @@ -0,0 +1,81 @@ +.. SPDX-License-Identifier: GPL-2.0 + += +xLink-core software subsystem += + +The purpose of the xLink software subsystem is to facilitate communication +between multiple users on multiple nodes in the system. + +There are three types of xLink nodes: + +1. Remote Host: this is an external IA/x86 host system that is only capable of + communicating directly to the Local Host node on VPU 2.x products. +2. Local Host: this is the ARM core within the VPU 2.x SoC. The Local Host can + communicate upstream to the Remote Host node, and downstream to the VPU IP + node. +3. VPU IP: this is the Leon RT core within the VPU 2.x SoC. The VPU IP can only + communicate upstream to the Local Host node. + +xLink provides a common API across all interfaces for users to access xLink +functions and provides user space APIs via an IOCTL interface implemented in +the xLink core. + +xLink manages communications from one interface to another and provides routing +of data through multiple channels across a single physical interface. + +It exposes a common API across all interfac
[PATCH v4 25/34] misc: Add Keem Bay VPU manager
From: "Li, Tingqian"
VPU IP on Keem Bay SOC is a vision acceleration IP complex
under the control of a RTOS-based firmware (running on RISC
MCU inside the VPU IP) serving user-space application
running on CPU side for HW accelerated computer vision tasks.
This module is kernel counterpart of the VPUAL(VPU abstraction
layer) which bridges firmware on VPU side and applications on
CPU user-space, it assists firmware on VPU side serving multiple
user space application processes on CPU side concurrently while
also performing necessary data buffer management on behave of
VPU IP.
objmgr provides basic infrastructure for create/destroy VPU side
software object concurrently on demand of user-space application
and also automatically release leaked objects during handling of
application termination. Note this module only cares about the
life-cycle of such objects, it's up to the application and firmware
to define the behavior/operations of each object.
objmgr does it's job by communicating with firmware through a fixed
reserved xlink channel, using a very simple message protocol.
smm provides DMABuf allocation/import facilities to allow user-space
app pass data to/from VPU in zero-copy fashion. it also provided a
convenient ioctl function for converting virtual pointer of a mem-mapped
and imported DMABuf into it's corresponding dma address, to allow
user-space app to specify the sub-regions of a bigger DMABuf to be
processed by VPU.
Signed-off-by: Li Tingqian
Signed-off-by: Zhou Luwei
Signed-off-by: Wang jue
Signed-off-by: Mark Gross
---
drivers/misc/Kconfig | 1 +
drivers/misc/Makefile| 1 +
drivers/misc/vpumgr/Kconfig | 9 +
drivers/misc/vpumgr/Makefile | 3 +
drivers/misc/vpumgr/vpu_common.h | 31 ++
drivers/misc/vpumgr/vpu_mgr.c| 370
drivers/misc/vpumgr/vpu_smm.c| 554 +
drivers/misc/vpumgr/vpu_smm.h| 30 ++
drivers/misc/vpumgr/vpu_vcm.c| 584 +++
drivers/misc/vpumgr/vpu_vcm.h| 84 +
include/uapi/misc/vpumgr.h | 64
11 files changed, 1731 insertions(+)
create mode 100644 drivers/misc/vpumgr/Kconfig
create mode 100644 drivers/misc/vpumgr/Makefile
create mode 100644 drivers/misc/vpumgr/vpu_common.h
create mode 100644 drivers/misc/vpumgr/vpu_mgr.c
create mode 100644 drivers/misc/vpumgr/vpu_smm.c
create mode 100644 drivers/misc/vpumgr/vpu_smm.h
create mode 100644 drivers/misc/vpumgr/vpu_vcm.c
create mode 100644 drivers/misc/vpumgr/vpu_vcm.h
create mode 100644 include/uapi/misc/vpumgr.h
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 09ae65e98681..2d1f7b165cc8 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -484,4 +484,5 @@ source "drivers/misc/uacce/Kconfig"
source "drivers/misc/xlink-pcie/Kconfig"
source "drivers/misc/xlink-ipc/Kconfig"
source "drivers/misc/xlink-core/Kconfig"
+source "drivers/misc/vpumgr/Kconfig"
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f3a6eb03bae9..2936930f3edc 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
obj-y += xlink-pcie/
obj-$(CONFIG_XLINK_IPC)+= xlink-ipc/
obj-$(CONFIG_XLINK_CORE) += xlink-core/
+obj-$(CONFIG_VPUMGR) += vpumgr/
diff --git a/drivers/misc/vpumgr/Kconfig b/drivers/misc/vpumgr/Kconfig
new file mode 100644
index ..bb82ff83afd3
--- /dev/null
+++ b/drivers/misc/vpumgr/Kconfig
@@ -0,0 +1,9 @@
+config VPUMGR
+ tristate "VPU Manager"
+ depends on ARM64 && XLINK_CORE
+ help
+ VPUMGR manages life-cycle of VPU related resources which were
+ dynamically allocated on demands of user-space application
+
+ Select y or m if you have a processor including the Intel
+ Vision Processor (VPU) on it.
diff --git a/drivers/misc/vpumgr/Makefile b/drivers/misc/vpumgr/Makefile
new file mode 100644
index ..51441dc8a930
--- /dev/null
+++ b/drivers/misc/vpumgr/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_VPUMGR) += vpumgr.o
+vpumgr-objs := vpu_mgr.o vpu_smm.o vpu_vcm.o
diff --git a/drivers/misc/vpumgr/vpu_common.h b/drivers/misc/vpumgr/vpu_common.h
new file mode 100644
index ..cd474ffc05f3
--- /dev/null
+++ b/drivers/misc/vpumgr/vpu_common.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ * VPUMGR Kernel module - common definition
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+#ifndef _VPU_COMMON_H
+#define _VPU_COMMON_H
+#include
+#include
+
+#include
+
+#include "vpu_vcm.h"
+
+/* there will be one such device for each HW instance */
+struct vpumgr_device {
+ struct device *sdev;
+ struct device *dev;
+ dev_t devnum;
+ struct cdev cdev;
+ struct platform_device *pdev;
+
+ struct vcm_dev vcm;
+ struct dentry *debugfs_root;
+
+ stru
[PATCH v4 00/34] Intel Vision Processing base enabling
From: Mark Gross The Intel Vision Processing Unit (VPU) is an IP block that is showing up for the first time as part of the Keem Bay SOC. Keem Bay is a quad core A53 Arm SOC. It is designed to be used as a stand alone SOC as well as in an PCIe Vision Processing accelerator add in card. This forth version of this patch set includes updates to the dt yaml files and some missed updates from feedback given on the V2 patch set for keembay-vpu-ipc and the Kconfig for intel_tsens At the bottom of this coverletter is the delta between v2 and V3 for easy review of the modifications. Feels like things are converging. :) Thanks for looking at these and providing feedback. --mark C, Udhayakumar (8): dt-bindings: misc: intel_tsens: Add tsens thermal bindings documentation misc: Tsens ARM host thermal driver. misc: Intel tsens IA host driver. Intel tsens i2c slave driver. misc:intel_tsens: Intel Keem Bay tsens driver. dt-bindings: misc: hddl_dev: Add hddl device management documentation misc: Hddl device management for local host misc: HDDL device management for IA host Daniele Alessandrelli (4): dt-bindings: mailbox: Add Intel VPU IPC mailbox bindings mailbox: vpu-ipc-mailbox: Add support for Intel VPU IPC mailbox dt-bindings: Add bindings for Keem Bay IPC driver keembay-ipc: Add Keem Bay IPC module Li, Tingqian (2): dt-bindings: misc: Add Keem Bay vpumgr misc: Add Keem Bay VPU manager Paul Murphy (2): dt-bindings: Add bindings for Keem Bay VPU IPC driver keembay-vpu-ipc: Add Keem Bay VPU IPC module Ramya P Karanth (1): Intel Keem Bay XLink SMBus driver Seamus Kelly (7): xlink-ipc: Add xlink ipc device tree bindings xlink-ipc: Add xlink ipc driver xlink-core: Add xlink core device tree bindings xlink-core: Add xlink core driver xLink xlink-core: Enable xlink protocol over pcie xlink-core: Enable VPU IP management and runtime control xlink-core: add async channel and events Srikanth Thokala (9): misc: xlink-pcie: Add documentation for XLink PCIe driver misc: xlink-pcie: lh: Add PCIe EPF driver for Local Host misc: xlink-pcie: lh: Add PCIe EP DMA functionality misc: xlink-pcie: lh: Add core communication logic misc: xlink-pcie: lh: Prepare changes for adding remote host driver misc: xlink-pcie: rh: Add PCIe EP driver for Remote Host misc: xlink-pcie: rh: Add core communication logic misc: xlink-pcie: Add XLink API interface misc: xlink-pcie: Add asynchronous event notification support for XLink mark gross (1): Add Vision Processing Unit (VPU) documentation. .../mailbox/intel,vpu-ipc-mailbox.yaml| 69 + .../bindings/misc/intel,hddl-client.yaml | 114 + .../bindings/misc/intel,intel-tsens.yaml | 118 + .../bindings/misc/intel,keembay-vpu-mgr.yaml | 48 + .../misc/intel,keembay-xlink-ipc.yaml | 51 + .../bindings/misc/intel,keembay-xlink.yaml| 29 + .../bindings/soc/intel/intel,keembay-ipc.yaml | 45 + .../soc/intel/intel,keembay-vpu-ipc.yaml | 143 ++ Documentation/hwmon/index.rst |2 + Documentation/hwmon/intel_tsens_host.rst | 71 + Documentation/hwmon/intel_tsens_sensor.rst| 67 + Documentation/i2c/busses/index.rst|1 + .../i2c/busses/intel-xlink-smbus.rst | 71 + Documentation/index.rst |1 + .../misc-devices/hddl_device_client.rst | 212 ++ .../misc-devices/hddl_device_server.rst | 205 ++ Documentation/misc-devices/index.rst |2 + Documentation/vpu/index.rst | 20 + Documentation/vpu/vpu-stack-overview.rst | 270 +++ Documentation/vpu/xlink-core.rst | 81 + Documentation/vpu/xlink-ipc.rst | 51 + Documentation/vpu/xlink-pcie.rst | 90 + MAINTAINERS | 54 + drivers/mailbox/Kconfig | 11 + drivers/mailbox/Makefile |2 + drivers/mailbox/vpu-ipc-mailbox.c | 297 +++ drivers/misc/Kconfig |7 + drivers/misc/Makefile |7 + drivers/misc/hddl_device/Kconfig | 26 + drivers/misc/hddl_device/Makefile |7 + drivers/misc/hddl_device/hddl_device.c| 565 + drivers/misc/hddl_device/hddl_device_lh.c | 764 +++ drivers/misc/hddl_device/hddl_device_rh.c | 837 +++ drivers/misc/hddl_device/hddl_device_util.h | 52 + drivers/misc/intel_tsens/Kconfig | 54 + drivers/misc/intel_tsens/Makefile | 10 + drivers/misc/intel_tsens/intel_tsens_host.c | 351 +++ drivers/misc/intel_tsens/intel_tsens_i2c.c| 119 + .../misc/intel_tsens/intel_tsens_thermal.c| 651 ++ .../misc/intel_tsens/intel_tsens_thermal.h| 38 + drivers/misc/intel_tsens/keembay_thermal.c| 169 ++ drivers/misc/intel_tsens/keembay_tsens.h | 366 +++ drivers/misc/vpumgr/Kconfig
[PATCH v3 03/34] mailbox: vpu-ipc-mailbox: Add support for Intel VPU IPC mailbox
From: Daniele Alessandrelli Add mailbox controller enabling inter-processor communication (IPC) between the CPU (aka, the Application Processor - AP) and the VPU on Intel Movidius SoCs like Keem Bay. The controller uses HW FIFOs to enable such communication. Specifically, there are two FIFOs, one for the CPU and one for VPU. Each FIFO can hold 128 entries (messages) of 32-bit each (but only 26 bits are actually usable, since the 6 least-significant bits are reserved). When the Linux kernel on the AP needs to send messages to the VPU firmware, it writes them to the VPU FIFO; similarly, when the VPU firmware needs to send messages to the AP, it writes them to the CPU FIFO. The AP is notified of pending messages in the CPU FIFO by means of the 'FIFO-not-empty' interrupt, which is generated by the CPU FIFO while not empty. This interrupt is cleared automatically once all messages have been read from the FIFO (i.e., the FIFO has been emptied). The hardware doesn't provide an TX done IRQ (i.e., an IRQ that allows the VPU firmware to notify the AP that the message put into the VPU FIFO has been received); however the AP can ensure that the message has been successfully put into the VPU FIFO (and therefore transmitted) by checking the VPU FIFO status register to ensure that writing the message didn't cause the FIFO to overflow. Therefore, the mailbox controller is configured as capable of tx_done IRQs and a tasklet is used to simulate the tx_done IRQ. The tasklet is activated by send_data() right after the message has been put into the VPU FIFO and the VPU FIFO status registers has been checked. If an overflow is reported by the status register, the tasklet passes -EBUSY to mbox_chan_txdone(), to notify the mailbox client of the failed TX. The client should therefore register a tx_done() callback to properly handle failed transmissions. Note: the 'txdone_poll' mechanism cannot be used because it doesn't provide a way to report a failed transmission. Signed-off-by: Daniele Alessandrelli --- MAINTAINERS | 1 + drivers/mailbox/Kconfig | 11 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/vpu-ipc-mailbox.c | 297 ++ 4 files changed, 311 insertions(+) create mode 100644 drivers/mailbox/vpu-ipc-mailbox.c diff --git a/MAINTAINERS b/MAINTAINERS index 2b82526a00dc..de23f6e5cfce 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9186,6 +9186,7 @@ M:Daniele Alessandrelli M: Mark Gross S: Supported F: Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml +F: drivers/mailbox/vpu-ipc-mailbox.c INTEL WIRELESS 3945ABG/BG, 4965AGN (iwlegacy) M: Stanislaw Gruszka diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index f4abe3529acd..cb50b541a5c6 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -29,6 +29,17 @@ config IMX_MBOX help Mailbox implementation for i.MX Messaging Unit (MU). +config INTEL_VPU_IPC_MBOX + tristate "Intel VPU IPC Mailbox" + depends on HAS_IOMEM + depends on OF || COMPILE_TEST + help + Mailbox implementation for enabling inter-processor communication + between application processors and Intel VPUs. + + Say Y or M here if you are building for an SoC equipped with an Intel + VPU. If M is selected, the module will be called vpu-ipc-mailbox. + config PLATFORM_MHU tristate "Platform MHU Mailbox" depends on OF diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 7194fa92c787..68768bb2ee43 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -56,3 +56,5 @@ obj-$(CONFIG_SUN6I_MSGBOX)+= sun6i-msgbox.o obj-$(CONFIG_SPRD_MBOX)+= sprd-mailbox.o obj-$(CONFIG_QCOM_IPCC)+= qcom-ipcc.o + +obj-$(CONFIG_INTEL_VPU_IPC_MBOX) += vpu-ipc-mailbox.o diff --git a/drivers/mailbox/vpu-ipc-mailbox.c b/drivers/mailbox/vpu-ipc-mailbox.c new file mode 100644 index ..ad161a7bbabb --- /dev/null +++ b/drivers/mailbox/vpu-ipc-mailbox.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel VPU IPC mailbox driver. + * + * Copyright (c) 2020-2021 Intel Corporation. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * The IPC FIFO registers (offsets to the base address defined in device tree). + */ + +/* + * TIM_IPC_FIFO - Write a 32-bit entry to FIFO. + * + * The entry to be put in the FIFO must be written to this register. + * + * NOTE: the 6 least-significant bits are reserved for the writing processor + * to include its processor ID, 0 <= x <= 62, so it can determine if the entry + * was written correctly by checking the appropriate bit of register + * TIM_IPC_FIFO_OF_FLAG[n]. + * + * Internally, the hardware increments FIFO write pointer and fill level. + * + */ +#define IPC_FIFO 0x00 + +/* The last 6 bits of an IPC
[PATCH v3 31/34] Intel Keem Bay XLink SMBus driver
From: Ramya P Karanth Adds XLink SMBus driver for Intel Keem Bay SoC. Xlink-smbus driver is a logical smbus adapter which uses Xlink (xlink-pcie) protocol as an interface. Keem Bay(s) vision accelerators are connected to the server via PCI interface. The Server needs to know the temperature of the Soc and the source to get the temperature can be either on board sensors or on chip sensors. The sensors are ideally connected over i2c bus of the Soc and the server does not have access to sensors present in the PCB. With this xlink-smbus interfaces, server access the on board/on chip sensors via xlink smbus adapter. Signed-off-by: Ramya P Karanth --- Documentation/i2c/busses/index.rst| 1 + .../i2c/busses/intel-xlink-smbus.rst | 71 +++ drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/xlink-smbus/Kconfig | 26 + drivers/misc/xlink-smbus/Makefile | 5 + drivers/misc/xlink-smbus/xlink-smbus.c| 467 ++ 7 files changed, 572 insertions(+) create mode 100644 Documentation/i2c/busses/intel-xlink-smbus.rst create mode 100644 drivers/misc/xlink-smbus/Kconfig create mode 100644 drivers/misc/xlink-smbus/Makefile create mode 100644 drivers/misc/xlink-smbus/xlink-smbus.c diff --git a/Documentation/i2c/busses/index.rst b/Documentation/i2c/busses/index.rst index 5e4077b08d86..6ce4a740f616 100644 --- a/Documentation/i2c/busses/index.rst +++ b/Documentation/i2c/busses/index.rst @@ -29,4 +29,5 @@ I2C Bus Drivers i2c-taos-evm i2c-viapro i2c-via + intel-xlink-smbus.rst scx200_acb diff --git a/Documentation/i2c/busses/intel-xlink-smbus.rst b/Documentation/i2c/busses/intel-xlink-smbus.rst new file mode 100644 index ..ab87d18051b4 --- /dev/null +++ b/Documentation/i2c/busses/intel-xlink-smbus.rst @@ -0,0 +1,71 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== +Kernel driver: xlink_smbus +== + +Supported chips: + * Intel Edge.AI Computer Vision platforms: Keem Bay + + Sufix: Bay + + Slave address: The address is selectable by device-tree. (TBD) + +Authors: +- Raja Subramanian, Lakshmi Bai +- Thalaiappan, Rathina +- Karanth, Ramya P + +Description +=== +The Intel Edge.AI Computer Vision platforms have to be monitored using platform +devices like sensors, fan controller, IO expander etc. Some of these devices +are memory mapped and some are i2c based. Either of these devices are not +directly accessible to the host. + +The host here refers to the server to which the vision accelerators are +connected over PCIe Interface. The Host needs to do a consolidated action based +on the parameters of platform devices. In general, most of the standard devices +(includes sensors, fan controller, IO expander etc) are I2C/SMBus based and are +used to provide the status of the accelerator. Standard drivers for these +devices are available based on i2c/smbus APIs. + +Instead of changing the sensor drivers to adapt to PCIe interface, a generic +i2c adapter "xlink-smbus" which underneath uses xlink as physical medium is +used. With xlink-smbus, the drivers for the platform devices doesn't need to +undergo any interface change. + +High-level architecture +=== + +Accessing Onchip devices:: + +--- --- +| Remote Host | | Local Host| +| IA CPU| | Vision platforms| +--- --- +| Onchip | |i2c slave| ==> Access the device +| sensor driver | |handler | ==> which is mmio based +--- --- +|Intel XLINK_SMBUS| |Intel XLINK_SMBUS| +| adpater | | adapter | +|(Master) | | (I2C_SLAVE) | +--- --- +| XLINK |<==> | XLINK | +---PCIE --- + +Accessing Onboard devices:: + +--- -- +| Remote Host | | Local Host | +| IA CPU| | Vision platforms | +--- -- +|On board | | i2c smbus | ==> Access the device +| sensor driver | | xfer [synopsys] | ==> which is on i2c bus +--- -- +|Intel XLINK_SMBUS| | Intel XLINK_SMBUS | +|
[PATCH v3 05/34] keembay-ipc: Add Keem Bay IPC module
From: Daniele Alessandrelli On the Intel Movidius SoC code named Keem Bay, communication between the Application Processor(AP) and the VPU is enabled by the Keem Bay Inter-Processor Communication (IPC) mechanism. Add the driver for using Keem Bay IPC from within the Linux Kernel. The IPC uses the following terminology: - Node:A processing entity that can use the IPC to communicate (currently, we just have two nodes, the AP and the VPU). - Link:Two nodes that can communicate over IPC form an IPC link (currently, we just have one link, the one formed by the AP and the VPU). - Channel: An IPC link can provide multiple IPC channels. IPC channels allow communication multiplexing, i.e., the same IPC link can be used by different applications for different communications. Each channel is identified by a channel ID, which must be unique within a single IPC link. Channels are divided in two categories, High-Speed (HS) channels and General-Purpose (GP) channels. HS channels have higher priority over GP channels. The Keem Bay IPC mechanism is built on top of the VPU IPC mailbox, which allows the AP and the VPU to exchange 32-bit messages. Specifically, the IPC uses shared memory (shared between the AP and the VPU) to allocate IPC packets and then exchanges them using the VPU IPC mailbox (the 32-bit physical address of the packet is passed as a message to the VPU IPC mailbox). IPC packets have a fixed structure containing the (VPU) physical address of the payload (which must be located in shared memory too) as well as other information (payload size, IPC channel ID, etc.). Each IPC node (i.e., both the AP and the VPU) has its own reserved memory region (in shared memory) from which it instantiates its own pool of IPC packets. When instantiated, IPC packets are marked as free. When the node needs to send an IPC message, it gets the first free packet it finds (from its own pool), marks it as allocated (used), and transfer its physical address to the destination node using the VPU IPC mailbox. The destination node uses the received physical address to access the IPC packet, process the packet, and, once done with it, marks it as free (so that the sender can reuse it). Cc: Paul Walmsley Cc: Palmer Dabbelt Cc: Borislav Petkov Cc: Damien Le Moal Cc: Peng Fan Cc: Shawn Guo Cc: Leonard Crestez Reviewed-by: Mark Gross Signed-off-by: Daniele Alessandrelli --- MAINTAINERS |8 + drivers/soc/Kconfig |1 + drivers/soc/Makefile |1 + drivers/soc/intel/Kconfig | 18 + drivers/soc/intel/Makefile|4 + drivers/soc/intel/keembay-ipc.c | 1364 + include/linux/soc/intel/keembay-ipc.h | 30 + 7 files changed, 1426 insertions(+) create mode 100644 drivers/soc/intel/Kconfig create mode 100644 drivers/soc/intel/Makefile create mode 100644 drivers/soc/intel/keembay-ipc.c create mode 100644 include/linux/soc/intel/keembay-ipc.h diff --git a/MAINTAINERS b/MAINTAINERS index de23f6e5cfce..684e64e958a4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9060,6 +9060,14 @@ F: drivers/crypto/keembay/keembay-ocs-aes-core.c F: drivers/crypto/keembay/ocs-aes.c F: drivers/crypto/keembay/ocs-aes.h +INTEL KEEM BAY IPC DRIVER +M: Daniele Alessandrelli +M: Mark Gross +S: Supported +F: Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml +F: drivers/soc/intel/keembay-ipc.c +F: include/linux/soc/intel/keembay-ipc.h + INTEL MANAGEMENT ENGINE (mei) M: Tomas Winkler L: linux-kernel@vger.kernel.org diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index d097d070f579..b9d69a1eedc7 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -8,6 +8,7 @@ source "drivers/soc/atmel/Kconfig" source "drivers/soc/bcm/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/imx/Kconfig" +source "drivers/soc/intel/Kconfig" source "drivers/soc/ixp4xx/Kconfig" source "drivers/soc/litex/Kconfig" source "drivers/soc/mediatek/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 699b758d28e4..1a6c00d2e32e 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_MACH_DOVE) += dove/ obj-y += fsl/ obj-$(CONFIG_ARCH_GEMINI) += gemini/ obj-y += imx/ +obj-y += intel/ obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/ diff --git a/drivers/soc/intel/Kconfig b/drivers/soc/intel/Kconfig new file mode 100644 index ..a575e31e47b4 --- /dev/null +++ b/drivers/soc/intel/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Keem Bay SoC drivers +# + +menu "Intel SoC drivers" + +confi
[PATCH v4 29/34] Intel tsens i2c slave driver.
From: "C, Udhayakumar"
Add Intel tsens i2c slave driver for Intel Edge.AI Computer Vision
platforms.
The tsens i2c slave driver enables reading of on chip sensors present
in the Intel Edge.AI Computer Vision platforms. In the tsens i2c module
various junction and SoC temperatures are reported using i2c slave
protocol.
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
drivers/misc/intel_tsens/Kconfig | 14 +++
drivers/misc/intel_tsens/Makefile | 1 +
drivers/misc/intel_tsens/intel_tsens_i2c.c | 119 +
3 files changed, 134 insertions(+)
create mode 100644 drivers/misc/intel_tsens/intel_tsens_i2c.c
diff --git a/drivers/misc/intel_tsens/Kconfig b/drivers/misc/intel_tsens/Kconfig
index 8b263fdd80c3..be8d27e81864 100644
--- a/drivers/misc/intel_tsens/Kconfig
+++ b/drivers/misc/intel_tsens/Kconfig
@@ -14,6 +14,20 @@ config INTEL_TSENS_LOCAL_HOST
Say Y if using a processor that includes the Intel VPU such as
Keem Bay. If unsure, say N.
+config INTEL_TSENS_I2C_SLAVE
+ bool "I2C slave driver for intel tsens"
+ depends on INTEL_TSENS_LOCAL_HOST
+ depends on I2C=y && I2C_SLAVE
+ help
+ This option enables tsens I2C slave driver.
+
+ This driver is used for reporting thermal data via I2C
+ SMBUS to remote host.
+ Enable this option if you want to have support for thermal
+ management controller.
+ Say Y if using a processor that includes the Intel VPU such as
+ Keem Bay. If unsure, say N.
+
config INTEL_TSENS_IA_HOST
tristate "Temperature sensor driver for intel tsens remote host"
depends on I2C && THERMAL
diff --git a/drivers/misc/intel_tsens/Makefile
b/drivers/misc/intel_tsens/Makefile
index 250dc484fb49..f6f41bbca80c 100644
--- a/drivers/misc/intel_tsens/Makefile
+++ b/drivers/misc/intel_tsens/Makefile
@@ -5,4 +5,5 @@
#
obj-$(CONFIG_INTEL_TSENS_LOCAL_HOST) += intel_tsens_thermal.o
+obj-$(CONFIG_INTEL_TSENS_I2C_SLAVE)+= intel_tsens_i2c.o
obj-$(CONFIG_INTEL_TSENS_IA_HOST) += intel_tsens_host.o
diff --git a/drivers/misc/intel_tsens/intel_tsens_i2c.c
b/drivers/misc/intel_tsens/intel_tsens_i2c.c
new file mode 100644
index ..520c3f4bf392
--- /dev/null
+++ b/drivers/misc/intel_tsens/intel_tsens_i2c.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *
+ * Intel tsens I2C thermal Driver
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include "intel_tsens_thermal.h"
+
+#define TSENS_BYTE_INDEX_SHIFT 0x6
+#define TSENS_BYTE_INDEX_MASK 0x3
+#define TSENS_SENSOR_TYPE_MASK 0x3F
+
+struct intel_tsens_i2c {
+ int sensor_type;
+ u16 buffer_idx;
+ bool read_only;
+ u8 idx_write_cnt;
+ struct intel_tsens_i2c_plat_data *plat_data;
+};
+
+static int intel_i2c_tsens_slave_cb(struct i2c_client *client,
+ enum i2c_slave_event event, u8 *val)
+{
+ struct intel_tsens_i2c *tsens_i2c = i2c_get_clientdata(client);
+ struct intel_tsens_i2c_plat_data *plat_data = tsens_i2c->plat_data;
+ int ret = 0;
+
+ switch (event) {
+ case I2C_SLAVE_WRITE_RECEIVED:
+ tsens_i2c->sensor_type = *val;
+ break;
+
+ case I2C_SLAVE_READ_PROCESSED:
+ case I2C_SLAVE_READ_REQUESTED:
+ if (plat_data->get_temp) {
+ int temp;
+ int sensor_type = tsens_i2c->sensor_type &
+ TSENS_SENSOR_TYPE_MASK;
+
+ if (!plat_data->get_temp(sensor_type, &temp,
+plat_data->pdata)) {
+ u8 offset = (tsens_i2c->sensor_type >>
+ TSENS_BYTE_INDEX_SHIFT) &
+ TSENS_BYTE_INDEX_MASK;
+ u8 *ptr_temp = (u8 *)&temp;
+
+ *val = ptr_temp[offset];
+ tsens_i2c->buffer_idx++;
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+ } else {
+ ret = -EINVAL;
+ }
+ break;
+
+ case I2C_SLAVE_STOP:
+ case I2C_SLAVE_WRITE_REQUESTED:
+ tsens_i2c->idx_write_cnt = 0;
+ tsens_i2c->buffer_idx = 0;
+ break;
+
+ default:
+ break;
+ }
+ return ret;
+}
+
+static int intel_i2c_tsens_slave_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{ struct intel_tsens_i2c *priv;
+ int ret;
+
+ if (!id->driver_data) {
+ dev_err(&client->dev, "No platform data");
+ return -EINVAL;
+ }
+ priv = devm
[PATCH v3 32/34] dt-bindings: misc: hddl_dev: Add hddl device management documentation
From: "C, Udhayakumar"
Add hddl device management documentation
The HDDL client driver acts as an software RTC to sync with network time.
It abstracts xlink protocol to communicate with remote IA host.
This driver exports the details about sensors available in the platform
to remote IA host as xlink packets.
This driver also handles device connect/disconnect events and identifies
board id and soc id using gpio's based on platform configuration.
Signed-off-by: C, Udhayakumar
---
.../bindings/misc/intel,hddl-client.yaml | 114 ++
1 file changed, 114 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/intel,hddl-client.yaml
diff --git a/Documentation/devicetree/bindings/misc/intel,hddl-client.yaml
b/Documentation/devicetree/bindings/misc/intel,hddl-client.yaml
new file mode 100644
index ..c1d121c35fc5
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,hddl-client.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/intel,hddl-client.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel hddl client device to handle platform management in Bay series
+
+maintainers:
+ - Udhayakumar C
+
+description: |
+ The HDDL client driver acts as an software RTC to sync with network time.
+ It abstracts xlink protocol to communicate with remote host. This driver
+ exports the details about sensors available in the platform to remote
+ host as xlink packets.
+ This driver also handles device connect/disconnect events and identifies
+ board id and soc id using gpio's based on platform configuration.
+
+select: false
+
+properties:
+ compatible:
+items:
+ - const: intel,hddl-client
+
+ reg:
+minItems: 4
+maxItems: 4
+
+ xlink_chan:
+minItems: 1
+maxItems: 1
+description: xlink channel number used for communication
+ with remote host for time sync and sharing sensor
+ details available in platform.
+
+ i2c_xlink_chan:
+minItems: 1
+maxItems: 1
+description: xlink channel number used for communication
+ with remote host for xlink i2c smbus.
+
+ sensor_name:
+type: object
+description:
+ Details about sensors and its configuration on local host and remote
+ host.
+
+properties:
+ compatible:
+items:
+ - const: intel_tsens
+
+ reg:
+description: i2c slave address for sensor.
+
+ local-host:
+minItems: 1
+maxItems: 1
+description: enable bit 0 to register sensor as i2c slave
+ in local host (normal i2c client)
+ enable bit 1 to mimic sensor as i2c slave
+ in local host (onchip sensors as i2c slave)
+ enable bit 2 to register i2c slave as xlink smbus slave
+ in local host.
+ remote-host:
+minItems: 1
+maxItems: 1
+description: enable bit 0 to register sensor as i2c slave
+ in remote host (normal i2c client)
+ enable bit 1 to mimic sensor as i2c slave
+ in remote host (onchip sensors as i2c slave)
+ enable bit 2 to register i2c slave as xlink smbus slave
+ in remote host.
+
+ bus:
+minItems: 1
+maxItems: 1
+description: i2c bus number for the i2c client device.
+
+required:
+ - compatible
+ - reg
+ - local-host
+ - remote-host
+ - bus
+
+required:
+ - compatible
+ - reg
+ - xlink_chan
+ - i2c_xlink_chan
+
+additionalProperties: false
+
+examples:
+ - |
+hddl_dev: hddl@2032 {
+ compatible = "intel,hddl-client";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+ reg = <0x0 0x2032 0x0 0x800>;
+ xlink_chan = <1080>;
+ i2c_xlink_chan = <1081>;
+ kmb_xlink_tj {
+ status = "okay";
+ compatible = "intel_tsens";
+ local-host = <0x3>;
+ remote-host = <0x3>;
+ bus = <0x1>;
+ };
+};
--
2.17.1
[PATCH v3 29/34] Intel tsens i2c slave driver.
From: "C, Udhayakumar"
Add Intel tsens i2c slave driver for Intel Edge.AI Computer Vision
platforms.
The tsens i2c slave driver enables reading of on chip sensors present
in the Intel Edge.AI Computer Vision platforms. In the tsens i2c module
various junction and SoC temperatures are reported using i2c slave
protocol.
Signed-off-by: C, Udhayakumar
---
drivers/misc/intel_tsens/Kconfig | 15 +++
drivers/misc/intel_tsens/Makefile | 1 +
drivers/misc/intel_tsens/intel_tsens_i2c.c | 119 +
3 files changed, 135 insertions(+)
create mode 100644 drivers/misc/intel_tsens/intel_tsens_i2c.c
diff --git a/drivers/misc/intel_tsens/Kconfig b/drivers/misc/intel_tsens/Kconfig
index 8b263fdd80c3..9b2198ab28c3 100644
--- a/drivers/misc/intel_tsens/Kconfig
+++ b/drivers/misc/intel_tsens/Kconfig
@@ -14,6 +14,21 @@ config INTEL_TSENS_LOCAL_HOST
Say Y if using a processor that includes the Intel VPU such as
Keem Bay. If unsure, say N.
+config INTEL_TSENS_I2C_SLAVE
+ bool "I2C slave driver for intel tsens"
+ depends on INTEL_TSENS_LOCAL_HOST
+ select I2C
+ select I2C_SLAVE
+ help
+ This option enables tsens I2C slave driver.
+
+ This driver is used for reporting thermal data via I2C
+ SMBUS to remote host.
+ Enable this option if you want to have support for thermal
+ management controller.
+ Say Y if using a processor that includes the Intel VPU such as
+ Keem Bay. If unsure, say N.
+
config INTEL_TSENS_IA_HOST
tristate "Temperature sensor driver for intel tsens remote host"
depends on I2C && THERMAL
diff --git a/drivers/misc/intel_tsens/Makefile
b/drivers/misc/intel_tsens/Makefile
index 250dc484fb49..f6f41bbca80c 100644
--- a/drivers/misc/intel_tsens/Makefile
+++ b/drivers/misc/intel_tsens/Makefile
@@ -5,4 +5,5 @@
#
obj-$(CONFIG_INTEL_TSENS_LOCAL_HOST) += intel_tsens_thermal.o
+obj-$(CONFIG_INTEL_TSENS_I2C_SLAVE)+= intel_tsens_i2c.o
obj-$(CONFIG_INTEL_TSENS_IA_HOST) += intel_tsens_host.o
diff --git a/drivers/misc/intel_tsens/intel_tsens_i2c.c
b/drivers/misc/intel_tsens/intel_tsens_i2c.c
new file mode 100644
index ..520c3f4bf392
--- /dev/null
+++ b/drivers/misc/intel_tsens/intel_tsens_i2c.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *
+ * Intel tsens I2C thermal Driver
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include "intel_tsens_thermal.h"
+
+#define TSENS_BYTE_INDEX_SHIFT 0x6
+#define TSENS_BYTE_INDEX_MASK 0x3
+#define TSENS_SENSOR_TYPE_MASK 0x3F
+
+struct intel_tsens_i2c {
+ int sensor_type;
+ u16 buffer_idx;
+ bool read_only;
+ u8 idx_write_cnt;
+ struct intel_tsens_i2c_plat_data *plat_data;
+};
+
+static int intel_i2c_tsens_slave_cb(struct i2c_client *client,
+ enum i2c_slave_event event, u8 *val)
+{
+ struct intel_tsens_i2c *tsens_i2c = i2c_get_clientdata(client);
+ struct intel_tsens_i2c_plat_data *plat_data = tsens_i2c->plat_data;
+ int ret = 0;
+
+ switch (event) {
+ case I2C_SLAVE_WRITE_RECEIVED:
+ tsens_i2c->sensor_type = *val;
+ break;
+
+ case I2C_SLAVE_READ_PROCESSED:
+ case I2C_SLAVE_READ_REQUESTED:
+ if (plat_data->get_temp) {
+ int temp;
+ int sensor_type = tsens_i2c->sensor_type &
+ TSENS_SENSOR_TYPE_MASK;
+
+ if (!plat_data->get_temp(sensor_type, &temp,
+plat_data->pdata)) {
+ u8 offset = (tsens_i2c->sensor_type >>
+ TSENS_BYTE_INDEX_SHIFT) &
+ TSENS_BYTE_INDEX_MASK;
+ u8 *ptr_temp = (u8 *)&temp;
+
+ *val = ptr_temp[offset];
+ tsens_i2c->buffer_idx++;
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+ } else {
+ ret = -EINVAL;
+ }
+ break;
+
+ case I2C_SLAVE_STOP:
+ case I2C_SLAVE_WRITE_REQUESTED:
+ tsens_i2c->idx_write_cnt = 0;
+ tsens_i2c->buffer_idx = 0;
+ break;
+
+ default:
+ break;
+ }
+ return ret;
+}
+
+static int intel_i2c_tsens_slave_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{ struct intel_tsens_i2c *priv;
+ int ret;
+
+ if (!id->driver_data) {
+ dev_err(&client->dev, "No platform data");
+ return -EINVAL;
+ }
+ priv = devm_kzalloc(&client->de
[PATCH v3 13/34] misc: xlink-pcie: rh: Add PCIe EP driver for Remote Host
From: Srikanth Thokala
Add PCIe Endpoint driver that configures PCIe BARs and MSIs on the
Remote Host
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
MAINTAINERS | 2 +-
drivers/misc/xlink-pcie/Kconfig | 11 +
drivers/misc/xlink-pcie/Makefile | 1 +
drivers/misc/xlink-pcie/common/xpcie.h | 1 +
drivers/misc/xlink-pcie/remote_host/Makefile | 3 +
drivers/misc/xlink-pcie/remote_host/main.c | 90
drivers/misc/xlink-pcie/remote_host/pci.c| 449 +++
drivers/misc/xlink-pcie/remote_host/pci.h| 62 +++
8 files changed, 618 insertions(+), 1 deletion(-)
create mode 100644 drivers/misc/xlink-pcie/remote_host/Makefile
create mode 100644 drivers/misc/xlink-pcie/remote_host/main.c
create mode 100644 drivers/misc/xlink-pcie/remote_host/pci.c
create mode 100644 drivers/misc/xlink-pcie/remote_host/pci.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3ca6c8c6341b..e05fa34d72ce 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1961,7 +1961,7 @@ F:
Documentation/devicetree/bindings/arm/intel,keembay.yaml
F: arch/arm64/boot/dts/intel/keembay-evm.dts
F: arch/arm64/boot/dts/intel/keembay-soc.dtsi
-ARM KEEM BAY XLINK PCIE SUPPORT
+ARM/INTEL KEEM BAY XLINK PCIE SUPPORT
M: Srikanth Thokala
M: Mark Gross
S: Supported
diff --git a/drivers/misc/xlink-pcie/Kconfig b/drivers/misc/xlink-pcie/Kconfig
index 46aa401d79b7..448b9bfbdfa2 100644
--- a/drivers/misc/xlink-pcie/Kconfig
+++ b/drivers/misc/xlink-pcie/Kconfig
@@ -1,3 +1,14 @@
+config XLINK_PCIE_RH_DRIVER
+ tristate "XLink PCIe Remote Host driver"
+ depends on PCI && X86_64
+ help
+ This option enables XLink PCIe Remote Host driver.
+
+ Choose M here to compile this driver as a module, name is mxlk.
+ This driver is used for XLink communication over PCIe,
+ and is to be loaded on the IA host which is connected to
+ the Intel Keem Bay.
+
config XLINK_PCIE_LH_DRIVER
tristate "XLink PCIe Local Host driver"
depends on PCI_ENDPOINT && ARCH_KEEMBAY
diff --git a/drivers/misc/xlink-pcie/Makefile b/drivers/misc/xlink-pcie/Makefile
index d693d382e9c6..1dd984d8d88c 100644
--- a/drivers/misc/xlink-pcie/Makefile
+++ b/drivers/misc/xlink-pcie/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_XLINK_PCIE_RH_DRIVER) += remote_host/
obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += local_host/
diff --git a/drivers/misc/xlink-pcie/common/xpcie.h
b/drivers/misc/xlink-pcie/common/xpcie.h
index 48529eb49be0..b5cf9242a59a 100644
--- a/drivers/misc/xlink-pcie/common/xpcie.h
+++ b/drivers/misc/xlink-pcie/common/xpcie.h
@@ -69,6 +69,7 @@ struct xpcie_mmio {
struct xpcie {
u32 status;
bool legacy_a0;
+ void *bar0;
void *mmio;
void *bar4;
diff --git a/drivers/misc/xlink-pcie/remote_host/Makefile
b/drivers/misc/xlink-pcie/remote_host/Makefile
new file mode 100644
index ..96374a43023e
--- /dev/null
+++ b/drivers/misc/xlink-pcie/remote_host/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_XLINK_PCIE_RH_DRIVER) += mxlk.o
+mxlk-objs := main.o
+mxlk-objs += pci.o
diff --git a/drivers/misc/xlink-pcie/remote_host/main.c
b/drivers/misc/xlink-pcie/remote_host/main.c
new file mode 100644
index ..ed1a431ed5d4
--- /dev/null
+++ b/drivers/misc/xlink-pcie/remote_host/main.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include "pci.h"
+#include "../common/core.h"
+
+#define HW_ID_LO_MASK GENMASK(7, 0)
+#define HW_ID_HI_MASK GENMASK(15, 8)
+
+static const struct pci_device_id xpcie_pci_table[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KEEMBAY), 0 },
+ { 0 }
+};
+
+static int intel_xpcie_probe(struct pci_dev *pdev,
+const struct pci_device_id *ent)
+{
+ bool new_device = false;
+ struct xpcie_dev *xdev;
+ u32 sw_devid;
+ u16 hw_id;
+ int ret;
+
+ hw_id = FIELD_PREP(HW_ID_HI_MASK, pdev->bus->number) |
+ FIELD_PREP(HW_ID_LO_MASK, PCI_SLOT(pdev->devfn));
+
+ sw_devid = FIELD_PREP(XLINK_DEV_INF_TYPE_MASK,
+ XLINK_DEV_INF_PCIE) |
+ FIELD_PREP(XLINK_DEV_PHYS_ID_MASK, hw_id) |
+ FIELD_PREP(XLINK_DEV_TYPE_MASK, XLINK_DEV_TYPE_KMB) |
+ FIELD_PREP(XLINK_DEV_PCIE_ID_MASK, XLINK_DEV_PCIE_0) |
+ FIELD_PREP(XLINK_DEV_FUNC_MASK, XLINK_DEV_FUNC_VPU);
+
+ xdev = intel_xpcie_get_device_by_id(sw_devid);
+ if (!xdev) {
+ xdev = intel_xpcie_create_device(sw_devid, pdev);
+ if (!xdev)
+ return -ENOMEM;
+
+ new_device = true;
+ }
+
+ ret = intel_xpcie_pci_init(xdev, pdev);
+ if (ret) {
+ intel_xpcie_remove_device(xdev);
+
[PATCH v4 17/34] xlink-ipc: Add xlink ipc device tree bindings
From: Seamus Kelly
Add device tree bindings for the xLink IPC driver which enables xLink to
control and communicate with the VPU IP present on the Intel Keem Bay
SoC.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Seamus Kelly
---
.../misc/intel,keembay-xlink-ipc.yaml | 51 +++
1 file changed, 51 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/intel,keembay-xlink-ipc.yaml
diff --git
a/Documentation/devicetree/bindings/misc/intel,keembay-xlink-ipc.yaml
b/Documentation/devicetree/bindings/misc/intel,keembay-xlink-ipc.yaml
new file mode 100644
index ..70a3061d024d
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,keembay-xlink-ipc.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) Intel Corporation. All rights reserved.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/intel,keembay-xlink-ipc.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel Keem Bay xlink IPC
+
+maintainers:
+ - Kelly Seamus
+
+description: |
+ The Keem Bay xlink IPC driver enables the communication/control sub-system
+ for internal IPC communications within the Intel Keem Bay SoC.
+
+properties:
+ compatible:
+oneOf:
+ - items:
+ - const: intel,keembay-xlink-ipc
+
+ memory-region:
+items:
+ - description: reference to the CSS xlink IPC reserved memory region.
+ - description: reference to the MSS xlink IPC reserved memory region.
+
+ intel,keembay-vpu-ipc-id:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description: The numeric ID identifying the VPU within the xLink stack.
+
+ intel,keembay-vpu-ipc-name:
+$ref: "/schemas/types.yaml#/definitions/string"
+description: User-friendly name for the VPU within the xLink stack.
+
+ intel,keembay-vpu-ipc:
+$ref: "/schemas/types.yaml#/definitions/phandle"
+description: reference to the corresponding intel,keembay-vpu-ipc node.
+
+additionalProperties: False
+
+examples:
+ - |
+xlink-ipc {
+compatible = "intel,keembay-xlink-ipc";
+memory-region = <&css_xlink_reserved>,
+<&mss_xlink_reserved>;
+intel,keembay-vpu-ipc-id = <0x0>;
+intel,keembay-vpu-ipc-name = "vpu-slice-0";
+intel,keembay-vpu-ipc = <&vpuipc>;
+};
--
2.17.1
[PATCH v3 21/34] xlink-core: Enable xlink protocol over pcie
From: Seamus Kelly
Enable host system access to the VPU over the xlink protocol over PCIe by
enabling channel multiplexing and dispatching. This allows for remote host
communication channels across pcie links.
add dispatcher
update multiplexer to utilise dispatcher
xlink-core: Patch set 2
Add xlink-dispatcher
creates tx and rx threads
enables queueing of messages for transmission and on reception
Update multiplexer to utilise dispatcher:
handle multiplexing channels over single interface link e.g.
PCIe
process messages received by dispatcher
pass messages created by API calls to dispatcher for
transmission
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Seamus Kelly
---
drivers/misc/xlink-core/Makefile| 2 +-
drivers/misc/xlink-core/xlink-core.c| 35 +-
drivers/misc/xlink-core/xlink-dispatcher.c | 441 +
drivers/misc/xlink-core/xlink-dispatcher.h | 26 +
drivers/misc/xlink-core/xlink-multiplexer.c | 498 +++-
5 files changed, 999 insertions(+), 3 deletions(-)
create mode 100644 drivers/misc/xlink-core/xlink-dispatcher.c
create mode 100644 drivers/misc/xlink-core/xlink-dispatcher.h
diff --git a/drivers/misc/xlink-core/Makefile b/drivers/misc/xlink-core/Makefile
index e82b7c72b6b9..ee81f9d05f2b 100644
--- a/drivers/misc/xlink-core/Makefile
+++ b/drivers/misc/xlink-core/Makefile
@@ -2,4 +2,4 @@
# Makefile for Keem Bay xlink Linux driver
#
obj-$(CONFIG_XLINK_CORE) += xlink.o
-xlink-objs += xlink-core.o xlink-multiplexer.o xlink-platform.o xlink-ioctl.o
+xlink-objs += xlink-core.o xlink-multiplexer.o xlink-dispatcher.o
xlink-platform.o xlink-ioctl.o
diff --git a/drivers/misc/xlink-core/xlink-core.c
b/drivers/misc/xlink-core/xlink-core.c
index dd8db834c184..bdbf8c6a99ca 100644
--- a/drivers/misc/xlink-core/xlink-core.c
+++ b/drivers/misc/xlink-core/xlink-core.c
@@ -21,6 +21,7 @@
#include "xlink-core.h"
#include "xlink-defs.h"
+#include "xlink-dispatcher.h"
#include "xlink-ioctl.h"
#include "xlink-multiplexer.h"
#include "xlink-platform.h"
@@ -151,6 +152,12 @@ static int kmb_xlink_probe(struct platform_device *pdev)
goto r_multiplexer;
}
+ // initialize dispatcher
+ rc = xlink_dispatcher_init(xlink_dev->pdev);
+ if (rc != X_LINK_SUCCESS) {
+ pr_err("Dispatcher initialization failed\n");
+ goto r_dispatcher;
+ }
// initialize xlink data structure
xlink_dev->nmb_connected_links = 0;
mutex_init(&xlink_dev->lock);
@@ -168,7 +175,7 @@ static int kmb_xlink_probe(struct platform_device *pdev)
/*Allocating Major number*/
if ((alloc_chrdev_region(&xdev, 0, 1, "xlinkdev")) < 0) {
dev_info(&pdev->dev, "Cannot allocate major number\n");
- goto r_multiplexer;
+ goto r_dispatcher;
}
dev_info(&pdev->dev, "Major = %d Minor = %d\n", MAJOR(xdev),
MINOR(xdev));
@@ -205,6 +212,8 @@ static int kmb_xlink_probe(struct platform_device *pdev)
class_destroy(dev_class);
r_class:
unregister_chrdev_region(xdev, 1);
+r_dispatcher:
+ xlink_dispatcher_destroy();
r_multiplexer:
xlink_multiplexer_destroy();
return -1;
@@ -220,6 +229,10 @@ static int kmb_xlink_remove(struct platform_device *pdev)
rc = xlink_multiplexer_destroy();
if (rc != X_LINK_SUCCESS)
pr_err("Multiplexer destroy failed\n");
+ // stop dispatchers and destroy
+ rc = xlink_dispatcher_destroy();
+ if (rc != X_LINK_SUCCESS)
+ pr_err("Dispatcher destroy failed\n");
mutex_unlock(&xlink->lock);
mutex_destroy(&xlink->lock);
@@ -314,6 +327,14 @@ enum xlink_error xlink_connect(struct xlink_handle *handle)
link->handle = *handle;
xlink->nmb_connected_links++;
kref_init(&link->refcount);
+ if (interface != IPC_INTERFACE) {
+ // start dispatcher
+ rc = xlink_dispatcher_start(link->id, &link->handle);
+ if (rc) {
+ pr_err("dispatcher start failed\n");
+ goto r_cleanup;
+ }
+ }
// initialize multiplexer connection
rc = xlink_multiplexer_connect(link->id);
if (rc) {
@@ -649,6 +670,7 @@ EXPORT_SYMBOL_GPL(xlink_release_data);
enum xlink_error xlink_disconnect(struct xlink_handle *handle)
{
struct xlink_link *link;
+ int interface = NULL_INTERFACE;
enum xlink_error rc = X_LINK_ERROR;
if (!xlink || !handle)
@@ -661,6 +683,17 @@ enum xlink_error xlink_disconnect(struct xlink_handle
*handle)
// decrement refcount, if count is 0 lock mutex and disconne
[PATCH v3 07/34] keembay-vpu-ipc: Add Keem Bay VPU IPC module
From: Paul Murphy Intel Keem Bay SoC contains a Vision Processing Unit (VPU) to enable machine vision and other applications. Enable Linux to control the VPU processor and provides an interface to the Keem Bay IPC for communicating with the VPU firmware. Specifically the driver provides the following functionality to other kernel components: - Starting (including loading the VPU firmware) / Stopping / Rebooting the VPU. - Getting notifications of VPU events (e.g., WDT events). - Communicating with the VPU via the Keem Bay IPC mechanism. In addition to the above, the driver also exposes SoC information (like stepping, device ID, etc.) to user-space via sysfs. Specifically, the following sysfs files are provided: - /sys/firmware/keembay-vpu-ipc/device_id - /sys/firmware/keembay-vpu-ipc/feature_exclusion - /sys/firmware/keembay-vpu-ipc/hardware_id - /sys/firmware/keembay-vpu-ipc/sku - /sys/firmware/keembay-vpu-ipc/stepping Reviewed-by: Mark Gross Signed-off-by: Paul Murphy Co-developed-by: Daniele Alessandrelli Signed-off-by: Daniele Alessandrelli Signed-off-by: Mark Gross --- MAINTAINERS |9 + drivers/soc/intel/Kconfig | 15 + drivers/soc/intel/Makefile|3 +- drivers/soc/intel/keembay-vpu-ipc.c | 2036 + include/linux/soc/intel/keembay-vpu-ipc.h | 62 + 5 files changed, 2124 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/intel/keembay-vpu-ipc.c create mode 100644 include/linux/soc/intel/keembay-vpu-ipc.h diff --git a/MAINTAINERS b/MAINTAINERS index 684e64e958a4..6742a1827cd9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9068,6 +9068,15 @@ F: Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml F: drivers/soc/intel/keembay-ipc.c F: include/linux/soc/intel/keembay-ipc.h +INTEL KEEM BAY VPU IPC DRIVER +M: Paul J Murphy +M: Daniele Alessandrelli +M: Mark Gross +S: Supported +F: Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml +F: drivers/soc/intel/keembay-vpu-ipc.c +F: include/linux/soc/intel/keembay-vpu-ipc.h + INTEL MANAGEMENT ENGINE (mei) M: Tomas Winkler L: linux-kernel@vger.kernel.org diff --git a/drivers/soc/intel/Kconfig b/drivers/soc/intel/Kconfig index a575e31e47b4..ebd23ea57d04 100644 --- a/drivers/soc/intel/Kconfig +++ b/drivers/soc/intel/Kconfig @@ -15,4 +15,19 @@ config KEEMBAY_IPC Select this if you are compiling the Kernel for an Intel SoC that includes the Intel Vision Processing Unit (VPU) such as Keem Bay. + +config KEEMBAY_VPU_IPC + tristate "Intel Keem Bay VPU IPC Driver" + depends on KEEMBAY_IPC + depends on HAVE_ARM_SMCCC + help + This option enables support for loading and communicating with + the firmware on the Vision Processing Unit (VPU) of the Keem Bay + SoC. The driver depends on the Keem Bay IPC driver to do + communication, and it depends on secure world monitor software to + do the control of the VPU state. + + Select this if you are compiling the Kernel for an Intel SoC that + includes the Intel Vision Processing Unit (VPU) such as Keem Bay. + endmenu diff --git a/drivers/soc/intel/Makefile b/drivers/soc/intel/Makefile index ecf0246e7822..363a81848843 100644 --- a/drivers/soc/intel/Makefile +++ b/drivers/soc/intel/Makefile @@ -1,4 +1,5 @@ # # Makefile for Keem Bay IPC Linux driver # -obj-$(CONFIG_KEEMBAY_IPC) += keembay-ipc.o +obj-$(CONFIG_KEEMBAY_IPC) += keembay-ipc.o +obj-$(CONFIG_KEEMBAY_VPU_IPC) += keembay-vpu-ipc.o diff --git a/drivers/soc/intel/keembay-vpu-ipc.c b/drivers/soc/intel/keembay-vpu-ipc.c new file mode 100644 index ..31b880195cac --- /dev/null +++ b/drivers/soc/intel/keembay-vpu-ipc.c @@ -0,0 +1,2036 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Keem Bay VPU IPC Driver. + * + * Copyright (c) 2018-2020 Intel Corporation. + * + * The purpose of this driver is to facilitate booting, control and + * communication with the VPU IP on the Keem Bay SoC. + * + * Specifically the driver provides the following functionality to other kernel + * components: + * - Loading the VPU firmware into DDR for the VPU to execute. + * - Starting / Stopping / Rebooting the VPU. + * - Getting notifications of VPU events (e.g., WDT events). + * - Communicating with the VPU using the Keem Bay IPC mechanism. + * + * In addition to the above, the driver also exposes SoC information (like + * stepping, device ID, etc.) to user-space via sysfs. + * + * + * VPU Firmware loading + * + * + * The VPU Firmware consists of both the RTOS and the application code meant to + * be run by the VPU. + * + * The VPU Firmware is loaded into DDR using the Linux Firmware API. The + * firmware is loaded into a specific reserved memory region in DDR and + * executed by the VPU directly from there. + * + * The VPU Firmware binary is expe
[PATCH v4 32/34] dt-bindings: misc: hddl_dev: Add hddl device management documentation
From: "C, Udhayakumar"
Add hddl device management documentation
The HDDL client driver acts as an software RTC to sync with network time.
It abstracts xlink protocol to communicate with remote IA host.
This driver exports the details about sensors available in the platform
to remote IA host as xlink packets.
This driver also handles device connect/disconnect events and identifies
board id and soc id using gpio's based on platform configuration.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
.../bindings/misc/intel,hddl-client.yaml | 114 ++
1 file changed, 114 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/intel,hddl-client.yaml
diff --git a/Documentation/devicetree/bindings/misc/intel,hddl-client.yaml
b/Documentation/devicetree/bindings/misc/intel,hddl-client.yaml
new file mode 100644
index ..c1d121c35fc5
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,hddl-client.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/intel,hddl-client.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel hddl client device to handle platform management in Bay series
+
+maintainers:
+ - Udhayakumar C
+
+description: |
+ The HDDL client driver acts as an software RTC to sync with network time.
+ It abstracts xlink protocol to communicate with remote host. This driver
+ exports the details about sensors available in the platform to remote
+ host as xlink packets.
+ This driver also handles device connect/disconnect events and identifies
+ board id and soc id using gpio's based on platform configuration.
+
+select: false
+
+properties:
+ compatible:
+items:
+ - const: intel,hddl-client
+
+ reg:
+minItems: 4
+maxItems: 4
+
+ xlink_chan:
+minItems: 1
+maxItems: 1
+description: xlink channel number used for communication
+ with remote host for time sync and sharing sensor
+ details available in platform.
+
+ i2c_xlink_chan:
+minItems: 1
+maxItems: 1
+description: xlink channel number used for communication
+ with remote host for xlink i2c smbus.
+
+ sensor_name:
+type: object
+description:
+ Details about sensors and its configuration on local host and remote
+ host.
+
+properties:
+ compatible:
+items:
+ - const: intel_tsens
+
+ reg:
+description: i2c slave address for sensor.
+
+ local-host:
+minItems: 1
+maxItems: 1
+description: enable bit 0 to register sensor as i2c slave
+ in local host (normal i2c client)
+ enable bit 1 to mimic sensor as i2c slave
+ in local host (onchip sensors as i2c slave)
+ enable bit 2 to register i2c slave as xlink smbus slave
+ in local host.
+ remote-host:
+minItems: 1
+maxItems: 1
+description: enable bit 0 to register sensor as i2c slave
+ in remote host (normal i2c client)
+ enable bit 1 to mimic sensor as i2c slave
+ in remote host (onchip sensors as i2c slave)
+ enable bit 2 to register i2c slave as xlink smbus slave
+ in remote host.
+
+ bus:
+minItems: 1
+maxItems: 1
+description: i2c bus number for the i2c client device.
+
+required:
+ - compatible
+ - reg
+ - local-host
+ - remote-host
+ - bus
+
+required:
+ - compatible
+ - reg
+ - xlink_chan
+ - i2c_xlink_chan
+
+additionalProperties: false
+
+examples:
+ - |
+hddl_dev: hddl@2032 {
+ compatible = "intel,hddl-client";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+ reg = <0x0 0x2032 0x0 0x800>;
+ xlink_chan = <1080>;
+ i2c_xlink_chan = <1081>;
+ kmb_xlink_tj {
+ status = "okay";
+ compatible = "intel_tsens";
+ local-host = <0x3>;
+ remote-host = <0x3>;
+ bus = <0x1>;
+ };
+};
--
2.17.1
[PATCH v4 01/34] Add Vision Processing Unit (VPU) documentation.
From: mark gross The Intel VPU needs a complicated SW stack to make it work. Add a directory to hold VPU related documentation including an architectural overview of the SW stack that the patches implement. Cc: Jonathan Corbet Signed-off-by: Mark Gross --- Documentation/index.rst | 1 + Documentation/vpu/index.rst | 16 ++ Documentation/vpu/vpu-stack-overview.rst | 270 +++ 3 files changed, 287 insertions(+) create mode 100644 Documentation/vpu/index.rst create mode 100644 Documentation/vpu/vpu-stack-overview.rst diff --git a/Documentation/index.rst b/Documentation/index.rst index 5888e8a7272f..81a02f2af939 100644 --- a/Documentation/index.rst +++ b/Documentation/index.rst @@ -137,6 +137,7 @@ needed). misc-devices/index scheduler/index mhi/index + vpu/index Architecture-agnostic documentation --- diff --git a/Documentation/vpu/index.rst b/Documentation/vpu/index.rst new file mode 100644 index ..7e290e048910 --- /dev/null +++ b/Documentation/vpu/index.rst @@ -0,0 +1,16 @@ +.. SPDX-License-Identifier: GPL-2.0-only + + +Vision Processor Unit Documentation + + +This documentation contains information for the Intel VPU stack. + +.. class:: toc-title + + Table of contents + +.. toctree:: + :maxdepth: 2 + + vpu-stack-overview diff --git a/Documentation/vpu/vpu-stack-overview.rst b/Documentation/vpu/vpu-stack-overview.rst new file mode 100644 index ..1fe9ce423177 --- /dev/null +++ b/Documentation/vpu/vpu-stack-overview.rst @@ -0,0 +1,270 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== +Intel VPU architecture +== + +Overview + + +The Intel Movidius acquisition has developed a Vision Processing Unit (VPU) +roadmap of products starting with Keem Bay (KMB). The hardware configurations +the VPU can support include: + +1. Standalone smart camera that does local Computer Vision (CV) processing in + camera +2. Standalone appliance or signel board computer connected to a network and + tethered cameras doing local CV processing +3. Embedded in a USB dongle or M.2 as an CV accelerator. +4. Multiple VPU enabled SOC's on a PCIe card as a CV accelerator in a larger IA + box or server. + +Keem Bay is the first instance of this family of products. This document +provides an architectural overview of the software stack supporting the VPU +enabled products. + +Keem Bay (KMB) is a Computer Vision AI processing SoC based on ARM A53 CPU that +provides Edge neural network acceleration (inference) and includes a Vision +Processing Unit (VPU) hardware. The ARM CPU SubSystem (CPUSS) interfaces +locally to the VPU and enables integration/interfacing with a remote host over +PCIe or USB or Ethernet interfaces. The interface between the CPUSS and the VPU +is implemented with hardware FIFOs (Control) and coherent memory mapping (Data) +such that zero copy processing can happen within the VPU. + +The KMB can be used in all 4 of the above classes of designs. + +We refer to the 'local host' as being the ARM part of the SoC, while the +'remote host' as the IA system hosting the KMB device(s). The KMB SoC boots +from an eMMC via uBoot and ARM Linux compatible device tree interface with an +expectation to fully boot within hundreds of milliseconds. There is also +support for downloading the kernel and root file system image from a remote +host. + +The eMMC can be updated with standard Mender update process. +See https://github.com/mendersoftware/mender + +The VPU is started and controlled from the A53 local host. Its firmware image +is loaded using the drive firware helper KAPI's. + +The VPU IP firware payload consists of a SPARC ISA RTEMS bootloader and/or +application binary. + +The interface allowing (remote or local) host clients to access VPU IP +capabilities is realized through an abstracted programming model, which +provides Remote Proxy APIs for a host CPU application to dynamically create and +execute CV and NN workloads on the VPU. All frameworks exposed through +programming model’s APIs are contained in the pre-compiled standard firmware +image. + +There is a significant software stack built up to support KMB and the use +cases. The rest of this documentation provides an overview of the components +of the stack. + +Keem Bay IPC + + +Directly interfaces with the KMB hardware FIFOs to provide zero copy processing +from the VPU. It implements the lowest level protocol for interacting with the +VPU. + +The Keem Bay IPC mechanism is based on shared memory and hardware FIFOs. +Specifically there are: + +* Two 128-entry hardware FIFOs, one for the CPU and one for the VPU. +* Two shared memory regions, used as memory pool for allocating IPC buffers. + +An IPC channel is a software abstraction allowing communication multiplexing, +so that multiple a
[PATCH v3 26/34] dt-bindings: misc: intel_tsens: Add tsens thermal bindings documentation
From: "C, Udhayakumar"
Add device tree bindings for local host thermal sensors
Intel Edge.AI Computer Vision platforms.
The tsens module enables reading of on chip sensors present
in the Intel Bay series SoC. In the tsens module various junction
temperature and SoC temperature are reported using thermal subsystem
and i2c subsystem.
Temperature data reported using thermal subsystem will be used for
various cooling agents such as DVFS, fan control and shutdown the
system in case of critical temperature.
Temperature data reported using i2c subsytem will be used by
platform manageability software running in remote host.
Acked-by: mark gross
Signed-off-by: C, Udhayakumar
---
.../bindings/misc/intel,intel-tsens.yaml | 122 ++
1 file changed, 122 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/intel,intel-tsens.yaml
diff --git a/Documentation/devicetree/bindings/misc/intel,intel-tsens.yaml
b/Documentation/devicetree/bindings/misc/intel,intel-tsens.yaml
new file mode 100644
index ..abac41995643
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,intel-tsens.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/intel,intel_tsens.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel Temperature sensors in Bay series
+
+maintainers:
+ - Udhayakumar C
+
+description: |
+ The tsens driver enables reading of onchip sensors present
+ in the Intel Bay SoC.
+ Each subnode of the tsens represents sensors available
+ on the soc.
+
+select: false
+
+properties:
+ compatible:
+items:
+ - const: intel,intel-tsens
+
+ plat_name:
+contains:
+ enum:
+- intel,keembay_thermal
+
+ reg:
+minItems: 1
+maxItems: 2
+
+ clocks:
+items:
+ - description: thermal sensor clock
+
+ clk-rate:
+minItems: 1
+maxItems: 1
+additionalItems: false
+items:
+ - description: thermal sensor clock freq
+
+ sensor_name:
+type: object
+description:
+ Details to configure sensor trip points and its types.
+
+properties:
+ passive_delay:
+minItems: 1
+maxItems: 1
+description: number of milliseconds to wait between polls when
+ performing passive cooling
+
+ polling_delay:
+minItems: 1
+maxItems: 1
+description: number of milliseconds to wait between polls when checking
+ whether trip points have been crossed (0 for interrupt
+ driven systems)
+
+ trip_temp:
+minItems: 1
+description: temperature for trip points
+
+ trip_type:
+minItems: 1
+description: trip type list for trip points
+
+required:
+ - passive_delay
+ - polling_delay
+ - trip_temp
+ - trip_type
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+tsens: tsens@2026 {
+compatible = "intel,intel-tsens";
+status = "disabled";
+#address-cells = <2>;
+#size-cells = <2>;
+plat_name = "intel,keembay_thermal";
+reg = <0x0 0x2026 0x0 0x100>;
+clocks = <&scmi_clk>;
+clk-rate = <125>;
+
+mss {
+passive_delay = <1000>;
+polling_delay = <2000>;
+trip_temp = <4 8 100>;
+trip_type = "passive", "passive", "critical";
+};
+
+css {
+passive_delay = <1000>;
+polling_delay = <2000>;
+trip_temp = <4 8 100>;
+trip_type = "passive", "passive", "critical";
+};
+
+nce {
+passive_delay = <1000>;
+polling_delay = <2000>;
+trip_temp = <4 8 100>;
+trip_type = "passive", "passive", "critical";
+};
+
+soc {
+passive_delay = <1000>;
+polling_delay = <2000>;
+trip_temp = <4 8 100>;
+trip_type = "passive", "passive", "critical";
+};
+ };
--
2.17.1
[PATCH v3 08/34] misc: xlink-pcie: Add documentation for XLink PCIe driver
From: Srikanth Thokala
Provide overview of XLink PCIe driver implementation
Cc: Jonathan Corbet
Cc: linux-...@vger.kernel.org
Reviewed-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
Documentation/vpu/index.rst | 1 +
Documentation/vpu/xlink-pcie.rst | 90
2 files changed, 91 insertions(+)
create mode 100644 Documentation/vpu/xlink-pcie.rst
diff --git a/Documentation/vpu/index.rst b/Documentation/vpu/index.rst
index 7e290e048910..661cc700ee45 100644
--- a/Documentation/vpu/index.rst
+++ b/Documentation/vpu/index.rst
@@ -14,3 +14,4 @@ This documentation contains information for the Intel VPU
stack.
:maxdepth: 2
vpu-stack-overview
+ xlink-pcie
diff --git a/Documentation/vpu/xlink-pcie.rst b/Documentation/vpu/xlink-pcie.rst
new file mode 100644
index ..85a70990e9c9
--- /dev/null
+++ b/Documentation/vpu/xlink-pcie.rst
@@ -0,0 +1,90 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+
+Kernel driver: Xlink-pcie driver
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+Suffix: Bay
+Slave address: 6240
+Datasheet: Publicly available at Intel
+
+Author: Srikanth Thokala srikanth.thok...@intel.com
+
+Introduction
+
+The Xlink-pcie driver provides transport layer implementation for
+the data transfers to support Xlink protocol subsystem communication with the
+peer device, i.e., between remote host system and Keem Bay device.
+
+The Keem Bay device is an ARM-based SOC that includes a vision processing
+unit (VPU) and deep learning, neural network core in the hardware.
+The Xlink-pcie driver exports a functional device endpoint to the Keem Bay
+device and supports two-way communication with the peer device.
+
+High-level architecture
+===
+Remote Host: IA CPU
+Local Host: ARM CPU (Keem Bay)::
+
+
++
+| Remote Host IA CPU | | Local Host ARM CPU (Keem Bay) |
|
+
+==+=+===+===+
+| User App| | User App |
|
+
+--+-+---+---+
+| XLink UAPI | | XLink UAPI|
|
+
+--+-+---+---+
+| XLink Core | | XLink Core|
|
+
+--+-+---+---+
+| XLink PCIe | | XLink PCIe|
|
+
+--+-+---+---+
+| XLink-PCIe Remote Host driver | | XLink-PCIe Local Host driver |
|
+
+--+-+---+---+
+
|-:-:-:-:-:-:-:-:-:-:-:-:-:-:-:-:-:|:|:-:-:-:-:-:-:-:-:-:-:-:-:-:-:-:-:-:|
+
+--+-+---+---+
+| PCIe Host Controller | | PCIe Device Controller|
HW|
+
+--+-+---+---+
+ ^ ^
+ | |
+ |- PCIe x2 Link -|
+
+This XLink PCIe driver comprises of two variants:
+* Local Host driver
+
+ * Intended for ARM CPU
+ * It is based on PCI Endpoint Framework
+ * Driver path: {tree}/drivers/misc/Xlink-pcie/local_host
+
+* Remote Host driver
+
+ * Intended for IA CPU
+ * It is a PCIe endpoint driver
+ * Driver path: {tree}/drivers/misc/Xlink-pcie/remote_host
+
+XLink PCIe communication between local host and remote host is achieved through
+ring buffer management and MSI/Doorbell interrupts.
+
+The Xlink-pcie driver subsystem registers the Keem Bay device as an endpoint
+driver and provides standard Linux PCIe sysfs interface:
+'/sys/bus/pci/devices/:xx:xx.0/'
+
+
+XLink protocol subsystem
+
+Xlink is an abstracted control and communication subsystem based on channel
+identification. It is intended to support VPU technology both at SoC level as
+well as at IP level, over multiple interfaces.
+
+- The Xlink subsystem abstracts several types of communication channels
+ underneath, allowing the usage of different interfaces with the
+ same function call interface.
+- The Communication channels are full-duplex protocol channels allowing
+ concurrent bidirectional communication.
+- The Xlink subsystem also supports control operations to VPU either
+ from standalone local system or from remote system based on communication
+ interface underneath.
+- The Xlink subsystem supports the following co
[PATCH v4 22/34] xlink-core: Enable VPU IP management and runtime control
From: Seamus Kelly
Enable VPU management including, enumeration, boot and runtime control.
Add APIs:
write control data:
used to transmit small, local data
start vpu:
calls boot_device API ( soon to be deprecated )
stop vpu
calls reset_device API ( soon to be deprecated )
reset vpu
calls reset_device API ( soon to be deprecated )
get device name:
Returns the device name for the input device id
This could be a char device path, for example "/dev/ttyUSB0"
for a serial device; or it could be a device string
description, for example, for PCIE "00:00.0 Host bridge: Intel
Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 01)"
get device list:
Returns the list of software device IDs for all connected
physical devices
get device status:
returns the current state of the input device
OFF - The device is off (D3cold/Slot power removed).
BUSY - device is busy and not available (device is
booting)
READY - device is available for use
ERROR - device HW failure is detected
RECOVERY - device is in recovery mode, waiting for
recovery operations
boot device:
When used on the remote host - starts the SOC device by calling
corresponding function from VPU Driver.
Takes firmware's 'binary_name' as input.
For Linux, the firmware image is expected to be located in
'/lib/firmware' folder or its subfolders.
For Linux, 'binary_name' is not a path but an image name that
will be searched in the default Linux search paths
('/lib/firmware').
When used on the local host - triggers the booting of VPUIP
device.
reset device:
When used on the remote host - resets the device by calling
corresponding VPU Driver function.
When used on the local host - resets the VPUIP device
get device mode:
query and returns the current device power mode
set device mode:
used for device throttling or entering various power modes
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Seamus Kelly
---
drivers/misc/xlink-core/xlink-core.c| 235
drivers/misc/xlink-core/xlink-defs.h| 2 +
drivers/misc/xlink-core/xlink-ioctl.c | 214 ++
drivers/misc/xlink-core/xlink-ioctl.h | 9 +
drivers/misc/xlink-core/xlink-multiplexer.c | 56 +
drivers/misc/xlink-core/xlink-platform.c| 86 +++
include/linux/xlink.h | 27 +++
7 files changed, 629 insertions(+)
diff --git a/drivers/misc/xlink-core/xlink-core.c
b/drivers/misc/xlink-core/xlink-core.c
index bdbf8c6a99ca..d0a3f98d16af 100644
--- a/drivers/misc/xlink-core/xlink-core.c
+++ b/drivers/misc/xlink-core/xlink-core.c
@@ -73,6 +73,8 @@ struct keembay_xlink_dev {
struct mutex lock; // protect access to xlink_dev
};
+static u8 volbuf[XLINK_MAX_BUF_SIZE]; // buffer for volatile transactions
+
/*
* global variable pointing to our xlink device.
*
@@ -264,6 +266,9 @@ static long xlink_ioctl(struct file *file, unsigned int
cmd, unsigned long arg)
case XL_READ_DATA:
rc = ioctl_read_data(arg);
break;
+ case XL_READ_TO_BUFFER:
+ rc = ioctl_read_to_buffer(arg);
+ break;
case XL_WRITE_DATA:
rc = ioctl_write_data(arg);
break;
@@ -276,9 +281,39 @@ static long xlink_ioctl(struct file *file, unsigned int
cmd, unsigned long arg)
case XL_CLOSE_CHANNEL:
rc = ioctl_close_channel(arg);
break;
+ case XL_START_VPU:
+ rc = ioctl_start_vpu(arg);
+ break;
+ case XL_STOP_VPU:
+ rc = xlink_stop_vpu();
+ break;
+ case XL_RESET_VPU:
+ rc = xlink_stop_vpu();
+ break;
case XL_DISCONNECT:
rc = ioctl_disconnect(arg);
break;
+ case XL_GET_DEVICE_NAME:
+ rc = ioctl_get_device_name(arg);
+ break;
+ case XL_GET_DEVICE_LIST:
+ rc = ioctl_get_device_list(arg);
+ break;
+ case XL_GET_DEVICE_STATUS:
+ rc = ioctl_get_device_status(arg);
+ break;
+ case XL_BOOT_DEVICE:
+ rc = ioctl_boot_device(arg);
+ break;
+ case XL_RESET_DEVICE:
+ rc = ioctl_reset_device(arg);
+ break;
+ case XL_GET_DEVIC
[PATCH v3 06/34] dt-bindings: Add bindings for Keem Bay VPU IPC driver
From: Paul Murphy
Add DT bindings documentation for the Keem Bay VPU IPC driver.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Reviewed-by: Mark Gross
Signed-off-by: Paul Murphy
Co-developed-by: Daniele Alessandrelli
Signed-off-by: Daniele Alessandrelli
---
.../soc/intel/intel,keembay-vpu-ipc.yaml | 153 ++
1 file changed, 153 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
diff --git
a/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
new file mode 100644
index ..cd1c4abe8bc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) Intel Corporation. All rights reserved.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-vpu-ipc.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel Keem Bay VPU IPC
+
+maintainers:
+ - Paul Murphy
+
+description:
+ The VPU IPC driver facilitates loading of firmware, control, and
communication
+ with the VPU over the IPC FIFO in the Intel Keem Bay SoC.
+
+properties:
+ compatible:
+oneOf:
+ - items:
+- const: intel,keembay-vpu-ipc
+
+ reg:
+items:
+ - description: NCE WDT registers
+ - description: NCE TIM_GEN_CONFIG registers
+ - description: MSS WDT registers
+ - description: MSS TIM_GEN_CONFIG registers
+
+ reg-names:
+items:
+ - const: nce_wdt
+ - const: nce_tim_cfg
+ - const: mss_wdt
+ - const: mss_tim_cfg
+
+ memory-region:
+items:
+ - description: reference to the VPU reserved memory region
+ - description: reference to the X509 reserved memory region
+ - description: reference to the MSS IPC area
+
+ clocks:
+items:
+ - description: cpu clock
+ - description: pll 0 out 0 rate
+ - description: pll 0 out 1 rate
+ - description: pll 0 out 2 rate
+ - description: pll 0 out 3 rate
+ - description: pll 1 out 0 rate
+ - description: pll 1 out 1 rate
+ - description: pll 1 out 2 rate
+ - description: pll 1 out 3 rate
+ - description: pll 2 out 0 rate
+ - description: pll 2 out 1 rate
+ - description: pll 2 out 2 rate
+ - description: pll 2 out 3 rate
+
+ clock-names:
+items:
+ - const: cpu_clock
+ - const: pll_0_out_0
+ - const: pll_0_out_1
+ - const: pll_0_out_2
+ - const: pll_0_out_3
+ - const: pll_1_out_0
+ - const: pll_1_out_1
+ - const: pll_1_out_2
+ - const: pll_1_out_3
+ - const: pll_2_out_0
+ - const: pll_2_out_1
+ - const: pll_2_out_2
+ - const: pll_2_out_3
+
+ interrupts:
+items:
+ - description: number of NCE sub-system WDT timeout IRQ
+ - description: number of MSS sub-system WDT timeout IRQ
+
+ interrupt-names:
+items:
+ - const: nce_wdt
+ - const: mss_wdt
+
+ intel,keembay-vpu-ipc-nce-wdt-redirect:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description:
+ Number to which we will request that the NCE sub-system
+ re-directs it's WDT timeout IRQ
+
+ intel,keembay-vpu-ipc-mss-wdt-redirect:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description:
+ Number to which we will request that the MSS sub-system
+ re-directs it's WDT timeout IRQ
+
+ intel,keembay-vpu-ipc-imr:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description:
+ IMR (isolated memory region) number which we will request
+ the runtime service uses to protect the VPU memory region
+ before authentication
+
+ intel,keembay-vpu-ipc-id:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description: The VPU ID to be passed to the VPU firmware.
+
+additionalProperties: False
+
+examples:
+ - |
+#include
+vpu-ipc@3f00209c {
+compatible = "intel,keembay-vpu-ipc";
+reg = <0x3f00209c 0x10>,
+ <0x3f003008 0x4>,
+ <0x2082009c 0x10>,
+ <0x20821008 0x4>;
+reg-names = "nce_wdt",
+"nce_tim_cfg",
+"mss_wdt",
+"mss_tim_cfg";
+memory-region = <&vpu_reserved>,
+<&vpu_x509_reserved>,
+<&mss_ipc_reserved>;
+clocks = <&scmi_clk 0>,
+ <&scmi_clk 0>,
+ <&scmi_clk 1>,
+ <&scmi_clk 2>,
+ <&scmi_clk 3>,
+ <&scmi_clk 4>,
+ <&scmi_clk 5>,
+ <&scmi_clk 6>,
+ <&scmi_clk 7>,
+ <&scmi_clk 8>,
+ <&scmi_clk 9>,
+ <&scmi_clk 10>,
+ <&scmi_clk 11>;
+clock-names = "cpu_clock",
+ "pll_0_out_0", "pll_0_out_1",
+
[PATCH v4 06/34] dt-bindings: Add bindings for Keem Bay VPU IPC driver
From: Paul Murphy
Add DT bindings documentation for the Keem Bay VPU IPC driver.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Reviewed-by: Mark Gross
Co-developed-by: Daniele Alessandrelli
Signed-off-by: Paul Murphy
Signed-off-by: Daniele Alessandrelli
Signed-off-by: Mark Gross
---
.../soc/intel/intel,keembay-vpu-ipc.yaml | 143 ++
1 file changed, 143 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
diff --git
a/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
new file mode 100644
index ..9dae8ab4c723
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) Intel Corporation. All rights reserved.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-vpu-ipc.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel Keem Bay VPU IPC
+
+maintainers:
+ - Paul Murphy
+ - Daniele Alessandrelli
+
+description:
+ This binding provides support for the Vision Processing Unit (VPU) found on
+ the Intel Keem Bay SoC.
+
+ The VPU is started and controlled by SoC CPU, which is in charge of loading
+ the VPU firmware. The SoC CPU can communicate with the VPU firmware using an
+ Inter-Processor Communication (IPC) mechanism.
+
+properties:
+ compatible:
+oneOf:
+ - items:
+ - const: intel,keembay-vpu-ipc
+
+ reg:
+items:
+ - description: NCE WDT registers
+ - description: NCE TIM_GEN_CONFIG registers
+ - description: MSS WDT registers
+ - description: MSS TIM_GEN_CONFIG registers
+
+ reg-names:
+items:
+ - const: nce_wdt
+ - const: nce_tim_cfg
+ - const: mss_wdt
+ - const: mss_tim_cfg
+
+ memory-region:
+items:
+ - description: reference to the VPU reserved memory region
+ - description: reference to the X509 reserved memory region
+ - description: reference to the MSS IPC area
+
+ clocks:
+items:
+ - description: cpu clock
+ - description: pll 0 out 0 rate
+ - description: pll 0 out 1 rate
+ - description: pll 0 out 2 rate
+ - description: pll 0 out 3 rate
+ - description: pll 1 out 0 rate
+ - description: pll 1 out 1 rate
+ - description: pll 1 out 2 rate
+ - description: pll 1 out 3 rate
+ - description: pll 2 out 0 rate
+ - description: pll 2 out 1 rate
+ - description: pll 2 out 2 rate
+ - description: pll 2 out 3 rate
+
+ clock-names:
+items:
+ - const: cpu_clock
+ - const: pll_0_out_0
+ - const: pll_0_out_1
+ - const: pll_0_out_2
+ - const: pll_0_out_3
+ - const: pll_1_out_0
+ - const: pll_1_out_1
+ - const: pll_1_out_2
+ - const: pll_1_out_3
+ - const: pll_2_out_0
+ - const: pll_2_out_1
+ - const: pll_2_out_2
+ - const: pll_2_out_3
+
+ interrupts:
+items:
+ - description: number of NCE sub-system WDT timeout IRQ
+ - description: number of MSS sub-system WDT timeout IRQ
+
+ interrupt-names:
+items:
+ - const: nce_wdt
+ - const: mss_wdt
+
+ intel,keembay-vpu-ipc-imr:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description:
+ Isolated Memory Region (IMR) number that the runtime service must use to
+ protect the VPU memory region before authentication.
+
+ intel,keembay-vpu-ipc-id:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description: The VPU ID to be passed to the VPU firmware.
+
+additionalProperties: False
+
+examples:
+ - |
+#include
+vpu-ipc@3f00209c {
+compatible = "intel,keembay-vpu-ipc";
+reg = <0x3f00209c 0x10>,
+ <0x3f003008 0x4>,
+ <0x2082009c 0x10>,
+ <0x20821008 0x4>;
+reg-names = "nce_wdt",
+"nce_tim_cfg",
+"mss_wdt",
+"mss_tim_cfg";
+memory-region = <&vpu_reserved>,
+<&vpu_x509_reserved>,
+<&mss_ipc_reserved>;
+clocks = <&scmi_clk 0>,
+ <&scmi_clk 0>,
+ <&scmi_clk 1>,
+ <&scmi_clk 2>,
+ <&scmi_clk 3>,
+ <&scmi_clk 4>,
+ <&scmi_clk 5>,
+ <&scmi_clk 6>,
+ <&scmi_clk 7>,
+ <&scmi_clk 8>,
+ <&scmi_clk 9>,
+ <&scmi_clk 10>,
+ <&scmi_clk 11>;
+clock-names = "cpu_clock",
+ "pll_0_out_0", "pll_0_out_1",
+ "pll_0_out_2", "pll_0_out_3",
+ "pll_1_out_0", "pll_1_out_1",
+ "pll_1_out_2", "pll_1_out_3",
+ "pll_2_out_0", "pll_2_out_1",
+
[PATCH v4 15/34] misc: xlink-pcie: Add XLink API interface
From: Srikanth Thokala
Provide interface for XLink layer to interact with XLink PCIe transport
layer on both local host and remote host.
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/common/interface.c | 107 +++
drivers/misc/xlink-pcie/local_host/Makefile | 1 +
drivers/misc/xlink-pcie/remote_host/Makefile | 1 +
3 files changed, 109 insertions(+)
create mode 100644 drivers/misc/xlink-pcie/common/interface.c
diff --git a/drivers/misc/xlink-pcie/common/interface.c
b/drivers/misc/xlink-pcie/common/interface.c
new file mode 100644
index ..fcc69a940a4c
--- /dev/null
+++ b/drivers/misc/xlink-pcie/common/interface.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include
+
+#include "core.h"
+#include "xpcie.h"
+
+/* Define xpcie driver interface API */
+int xlink_pcie_get_device_list(u32 *sw_device_id_list, u32 *num_devices)
+{
+ if (!sw_device_id_list || !num_devices)
+ return -EINVAL;
+
+ *num_devices = intel_xpcie_get_device_num(sw_device_id_list);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_list);
+
+int xlink_pcie_get_device_name(u32 sw_device_id, char *device_name,
+ size_t name_size)
+{
+ if (!device_name)
+ return -EINVAL;
+
+ return intel_xpcie_get_device_name_by_id(sw_device_id,
+device_name, name_size);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_name);
+
+int xlink_pcie_get_device_status(u32 sw_device_id, u32 *device_status)
+{
+ u32 status;
+ int rc;
+
+ if (!device_status)
+ return -EINVAL;
+
+ rc = intel_xpcie_get_device_status_by_id(sw_device_id, &status);
+ if (rc)
+ return rc;
+
+ switch (status) {
+ case XPCIE_STATUS_READY:
+ case XPCIE_STATUS_RUN:
+ *device_status = _XLINK_DEV_READY;
+ break;
+ case XPCIE_STATUS_ERROR:
+ *device_status = _XLINK_DEV_ERROR;
+ break;
+ case XPCIE_STATUS_RECOVERY:
+ *device_status = _XLINK_DEV_RECOVERY;
+ break;
+ case XPCIE_STATUS_OFF:
+ *device_status = _XLINK_DEV_OFF;
+ break;
+ default:
+ *device_status = _XLINK_DEV_BUSY;
+ break;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_get_device_status);
+
+int xlink_pcie_boot_device(u32 sw_device_id, const char *binary_name)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_boot_device);
+
+int xlink_pcie_connect(u32 sw_device_id)
+{
+ return intel_xpcie_pci_connect_device(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_connect);
+
+int xlink_pcie_read(u32 sw_device_id, void *data, size_t *const size,
+ u32 timeout)
+{
+ if (!data || !size)
+ return -EINVAL;
+
+ return intel_xpcie_pci_read(sw_device_id, data, size, timeout);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_read);
+
+int xlink_pcie_write(u32 sw_device_id, void *data, size_t *const size,
+u32 timeout)
+{
+ if (!data || !size)
+ return -EINVAL;
+
+ return intel_xpcie_pci_write(sw_device_id, data, size, timeout);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_write);
+
+int xlink_pcie_reset_device(u32 sw_device_id)
+{
+ return intel_xpcie_pci_reset_device(sw_device_id);
+}
+EXPORT_SYMBOL_GPL(xlink_pcie_reset_device);
diff --git a/drivers/misc/xlink-pcie/local_host/Makefile
b/drivers/misc/xlink-pcie/local_host/Makefile
index 65df94c7e860..16bb1e7345ac 100644
--- a/drivers/misc/xlink-pcie/local_host/Makefile
+++ b/drivers/misc/xlink-pcie/local_host/Makefile
@@ -3,3 +3,4 @@ mxlk_ep-objs := epf.o
mxlk_ep-objs += dma.o
mxlk_ep-objs += core.o
mxlk_ep-objs += ../common/util.o
+mxlk_ep-objs += ../common/interface.o
diff --git a/drivers/misc/xlink-pcie/remote_host/Makefile
b/drivers/misc/xlink-pcie/remote_host/Makefile
index e8074dbb1161..088e121ad46e 100644
--- a/drivers/misc/xlink-pcie/remote_host/Makefile
+++ b/drivers/misc/xlink-pcie/remote_host/Makefile
@@ -3,3 +3,4 @@ mxlk-objs := main.o
mxlk-objs += pci.o
mxlk-objs += core.o
mxlk-objs += ../common/util.o
+mxlk-objs += ../common/interface.o
--
2.17.1
[PATCH v4 11/34] misc: xlink-pcie: lh: Add core communication logic
From: Srikanth Thokala
Add logic to establish communication with the remote host which is through
ring buffer management and MSI/Doorbell interrupts
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Reviewed-by: Mark Gross
Signed-off-by: Mark Gross
Signed-off-by: Srikanth Thokala
---
drivers/misc/xlink-pcie/local_host/Makefile | 2 +
drivers/misc/xlink-pcie/local_host/core.c | 806
drivers/misc/xlink-pcie/local_host/core.h | 247 ++
drivers/misc/xlink-pcie/local_host/epf.c| 116 ++-
drivers/misc/xlink-pcie/local_host/epf.h| 23 +
drivers/misc/xlink-pcie/local_host/util.c | 375 +
drivers/misc/xlink-pcie/local_host/util.h | 70 ++
drivers/misc/xlink-pcie/local_host/xpcie.h | 63 ++
include/linux/xlink_drv_inf.h | 58 ++
9 files changed, 1752 insertions(+), 8 deletions(-)
create mode 100644 drivers/misc/xlink-pcie/local_host/core.c
create mode 100644 drivers/misc/xlink-pcie/local_host/core.h
create mode 100644 drivers/misc/xlink-pcie/local_host/util.c
create mode 100644 drivers/misc/xlink-pcie/local_host/util.h
create mode 100644 include/linux/xlink_drv_inf.h
diff --git a/drivers/misc/xlink-pcie/local_host/Makefile
b/drivers/misc/xlink-pcie/local_host/Makefile
index 54fc118e2dd1..28761751d43b 100644
--- a/drivers/misc/xlink-pcie/local_host/Makefile
+++ b/drivers/misc/xlink-pcie/local_host/Makefile
@@ -1,3 +1,5 @@
obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o
mxlk_ep-objs := epf.o
mxlk_ep-objs += dma.o
+mxlk_ep-objs += core.o
+mxlk_ep-objs += util.o
diff --git a/drivers/misc/xlink-pcie/local_host/core.c
b/drivers/misc/xlink-pcie/local_host/core.c
new file mode 100644
index ..c67ce2c3067d
--- /dev/null
+++ b/drivers/misc/xlink-pcie/local_host/core.c
@@ -0,0 +1,806 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay XLink PCIe Driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ */
+
+#include
+
+#include "epf.h"
+#include "core.h"
+#include "util.h"
+
+static struct xpcie *global_xpcie;
+
+static struct xpcie *intel_xpcie_core_get_by_id(u32 sw_device_id)
+{
+ return (sw_device_id == xlink_sw_id) ? global_xpcie : NULL;
+}
+
+static int intel_xpcie_map_dma(struct xpcie *xpcie, struct xpcie_buf_desc *bd,
+ int direction)
+{
+ struct xpcie_epf *xpcie_epf = container_of(xpcie,
+ struct xpcie_epf, xpcie);
+ struct pci_epf *epf = xpcie_epf->epf;
+ struct device *dma_dev = epf->epc->dev.parent;
+
+ bd->phys = dma_map_single(dma_dev, bd->data, bd->length, direction);
+
+ return dma_mapping_error(dma_dev, bd->phys);
+}
+
+static void intel_xpcie_unmap_dma(struct xpcie *xpcie,
+ struct xpcie_buf_desc *bd, int direction)
+{
+ struct xpcie_epf *xpcie_epf = container_of(xpcie,
+ struct xpcie_epf, xpcie);
+ struct pci_epf *epf = xpcie_epf->epf;
+ struct device *dma_dev = epf->epc->dev.parent;
+
+ dma_unmap_single(dma_dev, bd->phys, bd->length, direction);
+}
+
+static void intel_xpcie_set_cap_txrx(struct xpcie *xpcie)
+{
+ size_t tx_len = sizeof(struct xpcie_transfer_desc) *
+ XPCIE_NUM_TX_DESCS;
+ size_t rx_len = sizeof(struct xpcie_transfer_desc) *
+ XPCIE_NUM_RX_DESCS;
+ size_t hdr_len = sizeof(struct xpcie_cap_txrx);
+ u32 start = sizeof(struct xpcie_mmio);
+ struct xpcie_cap_txrx *cap;
+ struct xpcie_cap_hdr *hdr;
+ u16 next;
+
+ next = (u16)(start + hdr_len + tx_len + rx_len);
+ intel_xpcie_iowrite32(start, xpcie->mmio + XPCIE_MMIO_CAP_OFF);
+ cap = (void *)xpcie->mmio + start;
+ memset(cap, 0, sizeof(struct xpcie_cap_txrx));
+ cap->hdr.id = XPCIE_CAP_TXRX;
+ cap->hdr.next = next;
+ cap->fragment_size = XPCIE_FRAGMENT_SIZE;
+ cap->tx.ring = start + hdr_len;
+ cap->tx.ndesc = XPCIE_NUM_TX_DESCS;
+ cap->rx.ring = start + hdr_len + tx_len;
+ cap->rx.ndesc = XPCIE_NUM_RX_DESCS;
+
+ hdr = (struct xpcie_cap_hdr *)((void *)xpcie->mmio + next);
+ hdr->id = XPCIE_CAP_NULL;
+}
+
+static void intel_xpcie_txrx_cleanup(struct xpcie *xpcie)
+{
+ struct xpcie_epf *xpcie_epf = container_of(xpcie,
+ struct xpcie_epf, xpcie);
+ struct device *dma_dev = xpcie_epf->epf->epc->dev.parent;
+ struct xpcie_interface *inf = &xpcie->interfaces[0];
+ struct xpcie_stream *tx = &xpcie->tx;
+ struct xpcie_stream *rx = &xpcie->rx;
+ struct xpcie_transfer_desc *td;
+ int index;
+
+ xpcie->stop_flag = true;
+ xpcie->no_tx_buffer = false;
+ inf->data_avail = true;
+ wake_up_interruptible(&xpcie->tx_waitq);
+ wake_up_interruptible(&inf->rx_waitq);
+ mutex_lock(&xpcie->wlock);
+ mutex_lock(&inf->rlock);
+
+ for (inde
[PATCH v4 34/34] misc: HDDL device management for IA host
From: "C, Udhayakumar"
Add IA host hddl device management driver for Intel Edge.AI Computer Vision
platforms.
About Intel Edge.AI Computer Vision platforms:
-
The Intel Edge.AI Computer Vision platforms are vision processing systems
targeting machine vision applications for connected devices.
They are based on ARM A53 CPU running Linux and acts as a PCIe
endpoint device.
High-level architecture:
Remote Host IA CPU Local Host ARM CPU
---
| * Send time as xlink packet | |* Sync time with IA host |
| * receive sensor details| |* Prepare and share sensor|
| and register as i2c or| | details to IA host as |
| xlink smbus slaves| | xlink packets |
---
| hddl server | <=> | hddl client |
--- xlink
hddl device module:
---
The HDDL client driver acts as an software RTC to sync with network
time. It abstracts xlink protocol to communicate with remote host.
This driver exports the details about sensors available in the
platform to remote host as xlink packets.
This driver also handles device connect/disconnect events and
identifies board id and soc id using gpio's, based on platform
configuration.
- Remote Host driver
* Intended for IA CPU
* It is based on xlink Framework
* Driver path:
{tree}/drivers/misc/hddl_device/hddl_device_server.c
Local arm host and Remote IA host drivers communicates using
XLINK protocol.
Signed-off-by: C Udhayakumar
Signed-off-by: Mark Gross
---
.../misc-devices/hddl_device_server.rst | 205 +
Documentation/misc-devices/index.rst | 1 +
drivers/misc/hddl_device/Kconfig | 12 +
drivers/misc/hddl_device/Makefile | 2 +
drivers/misc/hddl_device/hddl_device_rh.c | 837 ++
5 files changed, 1057 insertions(+)
create mode 100644 Documentation/misc-devices/hddl_device_server.rst
create mode 100644 drivers/misc/hddl_device/hddl_device_rh.c
diff --git a/Documentation/misc-devices/hddl_device_server.rst
b/Documentation/misc-devices/hddl_device_server.rst
new file mode 100644
index ..0be37973d1fe
--- /dev/null
+++ b/Documentation/misc-devices/hddl_device_server.rst
@@ -0,0 +1,205 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Kernel driver: hddl_device_server
+=
+
+Supported chips:
+ * Intel Edge.AI Computer Vision platforms: Keem Bay
+
+Authors:
+- Thalaiappan, Rathina
+- Udhayakumar C
+
+High-level architecture
+===
+::
+
+Remote Host IA CPU Local Host ARM CPU
+---
+| * Send time as xlink packet | |* Sync time with IA host |
+| * receive sensor details| |* Prepare and share sensor|
+| and register as i2c or| | details to IA host as |
+| xlink smbus slaves| | xlink packets |
+---
+| hddl server | <=> | hddl client |
+--- xlink
+
+Overview
+
+
+This driver supports hddl device management for Intel Edge.AI Computer Vision
+platforms. This driver runs in IA host
+
+This driver supports the following features:
+
+ - Receives deatils of temperature sensor, current sensor and fan controller
+present in Intel Edge.AI Computer Vision platforms.
+ - Send Time sync data to Intel Edge.AI Computer Vision platform.
+ - Handles device connect and disconnect events.
+ - Get free slave address for memory mapped thermal sensors present in SoC
+(Documentation/hwmon/intel_tsens_sensors.rst) and share it with Intel
+Edge.AI Computer Vision platform.
+ - Registers i2c slave device for slaves present in Intel Edge.AI Computer
+Vision platform
+
+Keem Bay platform has
+Onchip sensors:
+
+ - Media Subsystem (mss) temperature sensor
+ - NN subsystem (nce) temperature sensor
+ - Compute subsystem (cse) temperature sensor
+ - SOC(Maximum of mss, nce and cse).
+
+Onboard sensors:
+
+ - two lm75 temperature sensors
+ - emc2103 fan controller
+ - ina3221 current sensor
+
+Driver Structure
+
+
+The driver provides a platform device where the ``probe`` and ``remove``
+operations are provided.
+
+ - probe: spawn kernel thread to monitor new PCIE devices.
+
+ - init task: Poll for new PCIE device with time interval of 5 seconds and
+creates connect task to setup new device.
+
+ - connect task: Connect task is the main entity which connects to hd
[PATCH v4 18/34] xlink-ipc: Add xlink ipc driver
From: Seamus Kelly Add xLink driver, which interfaces the xLink Core driver with the Keem Bay VPU IPC driver, thus enabling xLink to control and communicate with the VPU IP present on the Intel Keem Bay SoC. Specifically the driver enables xLink Core to: * Boot / Reset the VPU IP * Register to VPU IP event notifications (device connected, device disconnected, WDT event) * Query the status of the VPU IP (OFF, BUSY, READY, ERROR, RECOVERY) * Exchange data with the VPU IP, using the Keem Bay IPC mechanism - Including the ability to send 'volatile' data (i.e., small amount of data, up to 128-bytes that was not allocated in the CPU/VPU shared memory region) Cc: Jonathan Corbet Cc: Cc: Derek Kiernan Cc: Dragan Cvetic Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Cc: linux-...@vger.kernel.org Reviewed-by: Mark Gross Signed-off-by: Mark Gross Signed-off-by: Seamus Kelly --- Documentation/vpu/index.rst| 1 + Documentation/vpu/xlink-ipc.rst| 51 ++ MAINTAINERS| 6 + drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/xlink-ipc/Kconfig | 7 + drivers/misc/xlink-ipc/Makefile| 4 + drivers/misc/xlink-ipc/xlink-ipc.c | 878 + include/linux/xlink-ipc.h | 48 ++ 9 files changed, 997 insertions(+) create mode 100644 Documentation/vpu/xlink-ipc.rst create mode 100644 drivers/misc/xlink-ipc/Kconfig create mode 100644 drivers/misc/xlink-ipc/Makefile create mode 100644 drivers/misc/xlink-ipc/xlink-ipc.c create mode 100644 include/linux/xlink-ipc.h diff --git a/Documentation/vpu/index.rst b/Documentation/vpu/index.rst index 661cc700ee45..49c78bb65b83 100644 --- a/Documentation/vpu/index.rst +++ b/Documentation/vpu/index.rst @@ -15,3 +15,4 @@ This documentation contains information for the Intel VPU stack. vpu-stack-overview xlink-pcie + xlink-ipc diff --git a/Documentation/vpu/xlink-ipc.rst b/Documentation/vpu/xlink-ipc.rst new file mode 100644 index ..97ee62b10e93 --- /dev/null +++ b/Documentation/vpu/xlink-ipc.rst @@ -0,0 +1,51 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=== +Kernel driver: xLink IPC driver +=== + +Supported chips: + +* | Intel Edge.AI Computer Vision platforms: Keem Bay + | Suffix: Bay + | Datasheet: (not yet publicly available) + +Introduction + + +The xLink IPC driver interfaces the xLink Core driver with the Keem Bay VPU IPC +driver, thus enabling xLink to control and communicate with the VPU IP present +on the Intel Keem Bay SoC. + +Specifically the driver enables xLink Core to: + +* Boot / Reset the VPU IP +* Register to VPU IP event notifications (device connected, device disconnected, + WDT event) +* Query the status of the VPU IP (OFF, BUSY, READY, ERROR, RECOVERY) +* Exchange data with the VPU IP, using the Keem Bay IPC mechanism + + * Including the ability to send 'volatile' data (i.e. small amounts of data, +up to 128-bytes that was not allocated in the CPU/VPU shared memory region) + +Sending / Receiving 'volatile' data +=== + +Data to be exchanged with Keem Bay IPC needs to be allocated in the portion of +DDR shared between the CPU and VPU. + +This can be impractical for small amounts of data that user code can allocate +on the stack. + +To reduce the burden on user code, xLink Core provides special send / receive +functions to send up to 128 bytes of 'volatile data', i.e., data that is not +allocated in the shared memory and that might also disappear after the xLink +API is called (e.g., because allocated on the stack). + +The xLink IPC driver implements support for transferring such 'volatile data' +to the VPU using Keem Bay IPC. To this end, the driver reserves some memory in +the shared memory region. + +When volatile data is to be sent, xLink IPC allocates a buffer from the +reserved memory region and copies the volatile data to the buffer. The buffer +is then transferred to the VPU using Keem Bay IPC. diff --git a/MAINTAINERS b/MAINTAINERS index e05fa34d72ce..22a7a1b03601 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1961,6 +1961,12 @@ F: Documentation/devicetree/bindings/arm/intel,keembay.yaml F: arch/arm64/boot/dts/intel/keembay-evm.dts F: arch/arm64/boot/dts/intel/keembay-soc.dtsi +ARM/INTEL XLINK IPC SUPPORT +M: Seamus Kelly +M: Mark Gross +S: Supported +F: drivers/misc/xlink-ipc/ + ARM/INTEL KEEM BAY XLINK PCIE SUPPORT M: Srikanth Thokala M: Mark Gross diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index dfb98e444c6e..1f81ea915b95 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -482,4 +482,5 @@ source "drivers/misc/cardreader/Kconfig" source "drivers/misc/habanalabs/Kconfig" source "drivers/misc/uacce/Kconfig" source "drivers/misc/xlink-pcie/Kconfig" +source "drivers/misc/xlink-ipc/Kconfig" endmenu diff --git a
[PATCH v4 31/34] Intel Keem Bay XLink SMBus driver
From: Ramya P Karanth Adds XLink SMBus driver for Intel Keem Bay SoC. Xlink-smbus driver is a logical SMBus adapter which uses Xlink (xlink-pcie) protocol as an interface. Keem Bay(s) vision accelerators are connected to the server via PCI interface. The Server needs to know the temperature of the Soc and the source to get the temperature can be either on board sensors or on chip sensors. The sensors are ideally connected over i2c bus of the Soc and the server does not have access to sensors present in the PCB. With this xlink-smbus interfaces, server access the on board/on chip sensors via xlink smbus adapter. Signed-off-by: Ramya P Karanth Signed-off-by: Mark Gross --- Documentation/i2c/busses/index.rst| 1 + .../i2c/busses/intel-xlink-smbus.rst | 71 +++ drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/xlink-smbus/Kconfig | 26 + drivers/misc/xlink-smbus/Makefile | 5 + drivers/misc/xlink-smbus/xlink-smbus.c| 467 ++ 7 files changed, 572 insertions(+) create mode 100644 Documentation/i2c/busses/intel-xlink-smbus.rst create mode 100644 drivers/misc/xlink-smbus/Kconfig create mode 100644 drivers/misc/xlink-smbus/Makefile create mode 100644 drivers/misc/xlink-smbus/xlink-smbus.c diff --git a/Documentation/i2c/busses/index.rst b/Documentation/i2c/busses/index.rst index 5e4077b08d86..6ce4a740f616 100644 --- a/Documentation/i2c/busses/index.rst +++ b/Documentation/i2c/busses/index.rst @@ -29,4 +29,5 @@ I2C Bus Drivers i2c-taos-evm i2c-viapro i2c-via + intel-xlink-smbus.rst scx200_acb diff --git a/Documentation/i2c/busses/intel-xlink-smbus.rst b/Documentation/i2c/busses/intel-xlink-smbus.rst new file mode 100644 index ..ab87d18051b4 --- /dev/null +++ b/Documentation/i2c/busses/intel-xlink-smbus.rst @@ -0,0 +1,71 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== +Kernel driver: xlink_smbus +== + +Supported chips: + * Intel Edge.AI Computer Vision platforms: Keem Bay + + Sufix: Bay + + Slave address: The address is selectable by device-tree. (TBD) + +Authors: +- Raja Subramanian, Lakshmi Bai +- Thalaiappan, Rathina +- Karanth, Ramya P + +Description +=== +The Intel Edge.AI Computer Vision platforms have to be monitored using platform +devices like sensors, fan controller, IO expander etc. Some of these devices +are memory mapped and some are i2c based. Either of these devices are not +directly accessible to the host. + +The host here refers to the server to which the vision accelerators are +connected over PCIe Interface. The Host needs to do a consolidated action based +on the parameters of platform devices. In general, most of the standard devices +(includes sensors, fan controller, IO expander etc) are I2C/SMBus based and are +used to provide the status of the accelerator. Standard drivers for these +devices are available based on i2c/smbus APIs. + +Instead of changing the sensor drivers to adapt to PCIe interface, a generic +i2c adapter "xlink-smbus" which underneath uses xlink as physical medium is +used. With xlink-smbus, the drivers for the platform devices doesn't need to +undergo any interface change. + +High-level architecture +=== + +Accessing Onchip devices:: + +--- --- +| Remote Host | | Local Host| +| IA CPU| | Vision platforms| +--- --- +| Onchip | |i2c slave| ==> Access the device +| sensor driver | |handler | ==> which is mmio based +--- --- +|Intel XLINK_SMBUS| |Intel XLINK_SMBUS| +| adpater | | adapter | +|(Master) | | (I2C_SLAVE) | +--- --- +| XLINK |<==> | XLINK | +---PCIE --- + +Accessing Onboard devices:: + +--- -- +| Remote Host | | Local Host | +| IA CPU| | Vision platforms | +--- -- +|On board | | i2c smbus | ==> Access the device +| sensor driver | | xfer [synopsys] | ==> which is on i2c bus +--- -- +|Intel XLINK_SMBUS| | Intel XLI
[PATCH v4 24/34] dt-bindings: misc: Add Keem Bay vpumgr
From: "Li, Tingqian"
Add DT binding schema for VPU on Keem Bay ASoC platform
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Li Tingqian
Signed-off-by: Mark Gross
---
.../bindings/misc/intel,keembay-vpu-mgr.yaml | 48 +++
1 file changed, 48 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/intel,keembay-vpu-mgr.yaml
diff --git a/Documentation/devicetree/bindings/misc/intel,keembay-vpu-mgr.yaml
b/Documentation/devicetree/bindings/misc/intel,keembay-vpu-mgr.yaml
new file mode 100644
index ..a44f492277ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,keembay-vpu-mgr.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright (C) 2020 Intel
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/intel,keembay-vpu-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel VPU manager bindings
+
+maintainers:
+ - Li, Tingqian
+ - Zhou, Luwei
+
+description: |
+ The Intel VPU manager provides shared memory and process
+ depedent context management for Intel VPU hardware IP.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - intel,keembay-vpu-mgr
+ - intel,keembay-vpusmm
+
+ memory-region:
+description:
+ phandle to a node describing reserved memory (System RAM memory)
+ used by VPU (see bindings/reserved-memory/reserved-memory.txt)
+maxItems: 1
+
+ intel,keembay-vpu-ipc-id:
+$ref: /schemas/types.yaml#/definitions/uint32
+description:
+ the index of the VPU slice to be managed. Default is 0.
+
+required:
+ - compatible
+ - memory-region
+
+additionalProperties: false
+
+examples:
+ - |
+vpumgr0 {
+compatible = "intel,keembay-vpu-mgr";
+memory-region = <&vpu_reserved>;
+intel,keembay-vpu-ipc-id = <0x0>;
+};
--
2.17.1
[PATCH v3 20/34] xlink-core: Add xlink core driver xLink
From: Seamus Kelly Add xLink driver, which provides an abstracted control and communication subsystem based on channel identification. It is intended to support VPU technology both at SoC level as well as at IP level, over multiple interfaces. This initial patch enables local host user mode to open/close/read/write via IOCTLs. Specifically the driver enables application/process to: * Access a common xLink API across all interfaces from both kernel and user space. * Call typical APIs types (open, close, read, write) that you would associate with a communication interface. * Call other APIs that are related to other functions that the device can perform e.g. boot, reset get/set device mode. Device mode refers to the power load of the VPU and an API can be used to read and control it. * Use multiple commnication channels that the driver manages from one interface to another, providing routing of data through these multiple channels across a single physical interface. xLink: Add xLink Core device tree bindings Add device tree bindings for the xLink Core driver which enables xLink to control and communicate with the VPU IP present on the Intel Keem Bay SoC. Cc: Jonathan Corbet Cc: Derek Kiernan Cc: Dragan Cvetic Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Cc: linux-...@vger.kernel.org Reviewed-by: Mark Gross Signed-off-by: Seamus Kelly --- Documentation/vpu/index.rst | 1 + Documentation/vpu/xlink-core.rst| 81 +++ MAINTAINERS | 12 + drivers/misc/Kconfig| 1 + drivers/misc/Makefile | 1 + drivers/misc/xlink-core/Kconfig | 33 + drivers/misc/xlink-core/Makefile| 5 + drivers/misc/xlink-core/xlink-core.c| 738 drivers/misc/xlink-core/xlink-core.h| 22 + drivers/misc/xlink-core/xlink-defs.h| 175 + drivers/misc/xlink-core/xlink-ioctl.c | 212 ++ drivers/misc/xlink-core/xlink-ioctl.h | 21 + drivers/misc/xlink-core/xlink-multiplexer.c | 534 ++ drivers/misc/xlink-core/xlink-multiplexer.h | 35 + drivers/misc/xlink-core/xlink-platform.c| 160 + drivers/misc/xlink-core/xlink-platform.h| 65 ++ include/linux/xlink.h | 108 +++ include/uapi/misc/xlink_uapi.h | 145 18 files changed, 2349 insertions(+) create mode 100644 Documentation/vpu/xlink-core.rst create mode 100644 drivers/misc/xlink-core/Kconfig create mode 100644 drivers/misc/xlink-core/Makefile create mode 100644 drivers/misc/xlink-core/xlink-core.c create mode 100644 drivers/misc/xlink-core/xlink-core.h create mode 100644 drivers/misc/xlink-core/xlink-defs.h create mode 100644 drivers/misc/xlink-core/xlink-ioctl.c create mode 100644 drivers/misc/xlink-core/xlink-ioctl.h create mode 100644 drivers/misc/xlink-core/xlink-multiplexer.c create mode 100644 drivers/misc/xlink-core/xlink-multiplexer.h create mode 100644 drivers/misc/xlink-core/xlink-platform.c create mode 100644 drivers/misc/xlink-core/xlink-platform.h create mode 100644 include/linux/xlink.h create mode 100644 include/uapi/misc/xlink_uapi.h diff --git a/Documentation/vpu/index.rst b/Documentation/vpu/index.rst index 49c78bb65b83..cd4272e089ec 100644 --- a/Documentation/vpu/index.rst +++ b/Documentation/vpu/index.rst @@ -16,3 +16,4 @@ This documentation contains information for the Intel VPU stack. vpu-stack-overview xlink-pcie xlink-ipc + xlink-core diff --git a/Documentation/vpu/xlink-core.rst b/Documentation/vpu/xlink-core.rst new file mode 100644 index ..441c18230491 --- /dev/null +++ b/Documentation/vpu/xlink-core.rst @@ -0,0 +1,81 @@ +.. SPDX-License-Identifier: GPL-2.0 + += +xLink-core software subsystem += + +The purpose of the xLink software subsystem is to facilitate communication +between multiple users on multiple nodes in the system. + +There are three types of xLink nodes: + +1. Remote Host: this is an external IA/x86 host system that is only capable of + communicating directly to the Local Host node on VPU 2.x products. +2. Local Host: this is the ARM core within the VPU 2.x SoC. The Local Host can + communicate upstream to the Remote Host node, and downstream to the VPU IP + node. +3. VPU IP: this is the Leon RT core within the VPU 2.x SoC. The VPU IP can only + communicate upstream to the Local Host node. + +xLink provides a common API across all interfaces for users to access xLink +functions and provides user space APIs via an IOCTL interface implemented in +the xLink core. + +xLink manages communications from one interface to another and provides routing +of data through multiple channels across a single physical interface. + +It exposes a common API across all interfaces at both kernel and user
[PATCH v3 18/34] xlink-ipc: Add xlink ipc driver
From: Seamus Kelly Add xLink driver, which interfaces the xLink Core driver with the Keem Bay VPU IPC driver, thus enabling xLink to control and communicate with the VPU IP present on the Intel Keem Bay SoC. Specifically the driver enables xLink Core to: * Boot / Reset the VPU IP * Register to VPU IP event notifications (device connected, device disconnected, WDT event) * Query the status of the VPU IP (OFF, BUSY, READY, ERROR, RECOVERY) * Exchange data with the VPU IP, using the Keem Bay IPC mechanism - Including the ability to send 'volatile' data (i.e., small amount of data, up to 128-bytes that was not allocated in the CPU/VPU shared memory region) Cc: Jonathan Corbet Cc: Cc: Derek Kiernan Cc: Dragan Cvetic Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Cc: linux-...@vger.kernel.org Reviewed-by: Mark Gross Signed-off-by: Seamus Kelly Signed-off-by: Ryan Carnaghi --- Documentation/vpu/index.rst| 1 + Documentation/vpu/xlink-ipc.rst| 51 ++ MAINTAINERS| 6 + drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/xlink-ipc/Kconfig | 7 + drivers/misc/xlink-ipc/Makefile| 4 + drivers/misc/xlink-ipc/xlink-ipc.c | 878 + include/linux/xlink-ipc.h | 48 ++ 9 files changed, 997 insertions(+) create mode 100644 Documentation/vpu/xlink-ipc.rst create mode 100644 drivers/misc/xlink-ipc/Kconfig create mode 100644 drivers/misc/xlink-ipc/Makefile create mode 100644 drivers/misc/xlink-ipc/xlink-ipc.c create mode 100644 include/linux/xlink-ipc.h diff --git a/Documentation/vpu/index.rst b/Documentation/vpu/index.rst index 661cc700ee45..49c78bb65b83 100644 --- a/Documentation/vpu/index.rst +++ b/Documentation/vpu/index.rst @@ -15,3 +15,4 @@ This documentation contains information for the Intel VPU stack. vpu-stack-overview xlink-pcie + xlink-ipc diff --git a/Documentation/vpu/xlink-ipc.rst b/Documentation/vpu/xlink-ipc.rst new file mode 100644 index ..97ee62b10e93 --- /dev/null +++ b/Documentation/vpu/xlink-ipc.rst @@ -0,0 +1,51 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=== +Kernel driver: xLink IPC driver +=== + +Supported chips: + +* | Intel Edge.AI Computer Vision platforms: Keem Bay + | Suffix: Bay + | Datasheet: (not yet publicly available) + +Introduction + + +The xLink IPC driver interfaces the xLink Core driver with the Keem Bay VPU IPC +driver, thus enabling xLink to control and communicate with the VPU IP present +on the Intel Keem Bay SoC. + +Specifically the driver enables xLink Core to: + +* Boot / Reset the VPU IP +* Register to VPU IP event notifications (device connected, device disconnected, + WDT event) +* Query the status of the VPU IP (OFF, BUSY, READY, ERROR, RECOVERY) +* Exchange data with the VPU IP, using the Keem Bay IPC mechanism + + * Including the ability to send 'volatile' data (i.e. small amounts of data, +up to 128-bytes that was not allocated in the CPU/VPU shared memory region) + +Sending / Receiving 'volatile' data +=== + +Data to be exchanged with Keem Bay IPC needs to be allocated in the portion of +DDR shared between the CPU and VPU. + +This can be impractical for small amounts of data that user code can allocate +on the stack. + +To reduce the burden on user code, xLink Core provides special send / receive +functions to send up to 128 bytes of 'volatile data', i.e., data that is not +allocated in the shared memory and that might also disappear after the xLink +API is called (e.g., because allocated on the stack). + +The xLink IPC driver implements support for transferring such 'volatile data' +to the VPU using Keem Bay IPC. To this end, the driver reserves some memory in +the shared memory region. + +When volatile data is to be sent, xLink IPC allocates a buffer from the +reserved memory region and copies the volatile data to the buffer. The buffer +is then transferred to the VPU using Keem Bay IPC. diff --git a/MAINTAINERS b/MAINTAINERS index e05fa34d72ce..22a7a1b03601 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1961,6 +1961,12 @@ F: Documentation/devicetree/bindings/arm/intel,keembay.yaml F: arch/arm64/boot/dts/intel/keembay-evm.dts F: arch/arm64/boot/dts/intel/keembay-soc.dtsi +ARM/INTEL XLINK IPC SUPPORT +M: Seamus Kelly +M: Mark Gross +S: Supported +F: drivers/misc/xlink-ipc/ + ARM/INTEL KEEM BAY XLINK PCIE SUPPORT M: Srikanth Thokala M: Mark Gross diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index dfb98e444c6e..1f81ea915b95 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -482,4 +482,5 @@ source "drivers/misc/cardreader/Kconfig" source "drivers/misc/habanalabs/Kconfig" source "drivers/misc/uacce/Kconfig" source "drivers/misc/xlink-pcie/Kconfig" +source "drivers/misc/xlink-ipc/Kconfig" endmenu diff --gi
