Re: [PATCH 2/3] ARM: dts: Add DP PHY node to exynos5250.dtsi

[Hui Wang]

On 06/28/2013 01:58 PM, Jingoo Han wrote:

On Friday, June 28, 2013 2:42 PM, Kishon Vijay Abraham I wrote:

Hi,

On Friday 28 June 2013 10:53 AM, Jingoo Han wrote:

Add PHY provider node for the DP PHY.

Signed-off-by: Jingoo Han 
---
   arch/arm/boot/dts/exynos5250.dtsi |   13 -
   1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 41cd625..d1d6e14 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -614,6 +614,12 @@
interrupts = <0 94 0>;
};

+   dp_phy: video-phy@10040720 {
+   compatible = "samsung,exynos5250-dp-video-phy";
+   reg = <0x10040720 4>;
+   #phy-cells = <1>;

phy-cells can be '0' here since this phy_provider implements only one PHY.

Oh, thank you.
I will fix it.
Don't forget to fix the corresponding description in the 
samsung,exynos5250-dp-video-phy.txt as well. :-)

Best regards,
Jingoo Han


Thanks
Kishon

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Re: [PATCH v3 1/5] phy: Add driver for Exynos MIPI CSIS/DSIM DPHYs

[Hui Wang]

On 06/26/2013 11:02 PM, Sylwester Nawrocki wrote:

Add a PHY provider driver for the Samsung S5P/Exynos SoC MIPI CSI-2
receiver and MIPI DSI transmitter DPHYs.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
Changes since v2:
  - adapted to the generic PHY API v9: use phy_set/get_drvdata(),
  - fixed of_xlate callback to return ERR_PTR() instead of NULL,
  - namespace cleanup, put "GPL v2" as MODULE_LICENSE, removed pr_debug,
  - removed phy id check in __set_phy_state().
---

[...]

+
+   if (IS_EXYNOS_MIPI_DSIM_PHY_ID(id))
+   reset = EXYNOS_MIPI_PHY_MRESETN;
+   else
+   reset = EXYNOS_MIPI_PHY_SRESETN;
+
+   spin_lock_irqsave(&state->slock, flags);
Sorry for one stupid question here, why do you use spin_lock_irqsave() 
rather than spin_lock(),

I don't see the irq handler will use this spinlock anywhere in this c file.


Regards,
Hui.

+   reg = readl(addr);
+   if (on)
+   reg |= reset;
+   else
+   reg &= ~reset;
+   writel(reg, addr);
+
+   /* Clear ENABLE bit only if MRESETN, SRESETN bits are not set. */
+   if (on)
+   reg |= EXYNOS_MIPI_PHY_ENABLE;
+   else if (!(reg & EXYNOS_MIPI_PHY_RESET_MASK))
+   reg &= ~EXYNOS_MIPI_PHY_ENABLE;
+
+   writel(reg, addr);
+   spin_unlock_irqrestore(&state->slock, flags);
+   return 0;
+}



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