Re: [PATCH] [media] v4l2-dv-timings.h: CEA-861-F 4K timings have positive sync polarities

2016-04-25 Thread Hans Verkuil 
On 04/25/2016 10:51 AM, Martin Bugge wrote:
> Corrected sync polarities for CEA-861-F timings
> 3840x2160p24/25/30/50/60 and 4096x2160p24/25/30/50/60.

I posted this fix on Friday:

https://patchwork.linuxtv.org/patch/33963/

If you don't mind I'll go with that one.

Regards,

Hans

> 
> Cc: Hans Verkuil 
> Signed-off-by: Martin Bugge 
> ---
>  include/uapi/linux/v4l2-dv-timings.h | 30 --
>  1 file changed, 20 insertions(+), 10 deletions(-)
> 
> diff --git a/include/uapi/linux/v4l2-dv-timings.h 
> b/include/uapi/linux/v4l2-dv-timings.h
> index c039f1d..086168e 100644
> --- a/include/uapi/linux/v4l2-dv-timings.h
> +++ b/include/uapi/linux/v4l2-dv-timings.h
> @@ -183,7 +183,8 @@
>  
>  #define V4L2_DV_BT_CEA_3840X2160P24 { \
>   .type = V4L2_DV_BT_656_1120, \
> - V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
> + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
> + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
>   29700, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
>   V4L2_DV_BT_STD_CEA861, \
>   V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
> @@ -191,14 +192,16 @@
>  
>  #define V4L2_DV_BT_CEA_3840X2160P25 { \
>   .type = V4L2_DV_BT_656_1120, \
> - V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
> + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
> + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
>   29700, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
>   V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
>  }
>  
>  #define V4L2_DV_BT_CEA_3840X2160P30 { \
>   .type = V4L2_DV_BT_656_1120, \
> - V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
> + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
> + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
>   29700, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
>   V4L2_DV_BT_STD_CEA861, \
>   V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
> @@ -206,14 +209,16 @@
>  
>  #define V4L2_DV_BT_CEA_3840X2160P50 { \
>   .type = V4L2_DV_BT_656_1120, \
> - V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
> + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
> + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
>   59400, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
>   V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
>  }
>  
>  #define V4L2_DV_BT_CEA_3840X2160P60 { \
>   .type = V4L2_DV_BT_656_1120, \
> - V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
> + V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
> + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
>   59400, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
>   V4L2_DV_BT_STD_CEA861, \
>   V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
> @@ -221,7 +226,8 @@
>  
>  #define V4L2_DV_BT_CEA_4096X2160P24 { \
>   .type = V4L2_DV_BT_656_1120, \
> - V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
> + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
> + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
>   29700, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
>   V4L2_DV_BT_STD_CEA861, \
>   V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
> @@ -229,14 +235,16 @@
>  
>  #define V4L2_DV_BT_CEA_4096X2160P25 { \
>   .type = V4L2_DV_BT_656_1120, \
> - V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
> + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
> + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
>   29700, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
>   V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
>  }
>  
>  #define V4L2_DV_BT_CEA_4096X2160P30 { \
>   .type = V4L2_DV_BT_656_1120, \
> - V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
> + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
> + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
>   29700, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
>   V4L2_DV_BT_STD_CEA861, \
>   V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
> @@ -244,14 +252,16 @@
>  
>  #define V4L2_DV_BT_CEA_4096X2160P50 { \
>   .type = V4L2_DV_BT_656_1120, \
> - V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
> + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
> + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
>   59400, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
>   V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
>  }
>  
>  #define V4L2_DV_BT_CEA_4096X2160P60 { \
>   .type = V4L2_DV_BT_656_1120, \
> - V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
> + V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
> + V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
>   59400, 88, 88, 128, 8, 10,

[PATCH] [media] v4l2-dv-timings.h: CEA-861-F 4K timings have positive sync polarities

2016-04-25 Thread Martin Bugge 
Corrected sync polarities for CEA-861-F timings
3840x2160p24/25/30/50/60 and 4096x2160p24/25/30/50/60.

Cc: Hans Verkuil 
Signed-off-by: Martin Bugge 
---
 include/uapi/linux/v4l2-dv-timings.h | 30 --
 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/include/uapi/linux/v4l2-dv-timings.h 
b/include/uapi/linux/v4l2-dv-timings.h
index c039f1d..086168e 100644
--- a/include/uapi/linux/v4l2-dv-timings.h
+++ b/include/uapi/linux/v4l2-dv-timings.h
@@ -183,7 +183,8 @@
 
 #define V4L2_DV_BT_CEA_3840X2160P24 { \
.type = V4L2_DV_BT_656_1120, \
-   V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+   V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
29700, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, \
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -191,14 +192,16 @@
 
 #define V4L2_DV_BT_CEA_3840X2160P25 { \
.type = V4L2_DV_BT_656_1120, \
-   V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+   V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
29700, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
 }
 
 #define V4L2_DV_BT_CEA_3840X2160P30 { \
.type = V4L2_DV_BT_656_1120, \
-   V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+   V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
29700, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, \
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -206,14 +209,16 @@
 
 #define V4L2_DV_BT_CEA_3840X2160P50 { \
.type = V4L2_DV_BT_656_1120, \
-   V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+   V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
59400, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
 }
 
 #define V4L2_DV_BT_CEA_3840X2160P60 { \
.type = V4L2_DV_BT_656_1120, \
-   V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+   V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
59400, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, \
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -221,7 +226,8 @@
 
 #define V4L2_DV_BT_CEA_4096X2160P24 { \
.type = V4L2_DV_BT_656_1120, \
-   V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+   V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
29700, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, \
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -229,14 +235,16 @@
 
 #define V4L2_DV_BT_CEA_4096X2160P25 { \
.type = V4L2_DV_BT_656_1120, \
-   V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+   V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
29700, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
 }
 
 #define V4L2_DV_BT_CEA_4096X2160P30 { \
.type = V4L2_DV_BT_656_1120, \
-   V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+   V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
29700, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, \
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -244,14 +252,16 @@
 
 #define V4L2_DV_BT_CEA_4096X2160P50 { \
.type = V4L2_DV_BT_656_1120, \
-   V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+   V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
59400, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
 }
 
 #define V4L2_DV_BT_CEA_4096X2160P60 { \
.type = V4L2_DV_BT_656_1120, \
-   V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
+   V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
59400, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, \
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
-- 
2.4.11

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