[PATCH 1/2] mn88472: load demodulator register defaults

2014-12-07 Thread Benjamin Larsson 
Signed-off-by: Benjamin Larsson benja...@southpole.se
---
 drivers/staging/media/mn88472/mn88472.c  |  21 +
 drivers/staging/media/mn88472/mn88472_priv.h | 558 +++
 2 files changed, 579 insertions(+)

diff --git a/drivers/staging/media/mn88472/mn88472.c 
b/drivers/staging/media/mn88472/mn88472.c
index be8a6d5..ffee187 100644
--- a/drivers/staging/media/mn88472/mn88472.c
+++ b/drivers/staging/media/mn88472/mn88472.c
@@ -272,6 +272,20 @@ err:
return ret;
 }
 
+static int mn88472_load_defaults(struct mn88472_dev *dev)
+{
+   int i, ret = 0;
+
+   for (i = 0 ; i  sizeof(mn88472_init_tab)/sizeof(struct idx_num_val)
+   ; i++) {
+   ret |= regmap_write(dev-regmap[mn88472_init_tab[i].reg_idx],
+   mn88472_init_tab[i].reg_num,
+   mn88472_init_tab[i].reg_val);
+   }
+
+   return ret;
+}
+
 static int mn88472_init(struct dvb_frontend *fe)
 {
struct i2c_client *client = fe-demodulator_priv;
@@ -294,6 +308,13 @@ static int mn88472_init(struct dvb_frontend *fe)
if (ret)
goto err;
 
+   /* load register defaults */
+   ret = mn88472_load_defaults(dev);
+   if (ret) {
+   dev_err(client-dev, register defaults failed\n);
+   goto err;
+   }
+
/* request the firmware, this will block and timeout */
ret = request_firmware(fw, fw_file, client-dev);
if (ret) {
diff --git a/drivers/staging/media/mn88472/mn88472_priv.h 
b/drivers/staging/media/mn88472/mn88472_priv.h
index 9ba8c8b..b77ff1e 100644
--- a/drivers/staging/media/mn88472/mn88472_priv.h
+++ b/drivers/staging/media/mn88472/mn88472_priv.h
@@ -36,4 +36,562 @@ struct mn88472_dev {
int ts_clock;
 };
 
+struct idx_num_val {
+   unsigned char reg_idx;
+   unsigned char reg_num;
+   unsigned char reg_val;
+};
+
+struct idx_num_val mn88472_init_tab[] = {
+{ 2, 0x00, 0x66 },
+{ 2, 0x01, 0x00 },
+{ 2, 0x02, 0x01 },
+{ 2, 0x03, 0x03 },
+{ 2, 0x04, 0x00 },
+{ 2, 0x05, 0x00 },
+{ 2, 0x06, 0x00 },
+{ 2, 0x07, 0x00 },
+{ 2, 0x08, 0x00 },
+{ 2, 0x09, 0x00 },
+{ 2, 0x0a, 0x00 },
+{ 2, 0x0b, 0x00 },
+{ 2, 0x0c, 0x00 },
+{ 2, 0x0d, 0x00 },
+{ 2, 0x0e, 0x00 },
+{ 2, 0x0f, 0x00 },
+{ 2, 0x10, 0x3e },
+{ 2, 0x11, 0x70 },
+{ 2, 0x12, 0x64 },
+{ 2, 0x13, 0x8f },
+{ 2, 0x14, 0x80 },
+{ 2, 0x15, 0x00 },
+{ 2, 0x16, 0x08 },
+{ 2, 0x17, 0xee },
+{ 2, 0x18, 0x08 },
+{ 2, 0x19, 0xee },
+{ 2, 0x1a, 0x43 },
+{ 2, 0x1b, 0x00 },
+{ 2, 0x1c, 0x74 },
+{ 2, 0x1d, 0xe4 },
+{ 2, 0x1e, 0x26 },
+{ 2, 0x1f, 0x4f },
+{ 2, 0x20, 0x72 },
+{ 2, 0x21, 0x22 },
+{ 2, 0x22, 0x22 },
+{ 2, 0x23, 0x01 },
+{ 2, 0x24, 0x00 },
+{ 2, 0x25, 0x12 },
+{ 2, 0x26, 0x00 },
+{ 2, 0x27, 0x00 },
+{ 2, 0x28, 0x80 },
+{ 2, 0x29, 0x0c },
+{ 2, 0x2a, 0xf4 },
+{ 2, 0x2b, 0x13 },
+{ 2, 0x2c, 0x00 },
+{ 2, 0x2d, 0x20 },
+{ 2, 0x2e, 0x88 },
+{ 2, 0x2f, 0x00 },
+{ 2, 0x30, 0x80 },
+{ 2, 0x31, 0x80 },
+{ 2, 0x32, 0x00 },
+{ 2, 0x33, 0x00 },
+{ 2, 0x34, 0x00 },
+{ 2, 0x35, 0x00 },
+{ 2, 0x36, 0x00 },
+{ 2, 0x37, 0x00 },
+{ 2, 0x38, 0xca },
+{ 2, 0x39, 0x03 },
+{ 2, 0x3a, 0x02 },
+{ 2, 0x3b, 0x55 },
+{ 2, 0x3c, 0xd7 },
+{ 2, 0x3d, 0x00 },
+{ 2, 0x3e, 0x00 },
+{ 2, 0x3f, 0x22 },
+{ 2, 0x40, 0x00 },
+{ 2, 0x41, 0x38 },
+{ 2, 0x42, 0x22 },
+{ 2, 0x43, 0x00 },
+{ 2, 0x44, 0x38 },
+{ 2, 0x45, 0xd3 },
+{ 2, 0x46, 0x10 },
+{ 2, 0x47, 0xb5 },
+{ 2, 0x48, 0xa1 },
+{ 2, 0x49, 0x00 },
+{ 2, 0x4a, 0xd3 },
+{ 2, 0x4b, 0x07 },
+{ 2, 0x4c, 0x64 },
+{ 2, 0x4d, 0x0d },
+{ 2, 0x4e, 0x00 },
+{ 2, 0x4f, 0x05 },
+{ 2, 0x50, 0x00 },
+{ 2, 0x51, 0x55 },
+{ 2, 0x52, 0x20 },
+{ 2, 0x53, 0x00 },
+{ 2, 0x54, 0x24 },
+{ 2, 0x55, 0x64 },
+{ 2, 0x56, 0x44 },
+{ 2, 0x57, 0x33 },
+{ 2, 0x58, 0x1f },
+{ 2, 0x59, 0x00 },
+{ 2, 0x5a, 0x5a },
+{ 2, 0x5b, 0x03 },
+{ 2, 0x5c, 0xc0 },
+{ 2, 0x5d, 0x00 },
+{ 2, 0x5e, 0x00 },
+{ 2, 0x5f, 0x03 },
+{ 2, 0x60, 0x00 },
+{ 2, 0x61, 0x00 },
+{ 2, 0x62, 0x11 },
+{ 2, 0x63, 0x40 },
+{ 2, 0x64, 0x84 },
+{ 2, 0x65, 0x04 },
+{ 2, 0x66, 0x0c },
+{ 2, 0x67, 0x00 },
+{ 2, 0x68, 0x08 },
+{ 2, 0x69, 0x00 },
+{ 2, 0x6a, 0x00 },
+{ 2, 0x6b, 0x12 },
+{ 2, 0x6c, 0x21 },
+{ 2, 0x6d, 0x10 },
+{ 2, 0x6e, 0x01 },
+{ 2, 0x6f, 0x00 },
+{ 2, 0x70, 0x00 },
+{ 2, 0x71, 0x00 },
+{ 2, 0x72, 0xe8 },
+{ 2, 0x73, 0x48 },
+{ 2, 0x74, 0x40 },
+{ 2, 0x75, 0x00 },
+{ 2, 0x76, 0x1d },
+{ 2, 0x77, 0x19 },
+{ 2, 0x78, 0x1d },
+{ 2, 0x79, 0x19 },
+{ 2, 0x7a, 0x66 },
+{ 2, 0x7b, 0x8c },
+{ 2, 0x7c, 0x9f },
+{ 2, 0x7d, 0x08 },
+{ 2, 0x7e, 0x00 },
+{ 2, 0x7f, 0x00 },
+{ 2, 0x80, 0x00 },
+{ 2, 0x81, 0x00 },
+{ 2, 0x83, 0x00 },
+{ 2, 0x84, 0x00 },
+{ 2, 0x85, 0x00 },
+{ 2, 0x86, 0x00 },
+{ 2, 0x87, 0x00 },
+{ 2, 0x88, 0x00 },
+{ 2, 0x89, 0x00 },
+{ 2, 0x8a, 0x20 },
+{ 2, 0x8b, 0x49 },
+{ 2, 0x8c, 0x00 },
+{ 2, 0xc4, 0x00 },
+{ 2, 0xc5, 0x00 },
+{ 2, 0xc6, 0x00 },
+{ 2, 0xc7, 0x87 },
+{ 2, 0xc8, 0x40 },
+{ 2, 0xc9, 0x30 },
+{ 2, 0xca, 0x06 },
+{ 2, 0xcb, 0x02 },
+{ 2, 0xcc, 0x00 },
+{ 2, 0xcd, 0x3b },
+{ 2,

Re: [PATCH 1/2] mn88472: load demodulator register defaults

2014-12-07 Thread Antti Palosaari 

Moikka!
I don't like that at *all*. It is totally bad idea to write 550 
registers to default and even more bad it is done as single register 
at once. It is huge amount of I/O traffic in a situation device has 
problems with I/O. Did you even compared are those registers already 
same than POR (power on reset)?


550 registers means basically writing every single register of that 
chip. It is hard to imagine chip designers has made that bad mistake and 
set wrong default value for every register.


There is regmap already used, you likely need to learn what are POR 
default values and which registers need to be changed. Then teach all 
that info to RegMap and it will do shadow registering (to reduce I/O).


regard
Antti



On 12/08/2014 12:10 AM, Benjamin Larsson wrote:

Signed-off-by: Benjamin Larsson benja...@southpole.se
---
  drivers/staging/media/mn88472/mn88472.c  |  21 +
  drivers/staging/media/mn88472/mn88472_priv.h | 558 +++
  2 files changed, 579 insertions(+)

diff --git a/drivers/staging/media/mn88472/mn88472.c 
b/drivers/staging/media/mn88472/mn88472.c
index be8a6d5..ffee187 100644
--- a/drivers/staging/media/mn88472/mn88472.c
+++ b/drivers/staging/media/mn88472/mn88472.c
@@ -272,6 +272,20 @@ err:
return ret;
  }

+static int mn88472_load_defaults(struct mn88472_dev *dev)
+{
+   int i, ret = 0;
+
+   for (i = 0 ; i  sizeof(mn88472_init_tab)/sizeof(struct idx_num_val)
+   ; i++) {
+   ret |= regmap_write(dev-regmap[mn88472_init_tab[i].reg_idx],
+   mn88472_init_tab[i].reg_num,
+   mn88472_init_tab[i].reg_val);
+   }
+
+   return ret;
+}
+
  static int mn88472_init(struct dvb_frontend *fe)
  {
struct i2c_client *client = fe-demodulator_priv;
@@ -294,6 +308,13 @@ static int mn88472_init(struct dvb_frontend *fe)
if (ret)
goto err;

+   /* load register defaults */
+   ret = mn88472_load_defaults(dev);
+   if (ret) {
+   dev_err(client-dev, register defaults failed\n);
+   goto err;
+   }
+
/* request the firmware, this will block and timeout */
ret = request_firmware(fw, fw_file, client-dev);
if (ret) {
diff --git a/drivers/staging/media/mn88472/mn88472_priv.h 
b/drivers/staging/media/mn88472/mn88472_priv.h
index 9ba8c8b..b77ff1e 100644
--- a/drivers/staging/media/mn88472/mn88472_priv.h
+++ b/drivers/staging/media/mn88472/mn88472_priv.h
@@ -36,4 +36,562 @@ struct mn88472_dev {
int ts_clock;
  };

+struct idx_num_val {
+   unsigned char reg_idx;
+   unsigned char reg_num;
+   unsigned char reg_val;
+};
+
+struct idx_num_val mn88472_init_tab[] = {
+{ 2, 0x00, 0x66 },
+{ 2, 0x01, 0x00 },
+{ 2, 0x02, 0x01 },
+{ 2, 0x03, 0x03 },
+{ 2, 0x04, 0x00 },
+{ 2, 0x05, 0x00 },
+{ 2, 0x06, 0x00 },
+{ 2, 0x07, 0x00 },
+{ 2, 0x08, 0x00 },
+{ 2, 0x09, 0x00 },
+{ 2, 0x0a, 0x00 },
+{ 2, 0x0b, 0x00 },
+{ 2, 0x0c, 0x00 },
+{ 2, 0x0d, 0x00 },
+{ 2, 0x0e, 0x00 },
+{ 2, 0x0f, 0x00 },
+{ 2, 0x10, 0x3e },
+{ 2, 0x11, 0x70 },
+{ 2, 0x12, 0x64 },
+{ 2, 0x13, 0x8f },
+{ 2, 0x14, 0x80 },
+{ 2, 0x15, 0x00 },
+{ 2, 0x16, 0x08 },
+{ 2, 0x17, 0xee },
+{ 2, 0x18, 0x08 },
+{ 2, 0x19, 0xee },
+{ 2, 0x1a, 0x43 },
+{ 2, 0x1b, 0x00 },
+{ 2, 0x1c, 0x74 },
+{ 2, 0x1d, 0xe4 },
+{ 2, 0x1e, 0x26 },
+{ 2, 0x1f, 0x4f },
+{ 2, 0x20, 0x72 },
+{ 2, 0x21, 0x22 },
+{ 2, 0x22, 0x22 },
+{ 2, 0x23, 0x01 },
+{ 2, 0x24, 0x00 },
+{ 2, 0x25, 0x12 },
+{ 2, 0x26, 0x00 },
+{ 2, 0x27, 0x00 },
+{ 2, 0x28, 0x80 },
+{ 2, 0x29, 0x0c },
+{ 2, 0x2a, 0xf4 },
+{ 2, 0x2b, 0x13 },
+{ 2, 0x2c, 0x00 },
+{ 2, 0x2d, 0x20 },
+{ 2, 0x2e, 0x88 },
+{ 2, 0x2f, 0x00 },
+{ 2, 0x30, 0x80 },
+{ 2, 0x31, 0x80 },
+{ 2, 0x32, 0x00 },
+{ 2, 0x33, 0x00 },
+{ 2, 0x34, 0x00 },
+{ 2, 0x35, 0x00 },
+{ 2, 0x36, 0x00 },
+{ 2, 0x37, 0x00 },
+{ 2, 0x38, 0xca },
+{ 2, 0x39, 0x03 },
+{ 2, 0x3a, 0x02 },
+{ 2, 0x3b, 0x55 },
+{ 2, 0x3c, 0xd7 },
+{ 2, 0x3d, 0x00 },
+{ 2, 0x3e, 0x00 },
+{ 2, 0x3f, 0x22 },
+{ 2, 0x40, 0x00 },
+{ 2, 0x41, 0x38 },
+{ 2, 0x42, 0x22 },
+{ 2, 0x43, 0x00 },
+{ 2, 0x44, 0x38 },
+{ 2, 0x45, 0xd3 },
+{ 2, 0x46, 0x10 },
+{ 2, 0x47, 0xb5 },
+{ 2, 0x48, 0xa1 },
+{ 2, 0x49, 0x00 },
+{ 2, 0x4a, 0xd3 },
+{ 2, 0x4b, 0x07 },
+{ 2, 0x4c, 0x64 },
+{ 2, 0x4d, 0x0d },
+{ 2, 0x4e, 0x00 },
+{ 2, 0x4f, 0x05 },
+{ 2, 0x50, 0x00 },
+{ 2, 0x51, 0x55 },
+{ 2, 0x52, 0x20 },
+{ 2, 0x53, 0x00 },
+{ 2, 0x54, 0x24 },
+{ 2, 0x55, 0x64 },
+{ 2, 0x56, 0x44 },
+{ 2, 0x57, 0x33 },
+{ 2, 0x58, 0x1f },
+{ 2, 0x59, 0x00 },
+{ 2, 0x5a, 0x5a },
+{ 2, 0x5b, 0x03 },
+{ 2, 0x5c, 0xc0 },
+{ 2, 0x5d, 0x00 },
+{ 2, 0x5e, 0x00 },
+{ 2, 0x5f, 0x03 },
+{ 2, 0x60, 0x00 },
+{ 2, 0x61, 0x00 },
+{ 2, 0x62, 0x11 },
+{ 2, 0x63, 0x40 },
+{ 2, 0x64, 0x84 },
+{ 2, 0x65, 0x04 },
+{ 2, 0x66, 0x0c },
+{ 2, 0x67, 0x00 },
+{ 2, 0x68, 0x08 },
+{ 2, 0x69, 0x00 },
+{ 2, 0x6a, 0x00 },
+{ 2, 0x6b, 0x12 },
+{ 2, 0x6c, 0x21 },
+{ 2, 0x6d, 0x10 },
+{ 2, 0x6e, 0x01