[PATCH v3 36/48] adv7604: Make output format configurable through pad format operations
Replace the dummy video format operations by pad format operations that configure the output format. Signed-off-by: Laurent Pinchart --- drivers/media/i2c/adv7604.c | 280 include/media/adv7604.h | 56 - 2 files changed, 275 insertions(+), 61 deletions(-) diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c index 851b350..5aa7c29 100644 --- a/drivers/media/i2c/adv7604.c +++ b/drivers/media/i2c/adv7604.c @@ -53,6 +53,28 @@ MODULE_LICENSE("GPL"); /* ADV7604 system clock frequency */ #define ADV7604_fsc (28636360) +#define ADV7604_RGB_OUT(1 << 1) + +#define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0) +#define ADV7604_OP_FORMAT_SEL_10BIT(1 << 0) +#define ADV7604_OP_FORMAT_SEL_12BIT(2 << 0) + +#define ADV7604_OP_MODE_SEL_SDR_422(0 << 5) +#define ADV7604_OP_MODE_SEL_DDR_422(1 << 5) +#define ADV7604_OP_MODE_SEL_SDR_444(2 << 5) +#define ADV7604_OP_MODE_SEL_DDR_444(3 << 5) +#define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5) +#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) + +#define ADV7604_OP_CH_SEL_GBR (0 << 5) +#define ADV7604_OP_CH_SEL_GRB (1 << 5) +#define ADV7604_OP_CH_SEL_BGR (2 << 5) +#define ADV7604_OP_CH_SEL_RGB (3 << 5) +#define ADV7604_OP_CH_SEL_BRG (4 << 5) +#define ADV7604_OP_CH_SEL_RBG (5 << 5) + +#define ADV7604_OP_SWAP_CB_CR (1 << 0) + enum adv7604_type { ADV7604, ADV7611, @@ -63,6 +85,14 @@ struct adv7604_reg_seq { u8 val; }; +struct adv7604_format_info { + enum v4l2_mbus_pixelcode code; + u8 op_ch_sel; + bool rgb_out; + bool swap_cb_cr; + u8 op_format_sel; +}; + struct adv7604_chip_info { enum adv7604_type type; @@ -78,6 +108,9 @@ struct adv7604_chip_info { unsigned int tdms_lock_mask; unsigned int fmt_change_digital_mask; + const struct adv7604_format_info *formats; + unsigned int nformats; + void (*set_termination)(struct v4l2_subdev *sd, bool enable); void (*setup_irqs)(struct v4l2_subdev *sd); unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); @@ -101,12 +134,18 @@ struct adv7604_chip_info { struct adv7604_state { const struct adv7604_chip_info *info; struct adv7604_platform_data pdata; + struct v4l2_subdev sd; struct media_pad pads[ADV7604_PAD_MAX]; unsigned int source_pad; + struct v4l2_ctrl_handler hdl; + enum adv7604_pad selected_input; + struct v4l2_dv_timings timings; + const struct adv7604_format_info *format; + struct { u8 edid[256]; u32 present; @@ -771,6 +810,93 @@ static void adv7604_write_reg_seq(struct v4l2_subdev *sd, adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); } +/* - + * Format helpers + */ + +static const struct adv7604_format_info adv7604_formats[] = { + { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, + ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, + { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, + { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, + { V4L2_MBUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false, + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, + { V4L2_MBUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true, + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, + { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, + { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, + { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, + { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, + { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, + { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, + { V4L2_MBUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false
Re: [PATCH v3 36/48] adv7604: Make output format configurable through pad format operations
On 03/11/2014 04:10 PM, Laurent Pinchart wrote: > Replace the dummy video format operations by pad format operations that > configure the output format. > > Signed-off-by: Laurent Pinchart My apologies, I completely forgot to test this today. It's going to be Tuesday, I'm afraid. Sorry, Hans -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 36/48] adv7604: Make output format configurable through pad format operations
Hi Laurent, I've tested it and I thought I was going crazy. Everything was fine after applying this patch, but as soon as I applied the next patch (37/48) the colors were wrong. But that patch had nothing whatsoever to do with the bus ordering. You managed to make a small but crucial bug and it was pure bad luck that it ever worked. See details below: On 03/11/14 16:10, Laurent Pinchart wrote: > Replace the dummy video format operations by pad format operations that > configure the output format. > > Signed-off-by: Laurent Pinchart > --- > drivers/media/i2c/adv7604.c | 280 > > include/media/adv7604.h | 56 - > 2 files changed, 275 insertions(+), 61 deletions(-) > > diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c > index 851b350..5aa7c29 100644 > --- a/drivers/media/i2c/adv7604.c > +++ b/drivers/media/i2c/adv7604.c > @@ -53,6 +53,28 @@ MODULE_LICENSE("GPL"); > /* ADV7604 system clock frequency */ > #define ADV7604_fsc (28636360) > > +#define ADV7604_RGB_OUT (1 << 1) > + > +#define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0) > +#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) > +#define ADV7604_OP_FORMAT_SEL_12BIT (2 << 0) > + > +#define ADV7604_OP_MODE_SEL_SDR_422 (0 << 5) > +#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) > +#define ADV7604_OP_MODE_SEL_SDR_444 (2 << 5) > +#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) > +#define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5) > +#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) > + > +#define ADV7604_OP_CH_SEL_GBR(0 << 5) > +#define ADV7604_OP_CH_SEL_GRB(1 << 5) > +#define ADV7604_OP_CH_SEL_BGR(2 << 5) > +#define ADV7604_OP_CH_SEL_RGB(3 << 5) > +#define ADV7604_OP_CH_SEL_BRG(4 << 5) > +#define ADV7604_OP_CH_SEL_RBG(5 << 5) Note that these values are shifted 5 bits to the left... > + > +#define ADV7604_OP_SWAP_CB_CR(1 << 0) > + > enum adv7604_type { > ADV7604, > ADV7611, > @@ -63,6 +85,14 @@ struct adv7604_reg_seq { > u8 val; > }; > > +struct adv7604_format_info { > + enum v4l2_mbus_pixelcode code; > + u8 op_ch_sel; > + bool rgb_out; > + bool swap_cb_cr; > + u8 op_format_sel; > +}; > + > struct adv7604_chip_info { > enum adv7604_type type; > > @@ -78,6 +108,9 @@ struct adv7604_chip_info { > unsigned int tdms_lock_mask; > unsigned int fmt_change_digital_mask; > > + const struct adv7604_format_info *formats; > + unsigned int nformats; > + > void (*set_termination)(struct v4l2_subdev *sd, bool enable); > void (*setup_irqs)(struct v4l2_subdev *sd); > unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); > @@ -101,12 +134,18 @@ struct adv7604_chip_info { > struct adv7604_state { > const struct adv7604_chip_info *info; > struct adv7604_platform_data pdata; > + > struct v4l2_subdev sd; > struct media_pad pads[ADV7604_PAD_MAX]; > unsigned int source_pad; > + > struct v4l2_ctrl_handler hdl; > + > enum adv7604_pad selected_input; > + > struct v4l2_dv_timings timings; > + const struct adv7604_format_info *format; > + > struct { > u8 edid[256]; > u32 present; > @@ -771,6 +810,93 @@ static void adv7604_write_reg_seq(struct v4l2_subdev *sd, > adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); > } > > +/* > - > + * Format helpers > + */ > + > +static const struct adv7604_format_info adv7604_formats[] = { > + { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, > + ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, > + { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, > + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, > + { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, > + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, > + { V4L2_MBUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false, > + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, > + { V4L2_MBUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true, > + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, > + { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, > + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, > + { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, > + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, > + { V4L2_MBUS_FMT_UYVY
Re: [PATCH v3 36/48] adv7604: Make output format configurable through pad format operations
Hi Hans, On Tuesday 18 March 2014 10:32:32 Hans Verkuil wrote: > Hi Laurent, > > I've tested it and I thought I was going crazy. Everything was fine after > applying this patch, but as soon as I applied the next patch (37/48) the > colors were wrong. But that patch had nothing whatsoever to do with the > bus ordering. You managed to make a small but crucial bug and it was pure > bad luck that it ever worked. > > See details below: > > On 03/11/14 16:10, Laurent Pinchart wrote: > > Replace the dummy video format operations by pad format operations that > > configure the output format. > > > > Signed-off-by: Laurent Pinchart > > --- > > > > drivers/media/i2c/adv7604.c | 280 +++ > > include/media/adv7604.h | 56 - > > 2 files changed, 275 insertions(+), 61 deletions(-) > > > > diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c > > index 851b350..5aa7c29 100644 > > --- a/drivers/media/i2c/adv7604.c > > +++ b/drivers/media/i2c/adv7604.c > > @@ -53,6 +53,28 @@ MODULE_LICENSE("GPL"); > > > > /* ADV7604 system clock frequency */ > > #define ADV7604_fsc (28636360) > > > > +#define ADV7604_RGB_OUT(1 << 1) > > + > > +#define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0) > > +#define ADV7604_OP_FORMAT_SEL_10BIT(1 << 0) > > +#define ADV7604_OP_FORMAT_SEL_12BIT(2 << 0) > > + > > +#define ADV7604_OP_MODE_SEL_SDR_422(0 << 5) > > +#define ADV7604_OP_MODE_SEL_DDR_422(1 << 5) > > +#define ADV7604_OP_MODE_SEL_SDR_444(2 << 5) > > +#define ADV7604_OP_MODE_SEL_DDR_444(3 << 5) > > +#define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5) > > +#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) > > + > > +#define ADV7604_OP_CH_SEL_GBR (0 << 5) > > +#define ADV7604_OP_CH_SEL_GRB (1 << 5) > > +#define ADV7604_OP_CH_SEL_BGR (2 << 5) > > +#define ADV7604_OP_CH_SEL_RGB (3 << 5) > > +#define ADV7604_OP_CH_SEL_BRG (4 << 5) > > +#define ADV7604_OP_CH_SEL_RBG (5 << 5) > > Note that these values are shifted 5 bits to the left... [snip] > > +struct adv7604_format_info { > > + enum v4l2_mbus_pixelcode code; > > + u8 op_ch_sel; > > + bool rgb_out; > > + bool swap_cb_cr; > > + u8 op_format_sel; > > +}; [snip] > > +static const struct adv7604_format_info adv7604_formats[] = { > > + { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, > > + ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, > > + { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, > > + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, > > + { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, > > + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, > > + { V4L2_MBUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false, > > + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, > > + { V4L2_MBUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true, > > + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, > > + { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, > > + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, > > + { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, > > + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, > > + { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, > > + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, > > + { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, > > + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, > > + { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, > > + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, > > + { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, > > + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, > > + { V4L2_MBUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false, > > + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, > > + { V4L2_MBUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true, > > + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, > > + { V4L2_MBUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false, > > + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, > > + { V4L2_MBUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true, > > + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, > > + { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, > > + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, > > + { V4L2_MBUS_FMT
Re: [PATCH v3 36/48] adv7604: Make output format configurable through pad format operations
On 03/18/2014 02:02 PM, Laurent Pinchart wrote: > Hi Hans, > > On Tuesday 18 March 2014 10:32:32 Hans Verkuil wrote: >> Hi Laurent, >> >> I've tested it and I thought I was going crazy. Everything was fine after >> applying this patch, but as soon as I applied the next patch (37/48) the >> colors were wrong. But that patch had nothing whatsoever to do with the >> bus ordering. You managed to make a small but crucial bug and it was pure >> bad luck that it ever worked. >> >> See details below: >> >> On 03/11/14 16:10, Laurent Pinchart wrote: >>> Replace the dummy video format operations by pad format operations that >>> configure the output format. >>> >>> Signed-off-by: Laurent Pinchart >>> --- >>> >>> drivers/media/i2c/adv7604.c | 280 +++ >>> include/media/adv7604.h | 56 - >>> 2 files changed, 275 insertions(+), 61 deletions(-) >>> >>> diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c >>> index 851b350..5aa7c29 100644 >>> --- a/drivers/media/i2c/adv7604.c >>> +++ b/drivers/media/i2c/adv7604.c >>> @@ -53,6 +53,28 @@ MODULE_LICENSE("GPL"); >>> >>> /* ADV7604 system clock frequency */ >>> #define ADV7604_fsc (28636360) >>> >>> +#define ADV7604_RGB_OUT(1 << 1) >>> + >>> +#define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0) >>> +#define ADV7604_OP_FORMAT_SEL_10BIT(1 << 0) >>> +#define ADV7604_OP_FORMAT_SEL_12BIT(2 << 0) >>> + >>> +#define ADV7604_OP_MODE_SEL_SDR_422(0 << 5) >>> +#define ADV7604_OP_MODE_SEL_DDR_422(1 << 5) >>> +#define ADV7604_OP_MODE_SEL_SDR_444(2 << 5) >>> +#define ADV7604_OP_MODE_SEL_DDR_444(3 << 5) >>> +#define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5) >>> +#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) >>> + >>> +#define ADV7604_OP_CH_SEL_GBR (0 << 5) >>> +#define ADV7604_OP_CH_SEL_GRB (1 << 5) >>> +#define ADV7604_OP_CH_SEL_BGR (2 << 5) >>> +#define ADV7604_OP_CH_SEL_RGB (3 << 5) >>> +#define ADV7604_OP_CH_SEL_BRG (4 << 5) >>> +#define ADV7604_OP_CH_SEL_RBG (5 << 5) >> >> Note that these values are shifted 5 bits to the left... > > [snip] > >>> +struct adv7604_format_info { >>> + enum v4l2_mbus_pixelcode code; >>> + u8 op_ch_sel; >>> + bool rgb_out; >>> + bool swap_cb_cr; >>> + u8 op_format_sel; >>> +}; > > [snip] > >>> +static const struct adv7604_format_info adv7604_formats[] = { >>> + { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, >>> + ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, >>> + { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, >>> + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, >>> + { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, >>> + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, >>> + { V4L2_MBUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false, >>> + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, >>> + { V4L2_MBUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true, >>> + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, >>> + { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, >>> + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, >>> + { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, >>> + ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, >>> + { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, >>> + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, >>> + { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, >>> + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, >>> + { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, >>> + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, >>> + { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, >>> + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, >>> + { V4L2_MBUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false, >>> + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, >>> + { V4L2_MBUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true, >>> + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, >>> + { V4L2_MBUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false, >>> + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, >>> + { V4L2_MBUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true, >>> + ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, >>> + { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, >>> + ADV7604_OP_MODE_S