This patch adds basic DT bindings for the PL11x CLCD cells
and make their fbdev driver use them, together with the
Common Display Framework.
The DT provides information about the hardware configuration
and limitations (eg. the largest supported resolution)
but the video modes come exclusively from the Common
Display Framework drivers, referenced to by the standard CDF
binding.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
.../devicetree/bindings/video/arm,pl11x.txt| 35 +++
drivers/video/Kconfig |1 +
drivers/video/amba-clcd.c | 244
include/linux/amba/clcd.h |2 +
4 files changed, 282 insertions(+)
create mode 100644 Documentation/devicetree/bindings/video/arm,pl11x.txt
diff --git a/Documentation/devicetree/bindings/video/arm,pl11x.txt
b/Documentation/devicetree/bindings/video/arm,pl11x.txt
new file mode 100644
index 000..ee9534a
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/arm,pl11x.txt
@@ -0,0 +1,35 @@
+* ARM PrimeCell Color LCD Controller (CLCD) PL110/PL111
+
+Required properties:
+
+- compatible : must be one of:
+ arm,pl110, arm,primecell
+ arm,pl111, arm,primecell
+- reg : base address and size of the control registers block
+- interrupts : the combined interrupt
+- clocks : phandles to the CLCD (pixel) clock and the APB clocks
+- clock-names : clcdclk, apb_pclk
+- display : phandle to the display entity connected to the controller
+
+Optional properties:
+
+- label : string describing the controller location and/or usage
+- video-ram : phandle to DT node of the specialized video RAM to be used
+- max-hactive : maximum frame buffer width in pixels
+- max-vactive : maximum frame buffer height in pixels
+- max-bpp : maximum number of bits per pixel
+- big-endian-pixels : defining this property makes the pixel bytes being
+ accessed in Big Endian organization
+
+Example:
+
+ clcd@1f {
+ compatible = arm,pl111, arm,primecell;
+ reg = 0x1f 0x1000;
+ interrupts = 14;
+ clocks = v2m_oscclk1, smbclk;
+ clock-names = clcdclk, apb_pclk;
+ label = IOFPGA CLCD;
+ video-ram = v2m_vram;
+ display = v2m_muxfpga;
+ };
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 281e548..bad8166 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -340,6 +340,7 @@ config FB_ARMCLCD
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
+ select FB_MODE_HELPERS if OF
help
This framebuffer device driver is for the ARM PrimeCell PL110
Colour LCD controller. ARM PrimeCells provide the building
diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c
index 0a2cce7..778dc03 100644
--- a/drivers/video/amba-clcd.c
+++ b/drivers/video/amba-clcd.c
@@ -25,6 +25,11 @@
#include linux/amba/clcd.h
#include linux/clk.h
#include linux/hardirq.h
+#include linux/dma-mapping.h
+#include linux/of.h
+#include linux/of_address.h
+#include video/display.h
+#include video/videomode.h
#include asm/sizes.h
@@ -62,6 +67,10 @@ static void clcdfb_disable(struct clcd_fb *fb)
{
u32 val;
+ if (fb-panel-display)
+ display_entity_set_state(fb-panel-display,
+ DISPLAY_ENTITY_STATE_OFF);
+
if (fb-board-disable)
fb-board-disable(fb);
@@ -115,6 +124,11 @@ static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
*/
if (fb-board-enable)
fb-board-enable(fb);
+
+ if (fb-panel-display)
+ display_entity_set_state(fb-panel-display,
+ DISPLAY_ENTITY_STATE_ON);
+
}
static int
@@ -304,6 +318,13 @@ static int clcdfb_set_par(struct fb_info *info)
clcdfb_enable(fb, regs.cntl);
+ if (fb-panel-display) {
+ struct videomode mode;
+
+ videomode_from_fb_var_screeninfo(fb-fb.var, mode);
+ display_entity_update(fb-panel-display, mode);
+ }
+
#ifdef DEBUG
printk(KERN_INFO
CLCD: Registers set to\n
@@ -542,6 +563,226 @@ static int clcdfb_register(struct clcd_fb *fb)
return ret;
}
+#if defined(CONFIG_OF)
+static int clcdfb_of_get_tft_parallel_panel(struct clcd_panel *panel,
+ struct display_entity_interface_params *params)
+{
+ int r = params-p.tft_parallel.r_bits;
+ int g = params-p.tft_parallel.g_bits;
+ int b = params-p.tft_parallel.b_bits;
+
+ /* Bypass pixel clock divider, data output on the falling edge */
+ panel-tim2 = TIM2_BCD | TIM2_IPC;
+
+ /*
