From: Guennadi Liakhovetski [mailto:g.liakhovet...@gmx.de]
Sent: Sunday, 30 September, 2012 01:26
To: Albert Wang
Cc: cor...@lwn.net; linux-media@vger.kernel.org; Libin Yang
Subject: Re: [PATCH 1/4] [media] mmp: add register definition for marvell ccic
On Fri, 28 Sep 2012, Albert Wang wrote:
From: Libin Yang lby...@marvell.com
This patch adds the definition of CCIC1/2 Clock Reset register address
Signed-off-by: Albert Wang twan...@marvell.com
Signed-off-by: Libin Yang lby...@marvell.com
---
arch/arm/mach-mmp/include/mach/regs-apmu.h |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h
b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 7af8deb..f2cf231 100755
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -16,7 +16,8 @@
/* Clock Reset Control */
#define APMU_IREAPMU_REG(0x048)
#define APMU_LCDAPMU_REG(0x04c)
-#define APMU_CCIC APMU_REG(0x050)
+#define APMU_CCIC_RST APMU_REG(0x050)
+#define APMU_CCIC2_RST APMU_REG(0x0f4)
Assuming APMU_CCIC hasn't been used until now, changing its name is ok, but I
think,
registers in this list are ordered by their addresses, so, your addition
should go between
#define APMU_SDH3 APMU_REG(0x0ec)
#define APMU_ETH APMU_REG(0x0fc)
Sorry for late response.
Sure, you are right, we will change it in Version 2
Thanks
Guennadi
#define APMU_SDH0 APMU_REG(0x054)
#define APMU_SDH1 APMU_REG(0x058)
#define APMU_USBAPMU_REG(0x05c)
--
1.7.0.4
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
Thanks
Albert Wang
86-21-61092656
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