subject:"Re\: \[RFC v3 03\/13\] \[media\] exynos5\-fimc\-is\: Add driver core files"

Re: [RFC v3 03/13] [media] exynos5-fimc-is: Add driver core files

2013-08-05 Thread Arun Kumar K

Hi Sylwester,

On Sun, Aug 4, 2013 at 3:12 AM, Sylwester Nawrocki
 wrote:
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>
>> This driver is for the FIMC-IS IP available in Samsung Exynos5
>> SoC onwards. This patch adds the core files for the new driver.
>>
>> Signed-off-by: Arun Kumar K
>> Signed-off-by: Kilyeon Im
>> ---
>>   drivers/media/platform/exynos5-is/fimc-is-core.c |  394
>> ++
>>   drivers/media/platform/exynos5-is/fimc-is-core.h |  122 +++
>>   2 files changed, 516 insertions(+)
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
>>
>> diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c
>> b/drivers/media/platform/exynos5-is/fimc-is-core.c
>> new file mode 100644
>> index 000..7b7762b
>> --- /dev/null
>> +++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
>> @@ -0,0 +1,394 @@
>> +/*
>> + * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
>> +*
>> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
>> + * Arun Kumar K
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "fimc-is.h"
>> +#include "fimc-is-i2c.h"
>> +
>> +#define CLK_MCU_ISP_DIV0_FREQ  (200 * 100)
>> +#define CLK_MCU_ISP_DIV1_FREQ  (100 * 100)
>> +#define CLK_ISP_DIV0_FREQ  (134 * 100)
>> +#define CLK_ISP_DIV1_FREQ  (68 * 100)
>> +#define CLK_ISP_DIVMPWM_FREQ   (34 * 100)
>> +
>> +static char *fimc_is_clock_name[] = {
>> +   [IS_CLK_ISP]= "isp",
>> +   [IS_CLK_MCU_ISP]= "mcu_isp",
>> +   [IS_CLK_ISP_DIV0]   = "isp_div0",
>> +   [IS_CLK_ISP_DIV1]   = "isp_div1",
>> +   [IS_CLK_ISP_DIVMPWM]= "isp_divmpwm",
>> +   [IS_CLK_MCU_ISP_DIV0]   = "mcu_isp_div0",
>> +   [IS_CLK_MCU_ISP_DIV1]   = "mcu_isp_div1",
>> +};
>> +
>> +static void fimc_is_put_clocks(struct fimc_is *is)
>> +{
>> +   int i;
>> +
>> +   for (i = 0; i<  IS_CLK_MAX_NUM; i++) {
>> +   if (IS_ERR(is->clock[i]))
>> +   continue;
>> +   clk_unprepare(is->clock[i]);
>> +   clk_put(is->clock[i]);
>> +   is->clock[i] = NULL;
>> +   }
>> +}
>> +
>> +static int fimc_is_get_clocks(struct fimc_is *is)
>> +{
>> +   struct device *dev =&is->pdev->dev;
>>
>> +   int i, ret;
>> +
>> +   for (i = 0; i<  IS_CLK_MAX_NUM; i++) {
>> +   is->clock[i] = clk_get(dev, fimc_is_clock_name[i]);
>> +   if (IS_ERR(is->clock[i]))
>> +   goto err;
>> +   ret = clk_prepare(is->clock[i]);
>> +   if (ret<  0) {
>> +   clk_put(is->clock[i]);
>> +   is->clock[i] = ERR_PTR(-EINVAL);
>> +   goto err;
>> +   }
>> +   }
>> +   return 0;
>> +err:
>> +   fimc_is_put_clocks(is);
>> +   pr_err("Failed to get clock: %s\n", fimc_is_clock_name[i]);
>> +   return -ENXIO;
>> +}
>> +
>> +static int fimc_is_configure_clocks(struct fimc_is *is)
>> +{
>> +   int i, ret;
>> +
>> +   for (i = 0; i<  IS_CLK_MAX_NUM; i++)
>> +   is->clock[i] = ERR_PTR(-EINVAL);
>> +
>> +   ret = fimc_is_get_clocks(is);
>> +   if (ret)
>> +   return ret;
>> +
>> +   /* Set rates */
>> +   ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV0],
>> +   CLK_MCU_ISP_DIV0_FREQ);
>> +   if (ret)
>> +   return ret;
>> +   ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV1],
>> +   CLK_MCU_ISP_DIV1_FREQ);
>> +   if (ret)
>> +   return ret;
>> +   ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV0], CLK_ISP_DIV0_FREQ);
>> +   if (ret)
>> +   return ret;
>> +   ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV1], CLK_ISP_DIV1_FREQ);
>> +   if (ret)
>> +   return ret;
>> +   ret = clk_set_rate(is->clock[IS_CLK_ISP_DIVMPWM],
>> +   CLK_ISP_DIVMPWM_FREQ);
>> +   return ret;
>> +}
>> +
>> +static void fimc_is_pipelines_destroy(struct fimc_is *is)
>> +{
>> +   int i;
>> +
>> +   for (i = 0; i<  is->num_instance; i++)
>> +   fimc_is_pipeline_destroy(&is->pipeline[i]);
>> +}
>> +
>> +static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int
>> index,
>> +   struct d

Re: [RFC v3 03/13] [media] exynos5-fimc-is: Add driver core files

2013-08-03 Thread Sylwester Nawrocki


On 08/02/2013 05:02 PM, Arun Kumar K wrote:

This driver is for the FIMC-IS IP available in Samsung Exynos5
SoC onwards. This patch adds the core files for the new driver.

Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
---
  drivers/media/platform/exynos5-is/fimc-is-core.c |  394 ++
  drivers/media/platform/exynos5-is/fimc-is-core.h |  122 +++
  2 files changed, 516 insertions(+)
  create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
  create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c 
b/drivers/media/platform/exynos5-is/fimc-is-core.c
new file mode 100644
index 000..7b7762b
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
@@ -0,0 +1,394 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "fimc-is.h"
+#include "fimc-is-i2c.h"
+
+#define CLK_MCU_ISP_DIV0_FREQ  (200 * 100)
+#define CLK_MCU_ISP_DIV1_FREQ  (100 * 100)
+#define CLK_ISP_DIV0_FREQ  (134 * 100)
+#define CLK_ISP_DIV1_FREQ  (68 * 100)
+#define CLK_ISP_DIVMPWM_FREQ   (34 * 100)
+
+static char *fimc_is_clock_name[] = {
+   [IS_CLK_ISP]= "isp",
+   [IS_CLK_MCU_ISP]= "mcu_isp",
+   [IS_CLK_ISP_DIV0]   = "isp_div0",
+   [IS_CLK_ISP_DIV1]   = "isp_div1",
+   [IS_CLK_ISP_DIVMPWM]= "isp_divmpwm",
+   [IS_CLK_MCU_ISP_DIV0]   = "mcu_isp_div0",
+   [IS_CLK_MCU_ISP_DIV1]   = "mcu_isp_div1",
+};
+
+static void fimc_is_put_clocks(struct fimc_is *is)
+{
+   int i;
+
+   for (i = 0; i<  IS_CLK_MAX_NUM; i++) {
+   if (IS_ERR(is->clock[i]))
+   continue;
+   clk_unprepare(is->clock[i]);
+   clk_put(is->clock[i]);
+   is->clock[i] = NULL;
+   }
+}
+
+static int fimc_is_get_clocks(struct fimc_is *is)
+{
+   struct device *dev =&is->pdev->dev;
+   int i, ret;
+
+   for (i = 0; i<  IS_CLK_MAX_NUM; i++) {
+   is->clock[i] = clk_get(dev, fimc_is_clock_name[i]);
+   if (IS_ERR(is->clock[i]))
+   goto err;
+   ret = clk_prepare(is->clock[i]);
+   if (ret<  0) {
+   clk_put(is->clock[i]);
+   is->clock[i] = ERR_PTR(-EINVAL);
+   goto err;
+   }
+   }
+   return 0;
+err:
+   fimc_is_put_clocks(is);
+   pr_err("Failed to get clock: %s\n", fimc_is_clock_name[i]);
+   return -ENXIO;
+}
+
+static int fimc_is_configure_clocks(struct fimc_is *is)
+{
+   int i, ret;
+
+   for (i = 0; i<  IS_CLK_MAX_NUM; i++)
+   is->clock[i] = ERR_PTR(-EINVAL);
+
+   ret = fimc_is_get_clocks(is);
+   if (ret)
+   return ret;
+
+   /* Set rates */
+   ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV0],
+   CLK_MCU_ISP_DIV0_FREQ);
+   if (ret)
+   return ret;
+   ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV1],
+   CLK_MCU_ISP_DIV1_FREQ);
+   if (ret)
+   return ret;
+   ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV0], CLK_ISP_DIV0_FREQ);
+   if (ret)
+   return ret;
+   ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV1], CLK_ISP_DIV1_FREQ);
+   if (ret)
+   return ret;
+   ret = clk_set_rate(is->clock[IS_CLK_ISP_DIVMPWM],
+   CLK_ISP_DIVMPWM_FREQ);
+   return ret;
+}
+
+static void fimc_is_pipelines_destroy(struct fimc_is *is)
+{
+   int i;
+
+   for (i = 0; i<  is->num_instance; i++)
+   fimc_is_pipeline_destroy(&is->pipeline[i]);
+}
+
+static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
+   struct device_node *node)
+{
+   struct fimc_is_sensor *sensor =&is->sensor[index];
+   u32 tmp = 0;
+   int ret;
+
+   sensor->drvdata = exynos5_is_sensor_get_drvdata(node);
+   if (!sensor->drvdata) {
+   dev_err(&is->pdev->dev, "no driver data found for: %s\n",
+node->full_name);
+   return -EINVAL;
+   }
+
+   node = v4l2_of_get_next_endpoint(node, NULL);
+   if (!node)
+   return -ENXIO;
+
+   node = v4l2_of_get_remote_port(node);

Re: [RFC v3 03/13] [media] exynos5-fimc-is: Add driver core files

Re: [RFC v3 03/13] [media] exynos5-fimc-is: Add driver core files

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