Re: [PATCH] mmc: omap: remove clock rate hard coding

2011-12-20 Thread Shilimkar, Santosh 
On Tue, Dec 20, 2011 at 3:12 PM, Venkatraman S svenk...@ti.com wrote:
 From: Balaji TK balaj...@ti.com

 MMC master clock rate can vary for each instance of the MMC controller
 on the device. Use clk_get_rate instead to get the value.

  Signed-off-by: Balaji TK  balaj...@ti.com
  Reviewed-by: Venkatraman S svenk...@ti.com
 ---
Finally.
Feel free to add if you need one
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
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Re: [PATCH 0/4] Fix the left DMA_NONE from dma_transfer_direction migration

2011-12-20 Thread Shawn Guo 
On Tue, Dec 20, 2011 at 02:54:04PM +0530, Vinod Koul wrote:
 On Tue, 2011-12-13 at 23:48 +0800, Shawn Guo wrote:
  I have been working on -rc recently, and have not noticed the failure
  until I ran next tree today.  The mxs-mmc driver is broken on next
  tree because the DMA_NONE was left over from the dma_transfer_direction
  migration for mxs-dma and its client drivers.
  
 For DMA transfer, the NONE direction makes no sense?
 
 In your conetext, what are you trying to achieve?
 
The mxs-dma controller has a feature to program peripheral registers
with given values (mxs-dma PIO mode).  This is designed to pipeline
the operations.  For example, we can put mxs-mmc controller register
values into scatter list as one element together with actual data.
Triggering the mxs-dma, the dma will program the values into mxs-mmc
controller register to set up and enable mxs-mmc, and then dma
continue transfer data from/to mxs-mmc.  All these get done in one
dmaengine_submit().

And DMA_NONE was used to let mxs-dma know this is a PIO operation.

-- 
Regards,
Shawn

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[PATCH v4 2/4] ARM: pxa168: Add SDHCI support

2011-12-20 Thread Tanmay Upadhyay 
v2 - clock register for SDHCI are not common across all MMP SoCs.
 So, move PXA168 implementation to pxa168.c

v3 - sdhci-pxav1 driver code is merged with sdhci-pxav2. So, change
 the device name accordingly
   - start sdhci device numbering from 1 as other PXA168 devices
 does that

v4 - Use different names for SD clock registers for PXA168 instead
 of redefining them in pxa168.c. Suggested by Haojian Zhuang

Signed-off-by: Tanmay Upadhyay tanmay.upadh...@einfochips.com
Reviewed-by: Philip Rakity prak...@marvell.com
---
 arch/arm/mach-mmp/include/mach/pxa168.h|   20 ++
 arch/arm/mach-mmp/include/mach/regs-apmu.h |   40 ++-
 arch/arm/mach-mmp/pxa168.c |   39 +++
 3 files changed, 80 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h 
b/arch/arm/mach-mmp/include/mach/pxa168.h
index 7fb568d..a181608 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -15,6 +15,7 @@ extern void pxa168_clear_keypad_wakeup(void);
 #include plat/pxa27x_keypad.h
 #include mach/cputype.h
 #include linux/pxa168_eth.h
+#include linux/platform_data/pxa_sdhci.h
 
 extern struct pxa_device_desc pxa168_device_uart1;
 extern struct pxa_device_desc pxa168_device_uart2;
@@ -34,6 +35,10 @@ extern struct pxa_device_desc pxa168_device_nand;
 extern struct pxa_device_desc pxa168_device_fb;
 extern struct pxa_device_desc pxa168_device_keypad;
 extern struct pxa_device_desc pxa168_device_eth;
+extern struct pxa_device_desc pxa168_device_sdh1;
+extern struct pxa_device_desc pxa168_device_sdh2;
+extern struct pxa_device_desc pxa168_device_sdh3;
+extern struct pxa_device_desc pxa168_device_sdh4;
 
 struct pxa168_usb_pdata {
/* If NULL, default phy init routine for PXA168 would be called */
@@ -132,4 +137,19 @@ static inline int pxa168_add_eth(struct 
pxa168_eth_platform_data *data)
 {
return pxa_register_device(pxa168_device_eth, data, sizeof(*data));
 }
+
+static inline int pxa168_add_sdh(int id, struct sdhci_pxa_platdata *data)
+{
+   struct pxa_device_desc *d = NULL;
+
+   switch (id) {
+   case 1: d = pxa168_device_sdh1; break;
+   case 2: d = pxa168_device_sdh2; break;
+   case 3: d = pxa168_device_sdh3; break;
+   case 4: d = pxa168_device_sdh4; break;
+   default:
+   return -EINVAL;
+   }
+   return pxa_register_device(d, data, sizeof(*data));
+}
 #endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h 
b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 8447ac6..a84de77 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -17,27 +17,29 @@
 #define APMU_REG(x)(APMU_VIRT_BASE + (x))
 
 /* Clock Reset Control */
-#define APMU_IRE   APMU_REG(0x048)
-#define APMU_LCD   APMU_REG(0x04c)
-#define APMU_CCIC  APMU_REG(0x050)
-#define APMU_SDH0  APMU_REG(0x054)
-#define APMU_SDH1  APMU_REG(0x058)
-#define APMU_USB   APMU_REG(0x05c)
-#define APMU_NAND  APMU_REG(0x060)
-#define APMU_DMA   APMU_REG(0x064)
-#define APMU_GEU   APMU_REG(0x068)
-#define APMU_BUS   APMU_REG(0x06c)
-#define APMU_SDH2  APMU_REG(0x0e8)
-#define APMU_SDH3  APMU_REG(0x0ec)
-#define APMU_ETH   APMU_REG(0x0fc)
-
-#define APMU_FNCLK_EN  (1  4)
-#define APMU_AXICLK_EN (1  3)
-#define APMU_FNRST_DIS (1  1)
-#define APMU_AXIRST_DIS(1  0)
+#define APMU_IRE   APMU_REG(0x048)
+#define APMU_LCD   APMU_REG(0x04c)
+#define APMU_CCIC  APMU_REG(0x050)
+#define APMU_SDH0  APMU_REG(0x054)
+#define APMU_SDH1  APMU_REG(0x058)
+#define APMU_USB   APMU_REG(0x05c)
+#define APMU_NAND  APMU_REG(0x060)
+#define APMU_DMA   APMU_REG(0x064)
+#define APMU_GEU   APMU_REG(0x068)
+#define APMU_BUS   APMU_REG(0x06c)
+#define APMU_PXA168_SDH2   APMU_REG(0x0e0)
+#define APMU_PXA168_SDH3   APMU_REG(0x0e4)
+#define APMU_SDH2  APMU_REG(0x0e8)
+#define APMU_SDH3  APMU_REG(0x0ec)
+#define APMU_ETH   APMU_REG(0x0fc)
+
+#define APMU_FNCLK_EN  (1  4)
+#define APMU_AXICLK_EN (1  3)
+#define APMU_FNRST_DIS (1  1)
+#define APMU_AXIRST_DIS(1  0)
 
 /* Wake Clear Register */
-#define APMU_WAKE_CLR  APMU_REG(0x07c)
+#define APMU_WAKE_CLR  APMU_REG(0x07c)
 
 #define APMU_PXA168_KP_WAKE_CLR(1  7)
 #define APMU_PXA168_CFI_WAKE_CLR   (1  6)
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 76ca15c..023659b 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -65,6 +65,32 @@ void __init pxa168_init_irq(void)
pxa168_init_gpio();
 }
 
+static void sdh_clk_enable(struct clk *clk)
+{
+   void __iomem *reg_offset = clk-clk_rst;
+
+   /* Can't see any clean

Re: [PATCH v4 2/4] ARM: pxa168: Add SDHCI support

2011-12-20 Thread Haojian Zhuang 
On Tue, Dec 20, 2011 at 9:13 PM, Tanmay Upadhyay
tanmay.upadh...@einfochips.com wrote:
 v2 - clock register for SDHCI are not common across all MMP SoCs.
     So, move PXA168 implementation to pxa168.c

 v3 - sdhci-pxav1 driver code is merged with sdhci-pxav2. So, change
     the device name accordingly
   - start sdhci device numbering from 1 as other PXA168 devices
     does that

 v4 - Use different names for SD clock registers for PXA168 instead
     of redefining them in pxa168.c. Suggested by Haojian Zhuang

 Signed-off-by: Tanmay Upadhyay tanmay.upadh...@einfochips.com
 Reviewed-by: Philip Rakity prak...@marvell.com
 ---
  arch/arm/mach-mmp/include/mach/pxa168.h    |   20 ++
  arch/arm/mach-mmp/include/mach/regs-apmu.h |   40 ++-
  arch/arm/mach-mmp/pxa168.c                 |   39 +++
  3 files changed, 80 insertions(+), 19 deletions(-)

 diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h 
 b/arch/arm/mach-mmp/include/mach/pxa168.h
 index 7fb568d..a181608 100644
 --- a/arch/arm/mach-mmp/include/mach/pxa168.h
 +++ b/arch/arm/mach-mmp/include/mach/pxa168.h
 @@ -15,6 +15,7 @@ extern void pxa168_clear_keypad_wakeup(void);
  #include plat/pxa27x_keypad.h
  #include mach/cputype.h
  #include linux/pxa168_eth.h
 +#include linux/platform_data/pxa_sdhci.h

  extern struct pxa_device_desc pxa168_device_uart1;
  extern struct pxa_device_desc pxa168_device_uart2;
 @@ -34,6 +35,10 @@ extern struct pxa_device_desc pxa168_device_nand;
  extern struct pxa_device_desc pxa168_device_fb;
  extern struct pxa_device_desc pxa168_device_keypad;
  extern struct pxa_device_desc pxa168_device_eth;
 +extern struct pxa_device_desc pxa168_device_sdh1;
 +extern struct pxa_device_desc pxa168_device_sdh2;
 +extern struct pxa_device_desc pxa168_device_sdh3;
 +extern struct pxa_device_desc pxa168_device_sdh4;

  struct pxa168_usb_pdata {
        /* If NULL, default phy init routine for PXA168 would be called */
 @@ -132,4 +137,19 @@ static inline int pxa168_add_eth(struct 
 pxa168_eth_platform_data *data)
  {
        return pxa_register_device(pxa168_device_eth, data, sizeof(*data));
  }
 +
 +static inline int pxa168_add_sdh(int id, struct sdhci_pxa_platdata *data)
 +{
 +       struct pxa_device_desc *d = NULL;
 +
 +       switch (id) {
 +       case 1: d = pxa168_device_sdh1; break;
 +       case 2: d = pxa168_device_sdh2; break;
 +       case 3: d = pxa168_device_sdh3; break;
 +       case 4: d = pxa168_device_sdh4; break;
 +       default:
 +               return -EINVAL;
 +       }
 +       return pxa_register_device(d, data, sizeof(*data));
 +}
  #endif /* __ASM_MACH_PXA168_H */
 diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h 
 b/arch/arm/mach-mmp/include/mach/regs-apmu.h
 index 8447ac6..a84de77 100644
 --- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
 +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
 @@ -17,27 +17,29 @@
  #define APMU_REG(x)    (APMU_VIRT_BASE + (x))

  /* Clock Reset Control */
 -#define APMU_IRE       APMU_REG(0x048)
 -#define APMU_LCD       APMU_REG(0x04c)
 -#define APMU_CCIC      APMU_REG(0x050)
 -#define APMU_SDH0      APMU_REG(0x054)
 -#define APMU_SDH1      APMU_REG(0x058)
 -#define APMU_USB       APMU_REG(0x05c)
 -#define APMU_NAND      APMU_REG(0x060)
 -#define APMU_DMA       APMU_REG(0x064)
 -#define APMU_GEU       APMU_REG(0x068)
 -#define APMU_BUS       APMU_REG(0x06c)
 -#define APMU_SDH2      APMU_REG(0x0e8)
 -#define APMU_SDH3      APMU_REG(0x0ec)
 -#define APMU_ETH       APMU_REG(0x0fc)
 -
 -#define APMU_FNCLK_EN  (1  4)
 -#define APMU_AXICLK_EN (1  3)
 -#define APMU_FNRST_DIS (1  1)
 -#define APMU_AXIRST_DIS        (1  0)
 +#define APMU_IRE               APMU_REG(0x048)
 +#define APMU_LCD               APMU_REG(0x04c)
 +#define APMU_CCIC              APMU_REG(0x050)
 +#define APMU_SDH0              APMU_REG(0x054)
 +#define APMU_SDH1              APMU_REG(0x058)
 +#define APMU_USB               APMU_REG(0x05c)
 +#define APMU_NAND              APMU_REG(0x060)
 +#define APMU_DMA               APMU_REG(0x064)
 +#define APMU_GEU               APMU_REG(0x068)
 +#define APMU_BUS               APMU_REG(0x06c)
 +#define APMU_PXA168_SDH2       APMU_REG(0x0e0)
 +#define APMU_PXA168_SDH3       APMU_REG(0x0e4)
 +#define APMU_SDH2              APMU_REG(0x0e8)
 +#define APMU_SDH3              APMU_REG(0x0ec)
 +#define APMU_ETH               APMU_REG(0x0fc)
 +
 +#define APMU_FNCLK_EN          (1  4)
 +#define APMU_AXICLK_EN         (1  3)
 +#define APMU_FNRST_DIS         (1  1)
 +#define APMU_AXIRST_DIS                (1  0)

  /* Wake Clear Register */
 -#define APMU_WAKE_CLR  APMU_REG(0x07c)
 +#define APMU_WAKE_CLR          APMU_REG(0x07c)

  #define APMU_PXA168_KP_WAKE_CLR                (1  7)
  #define APMU_PXA168_CFI_WAKE_CLR       (1  6)
 diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
 index 76ca15c..023659b 100644
 --- a/arch/arm/mach-mmp/pxa168.c
 +++ b/arch/arm/mach-mmp/pxa168.c
 @@ -65,6 +65,32 @@ void

Re: [PATCH v4 2/4] ARM: pxa168: Add SDHCI support

2011-12-20 Thread Haojian Zhuang 
On Tue, Dec 20, 2011 at 9:25 PM, Haojian Zhuang
haojian.zhu...@gmail.com wrote:
 On Tue, Dec 20, 2011 at 9:13 PM, Tanmay Upadhyay
 tanmay.upadh...@einfochips.com wrote:
 v2 - clock register for SDHCI are not common across all MMP SoCs.
     So, move PXA168 implementation to pxa168.c

 v3 - sdhci-pxav1 driver code is merged with sdhci-pxav2. So, change
     the device name accordingly
   - start sdhci device numbering from 1 as other PXA168 devices
     does that

 v4 - Use different names for SD clock registers for PXA168 instead
     of redefining them in pxa168.c. Suggested by Haojian Zhuang

 Signed-off-by: Tanmay Upadhyay tanmay.upadh...@einfochips.com
 Reviewed-by: Philip Rakity prak...@marvell.com
 ---
  arch/arm/mach-mmp/include/mach/pxa168.h    |   20 ++
  arch/arm/mach-mmp/include/mach/regs-apmu.h |   40 
 ++-
  arch/arm/mach-mmp/pxa168.c                 |   39 
 +++
  3 files changed, 80 insertions(+), 19 deletions(-)

 diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h 
 b/arch/arm/mach-mmp/include/mach/pxa168.h
 index 7fb568d..a181608 100644
 --- a/arch/arm/mach-mmp/include/mach/pxa168.h
 +++ b/arch/arm/mach-mmp/include/mach/pxa168.h
 @@ -15,6 +15,7 @@ extern void pxa168_clear_keypad_wakeup(void);
  #include plat/pxa27x_keypad.h
  #include mach/cputype.h
  #include linux/pxa168_eth.h
 +#include linux/platform_data/pxa_sdhci.h

  extern struct pxa_device_desc pxa168_device_uart1;
  extern struct pxa_device_desc pxa168_device_uart2;
 @@ -34,6 +35,10 @@ extern struct pxa_device_desc pxa168_device_nand;
  extern struct pxa_device_desc pxa168_device_fb;
  extern struct pxa_device_desc pxa168_device_keypad;
  extern struct pxa_device_desc pxa168_device_eth;
 +extern struct pxa_device_desc pxa168_device_sdh1;
 +extern struct pxa_device_desc pxa168_device_sdh2;
 +extern struct pxa_device_desc pxa168_device_sdh3;
 +extern struct pxa_device_desc pxa168_device_sdh4;

  struct pxa168_usb_pdata {
        /* If NULL, default phy init routine for PXA168 would be called */
 @@ -132,4 +137,19 @@ static inline int pxa168_add_eth(struct 
 pxa168_eth_platform_data *data)
  {
        return pxa_register_device(pxa168_device_eth, data, sizeof(*data));
  }
 +
 +static inline int pxa168_add_sdh(int id, struct sdhci_pxa_platdata *data)
 +{
 +       struct pxa_device_desc *d = NULL;
 +
 +       switch (id) {
 +       case 1: d = pxa168_device_sdh1; break;
 +       case 2: d = pxa168_device_sdh2; break;
 +       case 3: d = pxa168_device_sdh3; break;
 +       case 4: d = pxa168_device_sdh4; break;
 +       default:
 +               return -EINVAL;
 +       }
 +       return pxa_register_device(d, data, sizeof(*data));
 +}
  #endif /* __ASM_MACH_PXA168_H */
 diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h 
 b/arch/arm/mach-mmp/include/mach/regs-apmu.h
 index 8447ac6..a84de77 100644
 --- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
 +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
 @@ -17,27 +17,29 @@
  #define APMU_REG(x)    (APMU_VIRT_BASE + (x))

  /* Clock Reset Control */
 -#define APMU_IRE       APMU_REG(0x048)
 -#define APMU_LCD       APMU_REG(0x04c)
 -#define APMU_CCIC      APMU_REG(0x050)
 -#define APMU_SDH0      APMU_REG(0x054)
 -#define APMU_SDH1      APMU_REG(0x058)
 -#define APMU_USB       APMU_REG(0x05c)
 -#define APMU_NAND      APMU_REG(0x060)
 -#define APMU_DMA       APMU_REG(0x064)
 -#define APMU_GEU       APMU_REG(0x068)
 -#define APMU_BUS       APMU_REG(0x06c)
 -#define APMU_SDH2      APMU_REG(0x0e8)
 -#define APMU_SDH3      APMU_REG(0x0ec)
 -#define APMU_ETH       APMU_REG(0x0fc)
 -
 -#define APMU_FNCLK_EN  (1  4)
 -#define APMU_AXICLK_EN (1  3)
 -#define APMU_FNRST_DIS (1  1)
 -#define APMU_AXIRST_DIS        (1  0)
 +#define APMU_IRE               APMU_REG(0x048)
 +#define APMU_LCD               APMU_REG(0x04c)
 +#define APMU_CCIC              APMU_REG(0x050)
 +#define APMU_SDH0              APMU_REG(0x054)
 +#define APMU_SDH1              APMU_REG(0x058)
 +#define APMU_USB               APMU_REG(0x05c)
 +#define APMU_NAND              APMU_REG(0x060)
 +#define APMU_DMA               APMU_REG(0x064)
 +#define APMU_GEU               APMU_REG(0x068)
 +#define APMU_BUS               APMU_REG(0x06c)
 +#define APMU_PXA168_SDH2       APMU_REG(0x0e0)
 +#define APMU_PXA168_SDH3       APMU_REG(0x0e4)
 +#define APMU_SDH2              APMU_REG(0x0e8)
 +#define APMU_SDH3              APMU_REG(0x0ec)
 +#define APMU_ETH               APMU_REG(0x0fc)
Since you only append APMU_PXA168_SDH2  APMU_PXA168_SDH3, you'd
better not touch other registers.
If you want to clean the code, you can submit another patch to handle it.

 +
 +#define APMU_FNCLK_EN          (1  4)
 +#define APMU_AXICLK_EN         (1  3)
 +#define APMU_FNRST_DIS         (1  1)
 +#define APMU_AXIRST_DIS                (1  0)

  /* Wake Clear Register */
 -#define APMU_WAKE_CLR  APMU_REG(0x07c)
 +#define APMU_WAKE_CLR          APMU_REG(0x07c)

  #define APMU_PXA168_KP_WAKE_CLR          

Re: [PATCH v4 2/4] ARM: pxa168: Add SDHCI support

2011-12-20 Thread Tanmay Upadhyay 



On Tuesday 20 December 2011 06:55 PM, Haojian Zhuang wrote:

On Tue, Dec 20, 2011 at 9:13 PM, Tanmay Upadhyay
tanmay.upadh...@einfochips.com  wrote:

v2 - clock register for SDHCI are not common across all MMP SoCs.
 So, move PXA168 implementation to pxa168.c

v3 - sdhci-pxav1 driver code is merged with sdhci-pxav2. So, change
 the device name accordingly
   - start sdhci device numbering from 1 as other PXA168 devices
 does that

v4 - Use different names for SD clock registers for PXA168 instead
 of redefining them in pxa168.c. Suggested by Haojian Zhuang

Signed-off-by: Tanmay Upadhyaytanmay.upadh...@einfochips.com
Reviewed-by: Philip Rakityprak...@marvell.com
---
  arch/arm/mach-mmp/include/mach/pxa168.h|   20 ++
  arch/arm/mach-mmp/include/mach/regs-apmu.h |   40 ++-
  arch/arm/mach-mmp/pxa168.c |   39 +++
  3 files changed, 80 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h 
b/arch/arm/mach-mmp/include/mach/pxa168.h
index 7fb568d..a181608 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -15,6 +15,7 @@ extern void pxa168_clear_keypad_wakeup(void);
  #includeplat/pxa27x_keypad.h
  #includemach/cputype.h
  #includelinux/pxa168_eth.h
+#includelinux/platform_data/pxa_sdhci.h

  extern struct pxa_device_desc pxa168_device_uart1;
  extern struct pxa_device_desc pxa168_device_uart2;
@@ -34,6 +35,10 @@ extern struct pxa_device_desc pxa168_device_nand;
  extern struct pxa_device_desc pxa168_device_fb;
  extern struct pxa_device_desc pxa168_device_keypad;
  extern struct pxa_device_desc pxa168_device_eth;
+extern struct pxa_device_desc pxa168_device_sdh1;
+extern struct pxa_device_desc pxa168_device_sdh2;
+extern struct pxa_device_desc pxa168_device_sdh3;
+extern struct pxa_device_desc pxa168_device_sdh4;

  struct pxa168_usb_pdata {
/* If NULL, default phy init routine for PXA168 would be called */
@@ -132,4 +137,19 @@ static inline int pxa168_add_eth(struct 
pxa168_eth_platform_data *data)
  {
return pxa_register_device(pxa168_device_eth, data, sizeof(*data));
  }
+
+static inline int pxa168_add_sdh(int id, struct sdhci_pxa_platdata *data)
+{
+   struct pxa_device_desc *d = NULL;
+
+   switch (id) {
+   case 1: d =pxa168_device_sdh1; break;
+   case 2: d =pxa168_device_sdh2; break;
+   case 3: d =pxa168_device_sdh3; break;
+   case 4: d =pxa168_device_sdh4; break;
+   default:
+   return -EINVAL;
+   }
+   return pxa_register_device(d, data, sizeof(*data));
+}
  #endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h 
b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 8447ac6..a84de77 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -17,27 +17,29 @@
  #define APMU_REG(x)(APMU_VIRT_BASE + (x))

  /* Clock Reset Control */
-#define APMU_IRE   APMU_REG(0x048)
-#define APMU_LCD   APMU_REG(0x04c)
-#define APMU_CCIC  APMU_REG(0x050)
-#define APMU_SDH0  APMU_REG(0x054)
-#define APMU_SDH1  APMU_REG(0x058)
-#define APMU_USB   APMU_REG(0x05c)
-#define APMU_NAND  APMU_REG(0x060)
-#define APMU_DMA   APMU_REG(0x064)
-#define APMU_GEU   APMU_REG(0x068)
-#define APMU_BUS   APMU_REG(0x06c)
-#define APMU_SDH2  APMU_REG(0x0e8)
-#define APMU_SDH3  APMU_REG(0x0ec)
-#define APMU_ETH   APMU_REG(0x0fc)
-
-#define APMU_FNCLK_EN  (1  4)
-#define APMU_AXICLK_EN (1  3)
-#define APMU_FNRST_DIS (1  1)
-#define APMU_AXIRST_DIS(1  0)
+#define APMU_IRE   APMU_REG(0x048)
+#define APMU_LCD   APMU_REG(0x04c)
+#define APMU_CCIC  APMU_REG(0x050)
+#define APMU_SDH0  APMU_REG(0x054)
+#define APMU_SDH1  APMU_REG(0x058)
+#define APMU_USB   APMU_REG(0x05c)
+#define APMU_NAND  APMU_REG(0x060)
+#define APMU_DMA   APMU_REG(0x064)
+#define APMU_GEU   APMU_REG(0x068)
+#define APMU_BUS   APMU_REG(0x06c)
+#define APMU_PXA168_SDH2   APMU_REG(0x0e0)
+#define APMU_PXA168_SDH3   APMU_REG(0x0e4)
+#define APMU_SDH2  APMU_REG(0x0e8)
+#define APMU_SDH3  APMU_REG(0x0ec)
+#define APMU_ETH   APMU_REG(0x0fc)
+
+#define APMU_FNCLK_EN  (1  4)
+#define APMU_AXICLK_EN (1  3)
+#define APMU_FNRST_DIS (1  1)
+#define APMU_AXIRST_DIS(1  0)

  /* Wake Clear Register */
-#define APMU_WAKE_CLR  APMU_REG(0x07c)
+#define APMU_WAKE_CLR  APMU_REG(0x07c)

  #define APMU_PXA168_KP_WAKE_CLR(1  7)
  #define APMU_PXA168_CFI_WAKE_CLR   (1  6)
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 76ca15c..023659b 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -65,6 +65,32 @@ void __init pxa168_init_irq(void)

Re: [PATCH v4 2/4] ARM: pxa168: Add SDHCI support

2011-12-20 Thread Tanmay Upadhyay 



On Tuesday 20 December 2011 07:08 PM, Haojian Zhuang wrote:

On Tue, Dec 20, 2011 at 9:25 PM, Haojian Zhuang
haojian.zhu...@gmail.com  wrote:

On Tue, Dec 20, 2011 at 9:13 PM, Tanmay Upadhyay
tanmay.upadh...@einfochips.com  wrote:

v2 - clock register for SDHCI are not common across all MMP SoCs.
 So, move PXA168 implementation to pxa168.c

v3 - sdhci-pxav1 driver code is merged with sdhci-pxav2. So, change
 the device name accordingly
   - start sdhci device numbering from 1 as other PXA168 devices
 does that

v4 - Use different names for SD clock registers for PXA168 instead
 of redefining them in pxa168.c. Suggested by Haojian Zhuang

Signed-off-by: Tanmay Upadhyaytanmay.upadh...@einfochips.com
Reviewed-by: Philip Rakityprak...@marvell.com
---
  arch/arm/mach-mmp/include/mach/pxa168.h|   20 ++
  arch/arm/mach-mmp/include/mach/regs-apmu.h |   40 ++-
  arch/arm/mach-mmp/pxa168.c |   39 +++
  3 files changed, 80 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h 
b/arch/arm/mach-mmp/include/mach/pxa168.h
index 7fb568d..a181608 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -15,6 +15,7 @@ extern void pxa168_clear_keypad_wakeup(void);
  #includeplat/pxa27x_keypad.h
  #includemach/cputype.h
  #includelinux/pxa168_eth.h
+#includelinux/platform_data/pxa_sdhci.h

  extern struct pxa_device_desc pxa168_device_uart1;
  extern struct pxa_device_desc pxa168_device_uart2;
@@ -34,6 +35,10 @@ extern struct pxa_device_desc pxa168_device_nand;
  extern struct pxa_device_desc pxa168_device_fb;
  extern struct pxa_device_desc pxa168_device_keypad;
  extern struct pxa_device_desc pxa168_device_eth;
+extern struct pxa_device_desc pxa168_device_sdh1;
+extern struct pxa_device_desc pxa168_device_sdh2;
+extern struct pxa_device_desc pxa168_device_sdh3;
+extern struct pxa_device_desc pxa168_device_sdh4;

  struct pxa168_usb_pdata {
/* If NULL, default phy init routine for PXA168 would be called */
@@ -132,4 +137,19 @@ static inline int pxa168_add_eth(struct 
pxa168_eth_platform_data *data)
  {
return pxa_register_device(pxa168_device_eth, data, sizeof(*data));
  }
+
+static inline int pxa168_add_sdh(int id, struct sdhci_pxa_platdata *data)
+{
+   struct pxa_device_desc *d = NULL;
+
+   switch (id) {
+   case 1: d =pxa168_device_sdh1; break;
+   case 2: d =pxa168_device_sdh2; break;
+   case 3: d =pxa168_device_sdh3; break;
+   case 4: d =pxa168_device_sdh4; break;
+   default:
+   return -EINVAL;
+   }
+   return pxa_register_device(d, data, sizeof(*data));
+}
  #endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h 
b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 8447ac6..a84de77 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -17,27 +17,29 @@
  #define APMU_REG(x)(APMU_VIRT_BASE + (x))

  /* Clock Reset Control */
-#define APMU_IRE   APMU_REG(0x048)
-#define APMU_LCD   APMU_REG(0x04c)
-#define APMU_CCIC  APMU_REG(0x050)
-#define APMU_SDH0  APMU_REG(0x054)
-#define APMU_SDH1  APMU_REG(0x058)
-#define APMU_USB   APMU_REG(0x05c)
-#define APMU_NAND  APMU_REG(0x060)
-#define APMU_DMA   APMU_REG(0x064)
-#define APMU_GEU   APMU_REG(0x068)
-#define APMU_BUS   APMU_REG(0x06c)
-#define APMU_SDH2  APMU_REG(0x0e8)
-#define APMU_SDH3  APMU_REG(0x0ec)
-#define APMU_ETH   APMU_REG(0x0fc)
-
-#define APMU_FNCLK_EN  (1  4)
-#define APMU_AXICLK_EN (1  3)
-#define APMU_FNRST_DIS (1  1)
-#define APMU_AXIRST_DIS(1  0)
+#define APMU_IRE   APMU_REG(0x048)
+#define APMU_LCD   APMU_REG(0x04c)
+#define APMU_CCIC  APMU_REG(0x050)
+#define APMU_SDH0  APMU_REG(0x054)
+#define APMU_SDH1  APMU_REG(0x058)
+#define APMU_USB   APMU_REG(0x05c)
+#define APMU_NAND  APMU_REG(0x060)
+#define APMU_DMA   APMU_REG(0x064)
+#define APMU_GEU   APMU_REG(0x068)
+#define APMU_BUS   APMU_REG(0x06c)
+#define APMU_PXA168_SDH2   APMU_REG(0x0e0)
+#define APMU_PXA168_SDH3   APMU_REG(0x0e4)
+#define APMU_SDH2  APMU_REG(0x0e8)
+#define APMU_SDH3  APMU_REG(0x0ec)
+#define APMU_ETH   APMU_REG(0x0fc)

Since you only append APMU_PXA168_SDH2  APMU_PXA168_SDH3, you'd
better not touch other registers.
If you want to clean the code, you can submit another patch to handle it.



Ok.

-- Tanmay


+
+#define APMU_FNCLK_EN  (1  4)
+#define APMU_AXICLK_EN (1  3)
+#define APMU_FNRST_DIS (1  1)
+#define APMU_AXIRST_DIS(1  0)

  /* Wake Clear Register */
-#define APMU_WAKE_CLR  APMU_REG(0x07c)
+#define APMU_WAKE_CLR  APMU_REG(0x07c)

  #define APMU_PXA168_KP_WAKE_CLR(1

[PATCH 1/1] mmc: User Application for testing SD/MMC Commands and extra IOCTL Command for MMC card reset

2011-12-20 Thread Shashidhar Hiremath 
The patch adds the user space application that uses the MMC ioctl to test the 
SD/MMC
commands. It also has the enhancement for an extra IOCTL command for resetting 
the card.
The extra ioctl becomes necessary since the user application implementation 
expects the card
to be in idle state independent of current state.To run the test module the 
mmc_block and
driver modules must be inserted first.

Signed-off-by: Shashidhar Hiremath shashidh...@vayavyalabs.com
---
 Documentation/mmc/cmd_test/Makefile   |9 ++
 Documentation/mmc/cmd_test/README |   10 ++
 Documentation/mmc/cmd_test/cmd_test.c |  245 +
 Documentation/mmc/cmd_test/cmd_test.h |   42 ++
 Documentation/mmc/cmd_test/config |  130 +
 drivers/mmc/card/block.c  |   43 ++
 include/linux/mmc/ioctl.h |1 +
 7 files changed, 480 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/mmc/cmd_test/Makefile
 create mode 100644 Documentation/mmc/cmd_test/README
 create mode 100644 Documentation/mmc/cmd_test/cmd_test.c
 create mode 100644 Documentation/mmc/cmd_test/cmd_test.h
 create mode 100644 Documentation/mmc/cmd_test/config

diff --git a/Documentation/mmc/cmd_test/Makefile 
b/Documentation/mmc/cmd_test/Makefile
new file mode 100644
index 000..5d2b85e
--- /dev/null
+++ b/Documentation/mmc/cmd_test/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the User Space Application for Testing Commands
+#
+all:CMD_TEST
+CMD_TEST:  cmd_test.o
+   gcc cmd_test.c -o cmd_test
+
+clean:
+   rm cmd_test.o cmd_test
diff --git a/Documentation/mmc/cmd_test/README 
b/Documentation/mmc/cmd_test/README
new file mode 100644
index 000..e0d03ab
--- /dev/null
+++ b/Documentation/mmc/cmd_test/README
@@ -0,0 +1,10 @@
+The Command Test Module implements the user space application for
+testing of the SD/MMC Commands.
+
+To Run the Module
+a. Do a Make
+b. Run the executable by name cmd_test
+c. The program prompts for the Command index
+d. Enter the Command number to be tested.
+e. The command's response and status will be displayed on terminal.
+
diff --git a/Documentation/mmc/cmd_test/cmd_test.c 
b/Documentation/mmc/cmd_test/cmd_test.c
new file mode 100644
index 000..ce24c84
--- /dev/null
+++ b/Documentation/mmc/cmd_test/cmd_test.c
@@ -0,0 +1,245 @@
+/*
+ * linux/Documentation/mmc/cmd_test/cmd_test.c
+ *
+ * This is a user space application that can be used to test few of the
+ * the SD/MMC commands.
+ * Author: Shashidhar Hiremath shashidh...@vayavyalabs.com
+ * Copyright 2011 VayavyaLabs Pvt. Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#include stdio.h
+#include fcntl.h
+#include linux/mmc/ioctl.h
+#include sys/ioctl.h
+#include string.h
+#include stdlib.h
+#include cmd_test.h
+
+
+static struct mmc_ioc_cmd mmc_local_cmd = {0};
+
+
+int main(void)
+{
+   int fd, ret_val, opcode, opc, i;
+   FILE *fp;
+   unsigned int *shifted_rca;
+   char stream[80];
+   char *local = NULL;
+   char *lhs_str = NULL;
+   char *rhs_str = NULL;
+   char *ret_str = NULL;
+   struct cmd **cmd_ptr = NULL;
+   struct cmd *test_cmd = NULL;
+
+   printf(Please Enter the Command Index to be tested\n);
+   scanf(%d, opcode);
+   if (opcode  55)
+   printf(\nERROR: Command not Supported\n\
+   Please Enter Command Index below 55\n);
+   cmd_ptr = calloc(55 , sizeof(struct cmd));
+   fp = fopen(config, r);
+
+   while (NULL != fgets(stream, 80, fp)) {
+   if ((stream[0] == '#') || (stream[0] == '}')
+   || (stream[0] == '{') || (stream[0] == '\n'))
+   continue;
+   local = strdup(stream);
+   lhs_str = strtok(local,  );
+   rhs_str = strtok(NULL,  );
+   remove_newline(rhs_str);
+   if (!strcmp(lhs_str, OPCODE)) {
+   opc = atoi(rhs_str);
+   cmd_ptr[opc] = calloc(1, sizeof(struct cmd));
+   cmd_ptr[opc]-opcode = opc;
+   } else if (!strcmp(lhs_str, ARG)) {
+   if (!strcmp(rhs_str, SHIFTED_RCA))
+   cmd_ptr[opc]-arg = IS_RCA;
+   else
+   cmd_ptr[opc]-arg = atoi(rhs_str);
+   } else if (!strcmp(lhs_str, FLAGS)) {
+   cmd_ptr[opc]-flags = rhs_str;
+   } else if (!strcmp(lhs_str, PRE_SEQ)) {
+   if (strcmp(rhs_str, NONE)) {
+   for (i = 0, (ret_str = strtok(rhs_str, ,));
+   (ret_str != NULL); i++,
+   (ret_str = strtok(NULL,

Re: PCI suspend warnings in 3.2-rc6

2011-12-20 Thread Rafael J. Wysocki 
On Tuesday, December 20, 2011, Chris Ball wrote:
 Hi,
 
 On Sun, Dec 18 2011, Rafael J. Wysocki wrote:
  On Sunday, December 18, 2011, Udo Steinberg wrote:
  When suspending to RAM, I'm getting a bunch of warnings from the PCI layer
  in Linux-3.2-rc6, which I didn't get with Linux-3.1. Please let me know if
  I should provide more information about platform, config, etc.
 
  This is a known issue with sdhci-pci and there's a patch fixing that,
  hopefully in the maintainer's tree waiting for the next merge window
 
 I'll push this for 3.2, thanks.

Thanks a lot!

Rafael
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Re: [PATCH v4 2/4] ARM: pxa168: Add SDHCI support

2011-12-20 Thread Haojian Zhuang 
On Wed, Dec 21, 2011 at 5:03 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
 Just two minor style issues in this patch.

 On Tue, Dec 20, 2011 at 06:43:01PM +0530, Tanmay Upadhyay wrote:
 +static inline int pxa168_add_sdh(int id, struct sdhci_pxa_platdata *data)
 +{
 +     struct pxa_device_desc *d = NULL;
 +
 +     switch (id) {
 +     case 1: d = pxa168_device_sdh1; break;
 +     case 2: d = pxa168_device_sdh2; break;
 +     case 3: d = pxa168_device_sdh3; break;
 +     case 4: d = pxa168_device_sdh4; break;

 Style.
        case X:
                d = y;
                break;

 +static void sdh_clk_disable(struct clk *clk)
 +{
 +     __raw_writel(__raw_readl(clk-clk_rst)  ~(clk-enable_val),

 Parens around clk-enable_val not required.

 +     INIT_CLKREG(clk_sdh1, NULL, PXA-SDHCLK),
 +     INIT_CLKREG(clk_sdh2, NULL, PXA-SDHCLK),
 +     INIT_CLKREG(clk_sdh3, NULL, PXA-SDHCLK),
 +     INIT_CLKREG(clk_sdh4, NULL, PXA-SDHCLK),

 So these clocks are registered with the same name?  How are they
 distinguished by clk_get()?


Yes, it's better to use devname.
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[GIT PULL] MMC fixes for 3.2

2011-12-20 Thread Chris Ball 
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

Hi Linus,

Please pull from:

  git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc.git for-linus

to receive three fixes for MMC for 3.2:

  * Revert automatic enabling of SDIO runtime PM (added in -rc1), after
finding that this has caused a regression for a few setups that we
don't know how to fix yet.  We'll try again in a later release.
  * Silence PCI suspend WARN_ON()s that appeared in -rc1 regarding
legacy PM support.  This patch is what makes the diffstat large.
  * Fix the type of a module_param in the vub300 driver.

These have been tested in linux-next, and there are no merge conflicts.
Thanks.


The following changes since commit 49df78074963c97e25debc3c67b72f059111607d:

  mmc: core: Fix deadlock when the CONFIG_MMC_UNSAFE_RESUME is not defined 
(2011-12-10 16:18:39 -0500)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc.git for-linus

for you to fetch changes up to 61074287c2965edf0fc75b54ae8f4ce99f182669:

  mmc: vub300: fix type of firmware_rom_wait_states module parameter 
(2011-12-19 15:56:09 -0800)

- 
Manuel Lauss (1):
  mmc: sdhci: remove state argument from sdhci_suspend_host

Ohad Ben-Cohen (1):
  Revert mmc: enable runtime PM by default

Rusty Russell (1):
  mmc: vub300: fix type of firmware_rom_wait_states module parameter

 drivers/mmc/core/host.c|   11 ---
 drivers/mmc/host/sdhci-cns3xxx.c   |5 +
 drivers/mmc/host/sdhci-dove.c  |5 +
 drivers/mmc/host/sdhci-esdhc-imx.c |5 +
 drivers/mmc/host/sdhci-of-esdhc.c  |5 +
 drivers/mmc/host/sdhci-of-hlwd.c   |5 +
 drivers/mmc/host/sdhci-pci.c   |   26 +-
 drivers/mmc/host/sdhci-pltfm.c |   18 +++---
 drivers/mmc/host/sdhci-pltfm.h |6 --
 drivers/mmc/host/sdhci-pxav2.c |5 +
 drivers/mmc/host/sdhci-pxav3.c |5 +
 drivers/mmc/host/sdhci-s3c.c   |   21 ++---
 drivers/mmc/host/sdhci-tegra.c |5 +
 drivers/mmc/host/sdhci.c   |2 +-
 drivers/mmc/host/sdhci.h   |2 +-
 drivers/mmc/host/vub300.c  |2 +-
 16 files changed, 53 insertions(+), 75 deletions(-)
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-- 
Chris Ball   c...@laptop.org   http://printf.net/
One Laptop Per Child
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Re: [PATCH] mmc: core: Fix voltage select in DDR mode

2011-12-20 Thread Girish K S 
Hi Chris,
can you add this in your pull request. Its been Acked by the authors
for the correction

regards
Girish K S

On 19 December 2011 22:49, Philip Rakity prak...@marvell.com wrote:

 On Dec 15, 2011, at 9:06 AM, Subhash Jadavani wrote:



 -Original Message-
 From: linux-mmc-ow...@vger.kernel.org [mailto:linux-mmc-
 ow...@vger.kernel.org] On Behalf Of Girish K S
 Sent: Thursday, December 15, 2011 5:28 PM
 To: linux-mmc@vger.kernel.org
 Cc: patc...@linaro.org; linux-samsung-...@vger.kernel.org; Girish K S;
 Philip Rakity; Arindam Nath; Chris Ball
 Subject: [PATCH] mmc: core: Fix voltage select in DDR mode

 This patch fixes the wrong comparison before setting the interface
 voltage in DDR mode.

 The assignment to the variable ddr before comaprison is either
 ddr = MMC_1_2V_DDR_MODE; or ddr == MMC_1_8V_DDR_MODE. But the
 comparison
 is done wth the extended csd value if (ddr ==
 EXT_CSD_CARD_TYPE_DDR_1_2V)

 cc: Philip Rakity prak...@marvell.com
 cc: Arindam Nath arindam.n...@amd.com
 cc: Chris Ball c...@laptop.org
 Signed-off-by: Girish K S girish.shivananja...@linaro.org
 ---
 drivers/mmc/core/mmc.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

 diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
 index 006e932..f0a9f1f 100644
 --- a/drivers/mmc/core/mmc.c
 +++ b/drivers/mmc/core/mmc.c
 @@ -1058,7 +1058,7 @@ static int mmc_init_card(struct mmc_host *host,
 u32 ocr,
                       *
                       * WARNING: eMMC rules are NOT the same as SD DDR
                       */
 -                    if (ddr == EXT_CSD_CARD_TYPE_DDR_1_2V) {
 +                    if (ddr == MMC_1_2V_DDR_MODE) {

 Looks fine.
 Acked-by: Subhash Jadavani subha...@codeaurora.org

 Acked-by: Philip Rakity prak...@marvell.com

 NOTE:  standard sdhci controller (version 3.0) does not support 1.2v 
 signaling.


                              err = mmc_set_signal_voltage(host,
                                      MMC_SIGNAL_VOLTAGE_120, 0);
                              if (err)
 --
 1.7.1

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Re: [PATCH 0/4] Fix the left DMA_NONE from dma_transfer_direction migration

2011-12-20 Thread Vinod Koul 
On Tue, 2011-12-20 at 20:54 +0800, Shawn Guo wrote:
 On Tue, Dec 20, 2011 at 02:54:04PM +0530, Vinod Koul wrote:
  On Tue, 2011-12-13 at 23:48 +0800, Shawn Guo wrote:
   I have been working on -rc recently, and have not noticed the failure
   until I ran next tree today.  The mxs-mmc driver is broken on next
   tree because the DMA_NONE was left over from the dma_transfer_direction
   migration for mxs-dma and its client drivers.
   
  For DMA transfer, the NONE direction makes no sense?
  
  In your conetext, what are you trying to achieve?
  
 The mxs-dma controller has a feature to program peripheral registers
 with given values (mxs-dma PIO mode).  This is designed to pipeline
 the operations.  For example, we can put mxs-mmc controller register
 values into scatter list as one element together with actual data.
 Triggering the mxs-dma, the dma will program the values into mxs-mmc
 controller register to set up and enable mxs-mmc, and then dma
 continue transfer data from/to mxs-mmc.  All these get done in one
 dmaengine_submit().
 
 And DMA_NONE was used to let mxs-dma know this is a PIO operation.
Sorry am little lost here. Why would DMA driver bother with a PIO mode,
that is something only peripheral driver would know about, mmc in your
case.

So what you are saying is the your dma has the capability to program the
peripheral registers in case of PIO mode, but why wouldn't the
peripheral driver do that instead? 

-- 
~Vinod

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[PATCH V7 0/2] HS200 Mode support for device and host

2011-12-20 Thread Girish K S 
changes in v7:
Updated with review comments for minor changes in host conditional
handling. added the handling for 4 bit bus width. 
Changes in v6:
   split the patch into 2 and classified them as a patch for device
   and host. Modified to include the review comments.
Changes in v5:
   Reduced the case statements for better code readability. Removed
   unused macro definitions. Modified the tuning function prototype
   and definition to support tuning for both SD and eMMC cards.
Changes in v4:
   Rebased onto chris-mmc/mmc-next branch. This patch is successfully
   applied on commit with id de022ed3fdc14808299b2fa66dbb1ed5ab921912.
Changes in v3:
   In the previous commits of chris-mmc/mmc-next branch, the patch with
   commit id (c0f22a2c92e357e7cb3988b0b13034d70b7461f9) defines caps2 for
   more capabilities. This patch version deletes the member ext_caps(created
   in my earlier patch) from struct mmc_host and reuses already accepted
   caps2 member.
Changes in v2:
   Rebased to latest chris-mmc/mmc-next branch. Resolved indentation
   problems identified in review. This patch has to be applied before
   the patch released for modifying the printk messages.
Changes in v1:
   Case statements in switch that produce same result have
   been combined to reduce repeated assignments.
   patch recreated after rebase to chris balls mmc-next branch.

Girish K S (2):
  mmc: core: HS200 mode support for eMMC 4.5
  mmc: host: Adds support for eMMC 4.5 HS200 mode

 drivers/mmc/core/bus.c |3 +-
 drivers/mmc/core/debugfs.c |3 +
 drivers/mmc/core/mmc.c |  142 +---
 drivers/mmc/core/sd.c  |3 +-
 drivers/mmc/core/sdio.c|4 +-
 drivers/mmc/host/sdhci.c   |   45 +++
 drivers/mmc/host/sdhci.h   |1 +
 include/linux/mmc/card.h   |3 +
 include/linux/mmc/host.h   |   11 +++-
 include/linux/mmc/mmc.h|   66 -
 include/linux/mmc/sdhci.h  |1 +
 11 files changed, 257 insertions(+), 25 deletions(-)

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[PATCH V7 1/2] mmc: core: HS200 mode support for eMMC 4.5

2011-12-20 Thread Girish K S 
This patch adds the support of the HS200 bus speed for eMMC 4.5 devices.
The eMMC 4.5 devices have support for 200MHz bus speed. The function
prototype of the tuning function is modified to handle the tuning command
number which is different in sd and mmc case.

cc: Chris Ball c...@laptop.org
Signed-off-by: Girish K S girish.shivananja...@linaro.org
---
 drivers/mmc/core/bus.c |3 +-
 drivers/mmc/core/debugfs.c |3 +
 drivers/mmc/core/mmc.c |  142 +---
 drivers/mmc/core/sd.c  |3 +-
 drivers/mmc/core/sdio.c|4 +-
 include/linux/mmc/card.h   |3 +
 include/linux/mmc/mmc.h|   66 -
 7 files changed, 211 insertions(+), 13 deletions(-)

diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c
index f8a228a..5d011a3 100644
--- a/drivers/mmc/core/bus.c
+++ b/drivers/mmc/core/bus.c
@@ -303,10 +303,11 @@ int mmc_add_card(struct mmc_card *card)
mmc_card_ddr_mode(card) ? DDR  : ,
type);
} else {
-   printk(KERN_INFO %s: new %s%s%s card at address %04x\n,
+   pr_info(%s: new %s%s%s%s card at address %04x\n,
mmc_hostname(card-host),
mmc_card_uhs(card) ? ultra high speed  :
(mmc_card_highspeed(card) ? high speed  : ),
+   (mmc_card_hs200(card) ? HS200  : ),
mmc_card_ddr_mode(card) ? DDR  : ,
type, card-rca);
}
diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c
index 027615d..9ab5b17 100644
--- a/drivers/mmc/core/debugfs.c
+++ b/drivers/mmc/core/debugfs.c
@@ -135,6 +135,9 @@ static int mmc_ios_show(struct seq_file *s, void *data)
case MMC_TIMING_UHS_DDR50:
str = sd uhs DDR50;
break;
+   case MMC_TIMING_MMC_HS200:
+   str = mmc high-speed SDR200;
+   break;
default:
str = invalid;
break;
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index f0a9f1f..4de3416 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -286,6 +286,27 @@ static int mmc_read_ext_csd(struct mmc_card *card, u8 
*ext_csd)
}
card-ext_csd.raw_card_type = ext_csd[EXT_CSD_CARD_TYPE];
switch (ext_csd[EXT_CSD_CARD_TYPE]  EXT_CSD_CARD_TYPE_MASK) {
+   case EXT_CSD_CARD_TYPE_SDR_ALL:
+   case EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_8V:
+   case EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_2V:
+   case EXT_CSD_CARD_TYPE_SDR_ALL_DDR_52:
+   card-ext_csd.hs_max_dtr = 2;
+   card-ext_csd.card_type = EXT_CSD_CARD_TYPE_SDR_200;
+   break;
+   case EXT_CSD_CARD_TYPE_SDR_1_2V_ALL:
+   case EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_1_8V:
+   case EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_1_2V:
+   case EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_52:
+   card-ext_csd.hs_max_dtr = 2;
+   card-ext_csd.card_type = EXT_CSD_CARD_TYPE_SDR_1_2V;
+   break;
+   case EXT_CSD_CARD_TYPE_SDR_1_8V_ALL:
+   case EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_1_8V:
+   case EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_1_2V:
+   case EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_52:
+   card-ext_csd.hs_max_dtr = 2;
+   card-ext_csd.card_type = EXT_CSD_CARD_TYPE_SDR_1_8V;
+   break;
case EXT_CSD_CARD_TYPE_DDR_52 | EXT_CSD_CARD_TYPE_52 |
 EXT_CSD_CARD_TYPE_26:
card-ext_csd.hs_max_dtr = 5200;
@@ -700,6 +721,58 @@ static int mmc_select_powerclass(struct mmc_card *card,
 }
 
 /*
+ * Selects the desired buswidth and switch to the HS200 mode
+ * if bus width set without error
+ */
+static int mmc_select_hs200(struct mmc_card *card)
+{
+   int err = 0;
+   struct mmc_host *host;
+   u32 bus_width = MMC_BUS_WIDTH_4;
+
+   BUG_ON(!card);
+
+   host = card-host;
+
+   if ((card-ext_csd.card_type  EXT_CSD_CARD_TYPE_SDR_1_2V)
+(host-caps2  MMC_CAP2_HS200_1_2V_SDR))
+   err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120, 0);
+
+   /*
+* Host is capable of 8bit transfer, then switch
+* the device to work in 8bit transfer mode. If the
+* mmc switch command returns error then switch to
+* 4bit transfer mode. On success set the corresponding
+* bus width on the host.
+*/
+   if (!err  host-caps  MMC_CAP_8_BIT_DATA) {
+   err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+EXT_CSD_BUS_WIDTH,
+EXT_CSD_BUS_WIDTH_8,
+card-ext_csd.generic_cmd6_time);
+   bus_width = MMC_BUS_WIDTH_8;
+   }
+
+   /* If the 8bit mode fails switch to 4 bit mode */
+   if (err) {
+   err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+

[PATCH V7 2/2] mmc: host: Adds support for eMMC 4.5 HS200 mode

2011-12-20 Thread Girish K S 
This patch adds support for the HS200 mode on the host side.
Also enables the tuning feature required when the HS200 mode
is selected.

cc: Chris Ball c...@laptop.org
Signed-off-by: Girish K S girish.shivananja...@linaro.org
---
 drivers/mmc/host/sdhci.c  |   45 ++---
 drivers/mmc/host/sdhci.h  |1 +
 include/linux/mmc/host.h  |   11 ++-
 include/linux/mmc/sdhci.h |1 +
 4 files changed, 46 insertions(+), 12 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index ab6018f..fb17e95 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -49,7 +49,7 @@ static void sdhci_finish_data(struct sdhci_host *);
 
 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
 static void sdhci_finish_command(struct sdhci_host *);
-static int sdhci_execute_tuning(struct mmc_host *mmc);
+static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
 static void sdhci_tuning_timer(unsigned long data);
 
 #ifdef CONFIG_PM_RUNTIME
@@ -1016,7 +1016,8 @@ static void sdhci_send_command(struct sdhci_host *host, 
struct mmc_command *cmd)
flags |= SDHCI_CMD_INDEX;
 
/* CMD19 is special in that the Data Present Select should be set */
-   if (cmd-data || (cmd-opcode == MMC_SEND_TUNING_BLOCK))
+   if (cmd-data || (cmd-opcode == MMC_SEND_TUNING_BLOCK) ||
+   (cmd-opcode == MMC_SEND_TUNING_BLOCK_HS200))
flags |= SDHCI_CMD_DATA;
 
sdhci_writew(host, SDHCI_MAKE_CMD(cmd-opcode, flags), SDHCI_COMMAND);
@@ -1287,7 +1288,7 @@ static void sdhci_request(struct mmc_host *mmc, struct 
mmc_request *mrq)
if ((host-flags  SDHCI_NEEDS_RETUNING) 
!(present_state  (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
spin_unlock_irqrestore(host-lock, flags);
-   sdhci_execute_tuning(mmc);
+   sdhci_execute_tuning(mmc, mrq-cmd-opcode);
spin_lock_irqsave(host-lock, flags);
 
/* Restore original mmc_request structure */
@@ -1371,7 +1372,8 @@ static void sdhci_do_set_ios(struct sdhci_host *host, 
struct mmc_ios *ios)
unsigned int clock;
 
/* In case of UHS-I modes, set High Speed Enable */
-   if ((ios-timing == MMC_TIMING_UHS_SDR50) ||
+   if ((ios-timing == MMC_TIMING_MMC_HS200) ||
+   (ios-timing == MMC_TIMING_UHS_SDR50) ||
(ios-timing == MMC_TIMING_UHS_SDR104) ||
(ios-timing == MMC_TIMING_UHS_DDR50) ||
(ios-timing == MMC_TIMING_UHS_SDR25) ||
@@ -1425,7 +1427,9 @@ static void sdhci_do_set_ios(struct sdhci_host *host, 
struct mmc_ios *ios)
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
/* Select Bus Speed Mode for host */
ctrl_2 = ~SDHCI_CTRL_UHS_MASK;
-   if (ios-timing == MMC_TIMING_UHS_SDR12)
+   if (ios-timing == MMC_TIMING_MMC_HS200)
+   ctrl_2 |= SDHCI_CTRL_HS_SDR200;
+   else if (ios-timing == MMC_TIMING_UHS_SDR12)
ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
else if (ios-timing == MMC_TIMING_UHS_SDR25)
ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
@@ -1673,7 +1677,7 @@ static int sdhci_start_signal_voltage_switch(struct 
mmc_host *mmc,
return err;
 }
 
-static int sdhci_execute_tuning(struct mmc_host *mmc)
+static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
 {
struct sdhci_host *host;
u16 ctrl;
@@ -1694,10 +1698,13 @@ static int sdhci_execute_tuning(struct mmc_host *mmc)
 * Host Controller needs tuning only in case of SDR104 mode
 * and for SDR50 mode when Use Tuning for SDR50 is set in
 * Capabilities register.
+* If the Host Controller supports the HS200 mode then tuning
+* function has to be executed.
 */
if (((ctrl  SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
(((ctrl  SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) 
-   (host-flags  SDHCI_SDR50_NEEDS_TUNING)))
+   (host-flags  SDHCI_SDR50_NEEDS_TUNING)) ||
+   (host-flags  SDHCI_HS200_NEEDS_TUNING))
ctrl |= SDHCI_CTRL_EXEC_TUNING;
else {
spin_unlock(host-lock);
@@ -1733,7 +1740,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc)
if (!tuning_loop_counter  !timeout)
break;
 
-   cmd.opcode = MMC_SEND_TUNING_BLOCK;
+   cmd.opcode = opcode;
cmd.arg = 0;
cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
cmd.retries = 0;
@@ -1748,7 +1755,17 @@ static int sdhci_execute_tuning(struct mmc_host *mmc)
 * block to the Host Controller. So we set

Re: [PATCH 0/4] Fix the left DMA_NONE from dma_transfer_direction migration

2011-12-20 Thread Shawn Guo 
On Wed, Dec 21, 2011 at 09:37:04AM +0530, Vinod Koul wrote:
 On Tue, 2011-12-20 at 20:54 +0800, Shawn Guo wrote:
  On Tue, Dec 20, 2011 at 02:54:04PM +0530, Vinod Koul wrote:
   On Tue, 2011-12-13 at 23:48 +0800, Shawn Guo wrote:
I have been working on -rc recently, and have not noticed the failure
until I ran next tree today.  The mxs-mmc driver is broken on next
tree because the DMA_NONE was left over from the dma_transfer_direction
migration for mxs-dma and its client drivers.

   For DMA transfer, the NONE direction makes no sense?
   
   In your conetext, what are you trying to achieve?
   
  The mxs-dma controller has a feature to program peripheral registers
  with given values (mxs-dma PIO mode).  This is designed to pipeline
  the operations.  For example, we can put mxs-mmc controller register
  values into scatter list as one element together with actual data.
  Triggering the mxs-dma, the dma will program the values into mxs-mmc
  controller register to set up and enable mxs-mmc, and then dma
  continue transfer data from/to mxs-mmc.  All these get done in one
  dmaengine_submit().
  
  And DMA_NONE was used to let mxs-dma know this is a PIO operation.
 Sorry am little lost here. Why would DMA driver bother with a PIO mode,
 that is something only peripheral driver would know about, mmc in your
 case.
 
The term PIO here may not the one on your mind.  I call it 'mxs-dma
pio'.  In this mode, mxs-dma hardware can write values into mmc
controller register without cpu involved.

 So what you are saying is the your dma has the capability to program the
 peripheral registers in case of PIO mode, but why wouldn't the
 peripheral driver do that instead? 
 
Yes, I'm saying mxs-dma has the capability to program the peripheral
registers, and that's called 'mxs-dma pio' mode.

-- 
Regards,
Shawn

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Re: [PATCH 0/4] Fix the left DMA_NONE from dma_transfer_direction migration

2011-12-20 Thread Vinod Koul 
On Wed, 2011-12-21 at 12:45 +0800, Shawn Guo wrote:
  
 The term PIO here may not the one on your mind.  I call it 'mxs-dma
 pio'.  In this mode, mxs-dma hardware can write values into mmc
 controller register without cpu involved.
what do you mean by values here?

-- 
~Vinod

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Re: [PATCH 0/4] Fix the left DMA_NONE from dma_transfer_direction migration

2011-12-20 Thread Shawn Guo 
On Wed, Dec 21, 2011 at 10:10:51AM +0530, Vinod Koul wrote:
 On Wed, 2011-12-21 at 12:45 +0800, Shawn Guo wrote:
   
  The term PIO here may not the one on your mind.  I call it 'mxs-dma
  pio'.  In this mode, mxs-dma hardware can write values into mmc
  controller register without cpu involved.
 what do you mean by values here?
 
The register values that we want to write to mmc controller registers
in this case.

-- 
Regards,
Shawn

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Re: [PATCH V7 1/2] mmc: core: HS200 mode support for eMMC 4.5

2011-12-20 Thread Philip Rakity 

On Dec 20, 2011, at 8:12 PM, Girish K S wrote:

 This patch adds the support of the HS200 bus speed for eMMC 4.5 devices.
 The eMMC 4.5 devices have support for 200MHz bus speed. The function
 prototype of the tuning function is modified to handle the tuning command
 number which is different in sd and mmc case.

 cc: Chris Ball c...@laptop.org
 Signed-off-by: Girish K S girish.shivananja...@linaro.org
 ---
 drivers/mmc/core/bus.c |3 +-
 drivers/mmc/core/debugfs.c |3 +
 drivers/mmc/core/mmc.c |  142 +---
 drivers/mmc/core/sd.c  |3 +-
 drivers/mmc/core/sdio.c|4 +-
 include/linux/mmc/card.h   |3 +
 include/linux/mmc/mmc.h|   66 -
 7 files changed, 211 insertions(+), 13 deletions(-)

 diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c
 index f8a228a..5d011a3 100644
 --- a/drivers/mmc/core/bus.c
 +++ b/drivers/mmc/core/bus.c
 @@ -303,10 +303,11 @@ int mmc_add_card(struct mmc_card *card)
mmc_card_ddr_mode(card) ? DDR  : ,
type);
} else {
 -   printk(KERN_INFO %s: new %s%s%s card at address %04x\n,
 +   pr_info(%s: new %s%s%s%s card at address %04x\n,
mmc_hostname(card-host),
mmc_card_uhs(card) ? ultra high speed  :
(mmc_card_highspeed(card) ? high speed  : ),
 +   (mmc_card_hs200(card) ? HS200  : ),
mmc_card_ddr_mode(card) ? DDR  : ,
type, card-rca);
}
 diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c
 index 027615d..9ab5b17 100644
 --- a/drivers/mmc/core/debugfs.c
 +++ b/drivers/mmc/core/debugfs.c
 @@ -135,6 +135,9 @@ static int mmc_ios_show(struct seq_file *s, void *data)
case MMC_TIMING_UHS_DDR50:
str = sd uhs DDR50;
break;
 +   case MMC_TIMING_MMC_HS200:
 +   str = mmc high-speed SDR200;
 +   break;
default:
str = invalid;
break;
 diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
 index f0a9f1f..4de3416 100644
 --- a/drivers/mmc/core/mmc.c
 +++ b/drivers/mmc/core/mmc.c
 @@ -286,6 +286,27 @@ static int mmc_read_ext_csd(struct mmc_card *card, u8 
 *ext_csd)
}
card-ext_csd.raw_card_type = ext_csd[EXT_CSD_CARD_TYPE];
switch (ext_csd[EXT_CSD_CARD_TYPE]  EXT_CSD_CARD_TYPE_MASK) {
 +   case EXT_CSD_CARD_TYPE_SDR_ALL:
 +   case EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_8V:
 +   case EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_2V:
 +   case EXT_CSD_CARD_TYPE_SDR_ALL_DDR_52:
 +   card-ext_csd.hs_max_dtr = 2;
 +   card-ext_csd.card_type = EXT_CSD_CARD_TYPE_SDR_200;
 +   break;
 +   case EXT_CSD_CARD_TYPE_SDR_1_2V_ALL:
 +   case EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_1_8V:
 +   case EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_1_2V:
 +   case EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_52:
 +   card-ext_csd.hs_max_dtr = 2;
 +   card-ext_csd.card_type = EXT_CSD_CARD_TYPE_SDR_1_2V;
 +   break;
 +   case EXT_CSD_CARD_TYPE_SDR_1_8V_ALL:
 +   case EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_1_8V:
 +   case EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_1_2V:
 +   case EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_52:
 +   card-ext_csd.hs_max_dtr = 2;
 +   card-ext_csd.card_type = EXT_CSD_CARD_TYPE_SDR_1_8V;
 +   break;
case EXT_CSD_CARD_TYPE_DDR_52 | EXT_CSD_CARD_TYPE_52 |
 EXT_CSD_CARD_TYPE_26:
card-ext_csd.hs_max_dtr = 5200;
 @@ -700,6 +721,58 @@ static int mmc_select_powerclass(struct mmc_card *card,
 }

 /*
 + * Selects the desired buswidth and switch to the HS200 mode
 + * if bus width set without error
 + */
 +static int mmc_select_hs200(struct mmc_card *card)
 +{
 +   int err = 0;
 +   struct mmc_host *host;
 +   u32 bus_width = MMC_BUS_WIDTH_4;
 +
 +   BUG_ON(!card);
 +
 +   host = card-host;
 +
 +   if ((card-ext_csd.card_type  EXT_CSD_CARD_TYPE_SDR_1_2V)
 +(host-caps2  MMC_CAP2_HS200_1_2V_SDR))
 +   err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120, 0);

if 1.2 volt is not supported should one try 1.8v signaling ?

 +
 +   /*
 +* Host is capable of 8bit transfer, then switch
 +* the device to work in 8bit transfer mode. If the
 +* mmc switch command returns error then switch to
 +* 4bit transfer mode. On success set the corresponding
 +* bus width on the host.
 +*/
 +   if (!err  host-caps  MMC_CAP_8_BIT_DATA) {
 +   err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
 +EXT_CSD_BUS_WIDTH,
 +EXT_CSD_BUS_WIDTH_8,
 +card-ext_csd.generic_cmd6_time);
 +   bus_width =

RE: [PATCH V7 1/2] mmc: core: HS200 mode support for eMMC 4.5

2011-12-20 Thread Subhash Jadavani 


 -Original Message-
 From: linux-mmc-ow...@vger.kernel.org [mailto:linux-mmc-
 ow...@vger.kernel.org] On Behalf Of Girish K S
 Sent: Wednesday, December 21, 2011 9:43 AM
 To: linux-mmc@vger.kernel.org
 Cc: patc...@linaro.org; linux-samsung-...@vger.kernel.org; Girish K S;
 Chris Ball
 Subject: [PATCH V7 1/2] mmc: core: HS200 mode support for eMMC 4.5
 
 This patch adds the support of the HS200 bus speed for eMMC 4.5
 devices.
 The eMMC 4.5 devices have support for 200MHz bus speed. The function
 prototype of the tuning function is modified to handle the tuning
 command
 number which is different in sd and mmc case.
 
 cc: Chris Ball c...@laptop.org
 Signed-off-by: Girish K S girish.shivananja...@linaro.org
 ---
  drivers/mmc/core/bus.c |3 +-
  drivers/mmc/core/debugfs.c |3 +
  drivers/mmc/core/mmc.c |  142
 +---
  drivers/mmc/core/sd.c  |3 +-
  drivers/mmc/core/sdio.c|4 +-
  include/linux/mmc/card.h   |3 +
  include/linux/mmc/mmc.h|   66 -

Looks like you have missed to add change in include/linux/mmc/host.h in
this patch.



  7 files changed, 211 insertions(+), 13 deletions(-)
 
 diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c
 index f8a228a..5d011a3 100644
 --- a/drivers/mmc/core/bus.c
 +++ b/drivers/mmc/core/bus.c
 @@ -303,10 +303,11 @@ int mmc_add_card(struct mmc_card *card)
   mmc_card_ddr_mode(card) ? DDR  : ,
   type);
   } else {
 - printk(KERN_INFO %s: new %s%s%s card at address %04x\n,
 + pr_info(%s: new %s%s%s%s card at address %04x\n,
   mmc_hostname(card-host),
   mmc_card_uhs(card) ? ultra high speed  :
   (mmc_card_highspeed(card) ? high speed  : ),
 + (mmc_card_hs200(card) ? HS200  : ),
   mmc_card_ddr_mode(card) ? DDR  : ,
   type, card-rca);
   }
 diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c
 index 027615d..9ab5b17 100644
 --- a/drivers/mmc/core/debugfs.c
 +++ b/drivers/mmc/core/debugfs.c
 @@ -135,6 +135,9 @@ static int mmc_ios_show(struct seq_file *s, void
 *data)
   case MMC_TIMING_UHS_DDR50:
   str = sd uhs DDR50;
   break;
 + case MMC_TIMING_MMC_HS200:
 + str = mmc high-speed SDR200;
 + break;
   default:
   str = invalid;
   break;
 diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
 index f0a9f1f..4de3416 100644
 --- a/drivers/mmc/core/mmc.c
 +++ b/drivers/mmc/core/mmc.c
 @@ -286,6 +286,27 @@ static int mmc_read_ext_csd(struct mmc_card *card,
 u8 *ext_csd)
   }
   card-ext_csd.raw_card_type = ext_csd[EXT_CSD_CARD_TYPE];
   switch (ext_csd[EXT_CSD_CARD_TYPE]  EXT_CSD_CARD_TYPE_MASK) {
 + case EXT_CSD_CARD_TYPE_SDR_ALL:
 + case EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_8V:
 + case EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_2V:
 + case EXT_CSD_CARD_TYPE_SDR_ALL_DDR_52:
 + card-ext_csd.hs_max_dtr = 2;
 + card-ext_csd.card_type = EXT_CSD_CARD_TYPE_SDR_200;
 + break;
 + case EXT_CSD_CARD_TYPE_SDR_1_2V_ALL:
 + case EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_1_8V:
 + case EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_1_2V:
 + case EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_52:
 + card-ext_csd.hs_max_dtr = 2;
 + card-ext_csd.card_type = EXT_CSD_CARD_TYPE_SDR_1_2V;
 + break;
 + case EXT_CSD_CARD_TYPE_SDR_1_8V_ALL:
 + case EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_1_8V:
 + case EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_1_2V:
 + case EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_52:
 + card-ext_csd.hs_max_dtr = 2;
 + card-ext_csd.card_type = EXT_CSD_CARD_TYPE_SDR_1_8V;
 + break;
   case EXT_CSD_CARD_TYPE_DDR_52 | EXT_CSD_CARD_TYPE_52 |
EXT_CSD_CARD_TYPE_26:
   card-ext_csd.hs_max_dtr = 5200;
 @@ -700,6 +721,58 @@ static int mmc_select_powerclass(struct mmc_card
 *card,
  }
 
  /*
 + * Selects the desired buswidth and switch to the HS200 mode
 + * if bus width set without error
 + */
 +static int mmc_select_hs200(struct mmc_card *card)
 +{
 + int err = 0;
 + struct mmc_host *host;
 + u32 bus_width = MMC_BUS_WIDTH_4;
 +
 + BUG_ON(!card);
 +
 + host = card-host;
 +
 + if ((card-ext_csd.card_type  EXT_CSD_CARD_TYPE_SDR_1_2V)
 +  (host-caps2  MMC_CAP2_HS200_1_2V_SDR))
 + err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120,
 0);
 +
 + /*
 +  * Host is capable of 8bit transfer, then switch
 +  * the device to work in 8bit transfer mode. If the
 +  * mmc switch command returns error then switch to
 +  * 4bit transfer mode. On success set the corresponding
 +  * bus width on the host.
 +  */
 + if (!err  host-caps  MMC_CAP_8_BIT_DATA) {
 + err =

[PATCH] mmc: use usleep_range() in mmc_delay()

2011-12-20 Thread Dmitry Antipov 

From f447d78db65c6675e69466e8ed08364ff065ac08 Mon Sep 17 00:00:00 2001
From: Dmitry Antipov dmitry.anti...@linaro.org
Date: Wed, 21 Dec 2011 10:51:03 +0400
Subject: [PATCH] mmc: use usleep_range() in mmc_delay()

---
 drivers/mmc/core/core.h |8 ++--
 1 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/core/core.h b/drivers/mmc/core/core.h
index 14664f1..a77851e 100644
--- a/drivers/mmc/core/core.h
+++ b/drivers/mmc/core/core.h
@@ -47,12 +47,8 @@ void mmc_power_off(struct mmc_host *host);

 static inline void mmc_delay(unsigned int ms)
 {
-   if (ms  1000 / HZ) {
-   cond_resched();
-   mdelay(ms);
-   } else {
-   msleep(ms);
-   }
+   unsigned long us = ms * USEC_PER_MSEC;
+   usleep_range(us, us + 1000);
 }

 void mmc_rescan(struct work_struct *work);
--
1.7.7.4

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[PATCH] MMC-4.5 Data Tag Support

2011-12-20 Thread Saugata Das 
From: Saugata Das saugata@linaro.org

MMC-4.5 data tag feature will be used to store the file system meta-data in the
tagged region of eMMC. This will improve the write and subsequent read transfer
time for the meta data.

Signed-off-by: Saugata Das saugata@linaro.org
---
 drivers/mmc/card/block.c |   17 +++--
 drivers/mmc/core/mmc.c   |   14 ++
 include/linux/mmc/card.h |2 ++
 include/linux/mmc/mmc.h  |3 +++
 4 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index a1cb21f..af3b6c3 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -995,6 +995,7 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
struct mmc_blk_request *brq = mqrq-brq;
struct request *req = mqrq-req;
struct mmc_blk_data *md = mq-data;
+   bool do_data_tag;
 
/*
 * Reliable writes are used to implement Forced Unit Access and
@@ -1071,6 +1072,16 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req 
*mqrq,
mmc_apply_rel_rw(brq, card, req);
 
/*
+* Data tag is used only during writing meta data to speed
+* up write and any subsequent read of this meta data
+*/
+   do_data_tag = (card-ext_csd.data_tag_unit_size) 
+   (req-cmd_flags  REQ_META) 
+   (rq_data_dir(req) == WRITE) 
+   ((brq-data.blocks * brq-data.blksz) =
+   card-ext_csd.data_tag_unit_size) ;
+
+   /*
 * Pre-defined multi-block transfers are preferable to
 * open ended-ones (and necessary for reliable writes).
 * However, it is not sufficient to just send CMD23,
@@ -1091,10 +1102,12 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req 
*mqrq,
 
if ((md-flags  MMC_BLK_CMD23) 
mmc_op_multi(brq-cmd.opcode) 
-   (do_rel_wr || !(card-quirks  MMC_QUIRK_BLK_NO_CMD23))) {
+   (do_rel_wr || !(card-quirks  MMC_QUIRK_BLK_NO_CMD23) ||
+   do_data_tag)) {
brq-sbc.opcode = MMC_SET_BLOCK_COUNT;
brq-sbc.arg = brq-data.blocks |
-   (do_rel_wr ? (1  31) : 0);
+   (do_rel_wr ? (1  31) : 0) |
+   (do_data_tag ? (1  29) : 0);
brq-sbc.flags = MMC_RSP_R1 | MMC_CMD_AC;
brq-mrq.sbc = brq-sbc;
}
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index dbf421a..244049b 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -488,6 +488,20 @@ static int mmc_read_ext_csd(struct mmc_card *card, u8 
*ext_csd)
ext_csd[EXT_CSD_CACHE_SIZE + 1]  8 |
ext_csd[EXT_CSD_CACHE_SIZE + 2]  16 |
ext_csd[EXT_CSD_CACHE_SIZE + 3]  24;
+
+   if (ext_csd[EXT_CSD_DATA_SECTOR_SIZE] == 1)
+   card-ext_csd.data_sector_size = 4096;
+   else
+   card-ext_csd.data_sector_size = 512;
+
+   if ((ext_csd[EXT_CSD_DATA_TAG_SUPPORT]  1) 
+   (ext_csd[EXT_CSD_TAG_UNIT_SIZE] = 8)) {
+   card-ext_csd.data_tag_unit_size =
+   ((unsigned int) 1  ext_csd[EXT_CSD_TAG_UNIT_SIZE]) *
+   (card-ext_csd.data_sector_size);
+   } else {
+   card-ext_csd.data_tag_unit_size = 0;
+   }
}
 
 out:
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index 415f2db..a55668d 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -71,6 +71,8 @@ struct mmc_ext_csd {
boolhpi_en; /* HPI enablebit */
boolhpi;/* HPI support bit */
unsigned inthpi_cmd;/* cmd used as HPI */
+   unsigned intdata_sector_size;   /* 512Bytes or 4KB */
+   unsigned intdata_tag_unit_size; /* DATA TAG UNIT size */
u8  raw_partition_support;  /* 160 */
u8  raw_erased_mem_count;   /* 181 */
u8  raw_ext_csd_structure;  /* 194 */
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index 0e71356..e076f7f 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -273,6 +273,7 @@ struct _mmc_csd {
 #define EXT_CSD_FLUSH_CACHE32  /* W */
 #define EXT_CSD_CACHE_CTRL 33  /* R/W */
 #define EXT_CSD_POWER_OFF_NOTIFICATION 34  /* R/W */
+#define EXT_CSD_DATA_SECTOR_SIZE   61  /* R */
 #define EXT_CSD_GP_SIZE_MULT   143 /* R/W */
 #define EXT_CSD_PARTITION_ATTRIBUTE156 /* R/W */
 #define EXT_CSD_PARTITION_SUPPORT  160 /* RO */
@@ -313,6 +314,8 @@ struct _mmc_csd {
 #define EXT_CSD_POWER_OFF_LONG_TIME247 /* RO */
 #define EXT_CSD_GENERIC_CMD6_TIME

[PATCH V2 1/2] SD/MMC: add an interface to re-initialize bounce buffer

2011-12-20 Thread Qiang Liu 
Add bounce_size under /sys/block/mmcblk0/bouncesz.
Support dynamic adjustment of bounce buffer in run-time (include mounted or
unmounted filesystem).

/sys/block/mmcblk0/bouncesz should be integer multiple of 512, the
value should be range from 4096 to 4194304.

1. use variable instead of MMC_QUEUE_BOUNCESZ;
2. Re-initialize bounce buffer accorinding to new bounce size at run-time;

Signed-off-by: Qiang Liu qiang@freescale.com
---
changes for V2
merge former 2 patches to 1

Here is the test results with different mmc bounce size, IOzone is used to
test performance of mass data transmission.
Environment:
PowerPC P1022DS platform, Sandisk Class 10, 4G memory card, EXT4 filesystem
[root@p2020ds root]# cat /sys/fs/   block/mmcblk0/bouncesz
65536
[root@p2020ds root]# mount /dev/mmcblk0p1 /mnt/
EXT4-fs (mmcblk0p1): mounted filesystem without journal. Opts:
[root@p2020ds root]# iozone -Rab result -i0 -i1 -r64 =-  -n1g -g4g -f /mnt/ff

  KB  reclen   write rewritereadreread
 1048576  64   14229   13286   662028   663372
 2097152  64   13758   126054954947443
 4194304  64   13435   122152197422096

[root@p2020ds root]# echo 262144  /sys/block/mmcblk0/bouncesz
[root@p2020ds root]# cat /sys/block/mmcblk0/bouncesz
262144
[root@p2020ds root]# iozone -Rab result -i0 -i1 -r64 -n1g -g4g -f /mnt/ff

  KB  reclen   write rewritereadreread
 1048576  64   19228   19416   676659   677785
 2097152  64   18512   184992697827055
 4194304  64   17932   181852194521805

[root@p2020ds root]# echo 8192  /sys/block/mmcblk0/bouncesz
[root@p2020ds root]# cat /sys/block/mmcblk0/bouncesz
8192
[root@p2020ds root]# iozone -Rab result -i0 -i1 -r64 -n1g -g1g -f /mnt/ff
  KB  reclen   write rewritereadreread
 1048576  6450683324   640266   641609
---
 drivers/mmc/card/block.c |   43 +++
 drivers/mmc/card/queue.c |  102 +-
 drivers/mmc/card/queue.h |6 +++
 3 files changed, 149 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index 0c959c9..790abe2 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -59,6 +59,9 @@ MODULE_ALIAS(mmc:block);
 #define INAND_CMD38_ARG_SECTRIM1 0x81
 #define INAND_CMD38_ARG_SECTRIM2 0x88

+#define MMC_MIN_QUEUE_BOUNCESZ 4096
+#define MMC_MAX_QUEUE_BOUNCESZ 4194304
+
 static DEFINE_MUTEX(block_mutex);

 /*
@@ -108,6 +111,7 @@ struct mmc_blk_data {
unsigned intpart_curr;
struct device_attribute force_ro;
struct device_attribute power_ro_lock;
+   struct device_attribute bouncesz;
int area_type;
 };

@@ -1633,6 +1637,7 @@ static void mmc_blk_remove_req(struct mmc_blk_data *md)
del_gendisk(md-disk);
}

+   device_remove_file(disk_to_dev(md-disk), md-bouncesz);
/* Then flush out any already in there */
mmc_cleanup_queue(md-queue);
mmc_blk_put(md);
@@ -1739,6 +1744,33 @@ static const struct mmc_fixup blk_fixups[] =
END_FIXUP
 };

+#ifdef CONFIG_MMC_BLOCK_BOUNCE
+static ssize_t mmc_bouncesz_show(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+return sprintf(buf, %u\n, mmc_queue_bouncesz);
+}
+
+static ssize_t mmc_bouncesz_store(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf, size_t count)
+{
+   unsigned int bouncesz;
+   struct mmc_blk_data *md;
+
+   if ((sscanf(buf, %d, bouncesz) != 1) ||
+   (bouncesz  MMC_MIN_QUEUE_BOUNCESZ) ||
+   (bouncesz  MMC_MAX_QUEUE_BOUNCESZ) ||
+   (bouncesz % 512 != 0))
+   return -EINVAL;
+
+   md = mmc_blk_get(dev_to_disk(dev));
+   mmc_reinit_bounce_queue(md-queue, md-queue.card, bouncesz);
+   mmc_blk_put(md);
+   return mmc_queue_bouncesz;
+}
+#endif
+
 static int mmc_blk_probe(struct mmc_card *card)
 {
struct mmc_blk_data *md, *part_md;
@@ -1771,6 +1803,17 @@ static int mmc_blk_probe(struct mmc_card *card)
mmc_set_drvdata(card, md);
mmc_fixup_device(card, blk_fixups);

+#ifdef CONFIG_MMC_BLOCK_BOUNCE
+   md-bouncesz.show = mmc_bouncesz_show;
+   md-bouncesz.store = mmc_bouncesz_store;
+   sysfs_attr_init(md-bouncesz.attr);
+   md-bouncesz.attr.name = bouncesz;
+   md-bouncesz.attr.mode = S_IRUGO | S_IWUSR;
+   err = device_create_file(disk_to_dev(md-disk), md-bouncesz);
+   if (err)
+   goto out;
+#endif
+
if (mmc_add_disk(md))
goto out;

diff --git a/drivers/mmc/card/queue.c b/drivers/mmc/card/queue.c
index dcad59c..c563e33 100644
---

[PATCH V2 2/2] mmc/doc: feature description of runtime bounce buffer size adjustment

2011-12-20 Thread Qiang Liu 
Add feature description about runtime bounce buffer size adjustment.

CC: Chris Ball c...@laptop.org
Signed-off-by: Qiang Liu qiang@freescale.com
---
changes for V2
add suplementary description of bouncesz limitation

 Documentation/mmc/mmc-dev-attrs.txt |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/Documentation/mmc/mmc-dev-attrs.txt 
b/Documentation/mmc/mmc-dev-attrs.txt
index 22ae844..1314cab 100644
--- a/Documentation/mmc/mmc-dev-attrs.txt
+++ b/Documentation/mmc/mmc-dev-attrs.txt
@@ -7,6 +7,8 @@ SD or MMC device.
 The following attributes are read/write.

force_roEnforce read-only access even if write protect 
switch is off.
+   bounceszSupport dynamic adjustment of bounce buffer 
size at runtime,
+   from 4096 to 4194304, integer multiple of 512 
bytes only.

 SD and MMC Device Attributes
 
--
1.6.4


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