Re: [PATCH v2 0/6] UHS-I support for sh_mobile_sdhi
On Thu, 2015-06-11 at 11:49 +0900, Simon Horman wrote: On Thu, Jun 11, 2015 at 12:57:57AM +0100, Ben Hutchings wrote: On Wed, 2015-06-10 at 11:16 +0200, Ulf Hansson wrote: On 10 June 2015 at 01:21, Ben Hutchings ben.hutchi...@codethink.co.uk wrote: This series adds support for UHS-I in sh_mobile_sdhi, partly implemented in tmio_mmc. This does not yet include tuning for SDR-104, but SDR-50 now works on the R8A7790 Lager board and another development board. The pfc block needs to be reconfigured from 3.3V to 1.8V signalling on the pins wired to the SD card. This is supported by adding separate functions for 1.8V signalling in sh-pfc (sdhi0_1v8 etc.). I expect that several SH SoCs have this capability, but I only have the R8A7790 data sheet so I only implemented it for that one. Changes since v1: - Reword commit message for mmc: tmio: Add UHS-I mode support - Make sh_mobile_sdhi_start_signal_voltage_switch() succeed if asked to switch to 3.3V and the regulator or pinctrl or pinctrl state is missing - Drop change to mmcif clock on Lager - Correct original author for sdhi clock changes on Lager Changes since the RFC: - Replace the 'regulator' devices for signal voltage switching with pinctrl functions and states - Drop 'mmc: sh_mobile_sdhi: Add actual clock rate support' as it's redundant - Use a switch statement in sh_mobile_sdhi_start_signal_voltage_switch() - Fix subject prefix for the DT changes Ben. Ben Hutchings (5): mmc: tmio: Add UHS-I mode support pinctrl: sh-pfc: Add set_mux operation to struct sh_pfc_function pinctrl: sh-pfc: r8a7790: Add separate functions for SDHI 1.8V operation mmc: sh_mobile_sdhi: Add UHS-I mode support ARM: shmobile: lager: Enable UHS-I SDR-50 Ian Molton (1): ARM: shmobile: lager: Set clock rates for SDHI arch/arm/boot/dts/r8a7790-lager.dts | 24 +++-- drivers/mmc/host/sh_mobile_sdhi.c| 60 +++ drivers/mmc/host/tmio_mmc.h | 3 ++ drivers/mmc/host/tmio_mmc_pio.c | 31 drivers/pinctrl/sh-pfc/core.c| 2 +- drivers/pinctrl/sh-pfc/core.h| 1 + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 70 +--- drivers/pinctrl/sh-pfc/pinctrl.c | 4 +++ drivers/pinctrl/sh-pfc/sh_pfc.h | 10 +- 9 files changed, 197 insertions(+), 8 deletions(-) -- 2.1.4 Hi Ben, I have looked at the mmc patches, those looks good to me. Regarding the pinctrl and ARM patches, I suppose these can be taken through their respective trees and I can take the mmc patches? The problem with that is that I think the device tree change will cause a regression if it's applied without the driver changes. I would much prefer if I could get the pinctrl and device tree changes acked by the respective maintainers to go through the MMC tree. (I should probably have said that up front.) Hi Ben, I may be misunderstanding the above, if so I apologise, but I would strongly prefer to avoid an arrangement where the kernel and device tree blob (DTS/DTSI - DTB) need to be upgrade in lock-step as this tends not to lead to a good experience for users. I agree. My preference would be to maintain backwards and forwards compatibility and if appropriate schedule removal of such compatibility. [...] The problem is that the 'sd-uhs-sdr50' property is interpreted by the MMC core, so I think it will start trying to use this mode even if the driver hasn't implemented the necessary operations. I don't see any way around that. The regression is relatively minor as I think the MMC core will fall back to a lower speed after failing to enable SDR50. But it will slow down probing of a card. Ben. -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2] mmc: enable Enhance Strobe for HS400.
Hi,
Thanks for review and sorry for late to reply. I am on a business travel.
-Original Message-
From: ritesh.harj...@gmail.com [mailto:ritesh.harj...@gmail.com] On Behalf Of
Ritesh Harjani
Sent: Saturday, June 06, 2015 5:50 AM
To: Sun, Yi Y
Cc: linux-mmc@vger.kernel.org; ulf.hans...@linaro.org
Subject: Re: [PATCH v2] mmc: enable Enhance Strobe for HS400.
Hi Sun,
Did you get to test this feature on any of the target?
Yes, this feature is tested on FPGA board. HS400 initialization pass and
read/write work well.
On Fri, Jun 5, 2015 at 8:20 AM, Yi Sun yi.y@intel.com wrote:
Enhance Strobe is defined in v5.1 eMMC spec. This commit is to
implement it.
Normal Strobe signal for HS400 is only provided during Data Out and
CRC Response. While Enhance Strobe is enabled, Strobe signal is
provided during Data Out, CRC Response and CMD Response.
While enabling Enhance Strobe, the initialization of HS400 does not
need enabling HS200 and executing tuning anymore.
If enhanced strobe is enabled, what about SDHCI_NEEDS_RETUNING flag ?
In case of CRC error, we do execute tuning, but now after support of enhanced
strobe, how will that be taken care of?
Per my knowledge, re-tuning is not needed for Enhance Strobe. Otherwise, the
eMMC HS400 initialization process should do it too, like HS200. But I really
miss something here not to do re-tuning if Enhance Strobe is enabled. I will
add it. To be frankly, on FPGA, there is no PM and CRC error happened so I do
not verify it. I will also try to simulate some scenarios to verify the process.
This simplifies the HS400 initialization process much.
Per spec, there is a STROBE_SUPPORT added in EXT_CSD register to
indicate that card supports Enhance Strobe or not. If it is supported,
host can enable this feature by enabling the most significant bit of
BUS_WIDTH before set HS_TIMING to HS400.
enhanced strobe feature also requires support from host controller side as
well. Dont you think we should provide some ops here for that?
Yes, thanks for suggestion!
Signed-off-by: Yi Sun yi.y@intel.com
---
drivers/mmc/core/mmc.c | 61
++
include/linux/mmc/card.h |1 +
include/linux/mmc/mmc.h |2 ++
3 files changed, 59 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index
e519e31..c9ef2de 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -585,6 +585,12 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8
*ext_csd)
card-ext_csd.ffu_capable =
(ext_csd[EXT_CSD_SUPPORTED_MODE] 0x1)
!(ext_csd[EXT_CSD_FW_CONFIG] 0x1);
+
+ /* Enhance Strobe is supported since v5.1 which rev should be
+* 8 but some eMMC devices can support it with rev 7. So
handle
+* Enhance Strobe here.
+*/
+ card-ext_csd.strobe_support =
+ ext_csd[EXT_CSD_STROBE_SUPPORT];
}
out:
return err;
@@ -1049,9 +1055,28 @@ static int mmc_select_hs400(struct mmc_card *card)
/*
* HS400 mode requires 8-bit bus width
*/
comment not valid?
- if (!(card-mmc_avail_type EXT_CSD_CARD_TYPE_HS400
- host-ios.bus_width == MMC_BUS_WIDTH_8))
- return 0;
+ if (card-ext_csd.strobe_support) {
+ if (!(card-mmc_avail_type EXT_CSD_CARD_TYPE_HS400
+ host-caps MMC_CAP_8_BIT_DATA))
+ return 0;
+
+ /* For Enhance Strobe flow. For non Enhance Strobe, signal
+* voltage will not be set.
+*/
+ if (card-mmc_avail_type EXT_CSD_CARD_TYPE_HS200_1_2V)
+ err = __mmc_set_signal_voltage(host,
+ MMC_SIGNAL_VOLTAGE_120);
+
+ if (err card-mmc_avail_type
EXT_CSD_CARD_TYPE_HS200_1_8V)
+ err = __mmc_set_signal_voltage(host,
+ MMC_SIGNAL_VOLTAGE_180);
+ if (err)
+ return err;
+ } else {
+ if (!(card-mmc_avail_type EXT_CSD_CARD_TYPE_HS400
+ host-ios.bus_width == MMC_BUS_WIDTH_8))
+ return 0;
+ }
/*
* Before switching to dual data rate operation for HS400, @@
-1072,15 +1097,36 @@ static int mmc_select_hs400(struct mmc_card *card)
return err;
}
+ val = EXT_CSD_DDR_BUS_WIDTH_8;
+ if (card-ext_csd.strobe_support)
+ val |= EXT_CSD_BUS_WIDTH_STROBE;
err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
EXT_CSD_BUS_WIDTH,
-EXT_CSD_DDR_BUS_WIDTH_8,
+val,
card-ext_csd.generic_cmd6_time);
if (err)
Re: [PATCH] mmc: sdhci: Clear MMC_CAP_1_8V_DDR in the SDHCI_QUIRK2_NO_1_8_V case
Hi Ulf,
On Thu, Jun 11, 2015 at 10:24 AM, Fabio Estevam
fabio.este...@freescale.com wrote:
- if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V)
+ if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) {
caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
SDHCI_SUPPORT_DDR50);
+ mmc-caps = ~MMC_CAP_1_8V_DDR;
+ }
Please discard this one. I think I found the problem inside sdhci-esdhc-imx.c.
Will send another patch later.
Thanks
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Re: [PATCH v2] mmc: meson: Add driver for the SD/MMC host found on Amlogic MesonX SoCs
On Wed, Jun 10, 2015 at 3:44 PM, Daniel Drake dr...@endlessm.com wrote:
On Wed, Jun 10, 2015 at 2:53 AM, Carlo Caione ca...@caione.org wrote:
+static int meson_mmc_map_dma(struct meson_mmc_host *host,
+struct mmc_data *data,
+unsigned int flags)
+{ u32 i, dma_len;
+ struct scatterlist *sg;
+
+ dma_len = dma_map_sg(mmc_dev(host-mmc), data-sg, data-sg_len,
+((data-flags MMC_DATA_READ) ?
+DMA_FROM_DEVICE : DMA_TO_DEVICE));
+ if (dma_len == 0) {
+ dev_err(mmc_dev(host-mmc), dma_map_sg failed\n);
+ return -ENOMEM;
+ }
+
+ for_each_sg(data-sg, sg, data-sg_len, i) {
+ if (sg-offset 3 || sg-length 3) {
+ dev_err(mmc_dev(host-mmc),
+ unaligned scatterlist: os %x length %d\n,
+ sg-offset, sg-length);
+ return -EINVAL;
+ }
+ }
If the offset/length check fails here, do you leak the DMA mapping?
If so, can you do the offset/length check first to avoid that?
Good idea. Fix in v3.
There should only ever be 1 entry in the scatterlist, right? In that
case you can do a simple check there, and then instead of looping,
just check the first entry in the scatterlist.
Right.
I'm going to wait a couple of days for more comments before submitting v3.
Thanks,
--
Carlo Caione | +39.340.80.30.096 | Endless
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[PATCH V2 2/3] i2c-piix4: Use Macro for AMD CZ SMBus device ID
Change AMD CZ SMBUS device ID from 0x790b to
use Macro definition
Signed-off-by: Wan ZongShun vincent@amd.com
---
drivers/i2c/busses/i2c-piix4.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
index 67cbec6..630bce6 100644
--- a/drivers/i2c/busses/i2c-piix4.c
+++ b/drivers/i2c/busses/i2c-piix4.c
@@ -245,7 +245,7 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
PIIX4_dev-device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS
PIIX4_dev-revision = 0x41) ||
(PIIX4_dev-vendor == PCI_VENDOR_ID_AMD
-PIIX4_dev-device == 0x790b
+PIIX4_dev-device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS
PIIX4_dev-revision = 0x49))
smb_en = 0x00;
else
@@ -545,7 +545,7 @@ static const struct pci_device_id piix4_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
- { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x790b) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
PCI_DEVICE_ID_SERVERWORKS_OSB4) },
{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
--
1.9.1
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[PATCH V2 1/3] pci_ids: Add AMD KERNCZ device ID support
The KERNCZ is new AMD SB/FCH generation name, like HUDSON2. We will adopt 0x790b as device ID since from this gereration. Signed-off-by: Wan ZongShun vincent@amd.com --- include/linux/pci_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 2f7b9a4..cb63a7b 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -579,6 +579,7 @@ #define PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE 0x7800 #define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS0x780b #define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c +#define PCI_DEVICE_ID_AMD_KERNCZ_SMBUS 0x790b #define PCI_VENDOR_ID_TRIDENT 0x1023 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX0x2000 -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] mmc: sdhci: Clear MMC_CAP_1_8V_DDR in the SDHCI_QUIRK2_NO_1_8_V case
From: Kevin Lemoi kevin.le...@savant.com
SDHCI_QUIRK2_NO_1_8_V flag should disable MMC_CAP_1_8V_DDR.
Otherwise we get the following errors when accessing eMMC on a mx6sl
board:
mmc0: MAN_BKOPS_EN bit is not set
mmc0: power class selection to bus width 8 ddr 4 failed
mmc0: error -110 whilst initialising MMC card
mmc0: MAN_BKOPS_EN bit is not set
mmc0: power class selection to bus width 8 ddr 4 failed
mmc0: error -110 whilst initialising MMC card
mmc0: MAN_BKOPS_EN bit is not set
mmc0: power class selection to bus width 8 ddr 4 failed
mmc0: error -110 whilst initialising MMC card
With this fix in place it is possible to successfully mount the rootfs
from the emmc on the mx6sl board with 'no-1-8-v' property passed in the
device tree.
Cc: sta...@vger.kernel.org
Signed-off-by: Kevin Lemoi kevin.le...@savant.com
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
drivers/mmc/host/sdhci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 706bb60..10304cc 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3140,9 +3140,11 @@ int sdhci_add_host(struct sdhci_host *host)
}
}
- if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V)
+ if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) {
caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
SDHCI_SUPPORT_DDR50);
+ mmc-caps = ~MMC_CAP_1_8V_DDR;
+ }
/* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
if (caps[1] (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
--
1.9.1
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[PATCH V2 3/3] SDHCI: Change AMD SDHCI quirk application scope
Change this quirk to apply to AMD Carrizo platform.
Signed-off-by: Wan ZongShun vincent@amd.com
Tested-by: Nath, Arindam arindam.n...@amd.com
Tested-by: Ramesh, Ramya ramya.ram...@amd.com
---
drivers/mmc/host/sdhci-pci.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index f208f20..94f54d2 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -724,14 +724,37 @@ static const struct sdhci_pci_fixes sdhci_rtsx = {
.probe_slot = rtsx_probe_slot,
};
+/*AMD chipset generation*/
+enum amd_chipset_gen {
+ AMD_CHIPSET_BEFORE_ML,
+ AMD_CHIPSET_CZ,
+ AMD_CHIPSET_NL,
+ AMD_CHIPSET_UNKNOWN,
+};
+
static int amd_probe(struct sdhci_pci_chip *chip)
{
struct pci_dev *smbus_dev;
+ enum amd_chipset_gen gen;
smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
+ if (smbus_dev) {
+ gen = AMD_CHIPSET_BEFORE_ML;
+ } else {
+ smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
+ if (smbus_dev) {
+ if (smbus_dev-revision 0x51)
+ gen = AMD_CHIPSET_CZ;
+ else
+ gen = AMD_CHIPSET_NL;
+ } else {
+ gen = AMD_CHIPSET_UNKNOWN;
+ }
+ }
- if (smbus_dev (smbus_dev-revision 0x51)) {
+ if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) {
chip-quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
chip-quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
}
--
1.9.1
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Re: [PATCH V2 2/3] i2c-piix4: Use Macro for AMD CZ SMBus device ID
On Thu, Jun 11, 2015 at 08:11:46PM +0800, Wan ZongShun wrote:
Change AMD CZ SMBUS device ID from 0x790b to
use Macro definition
Signed-off-by: Wan ZongShun vincent@amd.com
I think it makes sense that this patch goes in via MMC. This I2C change
is trivial, but for MMC there is more to handle. I don't expect
conflicts. So:
Acked-by: Wolfram Sang w...@the-dreams.de
---
drivers/i2c/busses/i2c-piix4.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
index 67cbec6..630bce6 100644
--- a/drivers/i2c/busses/i2c-piix4.c
+++ b/drivers/i2c/busses/i2c-piix4.c
@@ -245,7 +245,7 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
PIIX4_dev-device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS
PIIX4_dev-revision = 0x41) ||
(PIIX4_dev-vendor == PCI_VENDOR_ID_AMD
- PIIX4_dev-device == 0x790b
+ PIIX4_dev-device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS
PIIX4_dev-revision = 0x49))
smb_en = 0x00;
else
@@ -545,7 +545,7 @@ static const struct pci_device_id piix4_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
- { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x790b) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
PCI_DEVICE_ID_SERVERWORKS_OSB4) },
{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
--
1.9.1
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[PATCH] mmc: sdhci-esdhc-imx: Do not set MMC_CAP_1_8V_DDR in the 'no-1-8-v' case
From: Fabio Estevam fabio.este...@freescale.com
Since commit e2997c944dbdff3f (mmc: sdhci-esdhc-imx: add MMC_CAP_1_8V_DDR
for mx6) the driver sets the MMC_CAP_1_8V_DDR flag unconditionally on
mx6, but we should not do this when the 'no-1-8-v' property is passed via
device tree.
This causes the following errors when accessing eMMC on a mx6sl board:
mmc0: MAN_BKOPS_EN bit is not set
mmc0: power class selection to bus width 8 ddr 4 failed
mmc0: error -110 whilst initialising MMC card
So only set the MMC_CAP_1_8V_DDR flag when the 'no-1-8-v' property is
absent.
With this fix in place it is possible to successfully mount the rootfs
from the emmc on a mx6sl board which has 'no-1-8-v' property passed in the
device tree.
Fixes: e2997c944dbdff3f (mmc: sdhci-esdhc-imx: add MMC_CAP_1_8V_DDR for mx6)
Cc: sta...@vger.kernel.org
Reported-by: Kevin Lemoi kevin.le...@savant.com
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
drivers/mmc/host/sdhci-esdhc-imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index faf0cb9..b562faf 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -1005,7 +1005,6 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
if (esdhc_is_usdhc(imx_data)) {
writel(0x08100810, host-ioaddr + ESDHC_WTMK_LVL);
host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
- host-mmc-caps |= MMC_CAP_1_8V_DDR;
if (!(imx_data-socdata-flags ESDHC_FLAG_HS200))
host-quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
@@ -1094,6 +1093,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
/* sdr50 and sdr104 needs work on 1.8v signal voltage */
if ((boarddata-support_vsel) esdhc_is_usdhc(imx_data)
!IS_ERR(imx_data-pins_default)) {
+ host-mmc-caps |= MMC_CAP_1_8V_DDR;
imx_data-pins_100mhz = pinctrl_lookup_state(imx_data-pinctrl,
ESDHC_PINCTRL_STATE_100MHZ);
imx_data-pins_200mhz = pinctrl_lookup_state(imx_data-pinctrl,
--
1.9.1
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[PATCH] mmc: host: Fix mmc_alloc_host() error path
From: Fabio Estevam fabio.este...@freescale.com
If mmc_gpio_alloc() fails we miss to call 'kfree(host)', so rearrange
the error path to fix it.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
drivers/mmc/core/host.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 99a9c90..01fa1ed 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -566,10 +566,8 @@ struct mmc_host *mmc_alloc_host(int extra, struct device
*dev)
host-index = err;
spin_unlock(mmc_host_lock);
idr_preload_end();
- if (err 0) {
- kfree(host);
- return NULL;
- }
+ if (err 0)
+ goto err_kfree;
dev_set_name(host-class_dev, mmc%d, host-index);
@@ -578,10 +576,8 @@ struct mmc_host *mmc_alloc_host(int extra, struct device
*dev)
host-class_dev.class = mmc_host_class;
device_initialize(host-class_dev);
- if (mmc_gpio_alloc(host)) {
- put_device(host-class_dev);
- return NULL;
- }
+ if (mmc_gpio_alloc(host))
+ goto err_put_device;
mmc_host_clk_init(host);
@@ -605,6 +601,12 @@ struct mmc_host *mmc_alloc_host(int extra, struct device
*dev)
host-max_blk_count = PAGE_CACHE_SIZE / 512;
return host;
+
+err_put_device:
+ put_device(host-class_dev);
+err_kfree:
+ kfree(host);
+ return NULL;
}
EXPORT_SYMBOL(mmc_alloc_host);
--
1.9.1
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Re: [PATCH] mmc: sdhci-esdhc-imx: Do not set MMC_CAP_1_8V_DDR in the 'no-1-8-v' case
Hi Fabio,
On Thu, Jun 11, 2015 at 07:08:23PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Since commit e2997c944dbdff3f (mmc: sdhci-esdhc-imx: add MMC_CAP_1_8V_DDR
for mx6) the driver sets the MMC_CAP_1_8V_DDR flag unconditionally on
mx6, but we should not do this when the 'no-1-8-v' property is passed via
device tree.
This causes the following errors when accessing eMMC on a mx6sl board:
mmc0: MAN_BKOPS_EN bit is not set
mmc0: power class selection to bus width 8 ddr 4 failed
mmc0: error -110 whilst initialising MMC card
So only set the MMC_CAP_1_8V_DDR flag when the 'no-1-8-v' property is
absent.
With this fix in place it is possible to successfully mount the rootfs
from the emmc on a mx6sl board which has 'no-1-8-v' property passed in the
device tree.
Fixes: e2997c944dbdff3f (mmc: sdhci-esdhc-imx: add MMC_CAP_1_8V_DDR for mx6)
Cc: sta...@vger.kernel.org
Reported-by: Kevin Lemoi kevin.le...@savant.com
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
I think this patch will break the eMMC DDR 3.3v mode support.
Looking at EXT_CSD_CARD_TYPE_DDR_1_8V definition,
#define EXT_CSD_CARD_TYPE_DDR_1_8V (12) /* Card can run at 52MHz */
/* DDR mode @1.8V or 3V I/O */
it means the card can run at DDR mode on either 3V or 1.8V IO.
This patch disable the DDR capability unconditionally if no 1.8v IO support.
But there's indeed some confusion in mmc core that comments of MMC_CAP_1_8V_DDR
only indicates 1.8V DDR mode support which probably could be improved.
#define MMC_CAP_1_8V_DDR(1 11) /* can support */
/* DDR mode at 1.8V */
I guess why you issue passed with this change is because the DDR
mode is disabled.
Probably you need figure out why 3.3V DDR mode can't work for the board
in the issue, usually it's caused by timing, io pad setting and etc.
Regards
Dong Aisheng
---
drivers/mmc/host/sdhci-esdhc-imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index faf0cb9..b562faf 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -1005,7 +1005,6 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
if (esdhc_is_usdhc(imx_data)) {
writel(0x08100810, host-ioaddr + ESDHC_WTMK_LVL);
host-quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
- host-mmc-caps |= MMC_CAP_1_8V_DDR;
if (!(imx_data-socdata-flags ESDHC_FLAG_HS200))
host-quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
@@ -1094,6 +1093,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
/* sdr50 and sdr104 needs work on 1.8v signal voltage */
if ((boarddata-support_vsel) esdhc_is_usdhc(imx_data)
!IS_ERR(imx_data-pins_default)) {
+ host-mmc-caps |= MMC_CAP_1_8V_DDR;
imx_data-pins_100mhz = pinctrl_lookup_state(imx_data-pinctrl,
ESDHC_PINCTRL_STATE_100MHZ);
imx_data-pins_200mhz = pinctrl_lookup_state(imx_data-pinctrl,
--
1.9.1
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[GIT PULL] Update dw-mmc controller
Dear, Ulf. Could you pull this patch for mmc-next? Best Regards, Jaehoon Chung The following changes since commit 5fd26c7ecb32082745b0bd33c8e35badd1cb5a91: mmc: sdhci: Restore behavior while creating OCR mask (2015-06-08 09:49:57 +0200) are available in the git repository at: https://github.com/jh80chung/dw-mmc.git tags/dw_mmc-next-for-ulf for you to fetch changes up to d15283723e066512f7d4d18c78cf68d15a400b29: mmc: dw_mmc: insmod followed by rmmod will hung for eMMC (2015-06-12 01:42:02 +0900) Prabu Thangamuthu (1): mmc: dw_mmc: insmod followed by rmmod will hung for eMMC drivers/mmc/host/dw_mmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
