RE: [PATCH 0/2] Add clock post-rate-change notifier
Hi Paul, -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Paul Walmsley Sent: Saturday, June 21, 2008 4:44 AM To: linux-omap@vger.kernel.org Subject: [PATCH 0/2] Add clock post-rate-change notifier This series adds a clock rate change notifier to the OMAP clock framework. Currently only post-rate-change notification is implemented, although pre-rate-change notification is in the works. Was there any patch set posted after this with pre-rate change notifications support? I am currently working on CPUFreq patches and CPUFreq requires a pre notification to be able to update jiffies/BogoMips. regards, Rajendra -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Set correct off mode polarity
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6bb25cf..b0bc1b9 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -46,6 +46,8 @@
#define MAX_DPLL_WAIT_TRIES100
+#define OFFMODE_POL(13)
+
struct vdd_prcm_config *curr_vdd1_prcm_set;
struct vdd_prcm_config *curr_vdd2_prcm_set;
static struct clk *dpll1_clk, *dpll2_clk, *dpll3_clk;
@@ -684,6 +686,9 @@ int __init omap2_clk_init(void)
}
#endif
+ prm_clear_mod_reg_bits(OFFMODE_POL, OMAP3430_GR_MOD,
+ OMAP3_PRM_POLCTRL_OFFSET);
+
printk(KERN_INFO Clocking rate (Crystal/DPLL/ARM core):
%ld.%01ld/%ld/%ld MHz\n,
(osc_sys_ck.rate / 100), (osc_sys_ck.rate / 10) % 10,
@@ -797,7 +802,6 @@ static int omap3_select_table_rate(struct clk *clk,
unsigned long rate)
return -EINVAL;
}
-
if (clk == virt_vdd1_prcm_set) {
curr_mpu_speed = curr_vdd1_prcm_set-speed;
clk_set_rate(dpll1_clk, prcm_vdd-speed);
--
1.5.3.4
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[PATCH] Load triton2 scripts.
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
drivers/i2c/chips/Makefile|2 +-
drivers/i2c/chips/twl4030-power.c | 337 +
2 files changed, 338 insertions(+), 1 deletions(-)
create mode 100644 drivers/i2c/chips/twl4030-power.c
diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
index 1f81ebd..a44e617 100644
--- a/drivers/i2c/chips/Makefile
+++ b/drivers/i2c/chips/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_GPIOEXPANDER_OMAP) += gpio_expander_omap.o
obj-$(CONFIG_MENELAUS) += menelaus.o
obj-$(CONFIG_SENSORS_TSL2550) += tsl2550.o
obj-$(CONFIG_SENSORS_TSL2563) += tsl2563.o
-obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-pwrirq.o
+obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-pwrirq.o
twl4030-power.o
obj-$(CONFIG_TWL4030_GPIO) += twl4030-gpio.o
obj-$(CONFIG_TWL4030_USB) += twl4030-usb.o
obj-$(CONFIG_TWL4030_POWEROFF) += twl4030-poweroff.o
diff --git a/drivers/i2c/chips/twl4030-power.c
b/drivers/i2c/chips/twl4030-power.c
new file mode 100644
index 000..195c3c4
--- /dev/null
+++ b/drivers/i2c/chips/twl4030-power.c
@@ -0,0 +1,337 @@
+/*
+ * linux/drivers/i2c/chips/twl4030-power.c
+ *
+ * Handle TWL4030 Power initialization
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2006 Texas Instruments, Inc
+ *
+ * Written by Kalle Jokiniemi
+ * Peter De Schrijver [EMAIL PROTECTED]
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include linux/module.h
+#include linux/pm.h
+#include linux/i2c/twl4030.h
+
+#define PWR_P1_SW_EVENTS 0x10
+#define PWR_DEVOFF (10)
+
+#define PHY_TO_OFF_PM_MASTER(p)(p - 0x36)
+#define PHY_TO_OFF_PM_RECIEVER(p) (p - 0x5b)
+
+/* resource - hfclk */
+#define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECIEVER(0xe6)
+
+/* PM events */
+#define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
+#define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
+#define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
+#define R_CFG_P1_TRANSITIONPHY_TO_OFF_PM_MASTER(0x36)
+#define R_CFG_P2_TRANSITIONPHY_TO_OFF_PM_MASTER(0x37)
+#define R_CFG_P3_TRANSITIONPHY_TO_OFF_PM_MASTER(0x38)
+
+#define LVL_WAKEUP 0x08
+
+#define ENABLE_WARMRESET (14)
+
+/* sequence script */
+
+#define END_OF_SCRIPT 0x3f
+
+#define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
+#define R_SEQ_ADD_SA12 PHY_TO_OFF_PM_MASTER(0x56)
+#defineR_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
+#defineR_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
+#define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
+#define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
+
+/* Power bus message definitions */
+
+#define DEV_GRP_NULL 0x0
+#define DEV_GRP_P1 0x1
+#define DEV_GRP_P2 0x2
+#define DEV_GRP_P3 0x4
+
+#define RES_GRP_RES0x0
+#define RES_GRP_PP 0x1
+#define RES_GRP_RC 0x2
+#define RES_GRP_PP_RC 0x3
+#define RES_GRP_PR 0x4
+#define RES_GRP_PP_PR 0x5
+#define RES_GRP_RC_PR 0x6
+#define RES_GRP_ALL0x7
+
+#define RES_TYPE2_R0 0x0
+
+#define RES_TYPE_ALL 0x7
+
+#define RES_STATE_WRST 0xF
+#define RES_STATE_ACTIVE 0xE
+#define RES_STATE_SLEEP0x8
+#define RES_STATE_OFF 0x0
+
+/*
+* Power Bus Message Format
+*
+* Broadcast Message (16 Bits)
+* DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
+* RES_STATE[3:0]
+*
+* Singular Message (16 Bits)
+* DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
+*
+*/
+
+#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
+ (devgrp 13 | 1 12 | grp 9 | type2 7 | type 4 | state)
+
+#define MSG_SINGULAR(devgrp, id, state) \
+ (devgrp 13 | 0 12 | id 4 | state)
+
+#define R_PROTECT_KEY 0x0E
+#define KEY_1 0xC0
+#define KEY_2 0x0C
+
+struct triton_ins {
+ u16 pmb_message;
+ u8 delay;
+};
+
+
+#define CONFIG_DISABLE_HFCLK 1
+
+#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
+
+struct triton_ins sleep_on_seq[] __initdata = {
+ {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
+ {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
[PATCH] Add SYSOFFMODE option.
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED] --- arch/arm/plat-omap/Kconfig |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index d7b34ff..6f891b7 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -73,6 +73,12 @@ config OMAP_SMARTREFLEX compensation for VDD1 and VDD2, user must write 1 to /sys/power/sr_vddX_autocomp, where X is 1 or 2. +config OMAP_SYSOFFMODE +bool OFF mode support + depends on ARCH_OMAP34XX + help + Say Y if you want to allow OMAP to enter OFF mode. + config OMAP_SMARTREFLEX_TESTING bool Smartreflex testing support depends on OMAP_SMARTREFLEX -- 1.5.3.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Set correct off mode polarity
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6bb25cf..b0bc1b9 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -46,6 +46,8 @@
#define MAX_DPLL_WAIT_TRIES100
+#define OFFMODE_POL(13)
+
struct vdd_prcm_config *curr_vdd1_prcm_set;
struct vdd_prcm_config *curr_vdd2_prcm_set;
static struct clk *dpll1_clk, *dpll2_clk, *dpll3_clk;
@@ -684,6 +686,9 @@ int __init omap2_clk_init(void)
}
#endif
+ prm_clear_mod_reg_bits(OFFMODE_POL, OMAP3430_GR_MOD,
+ OMAP3_PRM_POLCTRL_OFFSET);
+
printk(KERN_INFO Clocking rate (Crystal/DPLL/ARM core):
%ld.%01ld/%ld/%ld MHz\n,
(osc_sys_ck.rate / 100), (osc_sys_ck.rate / 10) % 10,
@@ -797,7 +802,6 @@ static int omap3_select_table_rate(struct clk *clk,
unsigned long rate)
return -EINVAL;
}
-
if (clk == virt_vdd1_prcm_set) {
curr_mpu_speed = curr_vdd1_prcm_set-speed;
clk_set_rate(dpll1_clk, prcm_vdd-speed);
--
1.5.3.4
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RFC: OMAP3 SYS_OFF_MODE support
The following patch set introduces support for the OMAP3 SYS_OFF_MODE signal. This will cause a properly programmed triton2 to shutdown the VDD1 and VDD2 regulators when both core and MPU powerdomain are in off state. The patches includes programming triton2 with the appropriate scripts for the SDP3430 board. By default the OMAP3 polarity of the SYS_OFF_MODE signal is inverted compared to what triton2 expects. This means the polarity needs to be changed before the triton2 scripts are activated, otherwise the system will crash. At the moment this is done in omap2_clk_init as this function is called before triton2 is initialized. Better suggestions are welcome. Thanks to Kalle Jokiniemi for doing the initial patch and test work. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] Set correct off mode polarity
Hi, style comments inlined. On Mon, Jul 21, 2008 at 07:02:02PM +0300, Peter 'p2' De Schrijver wrote: +#define OFFMODE_POL (13) add spaces after 1 and before 3 (1 3) - unnecessary change ?!? -- balbi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] Load triton2 scripts.
On Mon, Jul 21, 2008 at 07:02:05PM +0300, Peter 'p2' De Schrijver wrote:
+/*
+*Power Bus Message Format
+*
+*Broadcast Message (16 Bits)
+*DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
+*RES_STATE[3:0]
+*
+*Singular Message (16 Bits)
+*DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
+*
+*/
This comment should follow the coding style:
/*
* Power Bus Message Format
*
* Broadcast Message (16 Bits)
* DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
* RES_STATE[3:0]
*
* Singular Message (16 Bits)
* DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
*/
+struct triton_ins {
+ u16 pmb_message;
+ u8 delay;
+};
+
+
extra line
+#define CONFIG_DISABLE_HFCLK 1
+
+#if defined(CONFIG_MACH_OMAP_3430SDP) ||
defined(CONFIG_MACH_OMAP_3430LABRADOR)
+
+struct triton_ins sleep_on_seq[] __initdata = {
+ {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
could you add spaces here??
{ MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4 },
--
balbi
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Re: [PATCH 0/0] Power domain and clock domain patches for omap
On Wed, Jul 16, 2008 at 06:19:05PM +0300, Tony Lindgren wrote: I'm reposting the series to a wider audience as Russell King suspected that other archs may be interested in reviewing these too, or at least some parts of the code. It would be nice to have some comment on these patches from other people. My suspicions is that this infrastructure is solving a problem found on other SoCs in addition to OMAP, and, if this is useful to other people, it should become cross-SoC infrastructure. Since I don't know the answer to whether it would be useful, I'm trying to ensure that these patches have sufficient exposure to people who _may_ know the answer. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/9] TWL4030: read and write module ISRs to clear them at init
Hello Peter, On Fri, 18 Jul 2008, Peter 'p2' De Schrijver wrote: On Thu, Jul 17, 2008 at 07:34:52PM -0600, ext Paul Walmsley wrote: TWL4030 interrupt status register bits can be cleared in one of two ways: either by reading from the register, or by writing a 1 to the appropriate bit(s) in the register. This behavior can be altered at any time by the twlmodule_SIH_CTRL.COR register bit (clear-on-read). twl4030-core.c does not touch these *_SIH_CTRL registers during boot, and the TWL4030 TRM is deeply confused as to whether COR=1 means that the registers are cleared on reads, or cleared on writes. That's true. But reality is fortunately not so confused :) COR=1 means all IRQs are acknowledged when reading the corresponding ISR. COR=0 means you need to write 1 to the bits in the ISR for interrupts you want to acknowledge. Hope this helps, thanks very much, it does help. Ought to save a little time on boot. Will post an updated set tomorrow... - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] TWL4030: convert old-style function documentation to current kerneldoc
On Fri, 18 Jul 2008, Felipe Balbi wrote: On Thu, 17 Jul 2008 20:15:51 -0600, Paul Walmsley [EMAIL PROTECTED] wrote: + * Results the result of operation - 0 is success I suppose you mean Returns here. thanks Felipe, fixed. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
