Re: [PATCH 3/4] HSMMC: Add support for the second controller
On Thursday 06 November 2008, Grazvydas Ignotas wrote: > I have another SD slot connected to MMC2 via transceiver (in addition > to usual MMC1). I wonder how can I add support for that? The easiest > way is to add remaining twl_mmc2_* functions mmc-twl4030.c, I plan a followon to the patch I just sent, which will let the GPIOs hook up more generically and remove the need for most such non-generic functions. > and it > works, but this stuff would be useless for all other boards, and I > know you hate #ifdefs here. It would help if you explained what needed #ifdeffing, so we don't need to guess. I didn't see schematics in any easily found location on openpandora.org (that's your board?). Do VMMC1 and GPIO-0/CD hook up to MMC1? Do VMMC2 and GPIO-1/CD hook up to MMC2? > Another way is to just copy mmc-twl4030.c > and add stuff there, but that would result in lots of code > duplication. BTW, we also have wifi chip on MMC3. > Any ideas? For MMC3 you'll need to write some stuff to hook to that controller ... currently only MMC1 and MMC2 are set up. - Dave -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[patch 2.6.28-rc3-omap git] hsmmc gpio updates
From: David Brownell <[EMAIL PROTECTED]>
Rework card detect GPIO handling in the twl4030 MMC glue: drive
it *only* from the hsmmc_info passed; remove most of remaining
"we know we're always a twl4030 GPIO" logic.
Add write-protect switch detection support to that glue. Stub
in a not-present WP GPIO into most boards. (Beagle's is real.)
Teach the hsmmc driver how to use the card detect and writeprotect
methods, and move some data structure init earlier so that when IRQs
come in, more of the data used by their handlers is initialized.
Verified on Beagle (WP, card detect events) and Overo (boots, both
card and wlan are seen). Beagle behaves fully, and is the model
to follow for the common case where the TWL4030 gpio-0 card detect
magic is used.
Most hsmmc boards need to list what GPIOs they use with MMC...
Note that supporting card detect and writeprotect GPIOs on a
second MMC slot, or using the MMC3 controller, requires some
interface updates that aren't part of this patch.
Signed-off-by: David Brownell <[EMAIL PROTECTED]>
---
arch/arm/mach-omap2/board-2430sdp.c |1
arch/arm/mach-omap2/board-3430sdp.c |2
arch/arm/mach-omap2/board-ldp.c |1
arch/arm/mach-omap2/board-omap2evm.c |1
arch/arm/mach-omap2/board-omap3beagle.c | 26 ++---
arch/arm/mach-omap2/board-omap3evm.c |1
arch/arm/mach-omap2/board-omap3pandora.c |1
arch/arm/mach-omap2/board-overo.c|2
arch/arm/mach-omap2/mmc-twl4030.c| 133 ++---
arch/arm/mach-omap2/mmc-twl4030.h|1
drivers/mmc/host/omap_hsmmc.c| 51 ---
11 files changed, 127 insertions(+), 93 deletions(-)
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -395,6 +395,7 @@ static struct twl4030_hsmmc_info mmc[] _
.mmc= 1,
.wires = 4,
.gpio_cd= -EINVAL,
+ .gpio_wp= -EINVAL,
},
{} /* Terminator */
};
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -450,11 +450,13 @@ static struct twl4030_hsmmc_info mmc[] _
.mmc= 1,
.wires = 8,
.gpio_cd= -EINVAL,
+ .gpio_wp= -EINVAL,
},
{
.mmc= 2,
.wires = 8,
.gpio_cd= -EINVAL,
+ .gpio_wp= -EINVAL,
},
{} /* Terminator */
};
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -346,6 +346,7 @@ static struct twl4030_hsmmc_info mmc[] _
.mmc= 1,
.wires = 4,
.gpio_cd= -EINVAL,
+ .gpio_wp= -EINVAL,
},
{} /* Terminator */
};
--- a/arch/arm/mach-omap2/board-omap2evm.c
+++ b/arch/arm/mach-omap2/board-omap2evm.c
@@ -345,6 +345,7 @@ static struct twl4030_hsmmc_info mmc[] _
.mmc= 1,
.wires = 4,
.gpio_cd= -EINVAL,
+ .gpio_wp= -EINVAL,
},
{} /* Terminator */
};
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -116,6 +116,15 @@ static struct twl4030_usb_data beagle_us
.usb_mode = T2_USB_MODE_ULPI,
};
+static struct twl4030_hsmmc_info mmc[] __initdata = {
+ {
+ .mmc= 1,
+ .wires = 8,
+ .gpio_wp= 29,
+ },
+ {} /* Terminator */
+};
+
static struct gpio_led gpio_leds[];
#include
@@ -135,6 +144,9 @@ static int beagle_twl_gpio_setup(struct
int status;
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
+ omap_cfg_reg(AH8_34XX_GPIO29);
+ mmc[0].gpio_cd = gpio + 0;
+ hsmmc_init(mmc);
/* REVISIT: need ehci-omap hooks for external VBUS
* power switch and overcurrent detect
@@ -319,15 +331,6 @@ static void __init omap3beagle_flash_ini
}
}
-static struct twl4030_hsmmc_info mmc[] __initdata = {
- {
- .mmc= 1,
- .wires = 8,
- .gpio_cd= TWL4030_GPIO_IRQ_NO(0),
- },
- {} /* Terminator */
-};
-
static void __init omap3_beagle_init(void)
{
omap3_beagle_i2c_init();
@@ -344,11 +347,6 @@ static void __init omap3_beagle_init(voi
#endif
omap_serial_init();
- omap_cfg_reg(AH8_34XX_GPIO29);
- gpio_request(29, "mmc0_wp");
- gpio_direction_input(29);
- hsmmc_init(mmc);
-
omap_cfg_reg(J25_34XX_GPIO170);
gpio_request(170, "DVI_nPD");
/* REVISIT leave DVI powered down until it's needed ... */
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -240,6 +24
3430SDP crash at boot time
Hi all,
Today when I attempted to boot on an 3430SDP with latest commit, I got a kernel
dump, which is this:
<7>eth0: No PHY found
<6>i2c /dev entries driver
i2c /dev entries driver
<4>Driver 'sd' needs updating - please use bus_type methods
Driver 'sd' needs updating - please use bus_type methods
<1>Unhandled fault: external abort on non-linefetch (0x1028) at 0xc920
Unhandled fault: external abort on non-linefetch (0x1028) at 0xc920
Internal error: : 1028 [#1]
Internal error: : 1028 [#1]
Modules linked in:Modules linked in:
CPU: 0Not tainted (2.6.28-rc3-omap1-05164-g0d272a9 #1)
CPU: 0Not tainted (2.6.28-rc3-omap1-05164-g0d272a9 #1)
PC is at cfi_qry_present+0x1c0/0x29c
PC is at cfi_qry_present+0x1c0/0x29c
LR is at cfi_qry_present+0x64/0x29c
LR is at cfi_qry_present+0x64/0x29c
pc : []lr : []psr: 6013
sp : c7817c38 ip : 0006 fp : c7817c74
pc : []lr : []psr: 6013
sp : c7817c38 ip : 0006 fp : c7817c74
r10: 0001 r9 : 0001 r8 :
r10: 0001 r9 : 0001 r8 :
r7 : 0002 r6 : c79e9968 r5 : 0002 r4 : 0001
r7 : 0002 r6 : c79e9968 r5 : 0002 r4 : 0001
r3 : c900 r2 : 0020 r1 : 0002 r0 : 5959
r3 : c900 r2 : 0020 r1 : 0002 r0 : 5959
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c5387f Table: 80004018 DAC: 0017
Control: 10c5387f Table: 80004018 DAC: 0017
Process swapper (pid: 1, stack limit = 0xc78162e0)
Process swapper (pid: 1, stack limit = 0xc78162e0)
Stack: (0xc7817c38 to 0xc7818000)
Stack: (0xc7817c38 to 0xc7818000)
7c20: 7c20:
5151 5151 5252 5252
7c40: 7c40: 5959 5959 c7817c50 c7817c50 0025 0025
0001 0001 c79e9968 c79e9968 0002 0002 0002 0002
7c60: 7c60: c7817ce8 c7817ce8 c7817ca4 c7817ca4 c7817c78
c7817c78 c01d1a60 c01d1a60 c01d1608 c01d1608 00ff 00ff
7c80: 7c80: c79e9968 c79e9968 0001 0001 c7817ce8 c7817ce8 c037d5a8
c037d5a8 c79e9968 c79e9968 c7817cdc c7817cdc c7817ca8 c7817ca8
7ca0: 7ca0: c01d0dbc c01d0dbc c01d18a4 c01d18a4 0006 0006 0004
0004 0007 0007 0001 0001 0002 0002 0001 0001
7cc0: 7cc0: c0395f24 c0395f24 c037d5a8 c037d5a8 c79e9968
c79e9968 c7817d4c c7817d4c c7817ce0 c7817ce0 c01d76ec c01d76ec c01d0d60 c01d0d60
7ce0: 7ce0: 2013 2013
0002 0002 0001 0001
7d00: 7d00:
7d20: 7d20: c7817d50 c7817d50 c0395f0c c0395f0c c0323cd9 c0323cd9 c79e9968
c79e9968 c037d188 c037d188 c037d5a8 c037d5a8 c037d1a8 c037d1a8
7d40: 7d40: c7817d5c c7817d5c c7817d50 c7817d50 c01d0d4c c01d0d4c c01d7684
c01d7684 c7817d7c c7817d7c c7817d60 c7817d60 c01d0d18 c01d0d18 c01d0d44 c01d0d44
7d60: 7d60: c79e9960 c79e9960 0400 0400 0400 0400 c037d188
c037d188 c7817da4 c7817da4 c7817d80 c7817d80 c001ceac c001ceac c01d0cd4 c01d0cd4
7d80: 7d80: c037d1b0 c037d1b0 c037d25c c037d25c c039600c c039600c c039600c
c039600c c0395050 c0395050 c001cdbc c001cdbc c7817db4 c7817db4 c7817da8 c7817da8
7da0: 7da0: c01af750 c01af750 c001cdec c001cdec c7817dd4 c7817dd4 c7817db8
c7817db8 c01ae970 c01ae970 c01af73c c01af73c c037d1b0 c037d1b0 c037d25c c037d25c
7dc0: 7dc0: c039600c c039600c c039600c c039600c c7817df4 c7817df4 c7817dd8
c7817dd8 c01aea84 c01aea84 c01ae8ac c01ae8ac c7817df8 c7817df8
7de0: 7de0: c01aea1c c01aea1c c039600c c039600c c7817e1c c7817e1c c7817df8
c7817df8 c01adeec c01adeec c01aea28 c01aea28 c78034d8 c78034d8 c037d1f8 c037d1f8
7e00: 7e00: c039600c c039600c c78c6ea0
c78c6ea0 c7817e2c c7817e2c c7817e20 c7817e20 c01ae7b8 c01ae7b8 c01adeac c01adeac
7e20: 7e20: c7817e5c c7817e5c c7817e30 c7817e30 c01ae374 c01ae374 c01ae7a4
c01ae7a4 c0323cb6 c0323cb6 c039600c c039600c c03a0400 c03a0400
7e40: 7e40: c039600c c039600c
c7817e84 c7817e84 c7817e60 c7817e60 c01aec78 c01aec78 c01ae2d8 c01ae2d8
7e60: 7e60: c03a0400 c03a0400 c0395fec c0395fec
c001cdbc c001cdbc c7817e94 c7817e94 c7817e88 c7817e88
7e80: 7e80: c01afae8 c01afae8 c01aebec c01aebec c7817eac c7817eac c7817e98
c7817e98 c01afb1c c01afb1c c01afa7c c01afa7c c03a0400 c03a0400 c0024a40 c0024a40
7ea0: 7ea0: c7817ebc c7817ebc c7817eb0 c7817eb0 c001cdd4 c001cdd4 c01afb10
c01afb10 c7817fdc
Re: [PATCH 3/4] HSMMC: Add support for the second controller
On Thursday 06 November 2008, Tony Lindgren wrote: > > > I'll have a look at write protect ... it wouldn't normally > > be an IRQ, just an input GPIO. Unlike the CD, which gets > > used for both purposes; that code looks iffy too. > > OK. We also need to figure out what to do if we need to support other > gpios than twl gpios. Mostly addressed in the patch you'll see. The remaining bit is better handling of debouncing. - Dave -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/4] HSMMC: Add support for the second controller
I have another SD slot connected to MMC2 via transceiver (in addition to usual MMC1). I wonder how can I add support for that? The easiest way is to add remaining twl_mmc2_* functions mmc-twl4030.c, and it works, but this stuff would be useless for all other boards, and I know you hate #ifdefs here. Another way is to just copy mmc-twl4030.c and add stuff there, but that would result in lots of code duplication. BTW, we also have wifi chip on MMC3. Any ideas? Gražvydas -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] Enable touchscreen in pandora's defconfig
This patch enables McSPI and ADS7846 driver in Pandora's defconfig. Signed-off-by: Grazvydas Ignotas <[EMAIL PROTECTED]> --- arch/arm/configs/omap3_pandora_defconfig | 227 -- 1 files changed, 151 insertions(+), 76 deletions(-) diff --git a/arch/arm/configs/omap3_pandora_defconfig b/arch/arm/configs/omap3_pandora_defconfig index ffed27d..1c2b7a2 100644 --- a/arch/arm/configs/omap3_pandora_defconfig +++ b/arch/arm/configs/omap3_pandora_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.27-omap1 -# Sat Oct 18 14:12:19 2008 +# Linux kernel version: 2.6.28-rc3-omap1 +# Wed Nov 5 22:02:43 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -22,8 +22,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_SUPPORTS_AOUT=y -CONFIG_ZONE_DMA=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0x CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -80,6 +78,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set @@ -88,15 +87,9 @@ CONFIG_SLAB=y # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -129,6 +122,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # System Type @@ -169,7 +163,7 @@ CONFIG_CLASSIC_RCU=y # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_DAVINCI is not set CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_MSM7X00A is not set +# CONFIG_ARCH_MSM is not set # # TI OMAP Implementations @@ -265,26 +259,30 @@ CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC000 # CONFIG_PREEMPT is not set CONFIG_HZ=128 CONFIG_AEABI=y CONFIG_OABI_COMPAT=y CONFIG_ARCH_FLATMEM_HAS_HOLES=y -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y # CONFIG_LEDS is not set CONFIG_ALIGNMENT_TRAP=y @@ -298,9 +296,10 @@ CONFIG_CMDLINE=" debug " # CONFIG_KEXEC is not set # -# CPU Frequency scaling +# CPU Power Management # # CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set # # Floating point emulation @@ -320,6 +319,8 @@ CONFIG_NEON=y # Userspace binary formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_MISC=y @@ -381,6 +382,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -401,14 +403,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -477,6 +473,8 @@ CONFIG_MTD_CFI_I2=y # # Self-contained MTD device drivers # +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -492,6 +490,7 @@ CONFIG_MTD_NAND=y # CONFIG_MTD_NAND_VERIFY_WRITE is not set # CONFIG_MTD_NAND_ECC_SMC is not set # CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set CONFIG_MTD_NAND_OMAP2=y CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_DISKONCHIP is not set @@ -637,7 +636,22 @@ CONFIG_INPUT_MOUSE=y # CONFIG_MOUSE_GPIO is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set +CONFI
[PATCH 2/3] Minor checkpatch cleanup
Clean a line over 80 characters.
Signed-off-by: Grazvydas Ignotas <[EMAIL PROTECTED]>
---
arch/arm/mach-omap2/board-omap3pandora.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c
b/arch/arm/mach-omap2/board-omap3pandora.c
index b10bf00..c2c4930 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -269,7 +269,8 @@ static struct twl4030_hsmmc_info mmc[] __initdata = {
static void __init omap3pandora_init(void)
{
omap3pandora_i2c_init();
- platform_add_devices(omap3pandora_devices,
ARRAY_SIZE(omap3pandora_devices));
+ platform_add_devices(omap3pandora_devices,
+ ARRAY_SIZE(omap3pandora_devices));
omap_board_config = omap3pandora_config;
omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
omap_serial_init();
--
1.5.4.3
--
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the body of a message to [EMAIL PROTECTED]
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[PATCH 1/3] Add touchscreen support for Pandora
This patch adds ADS7846 compatible touchscreen support for
OMAP3 Pandora.
Signed-off-by: Grazvydas Ignotas <[EMAIL PROTECTED]>
---
arch/arm/mach-omap2/board-omap3pandora.c | 57 ++
1 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c
b/arch/arm/mach-omap2/board-omap3pandora.c
index 9fd3499..b10bf00 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -25,6 +25,8 @@
#include
#include
+#include
+#include
#include
#include
@@ -45,6 +47,7 @@
#include
#include
#include
+#include
#include "sdram-micron-mt46h32m32lf-6.h"
#include "mmc-twl4030.h"
@@ -54,6 +57,8 @@
#define GPMC_CS0_BASE 0x60
#define GPMC_CS_SIZE 0x30
+#define OMAP3_PANDORA_TS_GPIO 94
+
static struct mtd_partition omap3pandora_nand_partitions[] = {
{
.name = "xloader",
@@ -185,6 +190,55 @@ static void __init omap3pandora_init_irq(void)
omap_gpio_init();
}
+static void __init omap3pandora_ads7846_init(void)
+{
+ int gpio = OMAP3_PANDORA_TS_GPIO;
+ int ret;
+
+ ret = gpio_request(gpio, "ads7846_pen_down");
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to request GPIO %d for "
+ "ads7846 pen down IRQ\n", gpio);
+ return;
+ }
+
+ gpio_direction_input(gpio);
+}
+
+static int ads7846_get_pendown_state(void)
+{
+ return !gpio_get_value(OMAP3_PANDORA_TS_GPIO);
+}
+
+static struct ads7846_platform_data ads7846_config = {
+ .x_max = 0x0fff,
+ .y_max = 0x0fff,
+ .x_plate_ohms = 180,
+ .pressure_max = 255,
+ .debounce_max = 10,
+ .debounce_tol = 3,
+ .debounce_rep = 1,
+ .get_pendown_state = ads7846_get_pendown_state,
+ .keep_vref_on = 1,
+};
+
+static struct omap2_mcspi_device_config ads7846_mcspi_config = {
+ .turbo_mode = 0,
+ .single_channel = 1, /* 0: slave, 1: master */
+};
+
+static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
+ {
+ .modalias = "ads7846",
+ .bus_num= 1,
+ .chip_select= 0,
+ .max_speed_hz = 150,
+ .controller_data= &ads7846_mcspi_config,
+ .irq= OMAP_GPIO_IRQ(OMAP3_PANDORA_TS_GPIO),
+ .platform_data = &ads7846_config,
+ }
+};
+
static struct platform_device omap3pandora_lcd_device = {
.name = "pandora_lcd",
.id = -1,
@@ -219,10 +273,13 @@ static void __init omap3pandora_init(void)
omap_board_config = omap3pandora_config;
omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
omap_serial_init();
+ spi_register_board_info(omap3pandora_spi_board_info,
+ ARRAY_SIZE(omap3pandora_spi_board_info));
hsmmc_init(mmc);
usb_musb_init();
usb_ehci_init();
omap3pandora_flash_init();
+ omap3pandora_ads7846_init();
}
static void __init omap3pandora_map_io(void)
--
1.5.4.3
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Re: [PATCH - Omapzoom][NAND] Add prefetch and DMA support
Hi,
Do you have any plans to use the prefetch engine's feature to
synchronise to ready/busy pin? (GPMC_PREFETCH_CONFIG1's SYNCHROMODE=1)
That way we could avoid the busy-wait for the flash to be ready.
- Juha
On Thu, Nov 6, 2008 at 5:57 AM, vimal singh <[EMAIL PROTECTED]> wrote:
> This patch adds prefetch support to access nand flash in both mpu and dma
> mode.
> This patch also adds 8-bit nand support (omap_read/write_buf8).
> Prefetch can be used for both 8- and 16-bit devices.
>
> Signed-off-by: Vimal Singh
> ---
> API's to access 8- and 16-bit NAND devices (omap_read/wirte_buf8/16)can be
> removed after sometime (once sufficient amount of testing is done for both
> kind
> of devices).
>
> vimal
> ---
> arch/arm/mach-omap2/gpmc.c | 95 +++
> arch/arm/plat-omap/include/mach/gpmc.h |4
> drivers/mtd/nand/Kconfig | 17 ++
> drivers/mtd/nand/omap2.c | 277
> -
> 4 files changed, 386 insertions(+), 7 deletions(-)
>
> Index: omapkernel/arch/arm/mach-omap2/gpmc.c
> ===
> --- omapkernel.orig/arch/arm/mach-omap2/gpmc.c 2008-11-06 12:49:34.0
> +0530
> +++ omapkernel/arch/arm/mach-omap2/gpmc.c 2008-11-06 12:49:57.0
> +0530
> @@ -54,6 +54,12 @@
> #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
> #define GPMC_SECTION_SHIFT 28 /* 128 MB */
>
> +#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH
> +#define CS_NUM_SHIFT 24
> +#define ENABLE_PREFETCH7
> +#define DMA_MPU_MODE 2
> +#endif
> +
> #ifdef CONFIG_OMAP3_PM
> /*
> * Structure to save/restore gpmc context
> @@ -407,6 +413,92 @@
> }
> EXPORT_SYMBOL(gpmc_cs_free);
>
> +#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH
> +/*
> + * gpmc_prefetch_init - configures default configuration for prefetch engine
> + */
> +static void gpmc_prefetch_init(void)
> +{
> + /* Setting the default threshold to 64 */
> + gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
> + gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x40 << 8);
> + gpmc_write_reg(GPMC_PREFETCH_CONFIG2, 0x0);
> +}
> +
> +/*
> + * gpmc_prefetch_start - configures and starts prefetch transfer
> + * @cs - nand cs (chip select) number
> + * @dma_mode: dma mode enable (1) or disable (0)
> + * @u32_count: number of bytes to be transferred
> + * @is_write: prefetch read(0) or write post(1) mode
> + */
> +void gpmc_prefetch_start(int cs, int dma_mode,
> + unsigned int u32_count, int is_write)
> +{
> + uint32_t prefetch_config1;
> + if (is_write) {
> + /* Set the amount of bytes to be prefetched */
> + gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
> +
> + /* Set dma/mpu mode, the post write and enable the engine
> +* Set which cs is using the post write
> +*/
> + prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
> + prefetch_config1 |= ((cs << CS_NUM_SHIFT) |
> + (dma_mode << DMA_MPU_MODE) |
> + (1 << ENABLE_PREFETCH) | 0x1);
> + gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
> + } else {
> + /* Set the amount of bytes to be prefetched */
> + gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
> +
> + /* Set dma/mpu mode, the prefech read and enable the engine
> +* Set which cs is using the prefetch
> +*/
> + prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
> + prefetch_config1 |= (((cs << CS_NUM_SHIFT) |
> + (dma_mode << DMA_MPU_MODE) |
> + (1 << ENABLE_PREFETCH)) & ~0x1);
> + gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
> + }
> + /* Start the prefetch engine */
> + gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
> +}
> +EXPORT_SYMBOL(gpmc_prefetch_start);
> +
> +/*
> + * gpmc_prefetch_stop - disables and stops the prefetch engine
> + */
> +void gpmc_prefetch_stop(void)
> +{
> + uint32_t prefetch_config1;
> + /* stop the PFPW engine */
> + gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
> +
> + /* Disable the PFPW engine */
> + prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
> + prefetch_config1 &= ~((0x07 << CS_NUM_SHIFT) |
> + (1 << ENABLE_PREFETCH) |
> + (1 << DMA_MPU_MODE) | 0x1);
> + gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
> +}
> +EXPORT_SYMBOL(gpmc_prefetch_stop);
> +
> +/*
> + * gpmc_prefetch_status - reads prefetch status of engine
> + */
> +int gpmc_prefetch_status(void)
> +{
> + return gpmc_read_reg(GPMC_PREFETCH_STATUS);
> +}
> +EXPORT_SYMBOL(gpmc_prefetch_statu
git pull request for omap-fixes (Re: [PATCH 0/4] omap fixes for -rc series)
* Russell King - ARM Linux <[EMAIL PROTECTED]> [081106 06:29]: > On Thu, Oct 30, 2008 at 07:11:14PM -0700, Tony Lindgren wrote: > > Here are few omap fixes for the current -rc series. > > These all look fine. The following changes since commit 45beca08dd8b6d6a65c5ffd730af2eac7a2c7a03: Linus Torvalds (1): Linux v2.6.28-rc3 are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git omap-fixes Sanjeev Premi (1): ARM: OMAP: Fix compiler warnings in gpmc.c Tony Lindgren (2): ARM: OMAP: Fix get_irqnr_and_base to clear spurious interrupt bits ARM: OMAP: Fix define for twl4030 irqs Zhaolei (1): ARM: OMAP: Fix debugfs_create_*'s error checking method for arm/plat-omap arch/arm/mach-omap2/gpmc.c|6 ++ arch/arm/plat-omap/clock.c| 20 ++-- arch/arm/plat-omap/include/mach/entry-macro.S |4 +++- arch/arm/plat-omap/include/mach/irqs.h|2 +- 4 files changed, 16 insertions(+), 16 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] beagle to build again
On Thu, Nov 06, 2008 at 09:11:12AM -0800, Tony Lindgren wrote: > * Felipe Balbi <[EMAIL PROTECTED]> [081106 06:03]: > > Add missing include and make beagle build again. > > Looks like this is covered by Dave's patch already. Yeah, just saw it. Thanks -- balbi -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] beagle to build again
* Felipe Balbi <[EMAIL PROTECTED]> [081106 06:03]: > Add missing include and make beagle build again. Looks like this is covered by Dave's patch already. Tony > > Signed-off-by: Felipe Balbi <[EMAIL PROTECTED]> > --- > > diff --git a/arch/arm/mach-omap2/board-omap3beagle.c > b/arch/arm/mach-omap2/board-omap3beagle.c > index 0f1c841..fb64845 100644 > --- a/arch/arm/mach-omap2/board-omap3beagle.c > +++ b/arch/arm/mach-omap2/board-omap3beagle.c > @@ -43,6 +43,7 @@ > #include > #include > > +#include "mmc-twl4030.h" > #include "twl4030-generic-scripts.h" > > #define GPMC_CS0_BASE 0x60 > > > -- > balbi > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to [EMAIL PROTECTED] > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/4] HSMMC: Add support for the second controller
* David Brownell <[EMAIL PROTECTED]> [081105 23:10]:
> On Wednesday 05 November 2008, Tony Lindgren wrote:
> > OK, I've pushed the hsmmc init patches. They still need work though.
> >
> > Please everybody check your board MMC configuration and send patches
> > as needed.
>
> See the appended build fixes ... :)
Oops, sorry I did not expect that kind of fixes!
> Also, I suspect there needs to be an MMC_CAP_8_BIT_DATA at
> some point, with hsmmc driver support.
>
>
> > Also the write protect interrupts are not handled, and gpio handling
> > is twl specific. Hopefully a better base for the code anyways.
>
> I'll have a look at write protect ... it wouldn't normally
> be an IRQ, just an input GPIO. Unlike the CD, which gets
> used for both purposes; that code looks iffy too.
OK. We also need to figure out what to do if we need to support other
gpios than twl gpios.
> Yes, a better base.
Thanks, pushing.
Tony
>
> - Dave
>
>
> = CUT HERE
> From: David Brownell <[EMAIL PROTECTED]>
>
> Build fixes for "HSMMC: Improve the interface for hsmmc_init()".
> The header file needs to work without MMC support enabled, and
> some board files needed to include it.
>
> Signed-off-by: David Brownell <[EMAIL PROTECTED]>
> ---
> arch/arm/mach-omap2/board-2430sdp.c |3 +++
> arch/arm/mach-omap2/board-ldp.c |3 +++
> arch/arm/mach-omap2/board-omap2evm.c |3 +++
> arch/arm/mach-omap2/board-omap3beagle.c |2 ++
> arch/arm/mach-omap2/board-omap3evm.c |2 ++
> arch/arm/mach-omap2/board-omap3pandora.c |2 ++
> arch/arm/mach-omap2/mmc-twl4030.h|8
> 7 files changed, 19 insertions(+), 4 deletions(-)
>
> --- a/arch/arm/mach-omap2/board-2430sdp.c
> +++ b/arch/arm/mach-omap2/board-2430sdp.c
> @@ -44,6 +44,9 @@
>
> #include
>
> +#include "mmc-twl4030.h"
> +
> +
> #define SDP2430_FLASH_CS0
> #define SDP2430_SMC91X_CS 5
>
> --- a/arch/arm/mach-omap2/board-ldp.c
> +++ b/arch/arm/mach-omap2/board-ldp.c
> @@ -41,6 +41,9 @@
> #include
> #include
>
> +#include "mmc-twl4030.h"
> +
> +
> #define CONFIG_DISABLE_HFCLK 1
>
> #define ENABLE_VAUX1_DEDICATED 0x03
> --- a/arch/arm/mach-omap2/board-omap2evm.c
> +++ b/arch/arm/mach-omap2/board-omap2evm.c
> @@ -41,6 +41,9 @@
> #include
> #include
>
> +#include "mmc-twl4030.h"
> +
> +
> #define GPMC_OFF_CONFIG1_0 0x60
>
> static struct mtd_partition omap2evm_nand_partitions[] = {
> --- a/arch/arm/mach-omap2/board-omap3beagle.c
> +++ b/arch/arm/mach-omap2/board-omap3beagle.c
> @@ -44,6 +44,8 @@
> #include
>
> #include "twl4030-generic-scripts.h"
> +#include "mmc-twl4030.h"
> +
>
> #define GPMC_CS0_BASE 0x60
> #define GPMC_CS_SIZE 0x30
> --- a/arch/arm/mach-omap2/board-omap3evm.c
> +++ b/arch/arm/mach-omap2/board-omap3evm.c
> @@ -40,6 +40,8 @@
>
> #include "sdram-micron-mt46h32m32lf-6.h"
> #include "twl4030-generic-scripts.h"
> +#include "mmc-twl4030.h"
> +
>
> static struct resource omap3evm_smc911x_resources[] = {
> [0] = {
> --- a/arch/arm/mach-omap2/board-omap3pandora.c
> +++ b/arch/arm/mach-omap2/board-omap3pandora.c
> @@ -47,6 +47,8 @@
> #include
>
> #include "sdram-micron-mt46h32m32lf-6.h"
> +#include "mmc-twl4030.h"
> +
>
> #define NAND_BLOCK_SIZE SZ_128K
> #define GPMC_CS0_BASE 0x60
> --- a/arch/arm/mach-omap2/mmc-twl4030.h
> +++ b/arch/arm/mach-omap2/mmc-twl4030.h
> @@ -6,20 +6,20 @@
> * published by the Free Software Foundation.
> */
>
> -#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
> - defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
> -
> struct twl4030_hsmmc_info {
> u8 mmc;/* controller 1/2/3 */
> u8 wires; /* 1/4/8 wires */
> int gpio_cd;/* or -EINVAL */
> };
>
> +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
> + defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
> +
> void hsmmc_init(struct twl4030_hsmmc_info *);
>
> #else
>
> -static inline void hsmmc_init(struct twl4030_hsmmc_info *)
> +static inline void hsmmc_init(struct twl4030_hsmmc_info *info)
> {
> }
>
>
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Re: [PATCH] OMAP3 powerdomains: remove RET from SGX power states list
* Paul Walmsley <[EMAIL PROTECTED]> [081106 03:09]:
> On Wed, 5 Nov 2008, Tony Lindgren wrote:
>
> > * Paul Walmsley <[EMAIL PROTECTED]> [081105 11:39]:
> > >
> > > The SGX device on OMAP3 does not support retention, so remove RET from
> > > the
> > > list of possible SGX power states. Problem debugged by Richard Woodruff
> > > <[EMAIL PROTECTED]>.
> >
> > Pushing.
>
> Just FYI, that patch prevents the kernel from booting due to a bug in
> pm34xx.c; patch below.
>
> Even with the follwoing patch, the initial power state setup code in
> pm34xx.c will bail out early since it still tries to set the SGX next
> power state to retention, which it does not support.
Pushing.
Tony
>
>
> - Paul
>
>
> OMAP3 PM: use list_for_each_entry_safe() when deleting list entries
>
> From: Paul Walmsley <[EMAIL PROTECTED]>
>
> The error path in clkdms_setup() needs to use list_for_each_entry_safe()
> when deleting entries from the list, or the kernel will crash.
>
> Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]>
> Cc: Jouni Högander <[EMAIL PROTECTED]>
> ---
> arch/arm/mach-omap2/pm34xx.c |4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index a11a657..da098d2 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -540,7 +540,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm)
>
> int __init omap3_pm_init(void)
> {
> - struct power_state *pwrst;
> + struct power_state *pwrst, *tmp;
> int ret;
>
> printk(KERN_ERR "Power Management for TI OMAP3.\n");
> @@ -583,7 +583,7 @@ err1:
> return ret;
> err2:
> free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
> - list_for_each_entry(pwrst, &pwrst_list, node) {
> + list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
> list_del(&pwrst->node);
> kfree(pwrst);
> }
--
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Re: [PATCH] OMAP3 flash: fix use of system_rev in board-3430sdp-flash.c
* Paul Walmsley <[EMAIL PROTECTED]> [081106 04:28]:
> Fix one remaining user of system_rev. This patch is needed for
> 3430SDP ES2 to boot after 4a4ada55c1bdaa2b9fd1293611b55ceba14b13e7.
>
> Bisected by Timo-Pekka Launonen's <[EMAIL PROTECTED]>
> list robot.
Nice to have that robot! :) Pushing.
Tony
> Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]>
> Cc: Timo-Pekka Launonen <[EMAIL PROTECTED]>
> Cc: Lauri Leukkunen <[EMAIL PROTECTED]>
> ---
> arch/arm/mach-omap2/board-3430sdp-flash.c |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-3430sdp-flash.c
> b/arch/arm/mach-omap2/board-3430sdp-flash.c
> index 6b0419c..51dd839 100644
> --- a/arch/arm/mach-omap2/board-3430sdp-flash.c
> +++ b/arch/arm/mach-omap2/board-3430sdp-flash.c
> @@ -210,7 +210,7 @@ void __init sdp3430_flash_init(void)
> gpmc_base_add = OMAP34XX_GPMC_VIRT;
>
> /* Configure start address and size of NOR device */
> - if (system_rev > OMAP3430_REV_ES1_0) {
> + if (omap_rev() > OMAP3430_REV_ES1_0) {
> sdp_nor_resource.start = FLASH_BASE_SDPV2;
> sdp_nor_resource.end= FLASH_BASE_SDPV2
> + FLASH_SIZE_SDPV2 - 1;
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to [EMAIL PROTECTED]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
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Re: [PATCH 0/4] omap fixes for -rc series
On Thu, Oct 30, 2008 at 07:11:14PM -0700, Tony Lindgren wrote: > Here are few omap fixes for the current -rc series. These all look fine. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] beagle to build again
Add missing include and make beagle build again. Signed-off-by: Felipe Balbi <[EMAIL PROTECTED]> --- diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 0f1c841..fb64845 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -43,6 +43,7 @@ #include #include +#include "mmc-twl4030.h" #include "twl4030-generic-scripts.h" #define GPMC_CS0_BASE 0x60 -- balbi -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH - Omapzoom][NAND] Add prefetch and DMA support
This patch adds prefetch support to access nand flash in both mpu and dma mode.
This patch also adds 8-bit nand support (omap_read/write_buf8).
Prefetch can be used for both 8- and 16-bit devices.
Signed-off-by: Vimal Singh
---
API's to access 8- and 16-bit NAND devices (omap_read/wirte_buf8/16)can be
removed after sometime (once sufficient amount of testing is done for both kind
of devices).
vimal
---
arch/arm/mach-omap2/gpmc.c | 95 +++
arch/arm/plat-omap/include/mach/gpmc.h |4
drivers/mtd/nand/Kconfig | 17 ++
drivers/mtd/nand/omap2.c | 277 -
4 files changed, 386 insertions(+), 7 deletions(-)
Index: omapkernel/arch/arm/mach-omap2/gpmc.c
===
--- omapkernel.orig/arch/arm/mach-omap2/gpmc.c 2008-11-06 12:49:34.0
+0530
+++ omapkernel/arch/arm/mach-omap2/gpmc.c 2008-11-06 12:49:57.0
+0530
@@ -54,6 +54,12 @@
#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
#define GPMC_SECTION_SHIFT 28 /* 128 MB */
+#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH
+#define CS_NUM_SHIFT 24
+#define ENABLE_PREFETCH7
+#define DMA_MPU_MODE 2
+#endif
+
#ifdef CONFIG_OMAP3_PM
/*
* Structure to save/restore gpmc context
@@ -407,6 +413,92 @@
}
EXPORT_SYMBOL(gpmc_cs_free);
+#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH
+/*
+ * gpmc_prefetch_init - configures default configuration for prefetch engine
+ */
+static void gpmc_prefetch_init(void)
+{
+ /* Setting the default threshold to 64 */
+ gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x40 << 8);
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG2, 0x0);
+}
+
+/*
+ * gpmc_prefetch_start - configures and starts prefetch transfer
+ * @cs - nand cs (chip select) number
+ * @dma_mode: dma mode enable (1) or disable (0)
+ * @u32_count: number of bytes to be transferred
+ * @is_write: prefetch read(0) or write post(1) mode
+ */
+void gpmc_prefetch_start(int cs, int dma_mode,
+ unsigned int u32_count, int is_write)
+{
+ uint32_t prefetch_config1;
+ if (is_write) {
+ /* Set the amount of bytes to be prefetched */
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
+
+ /* Set dma/mpu mode, the post write and enable the engine
+* Set which cs is using the post write
+*/
+ prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
+ prefetch_config1 |= ((cs << CS_NUM_SHIFT) |
+ (dma_mode << DMA_MPU_MODE) |
+ (1 << ENABLE_PREFETCH) | 0x1);
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
+ } else {
+ /* Set the amount of bytes to be prefetched */
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
+
+ /* Set dma/mpu mode, the prefech read and enable the engine
+* Set which cs is using the prefetch
+*/
+ prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
+ prefetch_config1 |= (((cs << CS_NUM_SHIFT) |
+ (dma_mode << DMA_MPU_MODE) |
+ (1 << ENABLE_PREFETCH)) & ~0x1);
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
+ }
+ /* Start the prefetch engine */
+ gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
+}
+EXPORT_SYMBOL(gpmc_prefetch_start);
+
+/*
+ * gpmc_prefetch_stop - disables and stops the prefetch engine
+ */
+void gpmc_prefetch_stop(void)
+{
+ uint32_t prefetch_config1;
+ /* stop the PFPW engine */
+ gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
+
+ /* Disable the PFPW engine */
+ prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
+ prefetch_config1 &= ~((0x07 << CS_NUM_SHIFT) |
+ (1 << ENABLE_PREFETCH) |
+ (1 << DMA_MPU_MODE) | 0x1);
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
+}
+EXPORT_SYMBOL(gpmc_prefetch_stop);
+
+/*
+ * gpmc_prefetch_status - reads prefetch status of engine
+ */
+int gpmc_prefetch_status(void)
+{
+ return gpmc_read_reg(GPMC_PREFETCH_STATUS);
+}
+EXPORT_SYMBOL(gpmc_prefetch_status);
+#else
+int gpmc_prefetch_status(void) {return 0; }
+void gpmc_prefetch_stop(void) {}
+void gpmc_prefetch_start(int cs, int dma_mode, unsigned int u32_count,
+ int is_write) {}
+#endif
+
static void __init gpmc_mem_init(void)
{
int cs;
@@ -474,6 +566,9 @@
gpmc_freq_cfg.freq_cfg = NULL;
gpmc_freq_cfg.total_no_of_freq = 0;
#endif
+#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH
+ gpmc_prefetch_init();
+#endif
gpmc_mem_init();
}
Index:
[PATCH - Omapzoom][NAND] removing nand hwecc warning for omap
Removing warning:
drivers/mtd/nand/omap2.c: In function 'omap_calculate_ecc':
drivers/mtd/nand/omap2.c:466: warning: unused variable 'chip'
Signed-off-by: Vimal Singh <[EMAIL PROTECTED]>
---
drivers/mtd/nand/omap2.c |1 -
1 files changed, 1 deletion(-)
Index: omapkernel/drivers/mtd/nand/omap2.c
===
--- omapkernel.orig/drivers/mtd/nand/omap2.c2008-11-06 12:48:05.0
+0530
+++ omapkernel/drivers/mtd/nand/omap2.c 2008-11-06 12:48:12.0 +0530
@@ -463,7 +463,6 @@
{
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
- register struct nand_chip *chip = mtd->priv;
unsigned long val = 0x0;
unsigned long reg;
--
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Re: [PATCH 04/10] ARM: OMAP2: Remove OMAP_PRM_REGADDR, OMAP_CM_REGADDR
Hi Russell, I've been on holiday, hence the delayed E-mail. On Mon, 27 Oct 2008, Russell King - ARM Linux wrote: > If I take this further, and detect clocks which result in > omap2_clk_wait_ready() being called, but we don't have a corresponding > [if]ck, I see at least these four warnings: > > CLK: omapctrl_ick.0: no other_clk but asked to wait_ready > CLK: sdrc_ick.0: no other_clk but asked to wait_ready > CLK: dpll4_m2x2_ck.0: no other_clk but asked to wait_ready > CLK: omap_32ksync_ick.0: no other_clk but asked to wait_ready > > So, presumably these ick clocks don't have corresponding fck clocks, > which means checking the fck register for the bit would be wrong? Yes, that's right. > So, here's the question: should any of the above clocks result in > omap2_wait_clock_ready() being called? If the answer is no, that's > great. If yes, are there missing clk structures for OMAP3? No, omap2_wait_clock_ready() shouldn't be called for those clocks. The current linux-omap git head does not call omap2_wait_clock_ready() in these cases, as far as I know. - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] OMAP: Fix McBSP spin_lock deadlock.
A spin_lock deadlock will occur when omap_mcbsp_request() is invoked.
omap_mcbsp_request() -->
clk_enable(mcbsp->clk) --> clk_enable get clockfw_lock, then call ->
omap2_clk_enable() -->
_omap2_clk_enable() -->
omap_mcbsp_clk_enable() -->
clk_enable(mcbsp_ick)--> now clk_enable acquire clockfw_lock again.
The solution:
If a alias clock has some relative clocks, enable relative clocks before enable
the alias clock.
Signed-off-by: Stanley.Miao <[EMAIL PROTECTED]>
---
arch/arm/mach-omap1/mcbsp.c | 67 ++--
arch/arm/mach-omap2/mcbsp.c | 88 +++---
arch/arm/plat-omap/clock.c |9 +++-
arch/arm/plat-omap/include/mach/clock.h |2 +
4 files changed, 47 insertions(+), 119 deletions(-)
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 7de7c69..cf220be 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -26,80 +26,45 @@
#define DPS_RSTCT2_PER_EN (1 << 0)
#define DSP_RSTCT2_WD_PER_EN (1 << 1)
-struct mcbsp_internal_clk {
- struct clk clk;
- struct clk **childs;
- int n_childs;
-};
-
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
-static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
+static void omap_mcbsp_clk_init(struct clk *mclk)
{
const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
int i;
- mclk->n_childs = ARRAY_SIZE(clk_names);
- mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
+ mclk->n_relatives = ARRAY_SIZE(clk_names);
+ mclk->relatives = kzalloc(mclk->n_relatives * sizeof(struct clk *),
GFP_KERNEL);
- for (i = 0; i < mclk->n_childs; i++) {
+ for (i = 0; i < mclk->n_relatives; i++) {
/* We fake a platform device to get correct device id */
struct platform_device pdev;
pdev.dev.bus = &platform_bus_type;
- pdev.id = mclk->clk.id;
- mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
- if (IS_ERR(mclk->childs[i]))
+ pdev.id = mclk->id;
+ mclk->relatives[i] = clk_get(&pdev.dev, clk_names[i]);
+ if (IS_ERR(mclk->relatives[i]))
printk(KERN_ERR "Could not get clock %s (%d).\n",
- clk_names[i], mclk->clk.id);
+ clk_names[i], mclk->id);
}
}
-static int omap_mcbsp_clk_enable(struct clk *clk)
-{
- struct mcbsp_internal_clk *mclk = container_of(clk,
- struct mcbsp_internal_clk, clk);
- int i;
-
- for (i = 0; i < mclk->n_childs; i++)
- clk_enable(mclk->childs[i]);
- return 0;
-}
-
-static void omap_mcbsp_clk_disable(struct clk *clk)
-{
- struct mcbsp_internal_clk *mclk = container_of(clk,
- struct mcbsp_internal_clk, clk);
- int i;
-
- for (i = 0; i < mclk->n_childs; i++)
- clk_disable(mclk->childs[i]);
-}
-
-static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
+static struct clk omap_mcbsp_clks[] = {
{
- .clk = {
- .name = "mcbsp_clk",
- .id = 1,
- .enable = omap_mcbsp_clk_enable,
- .disable= omap_mcbsp_clk_disable,
- },
+ .name = "mcbsp_clk",
+ .id = 1,
},
{
- .clk = {
- .name = "mcbsp_clk",
- .id = 3,
- .enable = omap_mcbsp_clk_enable,
- .disable= omap_mcbsp_clk_disable,
- },
+ .name = "mcbsp_clk",
+ .id = 3,
},
};
#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
#else
#define omap_mcbsp_clks_size 0
-static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
-static inline void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
+static struct clk __initdata *omap_mcbsp_clks;
+static inline void omap_mcbsp_clk_init(struct clk *mclk)
{ }
#endif
@@ -233,7 +198,7 @@ int __init omap1_mcbsp_init(void)
for (i = 0; i < omap_mcbsp_clks_size; i++) {
if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
- clk_register(&omap_mcbsp_clks[i].clk);
+ clk_register(&omap_mcbsp_clks[i]);
}
}
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index cae3ebe..20663e1 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -22,103 +22,57 @@
#include
#includ
Re: [PATCH] OMAP: Fix McBSP spin_lock deadlock.
On Wed, 2008-11-05 at 17:16 -0800, Tony Lindgren wrote:
> * David Brownell <[EMAIL PROTECTED]> [081105 15:53]:
> > On Wednesday 05 November 2008, Stanley.Miao wrote:
> > > @@ -333,7 +333,8 @@ struct omap_mcbsp_platform_data {
> > > u8 dma_rx_sync, dma_tx_sync;
> > > u16 rx_irq, tx_irq;
> > > struct omap_mcbsp_ops *ops;
> > > - char const *clk_name;
> > > + char const *ick_name;
> > > + char const *fck_name;
> > > };
> > >
> > > struct omap_mcbsp {
> >
> > I thought the idea was to fix this using the clock aliasing
> > facility ... so that the mcbsp driver would just
> >
> > ick = clk_get(dev, "ick");
> > fck = clk_get(dev, "fck");
> >
> > (with IS_ERR checks of course) and the platform data would
> > no longer need to hold those names.
> >
> > That approach can work on OMAP1 too ... I think this patch
> > breaks OMAP1 boards.
>
> Russell also has some ideas, so despite the nasty bug, let's put
> the clock aliasing and virtual clocks stuff on hold for a little
> while. Meanwhile, maybe we can just add some function for the
> virtual clock that does not cause the recursion?
After considering your suggestions, I change to another solution and
will re-send the patch.
Stanley.
>
> Tony
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[PATCH] OMAP3 flash: fix use of system_rev in board-3430sdp-flash.c
Fix one remaining user of system_rev. This patch is needed for
3430SDP ES2 to boot after 4a4ada55c1bdaa2b9fd1293611b55ceba14b13e7.
Bisected by Timo-Pekka Launonen's <[EMAIL PROTECTED]>
list robot.
Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]>
Cc: Timo-Pekka Launonen <[EMAIL PROTECTED]>
Cc: Lauri Leukkunen <[EMAIL PROTECTED]>
---
arch/arm/mach-omap2/board-3430sdp-flash.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/board-3430sdp-flash.c
b/arch/arm/mach-omap2/board-3430sdp-flash.c
index 6b0419c..51dd839 100644
--- a/arch/arm/mach-omap2/board-3430sdp-flash.c
+++ b/arch/arm/mach-omap2/board-3430sdp-flash.c
@@ -210,7 +210,7 @@ void __init sdp3430_flash_init(void)
gpmc_base_add = OMAP34XX_GPMC_VIRT;
/* Configure start address and size of NOR device */
- if (system_rev > OMAP3430_REV_ES1_0) {
+ if (omap_rev() > OMAP3430_REV_ES1_0) {
sdp_nor_resource.start = FLASH_BASE_SDPV2;
sdp_nor_resource.end= FLASH_BASE_SDPV2
+ FLASH_SIZE_SDPV2 - 1;
--
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Re: current git head craters on boot due to some MTD problem
Hi, On Thu, 6 Nov 2008, Paul Walmsley wrote: > The current git head crashes on boot due to some MTD-related problem on > 3430SDP. Partial boot log below. Timo-Pekka's robot tracked this down to commit 4a4ada55c1bdaa2b9fd1293611b55ceba14b13e7, which is the system_rev to omap_rev() change. board-3430sdp-flash.c needs to use omap_rev() also and not system_rev. Will send patch as a separate E-mail. - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
current git head craters on boot due to some MTD problem
Hi,
The current git head crashes on boot due to some MTD-related problem on
3430SDP. Partial boot log below.
- Paul
<4>Driver 'sd' needs updating - please use bus_type methods
Driver 'sd' needs updating - please use bus_type methods
<1>Unhandled fault: external abort on non-linefetch (0x1028) at 0xc920
Unhandled fault: external abort on non-linefetch (0x1028) at 0xc920
Internal error: : 1028 [#1]
Internal error: : 1028 [#1]
Modules linked in:Modules linked in:
CPU: 0Not tainted (2.6.28-rc3-omap1-05164-g0d272a9 #128)
CPU: 0Not tainted (2.6.28-rc3-omap1-05164-g0d272a9 #128)
PC is at cfi_qry_present+0x1c0/0x29c
PC is at cfi_qry_present+0x1c0/0x29c
LR is at cfi_qry_present+0x64/0x29c
LR is at cfi_qry_present+0x64/0x29c
pc : []lr : []psr: 6013
sp : c7817c38 ip : 0006 fp : c7817c74
pc : []lr : []psr: 6013
sp : c7817c38 ip : 0006 fp : c7817c74
r10: 0001 r9 : 0001 r8 :
r10: 0001 r9 : 0001 r8 :
r7 : 0002 r6 : c79fd968 r5 : 0002 r4 : 0001
r7 : 0002 r6 : c79fd968 r5 : 0002 r4 : 0001
r3 : c900 r2 : 0020 r1 : 0002 r0 : 5959
r3 : c900 r2 : 0020 r1 : 0002 r0 : 5959
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c5387f Table: 80004018 DAC: 0017
Control: 10c5387f Table: 80004018 DAC: 0017
Process swapper (pid: 1, stack limit = 0xc78162e0)
Process swapper (pid: 1, stack limit = 0xc78162e0)
Stack: (0xc7817c38 to 0xc7818000)
Stack: (0xc7817c38 to 0xc7818000)
7c20: 7c20:
5151 5151 5252 5252
7c40: 7c40: 5959 5959 c7817c50 c7817c50 0025 0025
0001 0001 c79fd968 c79fd968 0002 0002 0002
0002
7c60: 7c60: c7817ce8 c7817ce8 c7817ca4 c7817ca4 c7817c78
c7817c78 c01d1a60 c01d1a60 c01d1608 c01d1608 00ff 00ff
7c80: 7c80: c79fd968 c79fd968 0001 0001 c7817ce8 c7817ce8 c037d5a8
c037d5a8 c79fd968 c79fd968 c7817cdc c7817cdc c7817ca8
c7817ca8
7ca0: 7ca0: c01d0dbc c01d0dbc c01d18a4 c01d18a4 0006 0006 0004
0004 0007 0007 0001 0001 0002 0002 0001
0001
7cc0: 7cc0: c0395f24 c0395f24 c037d5a8 c037d5a8 c79fd968
c79fd968 c7817d4c c7817d4c c7817ce0 c7817ce0 c01d76ec c01d76ec c01d0d60
c01d0d60
7ce0: 7ce0: 2013 2013
0002 0002 0001 0001
7d00: 7d00:
7d20: 7d20: c7817d50 c7817d50 c0395f0c c0395f0c c0323cd9 c0323cd9 c79fd968
c79fd968 c037d188 c037d188 c037d5a8 c037d5a8 c037d1a8
c037d1a8
7d40: 7d40: c7817d5c c7817d5c c7817d50 c7817d50 c01d0d4c c01d0d4c c01d7684
c01d7684 c7817d7c c7817d7c c7817d60 c7817d60 c01d0d18 c01d0d18 c01d0d44
c01d0d44
7d60: 7d60: c79fd960 c79fd960 0400 0400 0400 0400 c037d188
c037d188 c7817da4 c7817da4 c7817d80 c7817d80 c001ceac c001ceac c01d0cd4
c01d0cd4
Re: [PATCH] OMAP3 powerdomains: remove RET from SGX power states list
On Wed, 5 Nov 2008, Tony Lindgren wrote:
> * Paul Walmsley <[EMAIL PROTECTED]> [081105 11:39]:
> >
> > The SGX device on OMAP3 does not support retention, so remove RET from the
> > list of possible SGX power states. Problem debugged by Richard Woodruff
> > <[EMAIL PROTECTED]>.
>
> Pushing.
Just FYI, that patch prevents the kernel from booting due to a bug in
pm34xx.c; patch below.
Even with the follwoing patch, the initial power state setup code in
pm34xx.c will bail out early since it still tries to set the SGX next
power state to retention, which it does not support.
- Paul
OMAP3 PM: use list_for_each_entry_safe() when deleting list entries
From: Paul Walmsley <[EMAIL PROTECTED]>
The error path in clkdms_setup() needs to use list_for_each_entry_safe()
when deleting entries from the list, or the kernel will crash.
Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]>
Cc: Jouni Högander <[EMAIL PROTECTED]>
---
arch/arm/mach-omap2/pm34xx.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a11a657..da098d2 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -540,7 +540,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm)
int __init omap3_pm_init(void)
{
- struct power_state *pwrst;
+ struct power_state *pwrst, *tmp;
int ret;
printk(KERN_ERR "Power Management for TI OMAP3.\n");
@@ -583,7 +583,7 @@ err1:
return ret;
err2:
free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
- list_for_each_entry(pwrst, &pwrst_list, node) {
+ list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
list_del(&pwrst->node);
kfree(pwrst);
}
[SMC911x ]fix for driver resume and compilation warning
Hi,
I am trying out suspend, resume on an OMAP3 based board. What I see during
resume is that the SMC911x driver resume routing gets stuck after trying to
transmit the packet out of the controller. Some debug messages below:
--> smc911x_drv_resume
eth0: --> smc911x_reset
eth0: smc911x_reset timeout waiting for PM restore
eth0: --> smc911x_enable
eth0: --> smc911x_phy_configure()
eth0: --> smc911x_phy_reset()
eth0: phy caps=0x782d
eth0: phy advertised caps=0x0de1
eth0: --> smc911x_phy_check_media
smc911x_phy_read: phyaddr=0x1, phyreg=0x01, phydata=0x7809
smc911x_phy_read: phyaddr=0x1, phyreg=0x01, phydata=0x7809
eth0: link down
Restarting tasks ... eth0: --> smc911x_hard_start_xmit
eth0: --> smc911x_hardware_send_pkt
eth0: --> smc911x_hard_start_xmit
eth0: --> smc911x_hardware_send_pkt
eth0: --> smc911x_hard_start_xmit
eth0: --> smc911x_hardware_send_pkt
nfs: server 172.24.190.217 not responding, still trying
nfs: server 172.24.190.217 not responding, still trying
The following change makes it work fine: (The change within smc911x_drv_probe
function was to get rid of a compilation warning).
Additionally, the SMC9211 data sheet says that when we enter D2 sleep state, we
need to set the EDPWRDOWN bit in the PHY Mode control/status register and clear
it when we are back to D0. This is not done in the code as far as I can see. So
does it mean that the PHY is not powered down but the controller is? I have
another patch that fixes it. I will send that as well unless I am missing
something.
Thanks,
-Romit
Signed-off-by: Romit Dasgupta <[EMAIL PROTECTED]>
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 5051554..1f26ab0 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -2050,7 +2050,9 @@ err_out:
*/
static int smc911x_drv_probe(struct platform_device *pdev)
{
+#ifdef SMC_DYNAMIC_BUS_CONFIG
struct smc911x_platdata *pd = pdev->dev.platform_data;
+#endif
struct net_device *ndev;
struct resource *res;
struct smc911x_local *lp;
@@ -2182,9 +2184,9 @@ static int smc911x_drv_resume(struct platform_device *dev)
if (netif_running(ndev)) {
smc911x_reset(ndev);
- smc911x_enable(ndev);
if (lp->phy_type != 0)
smc911x_phy_configure(&lp->phy_configure);
+ smc911x_enable(ndev);
netif_device_attach(ndev);
}
}
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Re: [REVIEW PATCH 8/9] DSS: support for Beagle Board
Op 6 nov 2008, om 09:23 heeft Tomi Valkeinen het volgende geschreven: However, the bootloader turns the DVI chip on (at least the default beagle board u-boot). Only the old and broken TI u-boots do that, recent ones (2008.10) with the patches that are going upstream don't touch the DVI chip (nor the audio chips for that matter. regards, Koen PGP.sig Description: This is a digitally signed message part
[PATCH 1/5] omap iommu: tlb and pagetable primitives
This patch provides:
- iotlb_*() : iommu tlb operations
- iopgtable_*() : iommu pagetable(twl) operations
- iommu_*() : the other generic operations
and the entry points to register and acquire iommu object.
Signed-off-by: Hiroshi DOYU <[EMAIL PROTECTED]>
---
arch/arm/plat-omap/include/mach/iommu.h | 179 +++
arch/arm/plat-omap/iommu.c | 825 +++
arch/arm/plat-omap/iopgtable.h | 70 +++
3 files changed, 1074 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/plat-omap/include/mach/iommu.h
create mode 100644 arch/arm/plat-omap/iommu.c
create mode 100644 arch/arm/plat-omap/iopgtable.h
diff --git a/arch/arm/plat-omap/include/mach/iommu.h
b/arch/arm/plat-omap/include/mach/iommu.h
new file mode 100644
index 000..4024a40
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/iommu.h
@@ -0,0 +1,179 @@
+/*
+ * omap iommu: main structures
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_IOMMU_H
+#define __MACH_IOMMU_H
+
+#include
+#include
+
+struct iotlb_entry {
+ u32 da;
+ u32 pa;
+ unsigned int pgsz, prsvd, valid;
+ union {
+ u16 ap;
+ struct {
+ u32 endian, elsz, mixed;
+ };
+ };
+};
+
+struct iommu {
+ char*name;
+ struct module *owner;
+ u32 *flags;
+ struct clk *clk;
+ void __iomem*regbase;
+ unsigned intregsize;
+ struct device *dev;
+
+ unsigned intrefcount;
+ struct mutexiommu_lock; /* global for this whole object */
+
+ /*
+* We don't change iopgd for a situation like pgd for a task,
+* but share it globally for each iommu.
+*/
+ u32 *iopgd;
+ spinlock_t page_table_lock; /* protect iopgd */
+
+ int nr_tlb_entries;
+ int irq;
+
+ struct list_headmmap;
+ struct mutexmmap_lock; /* protect mmap */
+
+ int (*isr)(struct iommu *obj);
+};
+
+struct cr_regs {
+ union {
+ struct {
+ u16 cam_l;
+ u16 cam_h;
+ };
+ u32 cam;
+ };
+ union {
+ struct {
+ u16 ram_l;
+ u16 ram_h;
+ };
+ u32 ram;
+ };
+};
+
+struct iotlb_lock {
+ int base;
+ int vict;
+};
+
+/* architecture specific functions */
+struct iommu_functions {
+ unsigned long version;
+
+ int (*enable)(struct iommu *obj);
+ void (*disable)(struct iommu *obj);
+ u32 (*fault_isr)(struct iommu *obj, u32 *ra);
+
+ void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
+ void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
+
+ struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e);
+ int (*cr_valid)(struct cr_regs *cr);
+ u32 (*cr_to_virt)(struct cr_regs *cr);
+ void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
+ ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf);
+
+ pgprot_t (*get_pte_attr)(struct iotlb_entry *e);
+
+ ssize_t (*dump_regs)(struct iommu *obj, char *buf);
+};
+
+struct iommu_platform_data {
+ const char *name;
+ int nr_tlb_entries;
+ struct clk *clk;
+ char*clk_name;
+ struct resource *res;
+ int n_res;
+};
+
+#include
+
+/*
+ * utilities for super page(16MB, 1MB, 64KB and 4KB)
+ */
+
+#define iopgsz_max(bytes) \
+ (((bytes) >= SZ_16M) ? SZ_16M : \
+((bytes) >= SZ_1M) ? SZ_1M : \
+((bytes) >= SZ_64K) ? SZ_64K : \
+((bytes) >= SZ_4K) ? SZ_4K : 0)
+
+#define bytes_to_iopgsz(bytes) \
+ (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
+((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
+((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
+((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
+
+#define iopgsz_to_bytes(iopgsz)\
+ (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
+((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
+((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
+((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
+
+#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
+
+/*
+ * global functions
+ */
+extern void iommu_set_arch(const struct iommu_functions *ops);
+extern struct iommu_functions *iommu_get_arch(void);
+
+extern u32 iommu_arch_version(void);
+
+extern int load_iot
[PATCH 4/5] omap iommu: sysfs for userland interface
Signed-off-by: Hiroshi DOYU <[EMAIL PROTECTED]>
---
arch/arm/plat-omap/iommu-sysfs.c | 393 ++
1 files changed, 393 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/plat-omap/iommu-sysfs.c
diff --git a/arch/arm/plat-omap/iommu-sysfs.c b/arch/arm/plat-omap/iommu-sysfs.c
new file mode 100644
index 000..17f7903
--- /dev/null
+++ b/arch/arm/plat-omap/iommu-sysfs.c
@@ -0,0 +1,393 @@
+/*
+ * omap iommu: sysfs for userland interface
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "iopgtable.h"
+
+#define kobj_to_iommu(x) \
+ to_iommu((struct device *)container_of(x, struct device, kobj))
+
+static ssize_t generic_attr_show(struct device *dev,
+struct device_attribute *attr, char *buf)
+{
+ struct iommu *obj = to_iommu(dev);
+
+ if (strcmp(attr->attr.name, "name") == 0)
+ return sprintf(buf, "%s\n", obj->name);
+
+ if (strcmp(attr->attr.name, "version") == 0)
+ return sprintf(buf, "%08x\n", iommu_arch_version());
+
+ if (strcmp(attr->attr.name, "nr_tlb_entries") == 0)
+ return sprintf(buf, "%d\n", obj->nr_tlb_entries);
+
+ WARN_ON(1);
+ return 0;
+}
+static DEVICE_ATTR(name, S_IRUGO, generic_attr_show, NULL);
+static DEVICE_ATTR(nr_tlb_entries, S_IRUGO, generic_attr_show, NULL);
+static DEVICE_ATTR(version, S_IRUGO, generic_attr_show, NULL);
+
+static ssize_t iotlb_attr_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct iommu *obj = to_iommu(dev);
+ struct iotlb_entry e;
+ struct cr_regs cr;
+ u32 da;
+
+ sscanf(buf, "%x %x", &cr.cam, &cr.ram); /* FIXME: Add OMAP1 support */
+ dev_dbg(obj->dev, "c:%08x r:%08x\n", cr.cam, cr.ram);
+
+ if (!cr.cam || !cr.ram)
+ return -EINVAL;
+
+ da = iotlb_cr_to_virt(&cr);
+
+ clk_enable(obj->clk);
+
+ flush_iotlb_page(obj, da);
+
+ iotlb_cr_to_e(&cr, &e);
+ load_iotlb_entry(obj, &e);
+
+ clk_disable(obj->clk);
+
+ return count;
+}
+
+static ssize_t iotlb_attr_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int i;
+ struct iotlb_lock saved, l;
+ struct iommu *obj = to_iommu(dev);
+ char *p;
+
+ clk_enable(obj->clk);
+
+ iotlb_lock_get(obj, &saved);
+ memcpy(&l, &saved, sizeof(saved));
+
+ p = buf;
+ p += sprintf(p, "%8s %8s\n", "cam:", "ram:");
+ p += sprintf(p, "-\n");
+
+ for (i = 0; i < obj->nr_tlb_entries; i++) {
+ struct cr_regs cr;
+
+ l.vict = i;
+ iotlb_read_cr(obj, &l, &cr);
+
+ if (!iotlb_cr_valid(&cr))
+ continue;
+
+ p += iotlb_dump_cr(obj, &cr, p);
+ }
+ iotlb_lock_set(obj, &saved);
+ clk_disable(obj->clk);
+
+ return p - buf;
+}
+static DEVICE_ATTR(tlb, S_IRUGO | S_IWUSR, iotlb_attr_show, iotlb_attr_store);
+
+static ssize_t iopgtable_attr_store(struct device *dev,
+struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct iommu *obj = to_iommu(dev);
+ struct iotlb_entry e;
+ struct cr_regs cr;
+ u32 da;
+ int err;
+
+ sscanf(buf, "%x %x", &cr.cam, &cr.ram);
+ dev_dbg(obj->dev, "c:%08x r:%08x\n", cr.cam, cr.ram);
+
+ if (!cr.cam || !cr.ram)
+ return -EINVAL;
+
+ da = iotlb_cr_to_virt(&cr);
+
+ clk_enable(obj->clk);
+
+ iotlb_cr_to_e(&cr, &e);
+ err = iopgtable_store_entry(obj, &e);
+ if (err)
+ dev_err(obj->dev, "%s:\tfail to store cr\n", __func__);
+
+ clk_disable(obj->clk);
+
+ return count;
+}
+
+static ssize_t iopgtable_attr_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int i;
+ char *p = buf;
+ struct iommu *obj = to_iommu(dev);
+ u32 *iopgd;
+
+ /*
+* FIXME: analyze the content of attribute in detail
+*/
+
+ p += sprintf(p, "L: %8s %8s\n", "da:", "pa:");
+ p += sprintf(p, "-\n");
+
+ spin_lock(&obj->page_table_lock);
+
+ iopgd = iopgd_offset(obj, 0);
+ for (i = 0; i < PTRS_PER_IOPGD; i++, iopgd++) {
+ int j;
+ u32 *iopte;
+
+ if (!*iopgd)
+ continue;
+
+ if (!((u32)*iopgd & IOPGD_TABLE)) {
+
[PATCH 3/5] omap iommu: simple virtual address space management
This patch provides a device drivers, which has a omap iommu, with
address mapping APIs between device virtual address(iommu), physical
address and MPU virtual address.
There are 4 possible patterns for iommu virtual address(iova/da) mapping.
|iova/mapping iommu_ page
| dapa va (d)-(p)-(v) functiontype
---
1 | c c c1 - 1 - 1_kmap() / _kunmap() s
2 | c c,a c1 - 1 - 1 _kmalloc()/ _kfree()s
3 | c d c1 - n - 1_vmap() / _vunmap() s
4 | c d,a c1 - n - 1 _vmalloc()/ _vfree()n*
'iova': device iommu virtual address
'da': alias of 'iova'
'pa': physical address
'va': mpu virtual address
'c':contiguous memory area
'd':dicontiguous memory area
'a':anonymous memory allocation
'()': optional feature
'n':a normal page(4KB) size is used.
's':multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used.
'*':not yet, but feasible.
Signed-off-by: Hiroshi DOYU <[EMAIL PROTECTED]>
---
arch/arm/include/asm/io.h |2 +
arch/arm/mach-omap2/devices.c |2 +-
arch/arm/mm/ioremap.c |7 +
arch/arm/plat-omap/include/mach/iovmm.h | 91
arch/arm/plat-omap/iovmm.c | 844 +++
5 files changed, 945 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/plat-omap/include/mach/iovmm.h
create mode 100644 arch/arm/plat-omap/iovmm.c
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 7193485..97f4e35 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -75,6 +75,8 @@ extern void __iomem * __arm_ioremap_pfn(unsigned long,
unsigned long, size_t, un
extern void __iomem * __arm_ioremap(unsigned long, size_t, unsigned int);
extern void __iounmap(volatile void __iomem *addr);
+extern int remap_area_page(unsigned long virt, unsigned long phys);
+
/*
* Bad read/write accesses...
*/
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 32550a5..8eb38d9 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -58,7 +58,7 @@ static inline void omap_init_camera(void)
static struct resource cam_resources[] = {
{
.start = OMAP34XX_CAMERA_BASE,
- .end= OMAP34XX_CAMERA_BASE + 0x1B70,
+ .end= OMAP34XX_CAMERA_BASE + 0x6c,
.flags = IORESOURCE_MEM,
},
{
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index b81dbf9..80dba0c 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -110,6 +110,13 @@ static int remap_area_pages(unsigned long start, unsigned
long pfn,
return err;
}
+/* FIXME */
+int remap_area_page(unsigned long virt, unsigned long phys)
+{
+ return remap_area_pages(virt, __phys_to_pfn(phys), PAGE_SIZE,
+ get_mem_type(MT_DEVICE));
+}
+EXPORT_SYMBOL(remap_area_page);
void __check_kvm_seq(struct mm_struct *mm)
{
diff --git a/arch/arm/plat-omap/include/mach/iovmm.h
b/arch/arm/plat-omap/include/mach/iovmm.h
new file mode 100644
index 000..c4daac3
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/iovmm.h
@@ -0,0 +1,91 @@
+/*
+ * omap iommu: simple virtual address space management
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __IOMMU_MMAP_H
+#define __IOMMU_MMAP_H
+
+struct iovm_struct {
+ struct iommu*iommu; /* iommu object which this belongs to */
+ u32 da_start; /* area definition */
+ u32 da_end;
+ u32 flags; /* IOVMF_: see below */
+ struct list_headlist; /* linked in ascending order */
+ struct sg_table *sgt; /* collection of physical addresses */
+ void*va; /* mpu side mapped address */
+};
+
+/*
+ * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
+ *
+ * lower 16 bit is used for h/w and upper 16 bit is for s/w.
+ */
+#define IOVMF_SW_SHIFT 16
+#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT)
+#define IOVMF_HW_MASK (~(IOVMF_HW_SIZE - 1))
+#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL
+
+/*
+ * iovma: h/w flags derived from cam and ram attribute
+ */
+#define IOVMF_CAM_MASK (~((1 << 10) - 1))
+#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK)
+
+#define IOVMF_PGSZ_MASK
[PATCH 2/5] omap iommu: omap2 architecture specific functions
The structure 'arch_mmu' accommodates the difference between omap1 and
omap2/3.
This patch provides omap2/3 specific functions and its registration.
Signed-off-by: Hiroshi DOYU <[EMAIL PROTECTED]>
---
arch/arm/mach-omap2/Makefile |2 +
arch/arm/mach-omap2/iommu_omap2.c| 379 ++
arch/arm/plat-omap/include/mach/iommu2.h | 92 +++
3 files changed, 473 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/iommu_omap2.c
create mode 100644 arch/arm/plat-omap/include/mach/iommu2.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b59555d..c54ca0a 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -41,6 +41,8 @@ obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
mailbox_mach-objs := mailbox.o
mmu_mach-objs := mmu.o
+obj-$(CONFIG_OMAP_IOMMU) += iommu_omap2.o
+
# Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC)+= board-generic.o
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o board-h4-mmc.o
diff --git a/arch/arm/mach-omap2/iommu_omap2.c
b/arch/arm/mach-omap2/iommu_omap2.c
new file mode 100644
index 000..848b782
--- /dev/null
+++ b/arch/arm/mach-omap2/iommu_omap2.c
@@ -0,0 +1,379 @@
+/*
+ * omap iommu: omap2 architecture specific functions
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <[EMAIL PROTECTED]>,
+ * Paul Mundt and Toshihiro Kobayashi
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+/*
+ * omap2 architecture specific register bit definitions
+ */
+#define IOMMU_ARCH_VERSION 0x0011
+
+/* SYSCONF */
+#define MMU_SYS_IDLE_SHIFT 3
+#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT)
+#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT)
+#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
+#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
+
+#define MMU_SYS_SOFTRESET (1 << 1)
+#define MMU_SYS_AUTOIDLE 1
+
+/* SYSSTATUS */
+#define MMU_SYS_RESETDONE 1
+
+/* IRQSTATUS & IRQENABLE */
+#define MMU_IRQ_MULTIHITFAULT (1 << 4)
+#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
+#define MMU_IRQ_EMUMISS(1 << 2)
+#define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
+#define MMU_IRQ_TLBMISS(1 << 0)
+#define MMU_IRQ_MASK \
+ (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \
+MMU_IRQ_TRANSLATIONFAULT)
+
+/* MMU_CNTL */
+#define MMU_CNTL_SHIFT 1
+#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
+#define MMU_CNTL_EML_TLB (1 << 3)
+#define MMU_CNTL_TWL_EN(1 << 2)
+#define MMU_CNTL_MMU_EN(1 << 1)
+
+#define get_cam_va_mask(pgsz) \
+ (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff00 :\
+((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff0 :\
+((pgsz) == MMU_CAM_PGSZ_64K) ? 0x :\
+((pgsz) == MMU_CAM_PGSZ_4K) ? 0xf000 : 0)
+
+#if defined(CONFIG_ARCH_OMAP3)
+
+#define OMAP2_MMU_REG_SIZE 256
+
+/* Camera ISP MMU */
+#define OMAP2_MMU1_BASE0x480bd400
+#define OMAP2_MMU1_IRQ 24
+
+/* IVA2.2 MMU */
+#define OMAP2_MMU2_BASE0x5d00
+#define OMAP2_MMU2_IRQ 28
+
+static struct resource iommu1_res[] = { /* Camera ISP MMU */
+ {
+ .start = OMAP2_MMU1_BASE,
+ .end= OMAP2_MMU1_BASE + OMAP2_MMU_REG_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = OMAP2_MMU1_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource iommu2_res[] = { /* IVA2.2 MMU */
+ {
+ .start = OMAP2_MMU2_BASE,
+ .end= OMAP2_MMU2_BASE + OMAP2_MMU_REG_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = OMAP2_MMU2_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct iommu_platform_data omap2_iommu_platform_data[] = {
+ {
+ .name = "isp",
+ .nr_tlb_entries = 8,
+ .clk_name = "cam_ick",
+ .res = iommu1_res,
+ .n_res = ARRAY_SIZE(iommu1_res),
+ },
+ {
+ .name = "iva2",
+ .nr_tlb_entries = 32,
+ .clk_name = "iva2_ck",
+ .res = iommu2_res,
+ .n_res = ARRAY_SIZE(iommu2_res),
+ },
+};
+#else
+static struct iommu_platform_data omap2_iommu_platform_data[];
+#endif /* CONFIG_ARCH_OMAP3 */
+
+static int __init iommu_device_init(void
[PATCH 5/5] omap iommu: entries for Kconfig and Makefile
Signed-off-by: Hiroshi DOYU <[EMAIL PROTECTED]> --- arch/arm/plat-omap/Kconfig |8 arch/arm/plat-omap/Makefile |1 + 2 files changed, 9 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 4df57d5..76bf4e7 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -174,6 +174,14 @@ config OMAP_MMU_FWK Say Y here if you want to use OMAP MMU framework support for DSP, IVA1.0 and Camera in OMAP1/2. +config OMAP_IOMMU + bool "IOMMU support" + depends on ARCH_OMAP + default n + help + Say Y here if you want to use OMAP MMU framework support for + IVA2 and Camera in OMAP3. + config OMAP_MBOX_FWK tristate "Mailbox framework support" depends on ARCH_OMAP diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 8e4ba1c..13946b3 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_I2C_OMAP) += i2c.o # OMAP MMU framework obj-$(CONFIG_OMAP_MMU_FWK) += mmu.o +obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o iommu-sysfs.o # OMAP mailbox framework obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o -- 1.6.0.3.613.g9f8f13 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [REVIEW PATCH 8/9] DSS: support for Beagle Board
On Thu, 2008-11-06 at 01:21 +0200, ext David Brownell wrote:
> On Wednesday 05 November 2008, Jarkko Nikula wrote:
> > > + r = gpio_request(beagle_display_data_dvi.panel_reset_gpio,
> "DVI reset GPIO");
> > > + if(r < 0) {
> >
> > GPIO label "DVI reset" is enough.
>
> Surely this ** doesn't work ** at least against the OMAP git tree
> which already has:
Well, it surely does! =)
But good catch, I'll fix it. There's probably a warning on kernel log
about "can't get a gpio".
>
> omap_cfg_reg(J25_34XX_GPIO170);
> gpio_request(170, "DVI_nPD");
> /* REVISIT leave DVI powered down until it's needed ... */
> gpio_direction_output(170, true);
>
> Label matches the DVI chip, not board schematics. Agreed,
> it's not a reset.
>
> I'd like to see any FB/DSS/... updates have the property that
> the TFP410 chip is powered down *unless* both (a) the frame
> buffer/DSS/... driver is active, and (b) the DVI channel is
> in use.
>
> So for example a kernel without FB/DSS/... configured, that
> DVI chip is never powered up. And when only the S-Video channel
> is used, DVI isn't powered up either.
>
Well, my drivers do not enable the DVI chip unless DVI is in use. It is
in use by default, but you can turn it off. And if the whole DSS is not
compiled in, then no body will turn the DVI chip on.
However, the bootloader turns the DVI chip on (at least the default
beagle board u-boot). If the kernel by default turns the DVI chip off,
and then later on when the DSS starts, we'll have a glitch on the
display. Not that there currently is support for glitchless transition
from bootloader display to kernel display, but still...
> - Dave
>
Tomi
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