[PATCH] OMAP2/3 clock: fix CONFIG_OMAP_RESET_CLOCKS
Hello Russell,
Kevin Hilman kindly alerted me to a bugfix patch that I had omitted from
the sets that I sent to you recently. It's inserted below. Perhaps you
might consider merging it along with the other sets that you are working
on? Without it, chip power management won't work correctly.
The good news is that it is a small and self-contained patch that should
be possible to apply at any point after patch D 08.
thanks,
- Paul
From: Paul Walmsley p...@pwsan.com
Date: Thu, 5 Feb 2009 00:58:23 -0700
OMAP2/3 clock: fix CONFIG_OMAP_RESET_CLOCKS
plat-omap/clock.c was skipping clocks with enable_reg == 0. This no longer
works now that we use enable_reg as an offset from a PRCM module.
Problem found and traced by Tero Kristo tero.kri...@nokia.com -
thanks Tero.
linux-omap source commit is 4c1cb27545d19642d43874ebeacef83bf3566b86.
Signed-off-by: Paul Walmsley p...@pwsan.com
Signed-off-by: Tony Lindgren t...@atomide.com
Cc: Tero Kristo tero.kri...@nokia.com
---
arch/arm/plat-omap/clock.c |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index c1fad02..bdf2cd4 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -547,8 +547,11 @@ static int __init clk_disable_unused(void)
unsigned long flags;
list_for_each_entry(ck, clocks, node) {
- if (ck-usecount 0 || (ck-flags ALWAYS_ENABLED) ||
- ck-enable_reg == 0)
+ if (ck-usecount 0 ||
+ (ck-flags (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)))
+ continue;
+
+ if (cpu_class_is_omap1() ck-enable_reg == 0)
continue;
spin_lock_irqsave(clockfw_lock, flags);
--
1.6.0.2.GIT
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RE: [PATCH F 06/12] OMAP2/3 clock: every clock must have a clkdm
Hi Richard, On Tue, 3 Feb 2009, Woodruff, Richard wrote: Virtual clocks should soon be eliminated from the OMAP clock tree. ( Virtual clocks is here used to refer a clock that does not have a referent in the hardware; the usage of the term in the code is loose.) So far as I know, all of the OMAP virtual clocks have either turned out to be superfluous (and prone to spinlock recursion bugs), or to be better implemented outside of the clock framework (such as the virtual OPP clocks). We've eliminated the former. We should be able to eliminate the latter in a few months. What is your idea for replacement of virtual OPPs? Especially on OMAP2 they were useful with tightly coupled clock sets. Some later versions of 2420 were characterized such that some of the dependencies could be ignored but that is not the case for all of them. The centerline design as I understand it wasn't for this. It just happened that enough margin was there in some binn'ed lots to do this. The rates and voltages would still be tightly coupled; the OPP change just wouldn't be handled by the clock framework. Will send patches to you once the code is fully baked, the patches would probably the best thing to comment on... - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH PM 0/2] OMAP McSPI: Fixes to save/restore
Hello, Here's two fixes for the recent save/restore change (OMAP3 McSPI: Adds context save/restore), which does not seem to work with chip select. Jouni Hogander already sent one patch, but it does not solve all the problems. This patch updates the shadow value on every write, and uses it instead of reading the register. A. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH PM 1/2] OMAP McSPI: Fix context save/restore
Fix context save/restore to work with chip select. Also update the shadow
CHCONF0 register on every write and eliminate register reads.
Signed-off-by: Aaro Koskinen aaro.koski...@nokia.com
---
drivers/spi/omap2_mcspi.c | 51 +---
1 files changed, 29 insertions(+), 22 deletions(-)
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index a7ee3b7..4d09777 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -134,6 +134,7 @@ struct omap2_mcspi_cs {
void __iomem*base;
unsigned long phys;
int word_len;
+ u32 chconf0;
};
/* used for context save and restore, structure members to be updated whenever
@@ -142,7 +143,6 @@ struct omap2_mcspi_cs {
struct omap2_mcspi_regs {
u32 sysconfig;
u32 modulctrl;
- u32 chconf0;
u32 wakeupenable;
};
@@ -187,12 +187,27 @@ static inline u32 mcspi_read_cs_reg(const struct
spi_device *spi, int idx)
return __raw_readl(cs-base + idx);
}
+static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
+{
+ struct omap2_mcspi_cs *cs = spi-controller_state;
+
+ return cs-chconf0;
+}
+
+static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
+{
+ struct omap2_mcspi_cs *cs = spi-controller_state;
+
+ cs-chconf0 = val;
+ mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
+}
+
static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
int is_read, int enable)
{
u32 l, rw;
- l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
+ l = mcspi_cached_chconf0(spi);
if (is_read) /* 1 is read, 0 write */
rw = OMAP2_MCSPI_CHCONF_DMAR;
@@ -200,7 +215,7 @@ static void omap2_mcspi_set_dma_req(const struct spi_device
*spi,
rw = OMAP2_MCSPI_CHCONF_DMAW;
MOD_REG_BIT(l, rw, enable);
- mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
}
static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
@@ -215,9 +230,9 @@ static void omap2_mcspi_force_cs(struct spi_device *spi,
int cs_active)
{
u32 l;
- l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
+ l = mcspi_cached_chconf0(spi);
MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
- mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
}
static void omap2_mcspi_set_master_mode(struct spi_master *master)
@@ -248,10 +263,6 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi
*mcspi)
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
omap2_mcspi_ctx[spi_cntrl-bus_num - 1].sysconfig);
- mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_CHCONF0,
- omap2_mcspi_ctx[spi_cntrl-bus_num - 1].chconf0);
-
-
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
omap2_mcspi_ctx[spi_cntrl-bus_num - 1].wakeupenable);
}
@@ -392,7 +403,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
spi_transfer *xfer)
c = count;
word_len = cs-word_len;
- l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
+ l = mcspi_cached_chconf0(spi);
l = ~OMAP2_MCSPI_CHCONF_TRM_MASK;
/* We store the pre-calculated register addresses on stack to speed
@@ -432,8 +443,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
spi_transfer *xfer)
* more word i/o: switch to rx+tx
*/
if (c == 0 tx == NULL)
- mcspi_write_cs_reg(spi,
- OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
*rx++ = __raw_readl(rx_reg);
#ifdef VERBOSE
dev_dbg(spi-dev, read-%d %02x\n,
@@ -471,8 +481,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
spi_transfer *xfer)
* more word i/o: switch to rx+tx
*/
if (c == 0 tx == NULL)
- mcspi_write_cs_reg(spi,
- OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
*rx++ = __raw_readl(rx_reg);
#ifdef VERBOSE
dev_dbg(spi-dev, read-%d %04x\n,
@@ -510,8 +519,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
spi_transfer *xfer)
* more word i/o: switch to rx+tx
*/
if (c == 0 tx == NULL)
- mcspi_write_cs_reg(spi,
-
[PATCH PM 2/2] OMAP McSPI: spin_unlock_irq() missing
spin_unlock_irq() not called on failure path Signed-off-by: Aaro Koskinen aaro.koski...@nokia.com --- drivers/spi/omap2_mcspi.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index 4d09777..56e91a4 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c @@ -751,7 +751,7 @@ static void omap2_mcspi_work(struct work_struct *work) spin_lock_irq(mcspi-lock); if (omap2_mcspi_enable_clocks(mcspi)) - return; + goto out; /* We only enable one channel at a time -- the one whose message is * at the head of the queue -- although this controller would gladly @@ -855,6 +855,7 @@ static void omap2_mcspi_work(struct work_struct *work) omap2_mcspi_disable_clocks(mcspi); +out: spin_unlock_irq(mcspi-lock); } -- 1.5.4.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH PM 0/1] OMAP3: PM: Fix to prcm save/restore
This patch should fix the problem in locking DPLL2 after wake-up from OFF mode: clock: dpll2_ck failed transition to 'locked' clock: dpll2_ck failed transition to 'locked' clock: dpll2_ck failed transition to 'locked' clock: dpll2_ck failed transition to 'locked' prcm.c |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH PM 1/1] OMAP3: PM: Save and restore also CM_CLKSEL1_PLL_IVA2
CM_CLKSEL1_PLL_IVA2 is not saved/restored currently. This patch is
adding save and restore for it.
Signed-off-by: Jouni Hogander jouni.hogan...@nokia.com
---
arch/arm/mach-omap2/prcm.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index c64b668..7ccaf7f 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -36,6 +36,7 @@ static void __iomem *cm_base;
struct omap3_prcm_regs {
u32 control_padconf_sys_nirq;
+ u32 iva2_cm_clksel1;
u32 iva2_cm_clksel2;
u32 cm_sysconfig;
u32 sgx_cm_clksel;
@@ -218,6 +219,8 @@ void omap3_prcm_save_context(void)
{
prcm_context.control_padconf_sys_nirq =
omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
+ prcm_context.iva2_cm_clksel1 =
+cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
prcm_context.iva2_cm_clksel2 =
cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
@@ -371,6 +374,8 @@ void omap3_prcm_restore_context(void)
{
omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
OMAP343X_CONTROL_PADCONF_SYSNIRQ);
+ cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
+CM_CLKSEL1);
cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
CM_CLKSEL2);
__raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
--
1.6.0.1
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Re: PM branch updates: 3430sdp and omap3evm results
Ramesh Gupta Guntha grgupt...@gmail.com writes: Hi Kevin, On 2/4/09, Kevin Hilman khil...@deeprootsystems.com wrote: Ramesh Gupta Guntha grgupt...@gmail.com writes: Kevin, On 2/4/09, Kevin Hilman khil...@deeprootsystems.com wrote: Ramesh Gupta Guntha grgupt...@gmail.com writes: Hi, I am able to resolve all other issues with this pm branch except one issue, I am not able to enable the iva2 clock once system is suspended and resumed, I am getting below messages. 3clock: dpll2_ck failed transition to 'locked' clock: dpll2_ck failed transition to 'locked' 3clock: dpll2_ck failed transition to 'locked' clock: dpll2_ck failed transition to 'locked' Once after booting ( without adding bridgedriver/ installing bridgedriver) CM_CLKEN_PLL_IVA2 value shows as 0x37 indicates IVA2 DPLL in locked mode. once after system suspend the value is not restored I am seeing that as 0x11 indicates IVA2 DPLL is low power stop mode. Can any one please provide your inputs on the above error? I tried reconfiguring the CM_CLKEN_PLL_IVA2 to lock mode but still I am seeing the same messages as above while enabling iva2 clock. Are you suspending into retention or off-mode? I am suspending into Off mode. Do you see this problem when only going into retention? If not, sounds like we're missing some registers being saved/restored across off-mode. I am seeing this issue only with OFF mode , retention works fine for me, yeah, looks like some registers are not restored properly across off mode. please let me know your inputs on this. I have just updated the PM branch with a fix from Jouni to save/restore CM_CLKSEL1_PLL_IVA2. Can you try the latest PM branch? Thanks, Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH PM 1/2] OMAP McSPI: Fix context save/restore
- Original Message -
From: Kevin Hilman khil...@deeprootsystems.com
To: Hemanth V heman...@ti.com
Cc: Aaro Koskinen aaro.koski...@nokia.com; linux-omap@vger.kernel.org
Sent: Thursday, February 05, 2009 7:59 PM
Subject: Re: [PATCH PM 1/2] OMAP McSPI: Fix context save/restore
Hemanth V heman...@ti.com writes:
Fix context save/restore to work with chip select. Also update the
shadow
CHCONF0 register on every write and eliminate register reads.
I believe the shadow CHCONF register need to have only the default
configuration as initialized by omap2_mcspi_setup_transfer(), since other
other
bits are initialized as and when required by omap2_mcspi_work().
The original problem you saw might be because of not masking
OMAP2_MCSPI_CHCONF_TRM_MASK and OMAP2_MCSPI_CHCONF_FORCE bits while
storing to
shadow register.
Hemanth,
Can you address this problem and post a single patch with the full
save/restore.
I have reverted the original patch in the pm branch and would like
to see a single patch including the fixes from Jouni and Aaro.
Kevin,
Both fixes cannot be taken since they are conflicting, I would like
to go with Jouni's fix.
Hemanth
Kevin
Signed-off-by: Aaro Koskinen aaro.koski...@nokia.com
---
drivers/spi/omap2_mcspi.c | 51
+---
1 files changed, 29 insertions(+), 22 deletions(-)
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index a7ee3b7..4d09777 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -134,6 +134,7 @@ struct omap2_mcspi_cs {
void __iomem *base;
unsigned long phys;
int word_len;
+ u32 chconf0;
};
/* used for context save and restore, structure members to be updated
whenever
@@ -142,7 +143,6 @@ struct omap2_mcspi_cs {
struct omap2_mcspi_regs {
u32 sysconfig;
u32 modulctrl;
- u32 chconf0;
u32 wakeupenable;
};
@@ -187,12 +187,27 @@ static inline u32 mcspi_read_cs_reg(const struct
spi_device *spi, int idx)
return __raw_readl(cs-base + idx);
}
+static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
+{
+ struct omap2_mcspi_cs *cs = spi-controller_state;
+
+ return cs-chconf0;
+}
+
+static inline void mcspi_write_chconf0(const struct spi_device *spi,
u32 val)
+{
+ struct omap2_mcspi_cs *cs = spi-controller_state;
+
+ cs-chconf0 = val;
+ mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
+}
+
static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
int is_read, int enable)
{
u32 l, rw;
- l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
+ l = mcspi_cached_chconf0(spi);
if (is_read) /* 1 is read, 0 write */
rw = OMAP2_MCSPI_CHCONF_DMAR;
@@ -200,7 +215,7 @@ static void omap2_mcspi_set_dma_req(const struct
spi_device
*spi,
rw = OMAP2_MCSPI_CHCONF_DMAW;
MOD_REG_BIT(l, rw, enable);
- mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
}
static void omap2_mcspi_set_enable(const struct spi_device *spi, int
enable)
@@ -215,9 +230,9 @@ static void omap2_mcspi_force_cs(struct spi_device
*spi,
int cs_active)
{
u32 l;
- l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
+ l = mcspi_cached_chconf0(spi);
MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
- mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
}
static void omap2_mcspi_set_master_mode(struct spi_master *master)
@@ -248,10 +263,6 @@ static void omap2_mcspi_restore_ctx(struct
omap2_mcspi
*mcspi)
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
omap2_mcspi_ctx[spi_cntrl-bus_num - 1].sysconfig);
- mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_CHCONF0,
- omap2_mcspi_ctx[spi_cntrl-bus_num - 1].chconf0);
-
-
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
omap2_mcspi_ctx[spi_cntrl-bus_num - 1].wakeupenable);
}
@@ -392,7 +403,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
spi_transfer *xfer)
c = count;
word_len = cs-word_len;
- l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
+ l = mcspi_cached_chconf0(spi);
l = ~OMAP2_MCSPI_CHCONF_TRM_MASK;
/* We store the pre-calculated register addresses on stack to speed
@@ -432,8 +443,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
spi_transfer *xfer)
* more word i/o: switch to rx+tx
*/
if (c == 0 tx == NULL)
- mcspi_write_cs_reg(spi,
- OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
*rx++ = __raw_readl(rx_reg);
#ifdef VERBOSE
dev_dbg(spi-dev, read-%d %02x\n,
@@ -471,8 +481,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
spi_transfer *xfer)
* more word i/o: switch to rx+tx
*/
if (c == 0 tx == NULL)
- mcspi_write_cs_reg(spi,
- OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
*rx++ = __raw_readl(rx_reg);
#ifdef VERBOSE
dev_dbg(spi-dev, read-%d %04x\n,
@@ -510,8 +519,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
spi_transfer *xfer)
* more word i/o: switch to rx+tx
*/
if (c == 0 tx == NULL)
- mcspi_write_cs_reg(spi,
- OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
*rx++ = __raw_readl(rx_reg);
Re: [PATCH PM 1/2] OMAP McSPI: Fix context save/restore
ext Hemanth V heman...@ti.com writes: - Original Message - From: Kevin Hilman khil...@deeprootsystems.com To: Hemanth V heman...@ti.com Cc: Aaro Koskinen aaro.koski...@nokia.com; linux-omap@vger.kernel.org Sent: Thursday, February 05, 2009 7:59 PM Subject: Re: [PATCH PM 1/2] OMAP McSPI: Fix context save/restore Hemanth V heman...@ti.com writes: Fix context save/restore to work with chip select. Also update the shadow CHCONF0 register on every write and eliminate register reads. I believe the shadow CHCONF register need to have only the default configuration as initialized by omap2_mcspi_setup_transfer(), since other other bits are initialized as and when required by omap2_mcspi_work(). The original problem you saw might be because of not masking OMAP2_MCSPI_CHCONF_TRM_MASK and OMAP2_MCSPI_CHCONF_FORCE bits while storing to shadow register. Hemanth, Can you address this problem and post a single patch with the full save/restore. I have reverted the original patch in the pm branch and would like to see a single patch including the fixes from Jouni and Aaro. Kevin, Both fixes cannot be taken since they are conflicting, I would like to go with Jouni's fix. Bad thing in that one is that it doesn't work:) Kevin, to my understanding patches from Aaro Koskinen are working. If they are ok to you, please push them. So the patches are: [PATCH PM 0/2] OMAP McSPI: Fixes to save/restore [PATCH PM 1/2] OMAP McSPI: Fix context save/restore [PATCH PM 2/2] OMAP McSPI: spin_unlock_irq() missing and the sender is Koskinen Aaro. Those patches are working alone. -- Jouni Högander -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: PM branch updates: 3430sdp and omap3evm results
Kevin, I applied the patch maually at my end and tested, this works fine for me. anyway I will try with pm branch . thanks Ramesh Gupta G On 2/5/09, Kevin Hilman khil...@deeprootsystems.com wrote: Ramesh Gupta Guntha grgupt...@gmail.com writes: Hi Kevin, On 2/4/09, Kevin Hilman khil...@deeprootsystems.com wrote: Ramesh Gupta Guntha grgupt...@gmail.com writes: Kevin, On 2/4/09, Kevin Hilman khil...@deeprootsystems.com wrote: Ramesh Gupta Guntha grgupt...@gmail.com writes: Hi, I am able to resolve all other issues with this pm branch except one issue, I am not able to enable the iva2 clock once system is suspended and resumed, I am getting below messages. 3clock: dpll2_ck failed transition to 'locked' clock: dpll2_ck failed transition to 'locked' 3clock: dpll2_ck failed transition to 'locked' clock: dpll2_ck failed transition to 'locked' Once after booting ( without adding bridgedriver/ installing bridgedriver) CM_CLKEN_PLL_IVA2 value shows as 0x37 indicates IVA2 DPLL in locked mode. once after system suspend the value is not restored I am seeing that as 0x11 indicates IVA2 DPLL is low power stop mode. Can any one please provide your inputs on the above error? I tried reconfiguring the CM_CLKEN_PLL_IVA2 to lock mode but still I am seeing the same messages as above while enabling iva2 clock. Are you suspending into retention or off-mode? I am suspending into Off mode. Do you see this problem when only going into retention? If not, sounds like we're missing some registers being saved/restored across off-mode. I am seeing this issue only with OFF mode , retention works fine for me, yeah, looks like some registers are not restored properly across off mode. please let me know your inputs on this. I have just updated the PM branch with a fix from Jouni to save/restore CM_CLKSEL1_PLL_IVA2. Can you try the latest PM branch? Thanks, Kevin -- Thanks Ramesh Gupta G -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH PM 1/2] OMAP McSPI: Fix context save/restore
Hemanth V heman...@ti.com writes:
- Original Message -
From: Kevin Hilman khil...@deeprootsystems.com
To: Hemanth V heman...@ti.com
Cc: Aaro Koskinen aaro.koski...@nokia.com; linux-omap@vger.kernel.org
Sent: Thursday, February 05, 2009 7:59 PM
Subject: Re: [PATCH PM 1/2] OMAP McSPI: Fix context save/restore
Hemanth V heman...@ti.com writes:
Fix context save/restore to work with chip select. Also update the
shadow
CHCONF0 register on every write and eliminate register reads.
I believe the shadow CHCONF register need to have only the default
configuration as initialized by omap2_mcspi_setup_transfer(), since
other other
bits are initialized as and when required by omap2_mcspi_work().
The original problem you saw might be because of not masking
OMAP2_MCSPI_CHCONF_TRM_MASK and OMAP2_MCSPI_CHCONF_FORCE bits while
storing to
shadow register.
Hemanth,
Can you address this problem and post a single patch with the full
save/restore.
I have reverted the original patch in the pm branch and would like
to see a single patch including the fixes from Jouni and Aaro.
Kevin,
Both fixes cannot be taken since they are conflicting, I would like
to go with Jouni's fix.
Actually, I'd prefer to see Aaro's fix as it goes a little further to
optimize the save/restore path. He also fixed a locking bug.
Kevin
Kevin
Signed-off-by: Aaro Koskinen aaro.koski...@nokia.com
---
drivers/spi/omap2_mcspi.c | 51
+---
1 files changed, 29 insertions(+), 22 deletions(-)
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index a7ee3b7..4d09777 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -134,6 +134,7 @@ struct omap2_mcspi_cs {
void __iomem *base;
unsigned long phys;
int word_len;
+ u32 chconf0;
};
/* used for context save and restore, structure members to be
updated whenever
@@ -142,7 +143,6 @@ struct omap2_mcspi_cs {
struct omap2_mcspi_regs {
u32 sysconfig;
u32 modulctrl;
- u32 chconf0;
u32 wakeupenable;
};
@@ -187,12 +187,27 @@ static inline u32 mcspi_read_cs_reg(const struct
spi_device *spi, int idx)
return __raw_readl(cs-base + idx);
}
+static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
+{
+ struct omap2_mcspi_cs *cs = spi-controller_state;
+
+ return cs-chconf0;
+}
+
+static inline void mcspi_write_chconf0(const struct spi_device
*spi, u32 val)
+{
+ struct omap2_mcspi_cs *cs = spi-controller_state;
+
+ cs-chconf0 = val;
+ mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
+}
+
static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
int is_read, int enable)
{
u32 l, rw;
- l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
+ l = mcspi_cached_chconf0(spi);
if (is_read) /* 1 is read, 0 write */
rw = OMAP2_MCSPI_CHCONF_DMAR;
@@ -200,7 +215,7 @@ static void omap2_mcspi_set_dma_req(const
struct spi_device
*spi,
rw = OMAP2_MCSPI_CHCONF_DMAW;
MOD_REG_BIT(l, rw, enable);
- mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
}
static void omap2_mcspi_set_enable(const struct spi_device *spi,
int enable)
@@ -215,9 +230,9 @@ static void omap2_mcspi_force_cs(struct
spi_device *spi,
int cs_active)
{
u32 l;
- l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
+ l = mcspi_cached_chconf0(spi);
MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
- mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
}
static void omap2_mcspi_set_master_mode(struct spi_master *master)
@@ -248,10 +263,6 @@ static void omap2_mcspi_restore_ctx(struct
omap2_mcspi
*mcspi)
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
omap2_mcspi_ctx[spi_cntrl-bus_num - 1].sysconfig);
- mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_CHCONF0,
- omap2_mcspi_ctx[spi_cntrl-bus_num - 1].chconf0);
-
-
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
omap2_mcspi_ctx[spi_cntrl-bus_num - 1].wakeupenable);
}
@@ -392,7 +403,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
spi_transfer *xfer)
c = count;
word_len = cs-word_len;
- l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
+ l = mcspi_cached_chconf0(spi);
l = ~OMAP2_MCSPI_CHCONF_TRM_MASK;
/* We store the pre-calculated register addresses on stack to speed
@@ -432,8 +443,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
spi_transfer *xfer)
* more word i/o: switch to rx+tx
*/
if (c == 0 tx == NULL)
- mcspi_write_cs_reg(spi,
- OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
*rx++ = __raw_readl(rx_reg);
#ifdef VERBOSE
dev_dbg(spi-dev, read-%d %02x\n,
@@ -471,8 +481,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
spi_transfer *xfer)
* more word i/o: switch to rx+tx
*/
if (c == 0 tx == NULL)
- mcspi_write_cs_reg(spi,
- OMAP2_MCSPI_CHCONF0, l);
+ mcspi_write_chconf0(spi, l);
*rx++ = __raw_readl(rx_reg);
#ifdef VERBOSE
dev_dbg(spi-dev,
[PATCH 1/1] per board prm timings
API definition to set prm setup times
Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com
---
arch/arm/mach-omap2/pm.h |9 +
arch/arm/mach-omap2/pm34xx.c | 39 +--
2 files changed, 42 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 451f247..d79ea07 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -33,9 +33,18 @@ extern void *omap3_secure_ram_storage;
extern void omap2_block_sleep(void);
extern void omap2_allow_sleep(void);
#ifdef CONFIG_ARCH_OMAP3
+struct prm_setup_times {
+ u16 clksetup;
+ u16 voltsetup_time1;
+ u16 voltsetup_time2;
+ u16 voltoffset;
+ u16 voltsetup2;
+};
+
extern void omap3_pm_off_mode_enable(int);
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
+extern void omap3_set_prm_setup_times(struct prm_setup_times *setup_times);
#else
#define omap3_pm_off_mode_enable(int) do {} while (0);
#define omap3_pm_get_suspend_state(pwrdm) do {} while (0);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 44189a0..f531638 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -85,6 +85,14 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
static struct powerdomain *core_pwrdm, *per_pwrdm;
static struct powerdomain *cam_pwrdm;
+static struct prm_setup_times prm_setup = {
+ .clksetup = 0xff,
+ .voltsetup_time1 = 0xfff,
+ .voltsetup_time2 = 0xfff,
+ .voltoffset = 0xff,
+ .voltsetup2 = 0xff,
+};
+
static inline void omap3_per_save_context(void)
{
omap3_gpio_save_context();
@@ -880,6 +888,23 @@ int omap3_pm_set_suspend_state(struct powerdomain *pwrdm,
int state)
return -EINVAL;
}
+void omap3_set_prm_setup_times(struct prm_setup_times *setup_times)
+{
+ prm_setup.clksetup = setup_times-clksetup;
+ prm_setup.voltsetup_time1 = setup_times-voltsetup_time1;
+ prm_setup.voltsetup_time2 = setup_times-voltsetup_time2;
+ prm_setup.voltoffset = setup_times-voltoffset;
+ prm_setup.voltsetup2 = setup_times-voltsetup2;
+
+ printk(omap3_set_prm_setup_times %04x, %04x, %04x, %04x, %04x\n,
+ prm_setup.clksetup,
+ prm_setup.voltsetup_time1,
+ prm_setup.voltsetup_time2,
+ prm_setup.voltoffset,
+ prm_setup.voltsetup2);
+
+}
+
static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
struct power_state *pwrst;
@@ -1015,6 +1040,7 @@ err2:
static void __init configure_vc(void)
{
+
prm_write_mod_reg((R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA1_SHIFT) |
(R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA0_SHIFT),
OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
@@ -1044,21 +1070,22 @@ static void __init configure_vc(void)
OMAP3430_GR_MOD,
OMAP3_PRM_VC_I2C_CFG_OFFSET);
- /* Setup voltctrl and other setup times */
+ /* Setup value for voltctrl */
prm_write_mod_reg(OMAP3430_AUTO_RET,
OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET);
- prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
+ /* Write setup times */
+ prm_write_mod_reg(prm_setup.clksetup, OMAP3430_GR_MOD,
OMAP3_PRM_CLKSETUP_OFFSET);
- prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2
+ prm_write_mod_reg((prm_setup.voltsetup_time2
OMAP3430_SETUP_TIME2_SHIFT) |
- (OMAP3430_VOLTSETUP_TIME1
+ (prm_setup.voltsetup_time1
OMAP3430_SETUP_TIME1_SHIFT),
OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
- prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
+ prm_write_mod_reg(prm_setup.voltoffset, OMAP3430_GR_MOD,
OMAP3_PRM_VOLTOFFSET_OFFSET);
- prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
+ prm_write_mod_reg(prm_setup.voltsetup2, OMAP3430_GR_MOD,
OMAP3_PRM_VOLTSETUP2_OFFSET);
}
--
1.5.6.3
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Re: [PATCH] OMAP: MMC: recover from transfer failures - Resend
On Tue, 3 Feb 2009 15:05:58 +0100 Jean Pihet jpi...@mvista.com wrote: + while (OMAP_HSMMC_READ(host-base, + SYSCTL) SRD) + ; Is a __raw_readl() sufficient to prevent the cpu from burning up here, or should we add cpu_relax()? An infinite loop which assumes the hardware is perfect is always a worry. But I see the driver already does that, so we're no worse off.. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] OMAP: MMC: recover from transfer failures - Resend
On Thu, 5 Feb 2009, Andrew Morton wrote: On Tue, 3 Feb 2009 15:05:58 +0100 Jean Pihet jpi...@mvista.com wrote: + while (OMAP_HSMMC_READ(host-base, + SYSCTL) SRD) + ; Is a __raw_readl() sufficient to prevent the cpu from burning up here, or should we add cpu_relax()? The __raw_readl() should be sufficient. The MMC controller is located on the L4 CORE interconnect, so the round trip latency for the read from MMC is at least 90 ns, while the CPU cycle time is only about 1 to 2 ns. An infinite loop which assumes the hardware is perfect is always a worry. But I see the driver already does that, so we're no worse off.. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [patch 2.6.29-rc1-omap git] twl4030_keypad cleanup
On Wednesday 04 February 2009, Tony Lindgren wrote:
Start cleaning up the twl4030 keypad driver to become more
suitable for mainline.
- Remove false OMAP dependencies: names, mach/keypad.h, Kconfig
- We don't need a miniature header file
- Add missing input_sync()
- ...
The driver should also be renamed as twl4030_keypad.c; that will
be a different patch.
Pushing this to l-o tree, let me know when/if you need the patch
against the mainline tree added to the omap-upstream queue.
I'll (re?)send the mainline patch in a bit.
Meanwhile, here's the rename patch.
- Dave
= CUT HERE
From: David Brownell dbrown...@users.sourceforge.net
Rename this so it no longer presumes needless OMAP dependency.
Signed-off-by: David Brownell dbrown...@users.sourceforge.net
---
drivers/input/keyboard/Makefile |2
drivers/input/keyboard/omap-twl4030keypad.c | 489 -
drivers/input/keyboard/twl4030keypad.c | 493 ++
3 files changed, 494 insertions(+), 490 deletions(-)
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_KEYBOARD_OMAP) += omap-key
obj-$(CONFIG_OMAP_PS2) += innovator_ps2.o
obj-$(CONFIG_KEYBOARD_TSC2301) += tsc2301_kp.o
obj-$(CONFIG_KEYBOARD_LM8323) += lm8323.o
-obj-$(CONFIG_KEYBOARD_TWL4030) += omap-twl4030keypad.o
+obj-$(CONFIG_KEYBOARD_TWL4030) += twl4030keypad.o
obj-$(CONFIG_KEYBOARD_PXA27x) += pxa27x_keypad.o
obj-$(CONFIG_KEYBOARD_PXA930_ROTARY) += pxa930_rotary.o
obj-$(CONFIG_KEYBOARD_AAED2000)+= aaed2000_kbd.o
--- a/drivers/input/keyboard/omap-twl4030keypad.c
+++ /dev/null
@@ -1,489 +0,0 @@
-/*
- * drivers/input/keyboard/omap-twl4030keypad.c
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2008 Nokia Corporation
- *
- * Code re-written for 2430SDP by:
- * Syed Mohammed Khasim x0kha...@ti.com
- *
- * Initial Code:
- * Manjunatha G K manj...@ti.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include linux/kernel.h
-#include linux/module.h
-#include linux/init.h
-#include linux/interrupt.h
-#include linux/input.h
-#include linux/platform_device.h
-#include linux/i2c/twl4030.h
-
-/*
- * The TWL4030 family chips include a keypad controller that supports
- * up to an 8x8 switch matrix. The controller can issue system wakeup
- * events, since it uses only the always-on 32KiHz oscillator, and has
- * an internal state machine that decodes pressed keys, including
- * multi-key combinations.
- *
- * This driver lets boards define what keycodes they wish to report for
- * which scancodes, as part of the struct twl4030_keypad_data used in
- * the probe() routine.
- *
- * See the TPS65950 documentation; that's the general availability
- * version of the TWL5030 second generation part.
- */
-#define MAX_ROWS 8 /* TWL4030 hard limit */
-
-struct twl4030_keypad {
- unsigned*keymap;
- unsigned intkeymapsize;
- u16 kp_state[MAX_ROWS];
- unsignedn_rows;
- unsignedn_cols;
- unsignedirq;
-
- struct device *dbg_dev;
- struct input_dev *input;
-};
-
-#define ROWCOL_MASKKEY(0xf, 0xf, 0)
-#define KEYNUM_MASK~PERSISTENT_KEY(0xf, 0xf)
-
-/*--*/
-
-/* arbitrary prescaler value 0..7 */
-#define PTV_PRESCALER 4
-
-/* Register Offsets */
-#define KEYP_CTRL 0x00
-#define KEYP_DEB 0x01
-#define KEYP_LONG_KEY 0x02
-#define KEYP_LK_PTV0x03
-#define KEYP_TIMEOUT_L 0x04
-#define KEYP_TIMEOUT_H 0x05
-#define KEYP_KBC 0x06
-#define KEYP_KBR 0x07
-#define KEYP_SMS 0x08
-#define KEYP_FULL_CODE_7_0 0x09/* row 0 column status */
-#define KEYP_FULL_CODE_15_80x0a/* ... row 1 ... */
-#define KEYP_FULL_CODE_23_16 0x0b
-#define KEYP_FULL_CODE_31_24 0x0c
-#define KEYP_FULL_CODE_39_32 0x0d
-#define KEYP_FULL_CODE_47_40 0x0e
-#define KEYP_FULL_CODE_55_48
Re: [patch/rfc 2.6.28-rc2] input: twl4030_keypad driver
On Friday 30 January 2009, hartleys wrote:
I'd support an overall cleanup patch that fixes all those things at once.
How's this for a starting point? I'm willing to create a cleanup patch
for all the mach-omap1, mach-omap2, and mach-pxa users.
Signed-off-by: H Hartley Sweeten hswee...@visionengravers.com
I think none of the twl4030 keypad users are in mainline, so far...
My first reaction to this is that it's a bit incomplete.
It replaces only the KEY() macro in the $SUBJECT patch:
- There are two more public ones (for board files):
* KEY_PERSISTENT flags row/column values to ignore
* PERSISTENT_KEY (sigh) generates a row/col entry
with such a marking (instead of a keycode)
- Plus two driver-internal ones:
* ROWCOL_MASK to strip R/C from KEY()
* KEYCODE_MASK to stip the keycode from a KEY()
If there is going to be something reusable across the whole
input subsystem (for drivers that don't need fancy stuff),
it should really address the whole problem...
- Dave
---
diff --git a/include/linux/input.h b/include/linux/input.h
index 1249a0c..0879493 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -598,6 +598,14 @@ struct input_absinfo {
#define KEY_CNT(KEY_MAX+1)
/*
+ * Macro to pack the row/col of a key on a matrix keypad and it's associated
+ * KEY_* code into into an array. 4 bits are used for both the row and
column
+ * allowing for up to a 16x16 keypad. The row (_r) and column (_c) are
+ * interchangable depending on a keypad drivers usage.
+ */
+#define MATRIX_KEY(_r, _c, _v) (((_r) 28) | ((_c) 24) | (_v))
+
+/*
* Relative axes
*/
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Re: [REVIEW PATCH 11/14] OMAP34XXCAM: Add driver
Hello.
This could be something trivial.
On Tue, Jan 13, 2009 at 11:03 AM, Aguirre Rodriguez, Sergio Alberto
saagui...@ti.com wrote:
+/**
+ * struct omap34xxcam_hw_config - struct for vidioc_int_g_priv ioctl
+ * @xclk: OMAP34XXCAM_XCLK_A or OMAP34XXCAM_XCLK_B
+ * @sensor_isp: Is sensor smart/SOC or raw
+ * @s_pix_sparm: Access function to set pix and sparm.
+ * Pix will override sparm
+ */
+struct omap34xxcam_hw_config {
+ int dev_index; /* Index in omap34xxcam_sensors */
I found omap34xxcam_sensors in your comment, but it couldn't found anywhere.
Let me guess that it means omap34xxcam_videodev. Am I right?
Cheers.
Regards,
Nate
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Re: [PATCH B 06/10] OMAP3 pwrdm: add CORE SAR handling (for USBTLL module)
Hello Russell, On Sat, 31 Jan 2009, Russell King - ARM Linux wrote: On Thu, Jan 29, 2009 at 02:15:44AM -0700, Paul Walmsley wrote: Hi Richard, On Thu, 29 Jan 2009, Paul Walmsley wrote: TLLSAR is not functional till ES3.1 (and beyound). Is it possible to flag it this way? Yes, it's easy in this case. Thanks for the note. I will send along an updated patch for this. N.B. - fixxing this required a separate change to the omap_chip flag system, so I'll send the two necessary patches to the linux-omap mailing list for further testing. I'll hold off on this patch then. The patches that obsolete patch B 06 have lasted a week on linux-o...@vger without any comment, so am passing them along in subsequent E-mails. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] OMAP3: update ES level flags to discriminate between post-ES2 revisions
Some OMAP3 chip behaviors change in ES levels after ES2. Modify the
existing omap_chip flags to add options for ES3.0 and ES3.1.
Add a new macro, CHIP_GE_OMAP3430ES2, to cover ES levels from ES2
onwards - a common pattern for OMAP3 features. Update all current
users of the omap_chip macros to use this new macro.
Also add CHIP_GE_OMAP3430ES3_1 to cover the USBTLL SAR errata case
(described and fixed in the following patch)
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/clockdomains.h |6 +++---
arch/arm/mach-omap2/id.c |7 ++-
arch/arm/mach-omap2/powerdomains34xx.h |8
arch/arm/plat-omap/include/mach/cpu.h | 26 --
4 files changed, 33 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomains.h
b/arch/arm/mach-omap2/clockdomains.h
index b29035e..81b9b2b 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -185,7 +185,7 @@ static struct clockdomain sgx_clkdm = {
.pwrdm = { .name = sgx_pwrdm },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};
/*
@@ -240,7 +240,7 @@ static struct clockdomain usbhost_clkdm = {
.pwrdm = { .name = usbhost_pwrdm },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};
static struct clockdomain per_clkdm = {
@@ -290,7 +290,7 @@ static struct clockdomain dpll4_clkdm = {
static struct clockdomain dpll5_clkdm = {
.name = dpll5_clkdm,
.pwrdm = { .name = dpll5_pwrdm },
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};
#endif /* CONFIG_ARCH_OMAP34XX */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index b52a02f..34b5914 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -217,8 +217,13 @@ void __init omap2_check_revision(void)
omap_chip.oc = CHIP_IS_OMAP3430;
if (omap_rev() == OMAP3430_REV_ES1_0)
omap_chip.oc |= CHIP_IS_OMAP3430ES1;
- else if (omap_rev() OMAP3430_REV_ES1_0)
+ else if (omap_rev() = OMAP3430_REV_ES2_0
+omap_rev() = OMAP3430_REV_ES2_1)
omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+ else if (omap_rev() == OMAP3430_REV_ES3_0)
+ omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
+ else if (omap_rev() == OMAP3430_REV_ES3_1)
+ omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
} else {
pr_err(Uninitialized omap_chip, please fix!\n);
}
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h
b/arch/arm/mach-omap2/powerdomains34xx.h
index edfad42..6b9d126 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -221,7 +221,7 @@ static struct powerdomain core_34xx_es1_pwrdm = {
static struct powerdomain core_34xx_es2_pwrdm = {
.name = core_pwrdm,
.prcm_offs= CORE_MOD,
- .omap_chip= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+ .omap_chip= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
.pwrsts = PWRSTS_OFF_RET_ON,
.dep_bit = OMAP3430_EN_CORE_SHIFT,
.flags= PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
@@ -263,7 +263,7 @@ static struct powerdomain dss_pwrdm = {
static struct powerdomain sgx_pwrdm = {
.name = sgx_pwrdm,
.prcm_offs= OMAP3430ES2_SGX_MOD,
- .omap_chip= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+ .omap_chip= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
.wkdep_srcs = gfx_sgx_wkdeps,
.sleepdep_srcs= cam_gfx_sleepdeps,
/* XXX This is accurate for 3430 SGX, but what about GFX? */
@@ -331,7 +331,7 @@ static struct powerdomain neon_pwrdm = {
static struct powerdomain usbhost_pwrdm = {
.name = usbhost_pwrdm,
.prcm_offs= OMAP3430ES2_USBHOST_MOD,
- .omap_chip= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+ .omap_chip= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
.wkdep_srcs = per_usbhost_wkdeps,
.sleepdep_srcs= dss_per_usbhost_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
@@ -373,7 +373,7 @@ static struct powerdomain dpll4_pwrdm = {
static struct powerdomain dpll5_pwrdm = {
.name = dpll5_pwrdm,
.prcm_offs = PLL_MOD,
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+ .omap_chip =
[PATCH 3/3] OMAP3 powerdomains: make USBTLL SAR only available on ES3.1 and beyond
Richard Woodruff writes that chip errata prevent USBTLL SAR from working
on OMAP3 ES levels before ES3.1:
http://marc.info/?l=linux-arm-kernelm=123319614808833w=2
Update the OMAP3 powerdomain structures appropriately.
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: Richard Woodruff r-woodru...@ti.com
---
arch/arm/mach-omap2/powerdomains.h |4 ++--
arch/arm/mach-omap2/powerdomains34xx.h | 10 ++
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomains.h
b/arch/arm/mach-omap2/powerdomains.h
index 51623e2..691470e 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -171,8 +171,8 @@ static struct powerdomain *powerdomains_omap[] __initdata =
{
iva2_pwrdm,
mpu_34xx_pwrdm,
neon_pwrdm,
- core_34xx_es1_pwrdm,
- core_34xx_es2_pwrdm,
+ core_34xx_pre_es3_1_pwrdm,
+ core_34xx_es3_1_pwrdm,
cam_pwrdm,
dss_pwrdm,
per_pwrdm,
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h
b/arch/arm/mach-omap2/powerdomains34xx.h
index 6b9d126..4dcf94b 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -200,10 +200,12 @@ static struct powerdomain mpu_34xx_pwrdm = {
};
/* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_es1_pwrdm = {
+static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
.name = core_pwrdm,
.prcm_offs= CORE_MOD,
- .omap_chip= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
+ .omap_chip= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
+ CHIP_IS_OMAP3430ES2 |
+ CHIP_IS_OMAP3430ES3_0),
.pwrsts = PWRSTS_OFF_RET_ON,
.dep_bit = OMAP3430_EN_CORE_SHIFT,
.banks= 2,
@@ -218,10 +220,10 @@ static struct powerdomain core_34xx_es1_pwrdm = {
};
/* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_es2_pwrdm = {
+static struct powerdomain core_34xx_es3_1_pwrdm = {
.name = core_pwrdm,
.prcm_offs= CORE_MOD,
- .omap_chip= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
+ .omap_chip= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
.pwrsts = PWRSTS_OFF_RET_ON,
.dep_bit = OMAP3430_EN_CORE_SHIFT,
.flags= PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
--
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