Re: [PATCH 0/7 v6] OMAP3: clean up ASM sleep code
Hi Nishant, On Sat, Dec 18, 2010 at 11:56 PM, Nishanth Menon n...@ti.com wrote: jean.pi...@newoldbits.com had written, on 12/18/2010 09:44 AM, the following: Applies on top of Nishant's latest idle path errata fixes step 2, cf. http://marc.info/?l=linux-omapm=129139584919242w=2 Jean Pihet (7): OMAP3: remove unused code from the ASM sleep code OMAP2+: use global values for the SRAM PA addresses OMAP3: remove hardcoded values from the ASM sleep code OMAP3: re-organize the ASM sleep code OMAP3: rework of the ASM sleep code execution paths OMAP3: add comments for low power code errata OMAP3: ASM sleep code format rework just FYI - tested the series v6 as well with: SDP3430 and SDP3630 with script: http://elinux.org/OMAP_Power_Management#Quick_verification_of_suspend-idle_functionality Tested against v4 of my series. I have ensured that your series still applies cleanly on top of my new series. Thanks for that! Let me check and ack your latest v4 patches. -- Regards, Nishanth Menon Regards, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/7] OMAP: idle path errata fixes
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon n...@ti.com wrote: Hi, as discussed in [1], here is step 2 - idle path errata fixes. this is the next rev incorporating comments from V2 post of this series. Tested: this series: SDP3430 SDP3630 this series + ASM cleanup series[2] SDP3430 SDP3630 Test Script: http://elinux.org/OMAP_Power_Management#Quick_verification_of_suspend-idle_functionality This series + ASM cleanup series[2]: Tested OK on Beagleboard with full RET and OFF modes, using cpuidle. Tested-by: Jean Pihet j-pi...@ti.com V3: http://marc.info/?t=129140247800030r=1w=2 V2: http://marc.info/?l=linux-omapm=129106200408109w=2 Major change in V3: Erratas are now handled per silicon - it is much cleaner :) no more redundant cpu_is_omap34xx check anymore errata configure is __init as it should be Eduardo Valentin (1): OMAP3630: PM: Erratum i583: disable coreoff if ES1.2 Nishanth Menon (3): omap3: pm: introduce errata handling OMAP3630: PM: Erratum i608: disable RTA OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode Peter 'p2' De Schrijver (2): OMAP3: PM: Erratum i581 support: dll kick strategy OMAP3630: PM: Disable L2 cache while invalidating L2 cache Richard Woodruff (1): OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all arch/arm/mach-omap2/control.c | 13 +++- arch/arm/mach-omap2/control.h | 7 +- arch/arm/mach-omap2/cpuidle34xx.c | 29 -- arch/arm/mach-omap2/pm.h | 15 +++- arch/arm/mach-omap2/pm34xx.c | 46 +- arch/arm/mach-omap2/sleep34xx.S | 187 +++-- 6 files changed, 211 insertions(+), 86 deletions(-) bloat-o-meter report Vs 2.6.37-rc6 add/remove: 2/0 grow/shrink: 7/0 up/down: 297/0 (297) function old new delta omap3_pm_off_mode_enable 80 160 +80 omap3_pm_init 1792 1872 +80 omap3630_ctrl_disable_rta - 44 +44 omap3_save_scratchpad_contents 732 760 +28 static.__func__ 13783 13808 +25 vermagic 45 60 +15 linux_banner 132 147 +15 prcm_interrupt_handler 268 276 +8 pm34xx_errata - 2 +2 [1] http://marc.info/?l=linux-omapm=129045338806957w=2 [2] http://marc.info/?l=linux-omapm=129268746417556w=2 Cc: Charulatha Varadarajan ch...@ti.com Cc: Jean Pihet jean.pi...@newoldbits.com Cc: Kevin Hilman khil...@deeprootsystems.com Cc: Santosh Shilimkar santosh.shilim...@ti.com Cc: Tao Hu tgh...@motorola.com Cc: Tony Lindgren t...@atomide.com Cc: Vishwanath Sripathy vishwanath...@ti.com --- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 3/7] omap3: pm: introduce errata handling
Hi Nishant,
Here a few minor remarks about typos:
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon n...@ti.com wrote:
Introduce errata handling for omap3. This patch introduces
Use caps for OMAP3
errata variable and and stub for initialization which will be
and and - and
filled up by followon patches.
followon - follow-on?
Signed-off-by: Nishanth Menon n...@ti.com
---
Splitting the errata introduction out into it's own separate patch
arch/arm/mach-omap2/pm.h | 7 +++
arch/arm/mach-omap2/pm34xx.c | 9 +
2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0d75bfd..0348fd7 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -85,4 +85,11 @@ extern unsigned int save_secure_ram_context_sz;
extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
+#if defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3)
+extern u16 pm34xx_errata;
+#define IS_PM34XX_ERRATUM(id) (pm34xx_errata (id))
+#else
+#define IS_PM34XX_ERRATUM(id) 0
+#endif /* defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3) */
+
#endif
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 648b8c5..5702f41 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -68,6 +68,9 @@ static inline bool is_suspending(void)
#define OMAP343X_TABLE_VALUE_OFFSET 0xc0
#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
+/* pm34xx errata defined in pm.h */
+u16 pm34xx_errata;
+
struct power_state {
struct powerdomain *pwrdm;
u32 next_state;
@@ -1002,6 +1005,10 @@ void omap_push_sram_idle(void)
save_secure_ram_context_sz);
}
+static void __init pm_errata_configure(void)
+{
+}
+
static int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
@@ -1011,6 +1018,8 @@ static int __init omap3_pm_init(void)
if (!cpu_is_omap34xx())
return -ENODEV;
+ pm_errata_configure();
+
printk(KERN_ERR Power Management for TI OMAP3.\n);
/* XXX prcm_setup_regs needs to be before enabling hw
--
1.6.3.3
Jean
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Re: [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
On Mon, Dec 20, 2010 at 7:43 AM, Santosh Shilimkar santosh.shilim...@ti.com wrote: -Original Message- From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap- ow...@vger.kernel.org] On Behalf Of Nishanth Menon Sent: Sunday, December 19, 2010 4:24 AM To: linux-omap; linux-arm Cc: Jean Pihet; Kevin; Tony Subject: [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all From: Richard Woodruff r-woodru...@ti.com Analysis in TI kernel with ETM showed that using cache mapped flush in kernel instead of SO mapped flush cost drops by 65% (3.39mS down to 1.17mS) for clean_l2 which is used during sleep sequences. Overall: - speed up - unfortunately there isn't a good alternative flush method today - code reduction and less maintenance and potential bug in unmaintained code This also fixes the bug with the clean_l2 function usage. Reported-by: Tony Lindgren t...@atomide.com Cc: Kevin Hilman khil...@deeprootsystems.com Cc: Tony Lindgren t...@atomide.com [...@ti.com: ported rkw's proposal to 2.6.37-rc2] Signed-off-by: Nishanth Menon n...@ti.com Signed-off-by: Richard Woodruff r-woodru...@ti.com --- (no change in this series, posted for completeness) v2: https://patchwork.kernel.org/patch/365222/ v1: http://marc.info/?l=linux-omapm=129013171325210w=2 arch/arm/mach-omap2/sleep34xx.S | 79 ++ 1 files changed, 13 insertions(+), 66 deletions(-) diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach- omap2/sleep34xx.S index 2fb205a..2c20fcf 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -520,72 +520,17 @@ clean_caches: cmp r9, #1 /* Check whether L2 inval is required or not*/ bne skip_l2_inval clean_l2: - /* read clidr */ - mrc p15, 1, r0, c0, c0, 1 - /* extract loc from clidr */ - ands r3, r0, #0x700 - /* left align loc bit field */ - mov r3, r3, lsr #23 - /* if loc is 0, then no need to clean */ - beq finished - /* start clean at cache level 0 */ - mov r10, #0 -loop1: - /* work out 3x current cache level */ - add r2, r10, r10, lsr #1 - /* extract cache type bits from clidr*/ - mov r1, r0, lsr r2 - /* mask of the bits for current cache only */ - and r1, r1, #7 - /* see what cache we have at this level */ - cmp r1, #2 - /* skip if no cache, or just i-cache */ - blt skip - /* select current cache level in cssr */ - mcr p15, 2, r10, c0, c0, 0 - /* isb to sych the new cssrcsidr */ - isb - /* read the new csidr */ - mrc p15, 1, r1, c0, c0, 0 - /* extract the length of the cache lines */ - and r2, r1, #7 - /* add 4 (line length offset) */ - add r2, r2, #4 - ldr r4, assoc_mask - /* find maximum number on the way size */ - ands r4, r4, r1, lsr #3 - /* find bit position of way size increment */ - clz r5, r4 - ldr r7, numset_mask - /* extract max number of the index size*/ - ands r7, r7, r1, lsr #13 -loop2: - mov r9, r4 - /* create working copy of max way size*/ -loop3: - /* factor way and cache number into r11 */ - orr r11, r10, r9, lsl r5 - /* factor index number into r11 */ - orr r11, r11, r7, lsl r2 - /*clean invalidate by set/way */ - mcr p15, 0, r11, c7, c10, 2 - /* decrement the way*/ - subs r9, r9, #1 - bge loop3 - /*decrement the index */ - subs r7, r7, #1 - bge loop2 -skip: - add r10, r10, #2 - /* increment cache number */ - cmp r3, r10 - bgt loop1 -finished: - /*swith back to cache level 0 */ - mov r10, #0 - /* select current cache level in cssr */ - mcr p15, 2, r10, c0, c0, 0 - isb + /* + * Jump out to kernel flush routine + * - reuse that code is better + * - it executes in a cached space so is faster than refetch per- block + * - should be faster and will change with kernel + * - 'might' have to copy address, load and jump to it Would be good to clarify that this is needed to maintain the 'lr' when code is executed from SRAM Agree on that. Some comments have been posted at http://marc.info/?l=linux-omapm=129016170719489w=2. + */ + ldr r1, kernel_flush + mov lr, pc + bx r1 + skip_l2_inval: /* Data memory barrier and Data sync barrier */ mov r1, #0 @@ -668,5 +613,7 @@ cache_pred_disable_mask: .word 0xE7FB control_stat: .word CONTROL_STAT +kernel_flush: + .word v7_flush_dcache_all ENTRY(omap34xx_cpu_suspend_sz) .word . - omap34xx_cpu_suspend O.w Acked-by: Santosh Shilimkar santosh.shilim...@ti.com Acked-by: Jean Pihet j-pi...@ti.com -- 1.6.3.3 -- To
Re: [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon n...@ti.com wrote: From: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com Erratum i581 impacts OMAP3 platforms. PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing the DPLL not to be locked at times. IMPORTANT: *) This is not a complete workaround implementation as recommended by the silicon erratum. this is a support logic for detecting lockups and attempting to recover where possible and is known to provide stability in multiple platforms. *) This code is mostly important for inactive and retention. The ROM code waits for the maximum dll lock time when resuming from off mode. So for off mode this code isn't really needed. This should eventually get refactored as part of cleanups to sleep34xx.S Cc: Kevin Hilman khil...@deeprootsystems.com Cc: Tony Lindgren t...@atomide.com Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com --- (no change done, posting for completeness of the series) v2: https://patchwork.kernel.org/patch/365252/ typo correction- erratum, support, added comment from Peter from the thread to commit message v1: http://marc.info/?l=linux-omapm=129013172525234w=2 arch/arm/mach-omap2/sleep34xx.S | 52 +++--- 1 files changed, 47 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 2c20fcf..3fbd1e5 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -42,6 +42,7 @@ OMAP3430_PM_PREPWSTST) #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) +#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) #define SRAM_BASE_P 0x4020 #define CONTROL_STAT 0x480022F0 #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is @@ -554,31 +555,67 @@ skip_l2_inval: /* Make sure SDRC accesses are ok */ wait_sdrc_ok: + +/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */ + ldr r4, cm_idlest_ckgen +wait_dpll3_lock: + ldr r5, [r4] + tst r5, #1 + beq wait_dpll3_lock + ldr r4, cm_idlest1_core +wait_sdrc_ready: ldr r5, [r4] - and r5, r5, #0x2 - cmp r5, #0 - bne wait_sdrc_ok + tst r5, #0x2 + bne wait_sdrc_ready + /* allow DLL powerdown upon hw idle req */ ldr r4, sdrc_power ldr r5, [r4] bic r5, r5, #0x40 str r5, [r4] -wait_dll_lock: +is_dll_in_lock_mode: + /* Is dll in lock mode? */ ldr r4, sdrc_dlla_ctrl ldr r5, [r4] tst r5, #0x4 bxne lr /* wait till dll locks */ - ldr r4, sdrc_dlla_status +wait_dll_lock_timed: + ldr r4, wait_dll_lock_counter + add r4, r4, #1 + str r4, wait_dll_lock_counter + ldr r4, sdrc_dlla_status + mov r6, #8 /* Wait 20uS for lock */ +wait_dll_lock: + subs r6, r6, #0x1 + beq kick_dll It would be good to have more comments on the code flow here: - what are wait_dll_lock_counter and kick_counter used for? - what is the timing based on? Why 20uS for the wait time? - jumping back and forth to kick_dll and wait_dll_lock_timed is confusing. ldr r5, [r4] and r5, r5, #0x4 cmp r5, #0x4 bne wait_dll_lock bx lr + /* disable/reenable DLL if not locked */ +kick_dll: + ldr r4, sdrc_dlla_ctrl + ldr r5, [r4] + mov r6, r5 + bic r6, #(13) /* disable dll */ + str r6, [r4] + dsb + orr r6, r6, #(13) /* enable dll */ + str r6, [r4] + dsb + ldr r4, kick_counter + add r4, r4, #1 + str r4, kick_counter + b wait_dll_lock_timed + cm_idlest1_core: .word CM_IDLEST1_CORE_V +cm_idlest_ckgen: + .word CM_IDLEST_CKGEN_V sdrc_dlla_status: .word SDRC_DLLA_STATUS_V sdrc_dlla_ctrl: @@ -615,5 +652,10 @@ control_stat: .word CONTROL_STAT kernel_flush: .word v7_flush_dcache_all + /* these 2 words need to be at the end !!! */ +kick_counter: + .word 0 +wait_dll_lock_counter: + .word 0 Why do they need to be at the end? Also, at the end of what do they need to be? ENTRY(omap34xx_cpu_suspend_sz) .word . - omap34xx_cpu_suspend -- 1.6.3.3 Regards, Jean -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if ES1.2
On Mon, Dec 20, 2010 at 7:51 AM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
-Original Message-
From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
ow...@vger.kernel.org] On Behalf Of Nishanth Menon
Sent: Sunday, December 19, 2010 4:24 AM
To: linux-omap; linux-arm
Cc: Jean Pihet; Kevin; Tony
Subject: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if
ES1.2
From: Eduardo Valentin eduardo.valen...@nokia.com
Limitation i583: Self_Refresh Exit issue after OFF mode
Issue:
When device is waking up from OFF mode, then SDRC state machine sends
inappropriate sequence violating JEDEC standards.
Impact:
OMAP3630 ES1.2 is impacted as follows depending on the platform:
CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable,
while
for all other sysclk frequencies, varied levels of instability
seen based on varied parameters.
CS1: impacted
This patch takes option #3 as recommended by the Silicon erratum:
Avoid core power domain transitioning to OFF mode. Power consumption
impact is expected in this case.
To do this, we route core OFF requests to RET request on the impacted
revisions of silicon.
[...@ti.com: rebased the code to 2.6.37-rc2- short circuit code changed a
bit]
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Eduardo Valentin eduardo.valen...@nokia.com
---
v4: idle state control changed a bit -we wont register or enable
the states which cannot be enabled.
v3: http://marc.info/?t=129140247800027r=1w=2
no functional change in erratum wa implementation, just registration
of
erratum is collated to a single cpu detection and version check
v2: https://patchwork.kernel.org/patch/365262/
rebased to this patch series instead of depending on hs changes
fix typo for macro definition
v1: http://marc.info/?l=linux-omapm=129013173425266w=2
arch/arm/mach-omap2/cpuidle34xx.c | 10 ++
arch/arm/mach-omap2/pm.h | 1 +
arch/arm/mach-omap2/pm34xx.c | 24 +---
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-
omap2/cpuidle34xx.c
index f80d3f6..1b32e98 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -453,6 +453,16 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID
|
CPUIDLE_FLAG_CHECK_BM;
+
+ /*
+ * Erratum i583: implementation for ES rev Es1.2 on 3630. We
cannot
+ * enable OFF mode in a stable form for previous revisions.
+ * we disable C7 state as a result.
+ */
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
+ omap3_power_states[OMAP3_STATE_C7].valid = 0;
+ cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
WARN_ONCE in IDLE also would be good.
Agree on the WARN_ONCE remarks.
Other than that:
Acked-by: Jean Pihet j-pi...@ti.com
+ }
}
struct cpuidle_driver omap3_idle_driver = {
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 92ef400..9032d09 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
#define PM_RTA_ERRATUM_i608 (1 0)
+#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 1)
#if defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 21cd36e..7faea55 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
- omap3_cpuidle_update_states(state, state);
+ /*
+ * Erratum i583: implementation for ES rev Es1.2 on 3630. We
cannot
+ * enable OFF mode in a stable form for previous revisions,
restrict
+ * instead to RET
+ */
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
+ omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
+ else
+ omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst, pwrst_list, node) {
- pwrst-next_state = state;
- omap_set_pwrdm_state(pwrst-pwrdm, state);
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)
+ pwrst-pwrdm == core_pwrdm
+ state == PWRDM_POWER_OFF) {
+ pwrst-next_state = PWRDM_POWER_RET;
+ pr_err(%s: Core OFF disabled due to errata
i583\n,
Shoud we do this in every iteration or just WARN_ONCE do ??
+ __func__);
+ } else {
+ pwrst-next_state =
Re: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
Nishant,
Here are minor remarks about comments formatting.
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon n...@ti.com wrote:
Erratum id: i608
RTA (Retention Till Access) feature is not supported and leads to device
stability issues when enabled. This impacts modules with embedded memories
on OMAP3630
Workaround is to disable RTA on boot and coming out of core off.
For disabling rta coming out of off mode, we do this by overriding the
Use caps for RTA
restore pointer for 3630 to allow us restore handler as the first point of
This is not clear, maybe 'to allow us to restore handler' needs to be removed.
entry before caches are touched and is common for GP and HS devices.
to disable earlier than this could be possible by modifying the ppa for HS
Same here, it looks like the original sentence has been cut in pieces.
Use caps for PPA.
devices, but not for GP devices.
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: Tony Lindgren t...@atomide.com
[ambr...@ti.com: co-developer]
Signed-off-by: Ambresh K ambr...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Otherwise:
Acked-by: Jean Pihet j-pi...@ti.com
---
v4:
control register handling moved to control.c
errata handling framework introduction split out
into a separate patch
v3: http://marc.info/?t=129140247800026r=1w=2
additional comment to explain Ambresh's contrib
removed the redundant check for cpu_is34xx - it is already
done by pm_init
pm_errata_configure is __init
v2: https://patchwork.kernel.org/patch/365242/
fixed missing b restore for 3430 es3.1 code.
introduced erratum handling logic here splitting it out of uart errata
typo fixes for erratum
v1: http://marc.info/?l=linux-omapm=129013172825240w=2
arch/arm/mach-omap2/control.c | 13 -
arch/arm/mach-omap2/control.h | 7 ++-
arch/arm/mach-omap2/pm.h | 2 ++
arch/arm/mach-omap2/pm34xx.c | 10 ++
arch/arm/mach-omap2/sleep34xx.S | 26 ++
5 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 1fa3294..27ed558 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -241,7 +241,10 @@ void omap3_save_scratchpad_contents(void)
/* Populate the Scratchpad contents */
scratchpad_contents.boot_config_ptr = 0x0;
- if (omap_rev() != OMAP3430_REV_ES3_0
+ if (cpu_is_omap3630())
+ scratchpad_contents.public_restore_ptr =
+ virt_to_phys(get_omap3630_restore_pointer());
+ else if (omap_rev() != OMAP3430_REV_ES3_0
omap_rev() != OMAP3430_REV_ES3_1)
scratchpad_contents.public_restore_ptr =
virt_to_phys(get_restore_pointer());
@@ -474,4 +477,12 @@ void omap3_control_restore_context(void)
omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
return;
}
+
+void omap3630_ctrl_disable_rta(void)
+{
+ if (!cpu_is_omap3630())
+ return;
+ omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
+}
+
#endif /* CONFIG_ARCH_OMAP3 CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b6c6b7c..ec98dd7 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -204,6 +204,10 @@
#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
+/* 36xx-only RTA - Retention till Accesss control registers and bits */
+#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
+#define OMAP36XX_RTA_DISABLE 0x0
+
/* 34xx D2D idle-related pins, handled by PM core */
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
@@ -347,10 +351,11 @@ extern void omap3_save_scratchpad_contents(void);
extern void omap3_clear_scratchpad_contents(void);
extern u32 *get_restore_pointer(void);
extern u32 *get_es3_restore_pointer(void);
+extern u32 *get_omap3630_restore_pointer(void);
extern u32 omap3_arm_context[128];
extern void omap3_control_save_context(void);
extern void omap3_control_restore_context(void);
-
+extern void omap3630_ctrl_disable_rta(void);
#else
#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0348fd7..8d9aa3e 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -85,6 +85,8 @@ extern unsigned int save_secure_ram_context_sz;
extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
+#define PM_RTA_ERRATUM_i608 (1 0)
+
#if defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
#define
Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon n...@ti.com wrote:
From: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com
This disables L2 cache before invalidating it and reenables it afterwards.
This is be done according to ARM documentation. Currently this is identified
as being needed on OMAP3630 as the disable/enable is done from public side
while, on OMAP3430, this is done in the secure side.
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: Tony Lindgren t...@atomide.com
[...@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on
3630]
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Eduardo Valentin eduardo.valen...@nokia.com
Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com
Acked-by: Jean Pihet j-pi...@ti.com
---
v4: rebased only. no functional change
v3: http://marc.info/?l=linux-omapm=129139583519221w=2
collate all silicon specific errata under a single cpu detection code
making it elegant and more maintainable.
v2: https://patchwork.kernel.org/patch/365232/
rebased out to this series independent of HS bugfixes
v1: http://marc.info/?l=linux-omapm=129013171125204w=2
arch/arm/mach-omap2/pm.h | 2 ++
arch/arm/mach-omap2/pm34xx.c | 5 -
arch/arm/mach-omap2/sleep34xx.S | 30 ++
3 files changed, 36 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 8d9aa3e..5e0bee9 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -90,8 +90,10 @@ extern unsigned int omap34xx_cpu_suspend_sz;
#if defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
#define IS_PM34XX_ERRATUM(id) (pm34xx_errata (id))
+extern void enable_omap3630_toggle_l2_on_restore(void);
#else
#define IS_PM34XX_ERRATUM(id) 0
+static inline void enable_omap3630_toggle_l2_on_restore(void) { }
#endif /* defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3) */
#endif
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index b32a2ed..4ba7a06 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -1007,8 +1007,11 @@ void omap_push_sram_idle(void)
static void __init pm_errata_configure(void)
{
- if (cpu_is_omap3630())
+ if (cpu_is_omap3630()) {
pm34xx_errata |= PM_RTA_ERRATUM_i608;
+ /* Enable the l2 cache toggling in sleep logic */
+ enable_omap3630_toggle_l2_on_restore();
+ }
}
static int __init omap3_pm_init(void)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index cc3507b..d2eda01 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -111,6 +111,19 @@ ENTRY(get_omap3630_restore_pointer_sz)
.word . - get_omap3630_restore_pointer
.text
+/*
+ * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
+ * This function sets up a fflag that will allow for this toggling to take
+ * place on 3630. Hopefully some version in the future maynot need this
+ */
+ENTRY(enable_omap3630_toggle_l2_on_restore)
+ stmfd sp!, {lr} @ save registers on stack
+ /* Setup so that we will disable and enable l2 */
+ mov r1, #0x1
+ str r1, l2dis_3630
+ ldmfd sp!, {pc} @ restore regs and return
+
+ .text
/* Function call to get the restore pointer for for ES3 to resume from OFF */
ENTRY(get_es3_restore_pointer)
stmfd sp!, {lr} @ save registers on stack
@@ -283,6 +296,14 @@ restore:
moveq r9, #0x3 @ MPU OFF = L1 and L2 lost
movne r9, #0x1 @ Only L1 and L2 lost = avoid L2 invalidation
bne logic_l1_restore
+
+ ldr r0, l2dis_3630
+ cmp r0, #0x1 @ should we disable L2 on 3630?
+ bne skipl2dis
+ mrc p15, 0, r0, c1, c0, 1
+ bic r0, r0, #2 @ disable L2 cache
+ mcr p15, 0, r0, c1, c0, 1
+skipl2dis:
ldr r0, control_stat
ldr r1, [r0]
and r1, #0x700
@@ -343,6 +364,13 @@ smi: .word 0xE1600070 @ Call SMI monitor
(smieq)
mov r12, #0x2
.word 0xE1600070 @ Call SMI monitor (smieq)
logic_l1_restore:
+ ldr r1, l2dis_3630
+ cmp r1, #0x1 @ Do we need to re-enable L2 on 3630?
+ bne skipl2reen
+ mrc p15, 0, r1, c1, c0, 1
+ orr r1, r1, #2 @ re-enable L2 cache
+ mcr p15, 0, r1, c1, c0, 1
+skipl2reen:
mov r1, #0
/* Invalidate all instruction caches to PoU
* and flush branch target cache */
@@ -678,6 +706,8 @@ control_mem_rta:
.word CONTROL_MEM_RTA_CTRL
kernel_flush:
.word v7_flush_dcache_all
+l2dis_3630:
+ .word 0
/* these 2 words need to be at the end !!! */
kick_counter:
Re: [PATCH v4 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon n...@ti.com wrote:
Currently omap3_cpuidle_update_states makes whole sale decision
on which C states to update based on enable_off_mode variable
Instead, achieve the same functionality by independently providing
mpu and core deepest states the system is allowed to achieve and
update the idle states accordingly.
Signed-off-by: Nishanth Menon n...@ti.com
Acked-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/cpuidle34xx.c | 19 ++-
arch/arm/mach-omap2/pm.h | 3 ++-
arch/arm/mach-omap2/pm34xx.c | 2 +-
3 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index 0d50b45..f80d3f6 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -293,25 +293,26 @@ select_state:
DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
/**
- * omap3_cpuidle_update_states - Update the cpuidle states.
+ * omap3_cpuidle_update_states() - Update the cpuidle states
+ * @mpu_deepest_state: Enable states upto and including this for mpu domain
+ * @core_deepest_state: Enable states upto and including this for
core domain
*
- * Currently, this function toggles the validity of idle states based upon
- * the flag 'enable_off_mode'. When the flag is set all states are valid.
- * Else, states leading to OFF state set to be invalid.
+ * This goes through the list of states available and enables and disables
the
+ * validity of C states based on deepest state that can be achieved for the
+ * variable domain
*/
-void omap3_cpuidle_update_states(void)
+void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32
core_deepest_state)
{
int i;
for (i = OMAP3_STATE_C1; i OMAP3_MAX_STATES; i++) {
struct omap3_processor_cx *cx = omap3_power_states[i];
- if (enable_off_mode) {
+ if ((cx-mpu_state = mpu_deepest_state)
+ (cx-core_state = core_deepest_state)) {
cx-valid = 1;
} else {
- if ((cx-mpu_state == PWRDM_POWER_OFF) ||
- (cx-core_state == PWRDM_POWER_OFF))
- cx-valid = 0;
+ cx-valid = 0;
}
}
}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 5e0bee9..92ef400 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -58,7 +58,8 @@ extern u32 sleep_while_idle;
#endif
#if defined(CONFIG_CPU_IDLE)
-extern void omap3_cpuidle_update_states(void);
+extern void omap3_cpuidle_update_states(u32 core_deepest_state,
+ u32 core_deepest_state);
#endif
#if defined(CONFIG_PM_DEBUG) defined(CONFIG_DEBUG_FS)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 4ba7a06..21cd36e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -928,7 +928,7 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
- omap3_cpuidle_update_states();
+ omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst, pwrst_list, node) {
--
1.6.3.3
--
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Re: [GIT] pull request: DMA hwmod changes
Hi Manju, I still have 2 comments on the patch #6: OMAP4: hwmod data: add system DMA. I'll sent them in a couple of minutes. Regards, Benoit On 12/19/2010 4:59 AM, G, Manjunath Kondaiah wrote: Hi Tony, Please pull the following dma hwmod changes into linux omap master branch. This pull request includes v2[http://thread.gmane.org/gmane.linux.ports.arm.omap/48695] + paul's sidle mode comments incorporated + acks for patch 3 and 4. The final series is boot tested on: OMAP3530(Beagle) N800 SDP2430 OMAP4430SDP(ES2.1) Full testing is done once again for SDP2430 and logs can be accessed at: http://pastebin.com/aJZGjdar The following changes since commit 205e4d6e8d892176d791b77a974efe7f561ca4c3: Merge branch 'for-next' (2010-12-17 19:32:47 -0800) are available in the git repository at: git://dev.omapzoom.org/pub/scm/manju/kernel-omap3-dev.git dma_hwmod Benoit Cousson (1): OMAP4: hwmod data: add system DMA G, Manjunath Kondaiah (8): OMAP: DMA: Replace read/write macros with functions OMAP: DMA: Introduce errata handling feature OMAP2420: hwmod data: add system DMA OMAP2430: hwmod data: add system DMA OMAP3: hwmod data: add system DMA OMAP1: DMA: Implement in platform device model OMAP2+: DMA: hwmod: Device registration OMAP: DMA: Convert DMA library into platform driver arch/arm/mach-omap1/Makefile |2 +- arch/arm/mach-omap1/dma.c | 390 arch/arm/mach-omap2/Makefile |2 +- arch/arm/mach-omap2/dma.c | 297 arch/arm/mach-omap2/omap_hwmod_2420_data.c | 86 arch/arm/mach-omap2/omap_hwmod_2430_data.c | 86 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 97 arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 101 arch/arm/plat-omap/dma.c | 697 arch/arm/plat-omap/include/plat/dma.h | 232 -- 10 files changed, 1450 insertions(+), 540 deletions(-) create mode 100644 arch/arm/mach-omap1/dma.c create mode 100644 arch/arm/mach-omap2/dma.c -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 0/12] dmtimer adaptation to platform_driver
dmtimer adaptation to platform_driver.
This patch series is adaptation of dmtimer code to platform driver
using omap_device and omap_hwmod abstraction.
Tested on following platforms:
OMAP1710 H3 SDP
OMAP2420 N800
OMAP2430 SDP
OMAP3430 SDP
OMAP3630 SDP
OMAP4430 SDP
Baseline:
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
v7:
(1) In omap1_dm_timer_set_src(), the computation of shift value to respective
dmtimer clock source was corrected:
From:
int n = (pdev-id) 1;
To:
int n = (pdev-id - 1) 1;
This change is needed because dmtimer is indexed from 1 now instead of 0.
(2) In omap1_dm_timer_init(void) memory resource end address chnaged:
From:
res[0].end = base + 0xff;
To:
res[0].end = base + 0x46;
This was causing request_mem_region() failure in driver probe().
(3) In the export APIs there are some calls which are not applicable to OMAP1.
They have been made conditional now. They include following calls:
timer-fclk = clk_get(timer-pdev-dev, fck);
omap_dm_timer_enable()
omap_dm_timer_disable()
(4) Remove usage of cpu_is_omap16xx() and instead a flag has been added in
struct dmtimer_platform_data {
...
u32 is_omap16xx:1;
}
This flag is set to 1 in mach-omap1/dmtimer.c and set to 0 in
mach-omap2/dmtimer.c
This flag is used in plat-omap/dmtimer.c wherever it needs to distiguish
omap16xx.
(5) Remove #include plat/omap_device.h from mach-omap1/dmtimer.c
(6) Instead of using macros like INT_24XX_GPTIMERx, use the numbers
directly in OMAP2420, OMAP2430 and OMAP3xxx hwmod database.
(7) pm_runtime_get_sync() and pm_runtime_put_sync() return value check modified
from positive to negative value:
if (pm_runtime_get_sync(...) 0) {
...
}
TODO:
(1) OFF Mode support
(2) Upgrade timeout implementation in low-level read/write access to return
error condition to EXPORT APIs. This is re-frained in the present implementation
because that would involve change to EXPORTED APIs. Besides, there is no clear
design as yet which is agreed upon by the community.
v6:
(1) Removed reset functions to mach-omap1/dmtimer.c.
Access to reset function from plat-omap/dmtimer.c is provided by means
of function pointer.
(2) Remove multiple calls to omap_device_build() for registering timer devices
during early and regular initialization. Regular device registration is now done
by reading data from temporary list. This list is populated during early init
where timer data is read from hwmod database and corresponding memory allocated.
(3) kfree(pdata) under error condition since platform_device_unregister does
not free its pdata.
(4) Removed extra header inclusion in mach-omap2 and plat-omap
NOTE: omap_dm_timer.id field could not be removed because during regular boot
there is no mechanism to match the current pdev with corresponding entry in the
timer list which was partially initialized during early boot.
v4:
(1) clock aliases are renamed as 32k_ck, sys_ck and alt_ck
(2) incorporate missing clk_put() for corresponding clk_get()
(3) modified clk_get()/clk_put() to be called once once in platform driver.
(4) consistent header for new files
(5) check return value of omap_hwmod_for_each_by_class() in device init
routines.
(6) remove is_abe_timer field in dmtimer_platform_data structure. this is
no longer needed with new input clock source aliasing.
(7) proper splitting of patch series
(8) remove register map from hwmod database.
(9) remove clock source strings array from hwmod database and associated
structure declaration from plat/dmtimer.h. this is no longer needed.
(10) remove dev_attr from hwmod database. this is no longer needed.
(11) use register offsets to identify OMAP 4 registers instead of register map.
(12) remove clock source name strings from hwmod database.
(13) introduce new mechanism for getting struct clk associated with clock source
names. this is achieved by adding clock alisases for all supported clock
sources.
(14) remove clock setup functions in mach-omap2 for populating struct clk
associated with all input clock sources because this is no longer needed with
above implementation.
(15) device names changed from dmtimer to omap-timer
(16) device index starts from 1 instead of 0
(17) remove .init_name from hwmod database. this is not needed.
(18) introduce separate functions for reading/writing interrupt registers
instead of
doing all operations within a single function.
v3:
(1) multi-line comment error correction
(2) provision to allow any of the available dmtimers as early timers
instead of restricting them to millisecond timers only.
(3) in 'struct omap_dmtimer{}' is_initialized flag is redundant and
so must be removed. if the element is found in the list it is already
initialized.
(4) remove 'found' flag in omap_dm_timer_request() and
omap_dm_timer_request_specific() functions.
this is not needed with alternate implementation.
(5) use .init_name to initialize device names so that it can be identified
during early boot as well. This is to avoid duplicate functions for clock
[PATCH v7 8/12] OMAP: dmtimer: platform driver
From: Thara Gopinath th...@ti.com
Add dmtimer platform driver functions which include:
(1) platform driver initialization
(2) driver probe function
(3) driver remove function
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Reviewed-by: Varadarajan, Charulatha ch...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 168 -
arch/arm/plat-omap/include/plat/dmtimer.h |4 +
2 files changed, 171 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 1bfaf09..effdc6f 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -43,6 +43,8 @@
#include linux/delay.h
#include linux/io.h
#include linux/module.h
+#include linux/slab.h
+#include linux/err.h
#include mach/hardware.h
#include plat/dmtimer.h
#include mach/irqs.h
@@ -257,7 +259,8 @@ static struct omap_dm_timer *dm_timers;
static const char **dm_source_names;
static struct clk **dm_source_clocks;
-static spinlock_t dm_timer_lock;
+static LIST_HEAD(omap_timer_list);
+static DEFINE_SPINLOCK(dm_timer_lock);
/*
* Reads timer registers in posted and non-posted mode. The posted mode bit
@@ -689,6 +692,169 @@ int omap_dm_timers_active(void)
}
EXPORT_SYMBOL_GPL(omap_dm_timers_active);
+/**
+ * omap_dm_timer_probe - probe function called for every registered device
+ * @pdev: pointer to current timer platform device
+ *
+ * Called by driver framework at the end of device registration for all
+ * timer devices.
+ */
+static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
+{
+ int ret;
+ unsigned long flags;
+ struct omap_dm_timer *timer;
+ struct resource *mem, *irq, *ioarea;
+ struct dmtimer_platform_data *pdata = pdev-dev.platform_data;
+
+ dev_dbg(pdev-dev, %s: +\n, __func__);
+
+ if (!pdata) {
+ dev_err(pdev-dev, %s: no platform data\n, __func__);
+ return -ENODEV;
+ }
+
+ spin_lock_irqsave(dm_timer_lock, flags);
+ list_for_each_entry(timer, omap_timer_list, node)
+ if (!pdata-is_early_init timer-id == pdev-id) {
+ timer-pdev = pdev;
+ spin_unlock_irqrestore(dm_timer_lock, flags);
+ dev_dbg(pdev-dev, Regular Probed\n);
+ return 0;
+ }
+ spin_unlock_irqrestore(dm_timer_lock, flags);
+
+ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (unlikely(!irq)) {
+ dev_err(pdev-dev, %s: no IRQ resource\n, __func__);
+ ret = -ENODEV;
+ goto err_free_pdev;
+ }
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (unlikely(!mem)) {
+ dev_err(pdev-dev, %s: no memory resource\n, __func__);
+ ret = -ENODEV;
+ goto err_free_pdev;
+ }
+
+ ioarea = request_mem_region(mem-start, resource_size(mem),
+ pdev-name);
+ if (!ioarea) {
+ dev_err(pdev-dev, %s: region already claimed\n, __func__);
+ ret = -EBUSY;
+ goto err_free_pdev;
+ }
+
+ timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
+ if (!timer) {
+ dev_err(pdev-dev, %s: no memory for omap_dm_timer\n,
+ __func__);
+ ret = -ENOMEM;
+ goto err_release_ioregion;
+ }
+
+ timer-io_base = ioremap(mem-start, resource_size(mem));
+ if (!timer-io_base) {
+ dev_err(pdev-dev, %s: ioremap failed\n, __func__);
+ ret = -ENOMEM;
+ goto err_free_mem;
+ }
+
+ /*
+* Following func pointers are required by OMAP1's reset code
+* in mach-omap1/dmtimer.c to access to low level read/write.
+*/
+ if (pdata-is_omap16xx) {
+ pdata-dm_timer_read_reg = omap_dm_timer_read_reg;
+ pdata-dm_timer_write_reg = omap_dm_timer_write_reg;
+ pdata-is_early_init = 0;
+ }
+
+ timer-id = pdev-id;
+ timer-irq = irq-start;
+ timer-pdev = pdev;
+ timer-reserved = 0;
+
+ /* add the timer element to the list */
+ spin_lock_irqsave(dm_timer_lock, flags);
+ list_add_tail(timer-node, omap_timer_list);
+ spin_unlock_irqrestore(dm_timer_lock, flags);
+
+ dev_dbg(pdev-dev, Early Probed\n);
+
+ return 0;
+
+err_free_mem:
+ kfree(timer);
+
+err_release_ioregion:
+ release_mem_region(mem-start, resource_size(mem));
+
+err_free_pdev:
+ kfree(pdata);
+ platform_device_unregister(pdev);
+
+ return ret;
+}
+
+/**
+ * omap_dm_timer_remove - cleanup a registered timer device
+ * @pdev: pointer to current timer platform device
+ *
+ * Called by driver framework whenever a timer device is unregistered.
+
[PATCH v7 11/12] OMAP: dmtimer: add timeout to low-level routines
The low-level read and write access routines wait on
write-pending register in posted mode to make sure that
previous write is complete on respective registers.
This waiting is done in an infinite while loop. Now it
is being modified to use timeout instead.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Reviewed-by: Varadarajan, Charulatha ch...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 32
1 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 8b1a5a4..ecaee41 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -41,6 +41,7 @@
#include linux/slab.h
#include linux/pm_runtime.h
#include linux/err.h
+#include plat/common.h
#include plat/dmtimer.h
/* register offsets */
@@ -152,6 +153,7 @@
#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR WPSHIFT))
+#define MAX_WRITE_PEND_WAIT1 /* 10ms timeout delay */
static LIST_HEAD(omap_timer_list);
static DEFINE_SPINLOCK(dm_timer_lock);
@@ -168,16 +170,23 @@ static DEFINE_SPINLOCK(dm_timer_lock);
static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
{
struct dmtimer_platform_data *pdata = timer-pdev-dev.platform_data;
+ int i = 0;
if (reg = OMAP_TIMER_WAKEUP_EN_REG)
reg += pdata-func_offset;
else if (reg = OMAP_TIMER_STAT_REG)
reg += pdata-intr_offset;
- if (timer-posted)
- while (readl(timer-io_base + (OMAP_TIMER_WRITE_PEND_REG
0xff))
-(reg WPSHIFT))
- cpu_relax();
+ if (timer-posted) {
+ omap_test_timeout(!(readl(timer-io_base +
+ ((OMAP_TIMER_WRITE_PEND_REG +
+ pdata-func_offset) 0xff)) (reg WPSHIFT)),
+ MAX_WRITE_PEND_WAIT, i);
+
+ if (WARN_ON_ONCE(i == MAX_WRITE_PEND_WAIT))
+ pr_err(: read timeout\n);
+ }
+
return readl(timer-io_base + (reg 0xff));
}
@@ -195,16 +204,23 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer
*timer, u32 reg,
u32 value)
{
struct dmtimer_platform_data *pdata = timer-pdev-dev.platform_data;
+ int i = 0;
if (reg = OMAP_TIMER_WAKEUP_EN_REG)
reg += pdata-func_offset;
else if (reg = OMAP_TIMER_STAT_REG)
reg += pdata-intr_offset;
- if (timer-posted)
- while (readl(timer-io_base + (OMAP_TIMER_WRITE_PEND_REG
0xff))
-(reg WPSHIFT))
- cpu_relax();
+ if (timer-posted) {
+ omap_test_timeout(!(readl(timer-io_base +
+ ((OMAP_TIMER_WRITE_PEND_REG +
+ pdata-func_offset) 0xff)) (reg WPSHIFT)),
+ MAX_WRITE_PEND_WAIT, i);
+
+ if (WARN_ON(i == MAX_WRITE_PEND_WAIT))
+ pr_err(: write timeout\n);
+ }
+
writel(value, timer-io_base + (reg 0xff));
}
--
1.6.0.4
--
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[PATCH v7 1/12] OMAP2+: dmtimer: add device names to flck nodes
From: Thara Gopinath th...@ti.com
Add device name to OMAP2 dmtimer fclk nodes so that the fclk nodes can be
retrieved by doing a clk_get with the corresponding device pointers or
device names.
NOTE: gpt1_fck is modified in patch-10 when we switch to platform device
driver. This is to make sure that each patch compiles and boots.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
Reviewed-by: Varadarajan, Charulatha ch...@ti.com
---
arch/arm/mach-omap2/clock2420_data.c | 58 +++--
arch/arm/mach-omap2/clock2430_data.c | 58 +++--
arch/arm/mach-omap2/clock3xxx_data.c | 46 --
arch/arm/mach-omap2/clock44xx_data.c | 42 ++--
4 files changed, 161 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2420_data.c
b/arch/arm/mach-omap2/clock2420_data.c
index 21f8562..d140807 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1803,27 +1803,27 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, gpt1_ick, gpt1_ick, CK_242X),
CLK(NULL, gpt1_fck, gpt1_fck, CK_242X),
CLK(NULL, gpt2_ick, gpt2_ick, CK_242X),
- CLK(NULL, gpt2_fck, gpt2_fck, CK_242X),
+ CLK(omap_timer.2, fck, gpt2_fck, CK_242X),
CLK(NULL, gpt3_ick, gpt3_ick, CK_242X),
- CLK(NULL, gpt3_fck, gpt3_fck, CK_242X),
+ CLK(omap_timer.3, fck, gpt3_fck, CK_242X),
CLK(NULL, gpt4_ick, gpt4_ick, CK_242X),
- CLK(NULL, gpt4_fck, gpt4_fck, CK_242X),
+ CLK(omap_timer.4, fck, gpt4_fck, CK_242X),
CLK(NULL, gpt5_ick, gpt5_ick, CK_242X),
- CLK(NULL, gpt5_fck, gpt5_fck, CK_242X),
+ CLK(omap_timer.5, fck, gpt5_fck, CK_242X),
CLK(NULL, gpt6_ick, gpt6_ick, CK_242X),
- CLK(NULL, gpt6_fck, gpt6_fck, CK_242X),
+ CLK(omap_timer.6, fck, gpt6_fck, CK_242X),
CLK(NULL, gpt7_ick, gpt7_ick, CK_242X),
- CLK(NULL, gpt7_fck, gpt7_fck, CK_242X),
+ CLK(omap_timer.7, fck, gpt7_fck, CK_242X),
CLK(NULL, gpt8_ick, gpt8_ick, CK_242X),
- CLK(NULL, gpt8_fck, gpt8_fck, CK_242X),
+ CLK(omap_timer.8, fck, gpt8_fck, CK_242X),
CLK(NULL, gpt9_ick, gpt9_ick, CK_242X),
- CLK(NULL, gpt9_fck, gpt9_fck, CK_242X),
+ CLK(omap_timer.9, fck, gpt9_fck, CK_242X),
CLK(NULL, gpt10_ick,gpt10_ick, CK_242X),
- CLK(NULL, gpt10_fck,gpt10_fck, CK_242X),
+ CLK(omap_timer.10,fck, gpt10_fck, CK_242X),
CLK(NULL, gpt11_ick,gpt11_ick, CK_242X),
- CLK(NULL, gpt11_fck,gpt11_fck, CK_242X),
+ CLK(omap_timer.11,fck, gpt11_fck, CK_242X),
CLK(NULL, gpt12_ick,gpt12_ick, CK_242X),
- CLK(NULL, gpt12_fck,gpt12_fck, CK_242X),
+ CLK(omap_timer.12,fck, gpt12_fck, CK_242X),
CLK(omap-mcbsp.1, ick, mcbsp1_ick,CK_242X),
CLK(omap-mcbsp.1, fck, mcbsp1_fck,CK_242X),
CLK(omap-mcbsp.2, ick, mcbsp2_ick,CK_242X),
@@ -1878,6 +1878,42 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, pka_ick, pka_ick, CK_242X),
CLK(NULL, usb_fck, usb_fck, CK_242X),
CLK(musb_hdrc,fck, osc_ck,CK_242X),
+ CLK(omap_timer.1, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.2, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.3, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.4, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.5, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.6, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.7, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.8, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.9, 32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.10,32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.11,32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.12,32k_ck, func_32k_ck, CK_243X),
+ CLK(omap_timer.1, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.2, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.3, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.4, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.5, sys_ck, sys_ck,CK_243X),
+ CLK(omap_timer.6, sys_ck,
[PATCH v7 5/12] OMAP4: hwmod data: add dmtimer
From: Cousson, Benoit b-cous...@ti.com
Add dmtimer data.
Signed-off-by: Cousson, Benoit b-cous...@ti.com
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Reviewed-by: Varadarajan, Charulatha ch...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 623
arch/arm/plat-omap/include/plat/dmtimer.h |1 +
2 files changed, 624 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7274db4..6da3ae3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -22,6 +22,7 @@
#include plat/omap_hwmod.h
#include plat/cpu.h
+#include plat/dmtimer.h
#include omap_hwmod_common_data.h
@@ -453,6 +454,614 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
};
/*
+ * 'timer' class
+ * general purpose timer module with accurate 1ms tick
+ * This class contains several variants: ['timer_1ms', 'timer']
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
+ .name = timer,
+ .sysc = omap44xx_timer_1ms_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
+ .name = timer,
+ .sysc = omap44xx_timer_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_2,
+};
+
+/* timer1 */
+static struct omap_hwmod omap44xx_timer1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
+ { .irq = 37 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
+ {
+ .pa_start = 0x4a318000,
+ .pa_end = 0x4a31807f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_wkup - timer1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
+ .master = omap44xx_l4_wkup_hwmod,
+ .slave = omap44xx_timer1_hwmod,
+ .clk= l4_wkup_clk_mux_ck,
+ .addr = omap44xx_timer1_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
+ omap44xx_l4_wkup__timer1,
+};
+
+static struct omap_hwmod omap44xx_timer1_hwmod = {
+ .name = timer1,
+ .class = omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
+ .main_clk = timer1_fck,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_timer1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* timer2 */
+static struct omap_hwmod omap44xx_timer2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
+ { .irq = 38 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
+ {
+ .pa_start = 0x48032000,
+ .pa_end = 0x4803207f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_per - timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
+ .master = omap44xx_l4_per_hwmod,
+ .slave = omap44xx_timer2_hwmod,
+ .clk= l4_div_ck,
+ .addr = omap44xx_timer2_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
+ omap44xx_l4_per__timer2,
+};
+
+static struct omap_hwmod omap44xx_timer2_hwmod = {
+ .name = timer2,
+ .class = omap44xx_timer_1ms_hwmod_class,
+ .mpu_irqs = omap44xx_timer2_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
+
[PATCH v7 7/12] OMAP2+: dmtimer: convert to platform devices
Add routines to converts dmtimers to platform devices. The device data
is obtained from hwmod database of respective platform and is registered
to device model after successful binding to driver. It also provides
provision to access timers during early boot when pm_runtime framework
is not completely up and running.
Signed-off-by: Tarun Kanti DebBarma tarun.ka...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Reviewed-by: Varadarajan, Charulatha ch...@ti.com
Acked-by: Cousson, Benoit b-cous...@ti.com
---
arch/arm/mach-omap2/Makefile |2 +-
arch/arm/mach-omap2/dmtimer.c | 194 +
2 files changed, 195 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/dmtimer.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 60e51bc..7700ccd 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
# Common support
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
-common.o
+common.o dmtimer.o
omap-2-3-common= irq.o sdrc.o prm2xxx_3xxx.o
hwmod-common = omap_hwmod.o \
diff --git a/arch/arm/mach-omap2/dmtimer.c b/arch/arm/mach-omap2/dmtimer.c
new file mode 100644
index 000..90ddb88
--- /dev/null
+++ b/arch/arm/mach-omap2/dmtimer.c
@@ -0,0 +1,194 @@
+/**
+ * OMAP2+ Dual-Mode Timers - platform device registration
+ *
+ * Contains first level initialization routines which extracts timers
+ * information from hwmod database and registers with linux device model.
+ * It also has low level function to change the timer input clock source.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma tarun.ka...@ti.com
+ * Thara Gopinath th...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/slab.h
+
+#include plat/dmtimer.h
+#include plat/omap_device.h
+
+/*
+ * OMAP4 IP revision has different register offsets
+ * for interrupt registers and functional registers.
+ */
+#define VERSION2_TIMER_WAKEUP_EN_REG_OFFSET0x14
+#define VERSION2_TIMER_STAT_REG_OFFSET 0x10
+
+static int early_timer_count __initdata = 1;
+
+struct dm_timer_data {
+ struct omap_device *od;
+ struct dmtimer_platform_data *pdata;
+ struct list_head node;
+};
+
+static __initdata LIST_HEAD(dm_timer_data_list);
+
+/**
+ * omap2_dm_timer_set_src - change the timer input clock source
+ * @pdev: timer platform device pointer
+ * @timer_clk: current clock source
+ * @source:array index of parent clock source
+ */
+static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
+{
+ int ret;
+ struct dmtimer_platform_data *pdata = pdev-dev.platform_data;
+ struct clk *fclk = clk_get(pdev-dev, fck);
+ struct clk *new_fclk;
+ char *fclk_name = 32k_ck; /* default name */
+
+ switch (source) {
+ case OMAP_TIMER_SRC_SYS_CLK:
+ fclk_name = sys_ck;
+ break;
+
+ case OMAP_TIMER_SRC_32_KHZ:
+ fclk_name = 32k_ck;
+ break;
+
+ case OMAP_TIMER_SRC_EXT_CLK:
+ if (pdata-timer_ip_type == OMAP_TIMER_IP_VERSION_1) {
+ fclk_name = alt_ck;
+ break;
+ }
+ dev_err(pdev-dev, %s: %d: invalid clk src.\n,
+ __func__, __LINE__);
+ return -EINVAL;
+ }
+
+ if (IS_ERR_OR_NULL(fclk)) {
+ dev_err(pdev-dev, %s: %d: clk_get() FAILED\n,
+ __func__, __LINE__);
+ return -EINVAL;
+ }
+
+ new_fclk = clk_get(pdev-dev, fclk_name);
+ if (IS_ERR_OR_NULL(new_fclk)) {
+ dev_err(pdev-dev, %s: %d: clk_get() %s FAILED\n,
+ __func__, __LINE__, fclk_name);
+ clk_put(fclk);
+ return -EINVAL;
+ }
+
+ ret = clk_set_parent(fclk, new_fclk);
+ if (IS_ERR_VALUE(ret)) {
+ dev_err(pdev-dev, %s: clk_set_parent() to %s FAILED\n,
+ __func__, fclk_name);
+ ret = -EINVAL;
+ }
+
+ clk_put(new_fclk);
+ clk_put(fclk);
+
+ return ret;
+}
+
+struct omap_device_pm_latency omap2_dmtimer_latency[] = {
+ {
+ .deactivate_func = omap_device_idle_hwmods,
+ .activate_func = omap_device_enable_hwmods,
+ .flags =
RE: [PATCH 3/7] OMAP3: remove hardcoded values from the ASM sleep code
-Original Message- From: jean.pi...@newoldbits.com [mailto:jean.pi...@newoldbits.com] Sent: Saturday, December 18, 2010 9:15 PM To: linux-omap@vger.kernel.org Cc: khil...@deeprootsystems.com; linux-arm- ker...@lists.infradead.org; Jean Pihet; Vishwanath BS Subject: [PATCH 3/7] OMAP3: remove hardcoded values from the ASM sleep code From: Jean Pihet j-pi...@ti.com Using macros from existing include files for registers addresses. Tested on N900 and Beagleboard with full RET and OFF modes, using cpuidle and suspend. Based on original patch from Vishwa. Signed-off-by: Jean Pihet j-pi...@ti.com Cc: Vishwanath BS vishwanath...@ti.com Acked-by: Vishwanath BS vishwanath...@ti.com Acked-by: Santosh Shilimkar santosh.shilim...@ti.com Tested-by: Nishanth Menon n...@ti.com --- arch/arm/mach-omap2/control.h |2 ++ arch/arm/mach-omap2/sleep34xx.S | 29 ++--- 2 files changed, 20 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach- omap2/control.h index d7911c5..72efefb 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -274,6 +274,8 @@ #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C +#define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ + OMAP343X_SCRATCHPAD + reg) /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach- omap2/sleep34xx.S index 406cd2a..8e9f38f 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -34,20 +34,27 @@ #include sdrc.h #include control.h -#define SDRC_SCRATCHPAD_SEM_V0xfa00291c - -#define PM_PREPWSTST_CORE_P 0x48306AE8 +/* + * Registers access definitions + */ +#define SDRC_SCRATCHPAD_SEM_OFFS 0xc +#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ + (SDRC_SCRATCHPAD_SEM_OFFS) +#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ + OMAP3430_PM_PREPWSTST #define PM_PWSTCTRL_MPU_POMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) #define CM_IDLEST_CKGEN_VOMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) -#define SRAM_BASE_P 0x4020 -#define CONTROL_STAT 0x480022F0 -#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\ - + OMAP36XX_CONTROL_MEM_RTA_CTRL) -#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is -* available */ -#define SCRATCHPAD_BASE_P(OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\ - + SCRATCHPAD_MEM_OFFS) +#define SRAM_BASE_P OMAP3_SRAM_PA +#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ + OMAP36XX_CONTROL_MEM_RTA_CTRL) + +/* Move this as correct place is available */ +#define SCRATCHPAD_MEM_OFFS 0x310 +#define SCRATCHPAD_BASE_P(OMAP343X_CTRL_BASE +\ + OMAP343X_CONTROL_MEM_WKUP +\ + SCRATCHPAD_MEM_OFFS) #define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) #define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) #define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) -- 1.7.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Is changing serial from /dev/ttySx to /dev/ttyOx a good idea?
Op 20 dec 2010, om 08:34 heeft Ming Lei het volgende geschreven: Hi, 2010/12/20 Abraham Arce abraham.arce.mor...@gmail.com: Hi, On Sun, Dec 19, 2010 at 9:04 PM, Ming Lei tom.leim...@gmail.com wrote: In fact, the transition is not friendly indeed for a user. I don't know why the transition is introduced, for what purpose? Who can give a explanation? Patch itself has one explanation, kernel commit is b612633b5928077441b979471869753bfa93d41a http://www.spinics.net/lists/linux-serial/msg02788.html The commit does not explain the cause of renaming ttyS to ttyO, does it? It does, ttyS* is reserved for 8250, nearly all ARM platforms have their own name (ttySAC, ttySA, etc). I'm surprised omap got away with this for so long. I'm not saying the change is a pain, I'm just saying I went through this years ago for strongarm. regards, Koen-- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if ES1.2
Santosh Shilimkar wrote, on 12/20/2010 12:51 AM:
[...]
+
+ /*
+* Erratum i583: implementation for ES rev Es1.2 on 3630. We
cannot
+* enable OFF mode in a stable form for previous revisions.
+* we disable C7 state as a result.
+*/
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
+ omap3_power_states[OMAP3_STATE_C7].valid = 0;
+ cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
WARN_ONCE in IDLE also would be good.
+ }
this state will not be active anyways as enable_off_mode is 0 by default.
}
struct cpuidle_driver omap3_idle_driver = {
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 92ef400..9032d09 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
#define PM_RTA_ERRATUM_i608 (1 0)
+#define PM_SDRC_WAKEUP_ERRATUM_i583(1 1)
#if defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 21cd36e..7faea55 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
- omap3_cpuidle_update_states(state, state);
+ /*
+* Erratum i583: implementation for ES rev Es1.2 on 3630. We
cannot
+* enable OFF mode in a stable form for previous revisions,
restrict
+* instead to RET
+*/
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
+ omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
+ else
+ omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst,pwrst_list, node) {
- pwrst-next_state = state;
- omap_set_pwrdm_state(pwrst-pwrdm, state);
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)
+ pwrst-pwrdm == core_pwrdm
+ state == PWRDM_POWER_OFF) {
+ pwrst-next_state = PWRDM_POWER_RET;
+ pr_err(%s: Core OFF disabled due to errata
i583\n,
Shoud we do this in every iteration or just WARN_ONCE do ??
every time off mode is enabled? this path is not exercised for every cpu
idle/suspend iteration.
--
Regards,
Nishanth Menon
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Re: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
Santosh Shilimkar wrote, on 12/20/2010 12:59 AM: [..] index 3fbd1e5..cc3507b 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -45,6 +45,8 @@ #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) #define SRAM_BASE_P 0x4020 #define CONTROL_STAT 0x480022F0 +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\ + + OMAP36XX_CONTROL_MEM_RTA_CTRL) Just a clarification. This register is not part of HW SAR SCM Registers, right ? Right. [..] -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 6/9] OMAP4: hwmod data: add system DMA
On 12/17/2010 4:39 PM, G, Manjunath Kondaiah wrote:
From: Benoit Coussonb-cous...@ti.com
Add OMAP4 DMA hwmod data
Signed-off-by: Benoit Coussonb-cous...@ti.com
Signed-off-by: G, Manjunath Kondaiahmanj...@ti.com
It will be good to explicitly list the changes you did compared to the
original generated version. Even if these are some minor changes.
I thought it was the original patch and it appears it is not the case :-(
The general minor commestic comment is you should try to keep the
original order of the structures. That does not changes anything, but
that will keep the file in sync with the generated one.
Tested-by: Kevin Hilmankhil...@deeprootsystems.com
Acked-by: Kevin Hilmankhil...@deeprootsystems.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 101
1 files changed, 101 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index d258936..50c00d6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -23,6 +23,7 @@
#includeplat/omap_hwmod.h
#includeplat/cpu.h
#includeplat/gpio.h
+#includeplat/dma.h
#include omap_hwmod_common_data.h
@@ -36,6 +37,7 @@
#define OMAP44XX_DMA_REQ_START 1
/* Backward references (IPs with Bus Master capability) */
+static struct omap_hwmod omap44xx_dma_system_hwmod;
static struct omap_hwmod omap44xx_dmm_hwmod;
static struct omap_hwmod omap44xx_emif_fw_hwmod;
static struct omap_hwmod omap44xx_l3_instr_hwmod;
@@ -216,6 +218,14 @@ static struct omap_hwmod_ocp_if
omap44xx_l3_main_1__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* dma_system - l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
+ .master =omap44xx_dma_system_hwmod,
+ .slave =omap44xx_l3_main_2_hwmod,
+ .clk= l3_div_ck,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg - l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
.master =omap44xx_l4_cfg_hwmod,
@@ -227,6 +237,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2
= {
/* l3_main_2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
omap44xx_l3_main_1__l3_main_2,
+ omap44xx_dma_system__l3_main_2,
omap44xx_l4_cfg__l3_main_2,
};
@@ -1376,6 +1387,93 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+
+/*
+ * 'dma' class
+ * dma controller for data exchange between memory to memory (i.e. internal or
+ * external memory) and gp peripherals to memory or memory to gp peripherals
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x002c,
+ .syss_offs = 0x0028,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
A new flag was introduce in 2.6.37 to handle properly the softreset
(SYSS_HAS_RESET_STATUS). You should use it otherwise the reset might not
work properly. The generated hwmod data was updated accordingly at that
time (git://gitorious.org/omap-pm/linux.git hwmods-omap4-full)
Here are the proper data:
+static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x002c,
+ .syss_offs = 0x0028,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields=omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
+ .name = dma,
+ .sysc =omap44xx_dma_sysc,
+};
+
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+ IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+ .lch_count = 32,
+};
+
+/* dma_system */
+static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
+ { .name = 0, .irq = 12 + OMAP44XX_IRQ_GIC_START },
+ { .name = 1, .irq = 13 + OMAP44XX_IRQ_GIC_START },
+ { .name = 2, .irq = 14 + OMAP44XX_IRQ_GIC_START },
+ { .name = 3, .irq = 15 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
+ {
+ .pa_start = 0x4a056000,
+ .pa_end
Re: [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
On Mon, Dec 20, 2010 at 11:23:27AM +0100, ext Jean Pihet wrote: On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon n...@ti.com wrote: From: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com Erratum i581 impacts OMAP3 platforms. PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing the DPLL not to be locked at times. IMPORTANT: *) This is not a complete workaround implementation as recommended by the silicon erratum. this is a support logic for detecting lockups and attempting to recover where possible and is known to provide stability in multiple platforms. *) This code is mostly important for inactive and retention. The ROM code waits for the maximum dll lock time when resuming from off mode. So for off mode this code isn't really needed. This should eventually get refactored as part of cleanups to sleep34xx.S Cc: Kevin Hilman khil...@deeprootsystems.com Cc: Tony Lindgren t...@atomide.com Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com --- (no change done, posting for completeness of the series) v2: https://patchwork.kernel.org/patch/365252/ typo correction- erratum, support, added comment from Peter from the thread to commit message v1: http://marc.info/?l=linux-omapm=129013172525234w=2 arch/arm/mach-omap2/sleep34xx.S | 52 +++--- 1 files changed, 47 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 2c20fcf..3fbd1e5 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -42,6 +42,7 @@ OMAP3430_PM_PREPWSTST) #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) +#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) #define SRAM_BASE_P 0x4020 #define CONTROL_STAT 0x480022F0 #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is @@ -554,31 +555,67 @@ skip_l2_inval: /* Make sure SDRC accesses are ok */ wait_sdrc_ok: + +/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */ + ldr r4, cm_idlest_ckgen +wait_dpll3_lock: + ldr r5, [r4] + tst r5, #1 + beq wait_dpll3_lock + ldr r4, cm_idlest1_core +wait_sdrc_ready: ldr r5, [r4] - and r5, r5, #0x2 - cmp r5, #0 - bne wait_sdrc_ok + tst r5, #0x2 + bne wait_sdrc_ready + /* allow DLL powerdown upon hw idle req */ ldr r4, sdrc_power ldr r5, [r4] bic r5, r5, #0x40 str r5, [r4] -wait_dll_lock: +is_dll_in_lock_mode: + /* Is dll in lock mode? */ ldr r4, sdrc_dlla_ctrl ldr r5, [r4] tst r5, #0x4 bxne lr /* wait till dll locks */ - ldr r4, sdrc_dlla_status +wait_dll_lock_timed: + ldr r4, wait_dll_lock_counter + add r4, r4, #1 + str r4, wait_dll_lock_counter + ldr r4, sdrc_dlla_status + mov r6, #8 /* Wait 20uS for lock */ +wait_dll_lock: + subs r6, r6, #0x1 + beq kick_dll It would be good to have more comments on the code flow here: - what are wait_dll_lock_counter and kick_counter used for? For debugging and statistics. So you can find out how many times a 'kick' was needed. - what is the timing based on? Why 20uS for the wait time? This is the maximum lock time of the dll according to TI for OMAP3430. - jumping back and forth to kick_dll and wait_dll_lock_timed is confusing. ldr r5, [r4] and r5, r5, #0x4 cmp r5, #0x4 bne wait_dll_lock bx lr + /* disable/reenable DLL if not locked */ +kick_dll: + ldr r4, sdrc_dlla_ctrl + ldr r5, [r4] + mov r6, r5 + bic r6, #(13) /* disable dll */ + str r6, [r4] + dsb + orr r6, r6, #(13) /* enable dll */ + str r6, [r4] + dsb + ldr r4, kick_counter + add r4, r4, #1 + str r4, kick_counter + b wait_dll_lock_timed + cm_idlest1_core: .word CM_IDLEST1_CORE_V +cm_idlest_ckgen: + .word CM_IDLEST_CKGEN_V sdrc_dlla_status: .word SDRC_DLLA_STATUS_V sdrc_dlla_ctrl: @@ -615,5 +652,10 @@ control_stat: .word CONTROL_STAT kernel_flush: .word v7_flush_dcache_all + /* these 2 words need to be at the end !!! */ +kick_counter: + .word 0 +wait_dll_lock_counter: + .word 0 Why do they need to be at the end? Also, at the end of
Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
Santosh Shilimkar wrote, on 12/20/2010 01:13 AM: [..] This is be done according to ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from public side while, on OMAP3430, this is done in the secure side. Can you point me to ARM doc which says for L2 invalidation, the controller needs to be disabled ? please see section 8.3 of the Cortex-A8 TRM -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
-Original Message- From: Nishanth Menon [mailto:n...@ti.com] Sent: Monday, December 20, 2010 5:15 PM To: Santosh Shilimkar Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache Santosh Shilimkar wrote, on 12/20/2010 01:13 AM: [..] This is be done according to ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from public side while, on OMAP3430, this is done in the secure side. Can you point me to ARM doc which says for L2 invalidation, the controller needs to be disabled ? please see section 8.3 of the Cortex-A8 TRM Yes. Have seen it and it doesn't say at least what your patch description is saying. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
-Original Message- From: Nishanth Menon [mailto:n...@ti.com] Sent: Monday, December 20, 2010 4:54 PM To: Santosh Shilimkar Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony Subject: Re: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA Santosh Shilimkar wrote, on 12/20/2010 12:59 AM: [..] index 3fbd1e5..cc3507b 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -45,6 +45,8 @@ #define CM_IDLEST_CKGEN_VOMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) #define SRAM_BASE_P 0x4020 #define CONTROL_STAT 0x480022F0 +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\ + + OMAP36XX_CONTROL_MEM_RTA_CTRL) Just a clarification. This register is not part of HW SAR SCM Registers, right ? Right. [..] Thanks. Acked-by: Santosh Shilimkar santosh.shilim...@ti.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
-Original Message- From: Nishanth Menon [mailto:n...@ti.com] Sent: Monday, December 20, 2010 6:38 PM To: Santosh Shilimkar Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache Santosh Shilimkar had written, on 12/20/2010 06:14 AM, the following: -Original Message- From: Nishanth Menon [mailto:n...@ti.com] Sent: Monday, December 20, 2010 5:15 PM To: Santosh Shilimkar Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache Santosh Shilimkar wrote, on 12/20/2010 01:13 AM: [..] This is be done according to ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from public side while, on OMAP3430, this is done in the secure side. Can you point me to ARM doc which says for L2 invalidation, the controller needs to be disabled ? please see section 8.3 of the Cortex-A8 TRM Yes. Have seen it and it doesn't say at least what your patch description is saying. See [1] To disable the L2 cache, but leave the L1 data cache enabled, use the following sequence: But it's not applicable to this piece of code. Your L1D is not ON here either. 1. Disable the C bit. for details on C bit: see [2] 2. Clean and invalidate the L1 and L2 caches. [...] Does this help or do you have a suggestion on how the commit message could be improved? Actually it doesn't. My worry is we might be trying to work-around some OMAP specific issue. But as I said initially we do change the AUXCTRL configuration and in that case the sequence is correct as per ARM TRM. So may be you could update the change log something like below. While coming out of MPU OSWR/OFF states, L2 controller is reseted. The reset behavior is implementation specific as per ARMv7 TRM and hence $L2 needs to be invalidated before it's use. Since the AUXCTRL register is also reconfigured, disable L2 cache before invalidating it and re-enables it afterwards. This is as per Cortex-A8 ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from public side while, on OMAP3430, this is done in the secure side. Regards, Santosh -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
Santosh Shilimkar had written, on 12/20/2010 07:29 AM, the following: [..] So may be you could update the change log something like below. While coming out of MPU OSWR/OFF states, L2 controller is reseted. The reset behavior is implementation specific as per ARMv7 TRM and hence $L2 needs to be invalidated before it's use. Since the AUXCTRL register is also reconfigured, disable L2 cache before invalidating it and re-enables it afterwards. This is as per Cortex-A8 ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from public side while, on OMAP3430, this is done in the secure side. Thanks, will update the rev5 patch with this commit log. -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Patch v5] AM35xx: Craneboard: Add USB EHCI support
From: Srinath srin...@mistralsolutions.com
AM3517/05 Craneboard has one EHCI interface on board using port1.
GPIO35 is used as power enable.
GPIO38 is used as port1 PHY reset.
History:
http://marc.info/?l=linux-omapw=2r=1s=Craneboard%253A%2BAdd%2BUSB%2BEHCI%2Bsupportq=b
Signed-off-by: Srinath srin...@mistralsolutions.com
---
arch/arm/mach-omap2/board-am3517crane.c | 48 +++
1 files changed, 48 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-am3517crane.c
b/arch/arm/mach-omap2/board-am3517crane.c
index 8ba4047..e56900f 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -19,6 +19,7 @@
#include linux/kernel.h
#include linux/init.h
+#include linux/gpio.h
#include mach/hardware.h
#include asm/mach-types.h
@@ -27,8 +28,14 @@
#include plat/board.h
#include plat/common.h
+#include plat/usb.h
#include mux.h
+#include control.h
+
+#define GPIO_USB_POWER 35
+#define GPIO_USB_NRESET38
+
/* Board initialization */
static struct omap_board_config_kernel am3517_crane_config[] __initdata = {
@@ -51,10 +58,51 @@ static void __init am3517_crane_init_irq(void)
omap_init_irq();
}
+static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
+ .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+ .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+
+ .phy_reset = true,
+ .reset_gpio_port[0] = GPIO_USB_NRESET,
+ .reset_gpio_port[1] = -EINVAL,
+ .reset_gpio_port[2] = -EINVAL
+};
+
static void __init am3517_crane_init(void)
{
+ int ret;
+
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_serial_init();
+
+ /* Configure GPIO for EHCI port */
+ if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
+ pr_err(Can not configure mux for GPIO_USB_NRESET %d\n,
+ GPIO_USB_NRESET);
+ return;
+ }
+
+ if (omap_mux_init_gpio(GPIO_USB_POWER, OMAP_PIN_OUTPUT)) {
+ pr_err(Can not configure mux for GPIO_USB_POWER %d\n,
+ GPIO_USB_POWER);
+ return;
+ }
+
+ ret = gpio_request(GPIO_USB_POWER, usb_ehci_enable);
+ if (ret 0) {
+ pr_err(Can not request GPIO %d\n, GPIO_USB_POWER);
+ return;
+ }
+
+ ret = gpio_direction_output(GPIO_USB_POWER, 1);
+ if (ret 0) {
+ gpio_free(GPIO_USB_POWER);
+ pr_err(Unable to initialize EHCI power\n);
+ return;
+ }
+
+ usb_ehci_init(ehci_pdata);
}
MACHINE_START(CRANEBOARD, AM3517/05 CRANEBOARD)
--
1.7.1.226.g770c5
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RE: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
-Original Message- From: Nishanth Menon [mailto:n...@ti.com] Sent: Monday, December 20, 2010 7:03 PM To: Santosh Shilimkar Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache Santosh Shilimkar had written, on 12/20/2010 07:29 AM, the following: [..] So may be you could update the change log something like below. While coming out of MPU OSWR/OFF states, L2 controller is reseted. The reset behavior is implementation specific as per ARMv7 TRM and hence $L2 needs to be invalidated before it's use. Since the AUXCTRL register is also reconfigured, disable L2 cache before invalidating it and re-enables it afterwards. This is as per Cortex-A8 ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from public side while, on OMAP3430, this is done in the secure side. Thanks, will update the rev5 patch with this commit log. Sure. With that change you could add, Acked-by: Santosh Shilimkar santosh.shilim...@ti.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 3/7] DSPBRIDGE: do not call follow_page
On Thu, May 27, 2010 at 7:02 PM, Ohad Ben-Cohen o...@wizery.com wrote:
Eliminate the call to follow_page. Instead, use the page
information that was kept during the proc_map call.
This also has the advantage that users can now only
specify memory areas that were previously mapped.
Signed-off-by: Ohad Ben-Cohen o...@wizery.com
I found another issue with this patch:
- if (memory_sync_vma((u32) pmpu_addr, ul_size, FlushMemType)) {
+ /* find requested memory are in cached mapping information */
+ map_obj = find_containing_mapping(pr_ctxt, (u32) pmpu_addr, ul_size);
+ if (!map_obj) {
+ pr_err(%s: find_containing_mapping failed\n, __func__);
+ status = -EFAULT;
+ goto err_out;
+ }
+ if (memory_sync_page(map_obj, (u32) pmpu_addr, ul_size, ul_flags)) {
pr_err(%s: InValid address parameters %p %x\n,
- __func__, pmpu_addr, ul_size);
+ __func__, pmpu_addr, ul_size);
status = -EFAULT;
}
find_containing_mapping() is taking the lock for dmm_map_list,
however, nothing prevents the map_obj to be destroyed after that,
specially if kcalloc sleeps, and then an unmap happens. While doing
some stress testing I found there's a race condition that makes
exactly that happen.
I'm sending some patches to fix that.
--
Felipe Contreras
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Re: [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
Santosh Shilimkar had written, on 12/20/2010 12:47 AM, the following: [..] diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach- omap2/sleep34xx.S index 2c20fcf..3fbd1e5 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -42,6 +42,7 @@ OMAP3430_PM_PREPWSTST) #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) +#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) We need to avoid these macro's calculating VA directly. But I guess it needs to be done more than just this line and hence can be done in a separate patch. yes - with the cleanups planned for this file, we could probably add it to that set I guess. -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
Peter 'p2' De Schrijver had written, on 12/20/2010 05:33 AM, the following: [..] + /* these 2 words need to be at the end !!! */ +kick_counter: + .word 0 +wait_dll_lock_counter: + .word 0 Why do they need to be at the end? Also, at the end of what do they need to be? At the end of omap34xx_cpu_suspend. As we don't know where in SRAM the counters will be, the code accessing those counters addresses them relative from (_omap_sram_idle + omap34xx_cpu_suspend_sz). Not sure if this part of the code made it to linux-omap though. I have not posted the change needed to expose these counters to userspace waiting for the churn in sleep34xx.S to settle down. -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] staging: tidspbridge: convert dmm_map_lock to sema
This is needed because the lock needs to be extended to protect the
mapping info access, which is used to construct a scatter-gather list,
and in the process, we might sleep.
Signed-off-by: Felipe Contreras felipe.contre...@nokia.com
---
.../staging/tidspbridge/include/dspbridge/drv.h|2 +-
drivers/staging/tidspbridge/rmgr/drv_interface.c |2 +-
drivers/staging/tidspbridge/rmgr/proc.c| 12 ++--
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/tidspbridge/include/dspbridge/drv.h
b/drivers/staging/tidspbridge/include/dspbridge/drv.h
index c1f363e..217c918 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/drv.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/drv.h
@@ -163,7 +163,7 @@ struct process_context {
/* DMM mapped memory resources */
struct list_head dmm_map_list;
- spinlock_t dmm_map_lock;
+ struct semaphore dmm_map_sema;
/* DMM reserved memory resources */
struct list_head dmm_rsv_list;
diff --git a/drivers/staging/tidspbridge/rmgr/drv_interface.c
b/drivers/staging/tidspbridge/rmgr/drv_interface.c
index 324fcdf..82c25c6 100644
--- a/drivers/staging/tidspbridge/rmgr/drv_interface.c
+++ b/drivers/staging/tidspbridge/rmgr/drv_interface.c
@@ -507,7 +507,7 @@ static int bridge_open(struct inode *ip, struct file *filp)
pr_ctxt = kzalloc(sizeof(struct process_context), GFP_KERNEL);
if (pr_ctxt) {
pr_ctxt-res_state = PROC_RES_ALLOCATED;
- spin_lock_init(pr_ctxt-dmm_map_lock);
+ sema_init(pr_ctxt-dmm_map_sema, 1);
INIT_LIST_HEAD(pr_ctxt-dmm_map_list);
spin_lock_init(pr_ctxt-dmm_rsv_lock);
INIT_LIST_HEAD(pr_ctxt-dmm_rsv_list);
diff --git a/drivers/staging/tidspbridge/rmgr/proc.c
b/drivers/staging/tidspbridge/rmgr/proc.c
index b47d7aa..77ab5f5 100644
--- a/drivers/staging/tidspbridge/rmgr/proc.c
+++ b/drivers/staging/tidspbridge/rmgr/proc.c
@@ -144,9 +144,9 @@ static struct dmm_map_object *add_mapping_info(struct
process_context *pr_ctxt,
map_obj-size = size;
map_obj-num_usr_pgs = num_usr_pgs;
- spin_lock(pr_ctxt-dmm_map_lock);
+ down(pr_ctxt-dmm_map_sema);
list_add(map_obj-link, pr_ctxt-dmm_map_list);
- spin_unlock(pr_ctxt-dmm_map_lock);
+ up(pr_ctxt-dmm_map_sema);
return map_obj;
}
@@ -170,7 +170,7 @@ static void remove_mapping_information(struct
process_context *pr_ctxt,
pr_debug(%s: looking for virt 0x%x size 0x%x\n, __func__,
dsp_addr, size);
- spin_lock(pr_ctxt-dmm_map_lock);
+ down(pr_ctxt-dmm_map_sema);
list_for_each_entry(map_obj, pr_ctxt-dmm_map_list, link) {
pr_debug(%s: candidate: mpu_addr 0x%x virt 0x%x size 0x%x\n,
__func__,
@@ -191,7 +191,7 @@ static void remove_mapping_information(struct
process_context *pr_ctxt,
pr_err(%s: failed to find given map info\n, __func__);
out:
- spin_unlock(pr_ctxt-dmm_map_lock);
+ up(pr_ctxt-dmm_map_sema);
}
static int match_containing_map_obj(struct dmm_map_object *map_obj,
@@ -211,7 +211,7 @@ static struct dmm_map_object *find_containing_mapping(
pr_debug(%s: looking for mpu_addr 0x%x size 0x%x\n, __func__,
mpu_addr, size);
- spin_lock(pr_ctxt-dmm_map_lock);
+ down(pr_ctxt-dmm_map_sema);
list_for_each_entry(map_obj, pr_ctxt-dmm_map_list, link) {
pr_debug(%s: candidate: mpu_addr 0x%x virt 0x%x size 0x%x\n,
__func__,
@@ -228,7 +228,7 @@ static struct dmm_map_object *find_containing_mapping(
map_obj = NULL;
out:
- spin_unlock(pr_ctxt-dmm_map_lock);
+ up(pr_ctxt-dmm_map_sema);
return map_obj;
}
--
1.7.3.3
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[PATCH 0/2] staging: tidspbridge: fix dma race condition
Hi, I found a race condition that triggers a kernel panic. It's explained in the following patches, but basically the map_obj that contains the user pages is being destroyed while doing a DMA operation (which requires that map_obj). My solution is to convert the spinlock to a semaphore, and exten the area protected (which might sleep). I have not tested these specific patches; they have been forward ported. But in a similar branch, they solve the issue. Felipe Contreras (2): staging: tidspbridge: convert dmm_map_lock to sema staging: tidspbridge: extend dmm_map semaphore .../staging/tidspbridge/include/dspbridge/drv.h|2 +- drivers/staging/tidspbridge/rmgr/drv_interface.c |2 +- drivers/staging/tidspbridge/rmgr/proc.c| 23 +--- 3 files changed, 17 insertions(+), 10 deletions(-) -- 1.7.3.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 3/7] omap3: pm: introduce errata handling
Jean Pihet had written, on 12/20/2010 04:18 AM, the following: Here a few minor remarks about typos: On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon n...@ti.com wrote: Introduce errata handling for omap3. This patch introduces Use caps for OMAP3 errata variable and and stub for initialization which will be and and - and filled up by followon patches. followon - follow-on? Thanks. Updated for v5 of the patch. -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] OMAP: Fix configuration of J-Type DPLLs to work for OMAP3 and OMAP4
On 12/18/2010 4:08 AM, Paul Walmsley wrote:
Hello Jon
On Fri, 17 Dec 2010, Jon Hunter wrote:
From: Jon Hunterjon-hun...@ti.com
J-Type DPLLs have additional configuration parameters that need to
be programmed when setting the multipler and divider for the DPLL.
These parameters being the sigma delta divider (SD_DIV) for the DPLL
and the digital controlled oscillator (DCO) to be used by the DPLL.
The current code is implemented specifically to configure the
OMAP3630 PER J-Type DPLL. The OMAP4430 USB DPLL is also a J-Type DPLL
and so this code needs to be updated to work for both OMAP3 and OMAP4
devices and any other future devices that have J-TYPE DPLLs.
For the OMAP3630 PER DPLL both the SD_DIV and DCO paramenters are
used but for the OMAP4430 USB DPLL only the SD_DIV field is used.
The current implementation will only program the SD_DIV and DCO
fields if the DPLL has both and hence this does not work for
OMAP4430.
In order to make the code more generic add two new fields to the
dpll_data structure for the SD_DIV field and DCO field bit-masks
and only program these fields if the masks are defined for a specific
DPLL. This simplifies the code and allows us to remove the flag
DPLL_NO_DCO_SEL.
Has this patch been tested on both OMAP36xx and OMAP4 ?
Yes, I performed a quick validation on both OMAP36xx Zoom3 and OMAP4
Blaze to make sure the values are calculated correctly and I see the
expected result in the register.
Signed-off-by: Jon Hunterjon-hun...@ti.com
---
arch/arm/mach-omap2/clock.h |1 -
arch/arm/mach-omap2/clock3xxx_data.c|2 +
arch/arm/mach-omap2/clock44xx_data.c|3 +-
arch/arm/mach-omap2/dpll3xxx.c | 53 +++---
arch/arm/plat-omap/include/plat/clock.h |5 ++-
5 files changed, 40 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index a535c7a..896584e 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -49,7 +49,6 @@
/* DPLL Type and DCO Selection Flags */
#define DPLL_J_TYPE 0x1
-#define DPLL_NO_DCO_SEL0x2
int omap2_clk_enable(struct clk *clk);
void omap2_clk_disable(struct clk *clk);
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-omap2/clock3xxx_data.c
index 0579604..461b1ca 100644
Any reason why you're removing this comment?
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -602,6 +602,8 @@ static struct dpll_data dpll4_dd_3630 __initdata = {
.autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
.idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.idlest_mask= OMAP3430_ST_PERIPH_CLK_MASK,
+ .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
+ .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
.max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
.min_divider= 1,
.max_divider= OMAP3_MAX_DPLL_DIV,
diff --git a/arch/arm/mach-omap2/clock44xx_data.c
b/arch/arm/mach-omap2/clock44xx_data.c
index bfcd19f..cef179e 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -913,7 +913,7 @@ static struct clk usb_hs_clk_div_ck = {
static struct dpll_data dpll_usb_dd = {
.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
.clk_bypass =usb_hs_clk_div_ck,
- .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL,
+ .flags = DPLL_J_TYPE,
.clk_ref=sys_clkin_ck,
.control_reg= OMAP4430_CM_CLKMODE_DPLL_USB,
.modes = (1 DPLL_LOW_POWER_BYPASS) | (1 DPLL_LOCKED),
@@ -924,6 +924,7 @@ static struct dpll_data dpll_usb_dd = {
.enable_mask= OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask= OMAP4430_ST_DPLL_CLK_MASK,
+ .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
.max_divider= OMAP4430_MAX_DPLL_DIV,
.min_divider= 1,
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index ed8d330..48df8e4 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -225,23 +225,18 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
}
/**
- * lookup_dco_sddiv - Set j-type DPLL4 compensation variables
+ * lookup_dco - Lookup DCO used by j-type DPLL
* @clk: pointer to a DPLL struct clk
* @dco: digital control oscillator selector
- * @sd_div: target sigma-delta divider
* @m: DPLL multiplier to set
* @n: DPLL divider to set
*
* See 36xx TRM section 3.5.3.3.3.2 Type B DPLL (Low-Jitter)
*
- * XXX This code is not needed for 3430/AM35xx; can it be optimized
- * out in non-multi-OMAP builds for those chips?
Any reason why you're removing this comment?
My thought here was that with this change the code will only be called
for DPLLs that have the sddiv_offset and dco_offset
Re: [PATCH v2] Keyboard: omap-keypad: use matrix_keypad.h
Hello,
On Sat, 18 Dec 2010, Janusz Krzysztofik wrote:
Most keypad drivers make use of the linux/input/matrix_keypad.h
defined macros, structures and inline functions.
Convert omap-keypad driver to use those as well, as suggested by a
compile time warning, hardcoded into the OMAP palt/keypad.h.
Created against linux-2.6.37-rc5.
Tested on Amstrad Delta.
Compile tested with omap1_defconfig and omap2plus_defconfig shrinked to
board-h4.
Signed-off-by: Janusz Krzysztofik jkrzy...@tis.icnet.pl
[...]
--- linux-2.6.37-rc5/arch/arm/mach-omap1/board-ams-delta.c.orig 2010-12-09
23:07:35.0 +0100
+++ linux-2.6.37-rc5/arch/arm/mach-omap1/board-ams-delta.c 2010-12-18
16:23:29.0 +0100
@@ -46,81 +46,79 @@ static u16 ams_delta_latch2_reg;
static int ams_delta_keymap[] = {
[...]
+static const struct matrix_keymap_data ams_delta_keymap_data = {
+ .keymap = ams_delta_keymap,
+ .keymap_size= ARRAY_SIZE(ams_delta_keymap),
+};
You should update the ams_delta_keymap type as well, otherwise this patch
will introduce the following sparse warning:
CHECK arch/arm/mach-omap1/board-ams-delta.c
arch/arm/mach-omap1/board-ams-delta.c:191:27: warning: incorrect type in
initializer (different signedness)
arch/arm/mach-omap1/board-ams-delta.c:191:27:expected unsigned int const
[usertype] *keymap
arch/arm/mach-omap1/board-ams-delta.c:191:27:got int static [toplevel]
*noident
I only checked E3, so other boards should be checked as well.
A.
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[PATCHv2] OMAP: pm.c correct the initcall for an early init.
omap2_common_pm_init is the API where generic system devices like mpu, l3 etc get initialized. This has to happen really early on during the boot and not at a later time. This is especially important with the new opp changes as these devices need to be built before the opp tables init happen. Today both are device initcalls and it works just because of the order of compilation. Making this postcore_initcall is ideal because the omap device layer init happens as a core_initcall and typically rest of the driver/device inits are arch_initcall or something lower. Signed-off-by: Thara Gopinath th...@ti.com --- arch/arm/mach-omap2/pm.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index cf1c4c9..227a211 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -143,5 +143,5 @@ static int __init omap2_common_pm_init(void) return 0; } -device_initcall(omap2_common_pm_init); +postcore_initcall(omap2_common_pm_init); -- 1.7.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] I2C: i2c-omap: Change device name: i2c_omap - omap_i2c
Tony Lindgren t...@atomide.com writes: * Cousson, Benoit b-cous...@ti.com [101210 00:29]: On 12/9/2010 11:18 PM, aaro.koski...@nokia.com wrote: Hi, Kevin Hilman [khil...@deeprootsystems.com]: Ben Dooksben-...@fluff.org writes: Renaming stuff like this is going to have an impact on the userspace as anyone looking through /sys's driver heirarchy is going to miss the old name... It all depends if you really want to go ahead with this... Yes, we are aware of the userspace impact, but this name change makes all devices on OMAP have consistent names and actually improves the ability to have userspace tools have consistent naming as well. So there are no imporant users, or if there is, they are prepared for this change? Well, I do not know any user of that today. Do you have some in mind? Sounds like it's safe for me to take these two. These should probably go via Paul's integration branch to avoid conflicts with the other omap_device/omap_hwmod code. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCHv4 2/7] HSI: omap_ssi: Introducing OMAP SSI driver
Hi Tony,
On Fri, 2010-12-17 at 16:30 -0800, ext Tony Lindgren wrote:
* Carlos Chinea carlos.chi...@nokia.com [101214 02:13]:
Introduces the OMAP SSI driver in the kernel.
The Synchronous Serial Interface (SSI) is a legacy version
of HSI. As in the case of HSI, it is mainly used to connect
Application engines (APE) with cellular modem engines (CMT)
in cellular handsets.
It provides a multichannel, full-duplex, multi-core communication
with no reference clock. The OMAP SSI block is capable of reaching
speeds of 110 Mbit/s.
...
+static int __init ssi_init(void)
+{
+ return platform_device_register(ssi_pdev);
+}
+subsys_initcall(ssi_init);
Is this safe to do for all omaps2+ machines?
Well, I think it is safe. SSI will be only built in, if it is explicitly
configured for that specific machine. And AFAIK, at susbsys initcall
time all other initializations that the OMAP SSI driver may need, will
be already in place.
But I may missed something here ?
Br,
--
Carlos Chinea carlos.chi...@nokia.com
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RE: [PATCH v2 03/17] OMAP3: hwmod data: add DSS DISPC RFBI DSI VENC
Hi, linux-omap-ow...@vger.kernel.org wrote: Hi, On Mon, 2010-11-29 at 17:21 +0530, ext Guruswamy Senthilvadivu wrote: From: Senthilvadivu Guruswamy svad...@ti.com Database generated for Display Sub System applicable for OMAP3430-ES2 onwards and OMAP36xx. dss is also considered as an IP as dispc,rfbi, and named as dss_dss. For all the IP modules in DSS, same clock is needed for enabling. hwmod sees as independent IPs, so same clock has to be repeated as .mainclk in each IP. OMAP3430ES1 do not have IDLEST bit to poll on for dss IP. So this hwmod is not applicable for 3430ES1. I'm not so familiar with hwmods, so I cannot comment much on the first three patches in this series. I'll continue going through the latter patches. One question though: what does the mainclk do? If it means a clock which enables access to the registers, I'm not sure it's entirely correct. The DSS clocking can be changed to get the functional clock from DSI PLL. On OMAP4 there are MODULEMODE bits for DSS and other domains, these need to be enabled to use the module, I think that's what mainclk represents here. You can have a look at the CM_DSS_DSS_CLKCTRL register in the OMAP4 TRM to get a better idea. So, instead of explicitly enabling/disabling the interface clocks like we did for DSS in omap3, we just need to ensure that MODULEMODE bits are set, setting this will take care of enabling/gating interface clocks based on the state of the clock domain. I think we consider the DSS1_ALWAYSON_FCK as the mainclk. Others, please correct me if I am wrong. Regards, Archit Then a general comment about all the patches in the series: The commit descriptions do not seem to be of very high quality. They are short and poorly formatted. The descriptions are almost as important as the patch itself. Here's a nice text about commit messages: http://who-t.blogspot.com/2009/12/on-commit-messages.html And some comments of my own: - Use capital letters for DSS, DISPC, etc. when not spesifically referring to some variable or similar. - Use space after comma. - Wrap the lines consistently. Now it looks like the lines are wrapped at random points in some commits. - Use an empty line between paragraphs - While I understand that you (me neither) are not native english speaker, try to spend some time to be sure that there are no errors due to carelessness. - Remember that the 00 patch is not saved in git, so it should only be an intro, and all the relevant information should be found in the actual commit messages. Tomi-- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/5 v3] OMAP3630: PM: Erratum i583: disable coreoff if ES1.2
Nishanth Menon n...@ti.com writes:
Kevin Hilman had written, on 12/17/2010 04:54 PM, the following:
Nishanth Menon n...@ti.com writes:
Kevin Hilman had written, on 12/16/2010 12:57 PM, the following:
Nishanth Menon n...@ti.com writes:
Nishanth Menon had written, on 12/15/2010 06:05 PM, the following:
Kevin Hilman had written, on 12/15/2010 05:47 PM, the following:
I agree that this additional check in sram_idle should be removed, but
as long as I handle it in omap3_pm_off_mode_enable where the next
states are configured, is'nt that enough or am I missing something?
Setting the next states only sets the default states, but CPUidle
changes them.
Looking closer at omap3_pm_off_mode_enable() though, it already calls
into CPUidle and disables the valid bit for any states that have
*either* MPU or core off.You'll probably just need to extend this
approach to disable only CORE off state(s).
Thx. it is clear now. let me see how to clean this up.
k. Does the attached look any better now :)?
Yes, but, I still don't quite like it. Basically, I'm not crazy about
the errata knowledge being centralized in pm34xx.c. How about this:
Move the Errata handling core code (pm_errata_* PM_ERRATTA_*) to pm.[ch]
as a single patch. Then both pm34xx.c and cpuidle34xx.c would be free
to use it.
This would allow CPUidle handle the errata itself in the 'update_states'
function. Or even better, if CPUidle core can check this errata, it
should probably just never register C7 in the first place, because it is
*never* a valid C-state.
Make sense?
hmm.. IMHO at the problems themselves:
a) cpuidle_params_table - this needs to become dynamically generated
if you'd like cpuidle to not know about the existance of the invalid
states at all(C7 has to disappear from it's radar - but extending it
to a generic solution where an inbetween C state might be disabled as
well)
b) extending the problem further - cpu idle state latencies by
themselves might vary between boards(PMIC variances causing delta in
voltage setup times as an example).. I suppose we have some way to
plug that data in as well? but irrelevant to this discussion. or maybe
some board would like to have a customized additional c state which is
not really practical for other platforms for what ever reasons..
c) if cpuidle where to get pm errata info, it is nice thing to do,
but, dont you think it is an overkill atm for just one errata?
d) omap_init_power_states may need some cleanups as well.. too many =
assignments IMHO..
e) On the topic of argument that the states controlled by
enable_off_mode is dynamic, though even though enable_off_mode is a
variable, it is in debugfs - not really a dynamic variant in a
product.. with that in mind, we may want to have off OR not have off
mode in a product board file and folks would probably call
omap3_pm_off_mode_enable or set the variable and set it to 1. That
makes it even more crazy IMHO.
f) Finally, where do we detect the erratas? it is more handy to have
them in one place - pm34xx.c was chosen to make it independent of
silicon type - pm44xx.c might endup having different set with it's own
requirements - so not all together convinced it should be in
pm.[ch]. I have tried to restrict the detection and usage purely to
the file that needs it - pm34xx.c
I think I agree to your overall thought that C state by itself
should'nt have been registered, but would'nt it be better to do the
cpuidle cleanups in a different context?
If you want to do all those cleanups, feel free. They all are valid.
However, your patch targets an isolated problem, and I'm OK with an
isolated fix.
All I was suggesting is moving the PM errata detection/macros etc. into
pm.h, and doing somthing simple (below) in CPUidle.
Kevin
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index 81b0a90..92873b4 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -452,6 +452,15 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
+
+/*
+ * Erratum i583: implementation for ES rev Es1.2 on 3630
+ * We cannot enable OFF mode in a stable form for previous
+ * revisions, transition instead to RET
+ */
+if (IS_PM34XX_ERRATUM(SDRC_WAKEUP_ERRATUM_i583)
+omap3_power_states[OMAP3_STATE_C7].valid = 0;
+ }
Look at the following sequence:
a) omap_init_power_states is called at init
omap3_power_states[OMAP3_STATE_C7].valid = 0
lets say we make cpuidle_params_table[OMAP3_STATE_C7].valid = 0 as
well here.
b) user enables enable_off_mode
omap3_pm_off_mode_enable(pm34xx.c) - calls omap3_cpuidle_update_states
for (i = OMAP3_STATE_C1; i OMAP3_MAX_STATES; i++) {
struct omap3_processor_cx *cx
[PATCH v6 00/10] OMAP: Adding Smartreflex and Voltage driver support
This patch series introduces smartreflex and voltage driver support for OMAP3430 and OMAP3630. SmartReflex modules do adaptive voltage control for real-time voltage adjustments. Originally all the functionalities introduced in this patch were present in arch/arm/mach-omap2/smartreflex.c file in Kevin's pm tree. This patch series does a major rewrite of this file and introduces a separate voltage driver. Major contributors to the original driver are Eduardo Valentin (1): OMAP3: PM: SmartReflex: Fix scheduled while atomic problem Kalle Jokiniemi (1): OMAP3: PM: SmartReflex driver integration Kevin Hilman (2): temp: SR: IO_ADDRESS conversion OMAP: SR: OPP interfaces removed from OMAP PM layer Nishanth Menon (1): omap3: pm: sr: replace get_opp with freq_to_opp Paul Walmsley (2): OMAP SR: use opp_find_opp_by_opp_id() OMAP SR: use OPP API for OPP ID, remove direct access Phil Carmody (2): OMAP3: PM: Don't do unnecessary searches in omap_sr_vdd*_autocomp_store OMAP3: PM: Early exit on invalid parameters Rajendra Nayak (9): OMAP3: SR: Fix init voltage on OPP change OMAP3: SR: Update VDD1/2 voltages at boot OMAP3: SR: Use sysclk for SR CLKLENGTH calc OMAP3: SR: Reset voltage level on SR disable OMAP3: SR: Replace printk's with pr_* calls OMAP3: SR: Remove redundant defines OMAP3: SR: Fix SR driver to check for omap-pm return values OMAP3: PM: Put optimal SMPS stabilization delay OMAP3: SR: Wait for VP idle before a VP disable Roger Quadros (4): OMAP3: PM: Fix Smartreflex when used with PM_NOOP layer OMAP3: PM: Make Smartreflex driver independent of SRF OMAP3: PM: Do not Enable SmartReflex if OPP tables not defined OMAP3: PM: Smartreflex: Fix VDD2 OPP determining logic Romit Dasgupta (1): omap: pm: SR: use enum for OPP types Teerth Reddy (1): OMAP3: SR: Replace SR_PASS/FAIL,SR_TRUE/FALSE Tero Kristo (1): Smartreflex: Avoid unnecessary spam This patch series is against pm-core branch of Kevin Hilman's OMAP PM tree with the following additional patch applied. https://patchwork.kernel.org/patch/421351/ The entire series with the dependencies are available at http://dev.omapzoom.org/?p=thara/omap-dvfs.git;a=summary head: kevin-pm-sr This patch series has been tested on OMAP3430 SDP with omap2plus_defconfig with the following menuconfig options enabled. System type - TI OMAP Implementations - Smartreflex Support System type - TI OMAP Implementations - Class 3 mode of Smartreflex Implementation Major Changes in v6 -Rebased to pm-core branch of Kevin Hilman's OMAP PM tree. Major Changes in v5 - Rebased to k.org 2.6.37-rc3 - Rebased to Nishant Menon's latest opp patches - Voltage pmic info structure extended to include a vast set of PMIC dependent parameters. - Smartreflex software n-target values support removed from the kernel. Instead n-target values are exposed as debugfs entries which can be written into by the user if needed. - Introduced a new file arch/arm/mach-omap2/omap_twl.c for specifying OMAP and TWL related info for the voltage layer. - Remove default enabling of smartreflex autocompensation during boot on OMAP3430 ES3.1 chips. Instead an API is provided that can be called from board files in case autocompensation needs to be enabled during boot up itself. - Other review comments on v4 Thara Gopinath (10): OMAP3: PM: Adding voltage driver support. OMAP: Introduce voltage domain information in the hwmod structures OMAP3: PM: Adding smartreflex driver support. OMAP3: PM: Adding smartreflex device file. OMAP3: PM: Adding smartreflex hwmod data OMAP3: PM: Adding smartreflex class3 driver OMAP3: PM: Adding T2 enabling of smartreflex support OMAP3: PM: Register TWL4030 pmic info with the voltage driver. OMAP3: PM: Adding debug support to Voltage and Smartreflex drivers OMAP3: PM: Program correct init voltages for VDD1 and VDD2 arch/arm/mach-omap2/Makefile |7 +- arch/arm/mach-omap2/control.h | 17 + arch/arm/mach-omap2/omap_hwmod_3xxx_data.c| 176 arch/arm/mach-omap2/omap_twl.c| 111 +++ arch/arm/mach-omap2/pm.c | 90 ++ arch/arm/mach-omap2/pm.h | 23 + arch/arm/mach-omap2/smartreflex-class3.c | 59 ++ arch/arm/mach-omap2/smartreflex.c | 1025 arch/arm/mach-omap2/sr_device.c | 131 +++ arch/arm/mach-omap2/voltage.c | 1292 + arch/arm/plat-omap/Kconfig| 31 + arch/arm/plat-omap/include/plat/omap_hwmod.h |5 +
[PATCH v6 04/10] OMAP3: PM: Adding smartreflex device file.
This patch adds support for device registration of various
smartreflex module present in the system. This patch introduces
the platform data for smartreflex devices which include
the efused n-target vaules, a parameter to indicate
whether smartreflex autocompensation needs to be
enabled on init or not. An API
omap_enable_smartreflex_on_init is provided for the
board files to enable smartreflex autocompensation during
system boot up.
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/Makefile|2 +-
arch/arm/mach-omap2/pm.c|2 +
arch/arm/mach-omap2/pm.h| 13
arch/arm/mach-omap2/sr_device.c | 131 +++
4 files changed, 147 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/sr_device.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b1bead0..4e6adbd 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -61,7 +61,7 @@ obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
voltage.o \
cpuidle34xx.o pm_bus.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
-obj-$(CONFIG_OMAP_SMARTREFLEX) += smartreflex.o
+obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 22adfb2..a05f590 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -21,6 +21,7 @@
#include powerdomain.h
#include clockdomain.h
+#include pm.h
static struct omap_device_pm_latency *pm_lats;
@@ -149,6 +150,7 @@ postcore_initcall(omap2_common_pm_init);
static int __init omap2_common_pm_late_init(void)
{
omap_voltage_late_init();
+ omap_devinit_smartreflex();
return 0;
}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 419c9d4..77d3ec2 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -11,6 +11,8 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
#define __ARCH_ARM_MACH_OMAP2_PM_H
+#include linux/err.h
+
#include powerdomain.h
extern void *omap3_secure_ram_storage;
@@ -99,4 +101,15 @@ extern unsigned int save_secure_ram_context_sz;
extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
+#ifdef CONFIG_OMAP_SMARTREFLEX
+extern int omap_devinit_smartreflex(void);
+extern void omap_enable_smartreflex_on_init(void);
+#else
+static inline int omap_devinit_smartreflex(void)
+{
+ return -EINVAL;
+}
+
+static inline void omap_enable_smartreflex_on_init(void) {}
+#endif
#endif
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
new file mode 100644
index 000..9a3538f
--- /dev/null
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -0,0 +1,131 @@
+/*
+ * OMAP3/OMAP4 smartreflex device file
+ *
+ * Author: Thara Gopinath th...@ti.com
+ *
+ * Based originally on code from smartreflex.c
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath th...@ti.com
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M x0080...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/err.h
+#include linux/slab.h
+
+#include plat/omap_device.h
+#include plat/smartreflex.h
+#include plat/voltage.h
+
+#include control.h
+
+static bool sr_enable_on_init;
+
+static struct omap_device_pm_latency omap_sr_latency[] = {
+ {
+ .deactivate_func = omap_device_idle_hwmods,
+ .activate_func = omap_device_enable_hwmods,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST
+ },
+};
+
+/* Read EFUSE values from control registers for OMAP3430 */
+static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
+ struct omap_sr_data *sr_data)
+{
+ struct omap_sr_nvalue_table *nvalue_table;
+ int i, count = 0;
+
+ while (volt_data[count].volt_nominal)
+ count++;
+
+ nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count,
+ GFP_KERNEL);
+
+ for (i = 0; i count; i++) {
+ u32 v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+
+ nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs;
+ nvalue_table[i].nvalue = v;
+ }
+
+ sr_data-nvalue_table = nvalue_table;
+ sr_data-nvalue_count = count;
+}
+
+static int sr_dev_init(struct omap_hwmod *oh, void *user)
+{
+ struct omap_sr_data *sr_data;
+ struct omap_device *od;
+ struct omap_volt_data *volt_data;
+ char *name =
[PATCH v6 02/10] OMAP: Introduce voltage domain information in the hwmod structures
This patch extends the device hwmod structure to contain
info about the voltage domain to which the device belongs to.
This is needed to support a device based DVFS where the
device knows which voltage domain it belongs to.
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/plat-omap/include/plat/omap_hwmod.h |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h
b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 62bdb23..09c46c1 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -34,6 +34,7 @@
#include linux/ioport.h
#include linux/spinlock.h
#include plat/cpu.h
+#include plat/voltage.h
struct omap_device;
@@ -449,6 +450,8 @@ struct omap_hwmod_class {
* @main_clk: main clock: OMAP clock name
* @_clk: pointer to the main struct clk (filled in at runtime)
* @opt_clks: other device clocks that drivers can request (0..*)
+ * @vdd_name: voltage domain name
+ * @voltdm: pointer to voltage domain (filled in at runtime)
* @masters: ptr to array of OCP ifs that this hwmod can initiate on
* @slaves: ptr to array of OCP ifs that this hwmod can respond on
* @dev_attr: arbitrary device attributes that can be passed to the driver
@@ -491,6 +494,8 @@ struct omap_hwmod {
const char *main_clk;
struct clk *_clk;
struct omap_hwmod_opt_clk *opt_clks;
+ char*vdd_name;
+ struct voltagedomain*voltdm;
struct omap_hwmod_ocp_if**masters; /* connect to *_IA */
struct omap_hwmod_ocp_if**slaves; /* connect to *_TA */
void*dev_attr;
--
1.7.0.4
--
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[PATCH v6 06/10] OMAP3: PM: Adding smartreflex class3 driver
Smartreflex Class3 implementation continuously monitors
silicon performance and instructs the Voltage Processors
to increase or decrease the voltage.
This patch adds smartreflex class 3 driver. This driver hooks
up with the generic smartreflex driver smartreflex.c to abstract
out class specific implementations out of the generic driver.
Class3 driver is chosen as the default class driver for smartreflex.
If any other class driver needs to be implemented, the init of that
driver should be called from the board file. That way the new class driver
will over-ride the Class3 driver.
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/Makefile |1 +
arch/arm/mach-omap2/smartreflex-class3.c | 59 ++
arch/arm/plat-omap/Kconfig |9 +
3 files changed, 69 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/smartreflex-class3.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 4e6adbd..1963f9e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
voltage.o \
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
+obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c
b/arch/arm/mach-omap2/smartreflex-class3.c
new file mode 100644
index 000..60e7055
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -0,0 +1,59 @@
+/*
+ * Smart reflex Class 3 specific implementations
+ *
+ * Author: Thara Gopinath th...@ti.com
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath th...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include plat/smartreflex.h
+
+static int sr_class3_enable(struct voltagedomain *voltdm)
+{
+ unsigned long volt = omap_voltage_get_nom_volt(voltdm);
+
+ if (!volt) {
+ pr_warning(%s: Curr voltage unknown. Cannot enable sr_%s\n,
+ __func__, voltdm-name);
+ return -ENODATA;
+ }
+
+ omap_vp_enable(voltdm);
+ return sr_enable(voltdm, volt);
+}
+
+static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
+{
+ omap_vp_disable(voltdm);
+ sr_disable(voltdm);
+ if (is_volt_reset)
+ omap_voltage_reset(voltdm);
+
+ return 0;
+}
+
+static int sr_class3_configure(struct voltagedomain *voltdm)
+{
+ return sr_configure_errgen(voltdm);
+}
+
+/* SR class3 structure */
+static struct omap_sr_class_data class3_data = {
+ .enable = sr_class3_enable,
+ .disable = sr_class3_disable,
+ .configure = sr_class3_configure,
+ .class_type = SR_CLASS3,
+};
+
+/* Smartreflex Class3 init API to be called from board file */
+static int __init sr_class3_init(void)
+{
+ pr_info(SmartReflex Class3 initialized\n);
+ return sr_register_class(class3_data);
+}
+late_initcall(sr_class3_init);
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 95ceca0..4029e6a 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -57,6 +57,15 @@ config OMAP_SMARTREFLEX
by default during system init via the enable_on_init flag
which an be passed as platform data to the smartreflex driver.
+config OMAP_SMARTREFLEX_CLASS3
+ bool Class 3 mode of Smartreflex Implementation
+ depends on OMAP_SMARTREFLEX TWL4030_CORE
+ help
+ Say Y to enable Class 3 implementation of Smartreflex
+
+ Class 3 implementation of Smartreflex employs continuous hardware
+ voltage calibration.
+
config OMAP_RESET_CLOCKS
bool Reset unused clocks during boot
depends on ARCH_OMAP
--
1.7.0.4
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[PATCH v6 05/10] OMAP3: PM: Adding smartreflex hwmod data
This patch adds the smartreflex hwmod data for OMAP3430
and OMAP3630.
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 176
1 files changed, 176 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8eb81b4..c98cfc0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -21,6 +21,8 @@
#include plat/l4_3xxx.h
#include plat/i2c.h
#include plat/gpio.h
+#include plat/smartreflex.h
+#include plat/smartreflex.h
#include omap_hwmod_common_data.h
@@ -52,6 +54,8 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod;
static struct omap_hwmod omap3xxx_gpio4_hwmod;
static struct omap_hwmod omap3xxx_gpio5_hwmod;
static struct omap_hwmod omap3xxx_gpio6_hwmod;
+static struct omap_hwmod omap34xx_sr1_hwmod;
+static struct omap_hwmod omap34xx_sr2_hwmod;
/* L3 - L4_CORE interface */
static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -260,9 +264,47 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* L4 CORE - SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
+ {
+ .pa_start = OMAP34XX_SR1_BASE,
+ .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
+ .master = omap3xxx_l4_core_hwmod,
+ .slave = omap34xx_sr1_hwmod,
+ .clk= sr_l4_ick,
+ .addr = omap3_sr1_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
+ .user = OCP_USER_MPU,
+};
+
+/* L4 CORE - SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
+ {
+ .pa_start = OMAP34XX_SR2_BASE,
+ .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
+ .master = omap3xxx_l4_core_hwmod,
+ .slave = omap34xx_sr2_hwmod,
+ .clk= sr_l4_ick,
+ .addr = omap3_sr2_addr_space,
+ .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
+ .user = OCP_USER_MPU,
+};
+
/* Slave interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
omap3xxx_l3_main__l4_core,
+ omap3_l4_core__sr1,
+ omap3_l4_core__sr2,
};
/* Master interfaces on the L4_CORE interconnect */
@@ -1092,6 +1134,135 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
+/* SR common */
+static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
+ .clkact_shift = 20,
+};
+
+static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
+ .sysc_offs = 0x24,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
+ .clockact = CLOCKACT_TEST_ICLK,
+ .sysc_fields= omap34xx_sr_sysc_fields,
+};
+
+static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
+ .name = smartreflex,
+ .sysc = omap34xx_sr_sysc,
+ .rev = 1,
+};
+
+static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
+ .sidle_shift= 24,
+ .enwkup_shift = 26
+};
+
+static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
+ .sysc_offs = 0x38,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+ SYSC_NO_CACHE),
+ .sysc_fields= omap36xx_sr_sysc_fields,
+};
+
+static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
+ .name = smartreflex,
+ .sysc = omap36xx_sr_sysc,
+ .rev = 2,
+};
+
+/* SR1 */
+static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
+ omap3_l4_core__sr1,
+};
+
+static struct omap_hwmod omap34xx_sr1_hwmod = {
+ .name = sr1_hwmod,
+ .class = omap34xx_smartreflex_hwmod_class,
+ .main_clk = sr1_fck,
+ .vdd_name = mpu,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_SR1_SHIFT,
+ .module_offs = WKUP_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
+ },
+ },
+ .slaves = omap3_sr1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
+ CHIP_IS_OMAP3430ES3_0 |
+ CHIP_IS_OMAP3430ES3_1),
+ .flags
[PATCH v6 07/10] OMAP3: PM: Adding T2 enabling of smartreflex support
This patch adds support in the twl4030 driver to enable smartreflex.
The smartreflex bit on twl4030 needs to be enabled by default irrespective
of whether smartreflex module is enabled on the OMAP side or not.
This is because without this bit enabled the voltage scaling through
vp forceupdate does not function properly.
Signed-off-by: Thara Gopinath th...@ti.com
---
drivers/mfd/twl-core.c | 13 +
include/linux/i2c/twl.h | 11 +++
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 35275ba..b895ceb 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -1046,6 +1046,7 @@ twl_probe(struct i2c_client *client, const struct
i2c_device_id *id)
/* Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
* Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
* SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
+* Also enable the smartreflex I2S bit.
*/
if (twl_class_is_4030()) {
@@ -1053,6 +1054,18 @@ twl_probe(struct i2c_client *client, const struct
i2c_device_id *id)
temp = ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \
I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
+
+ /* The smartreflex bit on twl4030 needs to be enabled by
+* default irrespective of whether smartreflex module is
+* enabled on the OMAP side or not. This is because without
+* this bit enabled the voltage scaling through
+* vp forceupdate does not function properly.
+*/
+ twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_PM_RECEIVER_DCDC_GLOBAL_CFG);
+ temp |= SMARTREFLEX_ENABLE;
+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_PM_RECEIVER_DCDC_GLOBAL_CFG);
}
status = add_children(pdata, id-driver_data);
diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index c760991..d392f06 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -434,6 +434,17 @@ static inline int twl6030_mmc_card_detect(struct device
*dev, int slot)
/*--*/
+/*
+ * PM Receiver module register offsets (use TWL4030_MODULE_PM_RECEIVER)
+ */
+
+#define TWL4030_PM_RECEIVER_DCDC_GLOBAL_CFG0x06
+
+/* Smartreflex I2S bus enable/ vmode enable bit */
+#define SMARTREFLEX_ENABLE BIT(3)
+
+/*--*/
+
/* Power bus message definitions */
/* The TWL4030/5030 splits its power-management resources (the various
--
1.7.0.4
--
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[PATCH v6 09/10] OMAP3: PM: Adding debug support to Voltage and Smartreflex drivers
This patch adds debug support to the voltage and smartreflex drivers.
This means a whole bunch of voltage processor and smartreflex
parameters are now visible through the pm debugfs.
The voltage parameters can be viewed at
/debug/voltage/vdd_x/parameter
and the smartreflex parameters can be viewed at
/debug/voltage/vdd_x/smartreflex/parameter
Also smartreflex n-target values are now exposed out at
/debug/voltage/vdd_x/smartreflex/nvalue/voltage
The interface to access smartreflex n-target values is a
read-write interface which means user has the flexibility
to change the n-target values for any opp.
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/smartreflex.c | 46 -
arch/arm/mach-omap2/voltage.c | 66 +
2 files changed, 110 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index eee23d0..52a05b3 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -31,6 +31,7 @@
#include pm.h
#define SMARTREFLEX_NAME_LEN 16
+#define NVALUE_NAME_LEN40
#define SR_DISABLE_TIMEOUT 200
struct omap_sr {
@@ -817,8 +818,9 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
struct omap_sr_data *pdata = pdev-dev.platform_data;
struct resource *mem, *irq;
- struct dentry *vdd_dbg_dir, *dbg_dir;
- int ret = 0;
+ struct dentry *vdd_dbg_dir, *dbg_dir, *nvalue_dir;
+ struct omap_volt_data *volt_data;
+ int i, ret = 0;
if (!sr_info) {
dev_err(pdev-dev, %s: unable to allocate sr_info\n,
@@ -897,6 +899,46 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
(void) debugfs_create_file(autocomp, S_IRUGO | S_IWUGO, dbg_dir,
(void *)sr_info, pm_sr_fops);
+ (void) debugfs_create_x32(errweight, S_IRUGO, dbg_dir,
+ sr_info-err_weight);
+ (void) debugfs_create_x32(errmaxlimit, S_IRUGO, dbg_dir,
+ sr_info-err_maxlimit);
+ (void) debugfs_create_x32(errminlimit, S_IRUGO, dbg_dir,
+ sr_info-err_minlimit);
+
+ nvalue_dir = debugfs_create_dir(nvalue, dbg_dir);
+ if (IS_ERR(nvalue_dir)) {
+ dev_err(pdev-dev, %s: Unable to create debugfs directory
+ for n-values\n, __func__);
+ return PTR_ERR(nvalue_dir);
+ }
+
+ omap_voltage_get_volttable(sr_info-voltdm, volt_data);
+ if (!volt_data) {
+ dev_warn(pdev-dev, %s: No Voltage table for the
+corresponding vdd vdd_%s. Cannot create debugfs
+ entries for n-values\n,
+ __func__, sr_info-voltdm-name);
+ return -ENODATA;
+ }
+
+ for (i = 0; i sr_info-nvalue_count; i++) {
+ char *name;
+ char volt_name[32];
+
+ name = kzalloc(NVALUE_NAME_LEN + 1, GFP_KERNEL);
+ if (!name) {
+ dev_err(pdev-dev, %s: Unable to allocate memory
+for n-value directory name\n, __func__);
+ return -ENOMEM;
+ }
+
+ strcpy(name, volt_);
+ sprintf(volt_name, %d, volt_data[i].volt_nominal);
+ strcat(name, volt_name);
+ (void) debugfs_create_x32(name, S_IRUGO | S_IWUGO, nvalue_dir,
+ (sr_info-nvalue_table[i].nvalue));
+ }
return ret;
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 875667f..b27fa4f 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -250,6 +250,47 @@ static void omap3_voltage_write_reg(u32 val, u16 mod, u8
offset)
omap2_prm_write_mod_reg(val, mod, offset);
}
+/* Voltage debugfs support */
+static int vp_volt_debug_get(void *data, u64 *val)
+{
+ struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
+ u8 vsel;
+
+ if (!vdd) {
+ pr_warning(Wrong paramater passed\n);
+ return -EINVAL;
+ }
+
+ vsel = vdd-read_reg(vdd-vp_reg.prm_mod, vdd-vp_offs.voltage);
+ pr_notice(curr_vsel = %x\n, vsel);
+
+ if (!vdd-pmic_info-vsel_to_uv) {
+ pr_warning(PMIC function to convert vsel to voltage
+ in uV not registerd\n);
+ return -EINVAL;
+ }
+
+ *val = vdd-pmic_info-vsel_to_uv(vsel);
+ return 0;
+}
+
+static int nom_volt_debug_get(void *data, u64 *val)
+{
+ struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
+
+ if (!vdd) {
+ pr_warning(Wrong paramater passed\n);
+ return -EINVAL;
+ }
+
+ *val =
[PATCH v6 08/10] OMAP3: PM: Register TWL4030 pmic info with the voltage driver.
This patch registers the TWL4030 PMIC specific informtion
with the voltage driver. Failing this patch the voltage driver
is unware of the formula to use for vsel to voltage and vice versa
conversion and lot of other PMIC dependent parameters.
This file is based on the arch/arm/plat-omap opp_twl_tpl.c file
by Paul Walmsley. The original file is replaced by this file.
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/Makefile |2 +
arch/arm/mach-omap2/omap_twl.c | 111
arch/arm/mach-omap2/pm.c |4 ++
arch/arm/mach-omap2/pm.h | 10
4 files changed, 127 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/omap_twl.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 1963f9e..ae29a00 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -18,6 +18,8 @@ obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common)
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
+obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
+
# SMP support ONLY available for OMAP4
obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
new file mode 100644
index 000..b8f0874
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -0,0 +1,111 @@
+/**
+ * OMAP and TWL PMIC specific intializations.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated.
+ * Thara Gopinath
+ * Copyright (C) 2009 Texas Instruments Incorporated.
+ * Nishanth Menon
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/err.h
+#include linux/io.h
+#include linux/kernel.h
+
+#include plat/voltage.h
+
+#define OMAP3_SRI2C_SLAVE_ADDR 0x12
+#define OMAP3_VDD_MPU_SR_CONTROL_REG 0x00
+#define OMAP3_VDD_CORE_SR_CONTROL_REG 0x01
+#define OMAP3_VP_CONFIG_ERROROFFSET0x00
+#define OMAP3_VP_VSTEPMIN_VSTEPMIN 0x1
+#define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04
+#define OMAP3_VP_VLIMITTO_TIMEOUT_US 200
+
+#define OMAP3430_VP1_VLIMITTO_VDDMIN 0x14
+#define OMAP3430_VP1_VLIMITTO_VDDMAX 0x42
+#define OMAP3430_VP2_VLIMITTO_VDDMIN 0x18
+#define OMAP3430_VP2_VLIMITTO_VDDMAX 0x2c
+
+#define OMAP3630_VP1_VLIMITTO_VDDMIN 0x18
+#define OMAP3630_VP1_VLIMITTO_VDDMAX 0x3c
+#define OMAP3630_VP2_VLIMITTO_VDDMIN 0x18
+#define OMAP3630_VP2_VLIMITTO_VDDMAX 0x30
+
+unsigned long twl4030_vsel_to_uv(const u8 vsel)
+{
+ return (((vsel * 125) + 6000)) * 100;
+}
+
+u8 twl4030_uv_to_vsel(unsigned long uv)
+{
+ return DIV_ROUND_UP(uv - 60, 12500);
+}
+
+static struct omap_volt_pmic_info omap3_mpu_volt_info = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .on_volt= 120,
+ .onlp_volt = 100,
+ .ret_volt = 975000,
+ .off_volt = 60,
+ .volt_setup_time= 0xfff,
+ .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin= OMAP3_VP_VSTEPMIN_VSTEPMIN,
+ .vp_vstepmax= OMAP3_VP_VSTEPMAX_VSTEPMAX,
+ .vp_vddmin = OMAP3430_VP1_VLIMITTO_VDDMIN,
+ .vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX,
+ .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
+ .pmic_reg = OMAP3_VDD_MPU_SR_CONTROL_REG,
+ .vsel_to_uv = twl4030_vsel_to_uv,
+ .uv_to_vsel = twl4030_uv_to_vsel,
+};
+
+static struct omap_volt_pmic_info omap3_core_volt_info = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .on_volt= 120,
+ .onlp_volt = 100,
+ .ret_volt = 975000,
+ .off_volt = 60,
+ .volt_setup_time= 0xfff,
+ .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin= OMAP3_VP_VSTEPMIN_VSTEPMIN,
+ .vp_vstepmax= OMAP3_VP_VSTEPMAX_VSTEPMAX,
+ .vp_vddmin = OMAP3430_VP2_VLIMITTO_VDDMIN,
+ .vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX,
+ .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
+ .pmic_reg = OMAP3_VDD_CORE_SR_CONTROL_REG,
+ .vsel_to_uv = twl4030_vsel_to_uv,
+ .uv_to_vsel = twl4030_uv_to_vsel,
+};
+
+int __init omap3_twl_init(void)
+{
+ struct voltagedomain *voltdm;
+
+ if (!cpu_is_omap34xx())
+ return -ENODEV;
+
+ if (cpu_is_omap3630()) {
+
[PATCH v6 10/10] OMAP3: PM: Program correct init voltages for VDD1 and VDD2
By default the system boots up at nominal voltage for every
voltage domain in the system. This patch puts VDD1 and VDD2
to the correct boot up voltage as per the opp tables specified.
This patch implements this by matching the rate of the main clock
of the voltage domain with the opp table and picking up the correct
voltage.
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/pm.c | 76 ++
1 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index e84f46b..cee86a5 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -13,6 +13,7 @@
#include linux/init.h
#include linux/io.h
#include linux/err.h
+#include linux/opp.h
#include plat/omap-pm.h
#include plat/omap_device.h
@@ -138,6 +139,76 @@ err:
return ret;
}
+/*
+ * This API is to be called during init to put the various voltage
+ * domains to the voltage as per the opp table. Typically we boot up
+ * at the nominal voltage. So this function finds out the rate of
+ * the clock associated with the voltage domain, finds out the correct
+ * opp entry and puts the voltage domain to the voltage specifies
+ * in the opp entry
+ */
+static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
+ struct device *dev)
+{
+ struct voltagedomain *voltdm;
+ struct clk *clk;
+ struct opp *opp;
+ unsigned long freq, bootup_volt;
+
+ if (!vdd_name || !clk_name || !dev) {
+ printk(KERN_ERR %s: Invalid parameters!\n, __func__);
+ goto exit;
+ }
+
+ voltdm = omap_voltage_domain_lookup(vdd_name);
+ if (IS_ERR(voltdm)) {
+ printk(KERN_ERR %s: Unable to get vdd pointer for vdd_%s\n,
+ __func__, vdd_name);
+ goto exit;
+ }
+
+ clk = clk_get(NULL, clk_name);
+ if (IS_ERR(clk)) {
+ printk(KERN_ERR %s: unable to get clk %s\n,
+ __func__, clk_name);
+ goto exit;
+ }
+
+ freq = clk-rate;
+ clk_put(clk);
+
+ opp = opp_find_freq_ceil(dev, freq);
+ if (IS_ERR(opp)) {
+ printk(KERN_ERR %s: unable to find boot up OPP for vdd_%s\n,
+ __func__, vdd_name);
+ goto exit;
+ }
+
+ bootup_volt = opp_get_voltage(opp);
+ if (!bootup_volt) {
+ printk(KERN_ERR %s: unable to find voltage corresponding
+ to the bootup OPP for vdd_%s\n, __func__, vdd_name);
+ goto exit;
+ }
+
+ omap_voltage_scale_vdd(voltdm, bootup_volt);
+ return 0;
+
+exit:
+ printk(KERN_ERR %s: Unable to put vdd_%s to its init voltage\n\n,
+ __func__, vdd_name);
+ return -EINVAL;
+}
+
+static void __init omap3_init_voltages(void)
+{
+ if (!cpu_is_omap34xx())
+ return;
+
+ omap2_set_init_voltage(mpu, dpll1_ck, mpu_dev);
+ omap2_set_init_voltage(core, l3_ick, l3_dev);
+}
+
static int __init omap2_common_pm_init(void)
{
omap2_init_processor_devices();
@@ -151,8 +222,13 @@ static int __init omap2_common_pm_late_init(void)
{
/* Init the OMAP TWL parameters */
omap3_twl_init();
+
/* Init the voltage layer */
omap_voltage_late_init();
+
+ /* Initialize the voltages */
+ omap3_init_voltages();
+
/* Smartreflex device init */
omap_devinit_smartreflex();
--
1.7.0.4
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[PATCH v6 03/10] OMAP3: PM: Adding smartreflex driver support.
SmartReflex modules do adaptive voltage control for real-time
voltage adjustments. With Smartreflex the power supply voltage
can be adapted to the silicon performance(manufacturing process,
temperature induced performance, age induced performance etc).
There are differnet classes of smartreflex implementation.
Class-0: Manufacturing Test Calibration
Class-1: Boot-Time Software Calibration
Class-2: Continuous Software Calibration
Class-3: Continuous Hardware Calibration
Class-4: Fully Integrated Power Management
OMAP3 has two smartreflex modules one associated with VDD MPU and the
other associated with VDD CORE.
This patch adds support for smartreflex driver. The driver is designed
for Class-1 , Class-2 and Class-3 support and is a platform driver.
Smartreflex driver can be enabled through a Kconfig option
SmartReflex support under System type-TI OMAP implementations menu.
Smartreflex autocompensation feature can be enabled runtime through
a debug fs option.
To enable smartreflex autocompensation feature
echo 1 /debug/voltage/vdd_X/smartreflex/autocomp
To disable smartreflex autocompensation feature
echo 0 /debug/voltage/vdd_X/smartreflex/autocomp
where X can be mpu, core , iva etc.
This patch contains code originally in linux omap pm branch.
Major contributors to this driver are
Lesly A M, Rajendra Nayak, Kalle Jokiniemi, Paul Walmsley,
Nishant Menon, Kevin Hilman.
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/Makefile |1 +
arch/arm/mach-omap2/smartreflex.c | 983 +
arch/arm/plat-omap/Kconfig| 22 +
arch/arm/plat-omap/include/plat/smartreflex.h | 245 ++
4 files changed, 1251 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/smartreflex.c
create mode 100644 arch/arm/plat-omap/include/plat/smartreflex.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 5034797..b1bead0 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
voltage.o \
cpuidle34xx.o pm_bus.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
+obj-$(CONFIG_OMAP_SMARTREFLEX) += smartreflex.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
new file mode 100644
index 000..eee23d0
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -0,0 +1,983 @@
+/*
+ * OMAP SmartReflex Voltage Control
+ *
+ * Author: Thara Gopinath th...@ti.com
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath th...@ti.com
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M x0080...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/interrupt.h
+#include linux/clk.h
+#include linux/io.h
+#include linux/debugfs.h
+#include linux/delay.h
+#include linux/slab.h
+#include linux/pm_runtime.h
+
+#include plat/common.h
+#include plat/smartreflex.h
+
+#include pm.h
+
+#define SMARTREFLEX_NAME_LEN 16
+#define SR_DISABLE_TIMEOUT 200
+
+struct omap_sr {
+ int srid;
+ int ip_type;
+ int nvalue_count;
+ boolautocomp_active;
+ u32 clk_length;
+ u32 err_weight;
+ u32 err_minlimit;
+ u32 err_maxlimit;
+ u32 accum_data;
+ u32 senn_avgweight;
+ u32 senp_avgweight;
+ u32 senp_mod;
+ u32 senn_mod;
+ unsigned intirq;
+ void __iomem*base;
+ struct platform_device *pdev;
+ struct list_headnode;
+ struct omap_sr_nvalue_table *nvalue_table;
+ struct voltagedomain*voltdm;
+};
+
+/* sr_list contains all the instances of smartreflex module */
+static LIST_HEAD(sr_list);
+
+static struct omap_sr_class_data *sr_class;
+static struct omap_sr_pmic_data *sr_pmic_data;
+
+static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
+{
+ __raw_writel(value, (sr-base + offset));
+}
+
+static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
[PATCH v6 01/10] OMAP3: PM: Adding voltage driver support.
This patch adds voltage driver support for OMAP3. The driver allows configuring the voltage controller and voltage processors during init and exports APIs to enable/disable voltage processors, scale voltage and reset voltage. The driver maintains the global voltage table on a per VDD basis which contains the various voltages supported by the VDD along with per voltage dependent data like smartreflex efuse offset, errminlimit and voltage processor errorgain. The driver also allows the voltage parameters dependent on the PMIC to be passed from the PMIC file through an API. The driver allows scaling of VDD voltages either through vc bypass method or through vp forceupdate method the choice being configurable through the board file. This patch contains code originally in linux omap pm branch smartreflex driver. Major contributors to this driver are Lesly A M, Rajendra Nayak, Kalle Jokiniemi, Paul Walmsley, Nishant Menon, Kevin Hilman. The separation of PMIC parameters into a separate structure which can be populated from the PMIC file is based on the work of Lun Chang from Motorola in an internal tree. Signed-off-by: Thara Gopinath th...@ti.com --- This patch has 14 checkpatch.pl above 80-chars warnings for the definitions of omap34xx_vddmpu_volt_data, omap36xx_vddmpu_volt_data, omap34xx_vddcore_volt_data and omap36xx_vddcore_volt_data structures. IMHO splitting of the entries in these structures affects readability and looks very ugly. Hence they are left as is. arch/arm/mach-omap2/Makefile |3 +- arch/arm/mach-omap2/control.h | 17 + arch/arm/mach-omap2/pm.c |8 + arch/arm/mach-omap2/voltage.c | 1226 + arch/arm/plat-omap/include/plat/voltage.h | 134 5 files changed, 1387 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-omap2/voltage.c create mode 100644 arch/arm/plat-omap/include/plat/voltage.h diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 7c79683..5034797 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -57,7 +57,8 @@ endif ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o -obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o +obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o voltage.o \ + cpuidle34xx.o pm_bus.o obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index 5289461..9fe32dc 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -148,6 +148,15 @@ #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) +#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) +#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) +#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) +#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) +#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) +#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) +#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) +#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) +#define OMAP343X_CONTROL_FUSE_SR(OMAP2_CONTROL_GENERAL + 0x0130) #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ @@ -164,6 +173,14 @@ #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) +/* OMAP3630 only CONTROL_GENERAL register offsets */ +#define OMAP3630_CONTROL_FUSE_OPP1G_VDD1(OMAP2_CONTROL_GENERAL + 0x0110) +#define OMAP3630_CONTROL_FUSE_OPP50_VDD1(OMAP2_CONTROL_GENERAL + 0x0114) +#define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) +#define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) +#define OMAP3630_CONTROL_FUSE_OPP50_VDD2(OMAP2_CONTROL_GENERAL + 0x0128) +#define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C) + /* AM35XX only CONTROL_GENERAL register offsets */ #define AM35XX_CONTROL_MSUSPENDMUX_6(OMAP2_CONTROL_GENERAL + 0x0038) #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 227a211..22adfb2 100644 --- a/arch/arm/mach-omap2/pm.c +++
[PATCH v5 3/5] OMAP4: PM: Program correct init voltages for scalable VDDs
By default the system boots up at nominal voltage for every
voltage domain in the system. This patch puts vdd_mpu, vdd_iva
and vdd_core to the correct boot up voltage as per the opp tables
specified. This patch implements this by matching the rate of
the main clock of the voltage domain with the opp table and
picking up the correct voltage.
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/pm.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 8d0b03b..2e80de8 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -209,6 +209,16 @@ static void __init omap3_init_voltages(void)
omap2_set_init_voltage(core, l3_ick, l3_dev);
}
+static void __init omap4_init_voltages(void)
+{
+ if (!cpu_is_omap44xx())
+ return;
+
+ omap2_set_init_voltage(mpu, dpll_mpu_ck, mpu_dev);
+ omap2_set_init_voltage(core, l3_div_ck, l3_dev);
+ omap2_set_init_voltage(iva, dpll_iva_m5x2_ck, iva_dev);
+}
+
static int __init omap2_common_pm_init(void)
{
omap2_init_processor_devices();
@@ -229,6 +239,7 @@ static int __init omap2_common_pm_late_init(void)
/* Initialize the voltages */
omap3_init_voltages();
+ omap4_init_voltages();
/* Smartreflex device init */
omap_devinit_smartreflex();
--
1.7.0.4
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[PATCH v5 4/5] OMAP4: hwmod: Add inital data for smartreflex modules.
From: Benoit Cousson b-cous...@ti.com
This patch adds the hwmod details for OMAP4 smartreflex modules.
Signed-off-by: Benoit Cousson b-cous...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 168
1 files changed, 168 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7367648..0a6e674 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1740,6 +1740,169 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+/*
+ * 'smartreflex' class
+ * smartreflex module (monitor silicon performance and outputs a measure of
+ * performance error)
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
+ .sidle_shift= 24,
+ .enwkup_shift = 26,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
+ .sysc_offs = 0x0038,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type_smartreflex,
+};
+
+static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
+ .name = smartreflex,
+ .sysc = omap44xx_smartreflex_sysc,
+ .rev = 2,
+};
+
+/* smartreflex_core */
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
+ { .irq = 19 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
+ {
+ .pa_start = 0x4a0dd000,
+ .pa_end = 0x4a0dd03f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_cfg - smartreflex_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
+ .master = omap44xx_l4_cfg_hwmod,
+ .slave = omap44xx_smartreflex_core_hwmod,
+ .clk= l4_div_ck,
+ .addr = omap44xx_smartreflex_core_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_core slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
+ omap44xx_l4_cfg__smartreflex_core,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+ .name = smartreflex_core,
+ .class = omap44xx_smartreflex_hwmod_class,
+ .mpu_irqs = omap44xx_smartreflex_core_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
+ .main_clk = smartreflex_core_fck,
+ .vdd_name = core,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_smartreflex_core_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* smartreflex_iva */
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
+ { .irq = 102 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
+ {
+ .pa_start = 0x4a0db000,
+ .pa_end = 0x4a0db03f,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l4_cfg - smartreflex_iva */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
+ .master = omap44xx_l4_cfg_hwmod,
+ .slave = omap44xx_smartreflex_iva_hwmod,
+ .clk= l4_div_ck,
+ .addr = omap44xx_smartreflex_iva_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_iva slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
+ omap44xx_l4_cfg__smartreflex_iva,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+ .name = smartreflex_iva,
+ .class = omap44xx_smartreflex_hwmod_class,
+ .mpu_irqs = omap44xx_smartreflex_iva_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
+ .main_clk = smartreflex_iva_fck,
+ .vdd_name = iva,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_smartreflex_iva_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
[PATCH v5 5/5] OMAP4: Smartreflex framework extensions
This patch extends the smartreflex framework to support
OMAP4. The changes are minor like compiling smartreflex Kconfig
option for OMAP4 also, and a couple of OMAP4 checks in
the smartreflex framework.
The change in sr_device.c where new logic has to be introduced
for reading the efuse registers is due to the fact that in OMAP4
the efuse registers are 24 bit aligned. A __raw_readl will
fail for non-32 bit aligned address and hence the 8-bit read
and shift.
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/smartreflex.c |8 ++--
arch/arm/mach-omap2/sr_device.c | 17 -
arch/arm/plat-omap/Kconfig|2 +-
3 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index 52a05b3..77ecebf 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -153,7 +153,11 @@ static void sr_set_clk_length(struct omap_sr *sr)
struct clk *sys_ck;
u32 sys_clk_speed;
- sys_ck = clk_get(NULL, sys_ck);
+ if (cpu_is_omap34xx())
+ sys_ck = clk_get(NULL, sys_ck);
+ else
+ sys_ck = clk_get(NULL, sys_clkin_ck);
+
if (IS_ERR(sys_ck)) {
dev_err(sr-pdev-dev, %s: unable to get sys clk\n,
__func__);
@@ -193,7 +197,7 @@ static void sr_set_regfields(struct omap_sr *sr)
* file or pmic specific data structure. In that case these structure
* fields will have to be populated using the pdata or pmic structure.
*/
- if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
sr-err_weight = OMAP3430_SR_ERRWEIGHT;
sr-err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
sr-accum_data = OMAP3430_SR_ACCUMDATA;
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 9a3538f..786d685 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -20,6 +20,7 @@
#include linux/err.h
#include linux/slab.h
+#include linux/io.h
#include plat/omap_device.h
#include plat/smartreflex.h
@@ -51,7 +52,21 @@ static void __init sr_set_nvalues(struct omap_volt_data
*volt_data,
GFP_KERNEL);
for (i = 0; i count; i++) {
- u32 v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+ u32 v;
+ /*
+* In OMAP4 the efuse registers are 24 bit aligned.
+* A __raw_readl will fail for non-32 bit aligned address
+* and hence the 8-bit read and shift.
+*/
+ if (cpu_is_omap44xx()) {
+ u16 offset = volt_data[i].sr_efuse_offs;
+
+ v = omap_ctrl_readb(offset) |
+ omap_ctrl_readb(offset + 1) 8 |
+ omap_ctrl_readb(offset + 2) 16;
+ } else {
+v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+ }
nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs;
nvalue_table[i].nvalue = v;
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 4029e6a..88ff484 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -37,7 +37,7 @@ config OMAP_DEBUG_LEDS
config OMAP_SMARTREFLEX
bool SmartReflex support
- depends on ARCH_OMAP3 PM
+ depends on (ARCH_OMAP3 || ARCH_OMAP4) PM
help
Say Y if you want to enable SmartReflex.
--
1.7.0.4
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Re: [PATCH 0/2] staging: tidspbridge: fix dma race condition
On Mon, Dec 20, 2010 at 4:25 PM, Felipe Contreras felipe.contre...@nokia.com wrote: I found a race condition that triggers a kernel panic. It's explained in the following patches, but basically the map_obj that contains the user pages is being destroyed while doing a DMA operation (which requires that map_obj). My solution is to convert the spinlock to a semaphore, and exten the area protected (which might sleep). I have not tested these specific patches; they have been forward ported. But in a similar branch, they solve the issue. Please disregard this patch series, I'll send a simpler single patch that does the trick. -- Felipe Contreras -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] staging: tidspbridge: protect dmm_map properly
We need to protect not only the dmm_map list, but the individual
map_obj's, otherwise, we might be building the scatter-gather list with
garbage. So, use the existing proc_lock for that.
I observed race conditions which caused kernel panics while running
stress tests. This patch fixes those.
Signed-off-by: Felipe Contreras felipe.contre...@nokia.com
---
drivers/staging/tidspbridge/rmgr/proc.c | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/tidspbridge/rmgr/proc.c
b/drivers/staging/tidspbridge/rmgr/proc.c
index b47d7aa..21052e3 100644
--- a/drivers/staging/tidspbridge/rmgr/proc.c
+++ b/drivers/staging/tidspbridge/rmgr/proc.c
@@ -781,12 +781,14 @@ int proc_begin_dma(void *hprocessor, void *pmpu_addr, u32
ul_size,
(u32)pmpu_addr,
ul_size, dir);
+ mutex_lock(proc_lock);
+
/* find requested memory are in cached mapping information */
map_obj = find_containing_mapping(pr_ctxt, (u32) pmpu_addr, ul_size);
if (!map_obj) {
pr_err(%s: find_containing_mapping failed\n, __func__);
status = -EFAULT;
- goto err_out;
+ goto no_map;
}
if (memory_give_ownership(map_obj, (u32) pmpu_addr, ul_size, dir)) {
@@ -795,6 +797,8 @@ int proc_begin_dma(void *hprocessor, void *pmpu_addr, u32
ul_size,
status = -EFAULT;
}
+no_map:
+ mutex_unlock(proc_lock);
err_out:
return status;
@@ -819,12 +823,14 @@ int proc_end_dma(void *hprocessor, void *pmpu_addr, u32
ul_size,
(u32)pmpu_addr,
ul_size, dir);
+ mutex_lock(proc_lock);
+
/* find requested memory are in cached mapping information */
map_obj = find_containing_mapping(pr_ctxt, (u32) pmpu_addr, ul_size);
if (!map_obj) {
pr_err(%s: find_containing_mapping failed\n, __func__);
status = -EFAULT;
- goto err_out;
+ goto no_map;
}
if (memory_regain_ownership(map_obj, (u32) pmpu_addr, ul_size, dir)) {
@@ -834,6 +840,8 @@ int proc_end_dma(void *hprocessor, void *pmpu_addr, u32
ul_size,
goto err_out;
}
+no_map:
+ mutex_unlock(proc_lock);
err_out:
return status;
}
@@ -1726,9 +1734,8 @@ int proc_un_map(void *hprocessor, void *map_addr,
(p_proc_object-hbridge_context, va_align, size_align);
}
- mutex_unlock(proc_lock);
if (status)
- goto func_end;
+ goto unmap_failed;
/*
* A successful unmap should be followed by removal of map_obj
@@ -1737,6 +1744,9 @@ int proc_un_map(void *hprocessor, void *map_addr,
*/
remove_mapping_information(pr_ctxt, (u32) map_addr, size_align);
+unmap_failed:
+ mutex_unlock(proc_lock);
+
func_end:
dev_dbg(bridge, %s: hprocessor: 0x%p map_addr: 0x%p status: 0x%x\n,
__func__, hprocessor, map_addr, status);
--
1.7.3.3
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Re: [PATCH v2] Keyboard: omap-keypad: use matrix_keypad.h
Monday 20 December 2010 16:29:32 Aaro Koskinen wrote:
Hello,
On Sat, 18 Dec 2010, Janusz Krzysztofik wrote:
Most keypad drivers make use of the linux/input/matrix_keypad.h
defined macros, structures and inline functions.
Convert omap-keypad driver to use those as well, as suggested by a
compile time warning, hardcoded into the OMAP palt/keypad.h.
Created against linux-2.6.37-rc5.
Tested on Amstrad Delta.
Compile tested with omap1_defconfig and omap2plus_defconfig
shrinked to board-h4.
Signed-off-by: Janusz Krzysztofik jkrzy...@tis.icnet.pl
[...]
--- linux-2.6.37-rc5/arch/arm/mach-omap1/board-ams-delta.c.orig
2010-12-09 23:07:35.0 +0100 +++
linux-2.6.37-rc5/arch/arm/mach-omap1/board-ams-delta.c
2010-12-18 16:23:29.0 +0100 @@ -46,81 +46,79 @@ static u16
ams_delta_latch2_reg;
static int ams_delta_keymap[] = {
[...]
+static const struct matrix_keymap_data ams_delta_keymap_data = {
+ .keymap = ams_delta_keymap,
+ .keymap_size= ARRAY_SIZE(ams_delta_keymap),
+};
You should update the ams_delta_keymap type as well, otherwise this
patch will introduce the following sparse warning:
CHECK arch/arm/mach-omap1/board-ams-delta.c
arch/arm/mach-omap1/board-ams-delta.c:191:27: warning: incorrect type in
initializer (different signedness)
arch/arm/mach-omap1/board-ams-delta.c:191:27:expected unsigned int const
[usertype] *keymap
arch/arm/mach-omap1/board-ams-delta.c:191:27:got int static [toplevel]
*noident
Hi Aaro,
How did you get this output? I'm using OpenEmbedded as my development
environment. Running make with C=1 (EXTRA_OEMAKE= C=1 ) displays a
lot but the above. Running sparse by hand breaks with unable to
open 'linux/init.h'. Any advice?
Thanks,
Janusz
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Re: [PATCH v2] Keyboard: omap-keypad: use matrix_keypad.h
On Mon, Dec 20, 2010 at 06:32:22PM +0100, Janusz Krzysztofik wrote:
Monday 20 December 2010 16:29:32 Aaro Koskinen wrote:
Hello,
On Sat, 18 Dec 2010, Janusz Krzysztofik wrote:
Most keypad drivers make use of the linux/input/matrix_keypad.h
defined macros, structures and inline functions.
Convert omap-keypad driver to use those as well, as suggested by a
compile time warning, hardcoded into the OMAP palt/keypad.h.
Created against linux-2.6.37-rc5.
Tested on Amstrad Delta.
Compile tested with omap1_defconfig and omap2plus_defconfig
shrinked to board-h4.
Signed-off-by: Janusz Krzysztofik jkrzy...@tis.icnet.pl
[...]
--- linux-2.6.37-rc5/arch/arm/mach-omap1/board-ams-delta.c.orig
2010-12-09 23:07:35.0 +0100 +++
linux-2.6.37-rc5/arch/arm/mach-omap1/board-ams-delta.c
2010-12-18 16:23:29.0 +0100 @@ -46,81 +46,79 @@ static u16
ams_delta_latch2_reg;
static int ams_delta_keymap[] = {
[...]
+static const struct matrix_keymap_data ams_delta_keymap_data = {
+ .keymap = ams_delta_keymap,
+ .keymap_size= ARRAY_SIZE(ams_delta_keymap),
+};
You should update the ams_delta_keymap type as well, otherwise this
patch will introduce the following sparse warning:
CHECK arch/arm/mach-omap1/board-ams-delta.c
arch/arm/mach-omap1/board-ams-delta.c:191:27: warning: incorrect type in
initializer (different signedness)
arch/arm/mach-omap1/board-ams-delta.c:191:27:expected unsigned int
const [usertype] *keymap
arch/arm/mach-omap1/board-ams-delta.c:191:27:got int static [toplevel]
*noident
Hi Aaro,
How did you get this output? I'm using OpenEmbedded as my development
environment. Running make with C=1 (EXTRA_OEMAKE= C=1 ) displays a
lot but the above. Running sparse by hand breaks with unable to
open 'linux/init.h'. Any advice?
Not sure why exactly your sparse does not pick it up (too old maybe?)
but the following:
--- linux-2.6.37-rc5/arch/arm/mach-omap1/board-ams-delta.c.orig 2010-12-09
23:07:35.0 +0100
+++ linux-2.6.37-rc5/arch/arm/mach-omap1/board-ams-delta.c 2010-12-18
16:23:29.0 +0100
@@ -46,81 +46,79 @@ static u16 ams_delta_latch2_reg;
static int ams_delta_keymap[] = {
KEY(0, 0, KEY_F1), /* Advert*/
should be
static const unisgned int ams_delta_keymap[] = {
Same goes for the rest of keymaps.
Thanks.
--
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Re: [PATCH] staging: tidspbridge: protect dmm_map properly
Felipe,
On Mon, Dec 20, 2010 at 11:12 AM, Felipe Contreras
felipe.contre...@nokia.com wrote:
We need to protect not only the dmm_map list, but the individual
map_obj's, otherwise, we might be building the scatter-gather list with
garbage. So, use the existing proc_lock for that.
I observed race conditions which caused kernel panics while running
stress tests. This patch fixes those.
Signed-off-by: Felipe Contreras felipe.contre...@nokia.com
---
drivers/staging/tidspbridge/rmgr/proc.c | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/tidspbridge/rmgr/proc.c
b/drivers/staging/tidspbridge/rmgr/proc.c
index b47d7aa..21052e3 100644
--- a/drivers/staging/tidspbridge/rmgr/proc.c
+++ b/drivers/staging/tidspbridge/rmgr/proc.c
@@ -781,12 +781,14 @@ int proc_begin_dma(void *hprocessor, void *pmpu_addr,
u32 ul_size,
(u32)pmpu_addr,
ul_size, dir);
+ mutex_lock(proc_lock);
May be you should use mutex_lock_interruptable instead of mutex_lock.
+
/* find requested memory are in cached mapping information */
map_obj = find_containing_mapping(pr_ctxt, (u32) pmpu_addr, ul_size);
if (!map_obj) {
pr_err(%s: find_containing_mapping failed\n, __func__);
status = -EFAULT;
- goto err_out;
+ goto no_map;
}
if (memory_give_ownership(map_obj, (u32) pmpu_addr, ul_size, dir)) {
@@ -795,6 +797,8 @@ int proc_begin_dma(void *hprocessor, void *pmpu_addr, u32
ul_size,
status = -EFAULT;
}
+no_map:
+ mutex_unlock(proc_lock);
err_out:
return status;
@@ -819,12 +823,14 @@ int proc_end_dma(void *hprocessor, void *pmpu_addr, u32
ul_size,
(u32)pmpu_addr,
ul_size, dir);
+ mutex_lock(proc_lock);
+
/* find requested memory are in cached mapping information */
map_obj = find_containing_mapping(pr_ctxt, (u32) pmpu_addr, ul_size);
if (!map_obj) {
pr_err(%s: find_containing_mapping failed\n, __func__);
status = -EFAULT;
- goto err_out;
+ goto no_map;
}
if (memory_regain_ownership(map_obj, (u32) pmpu_addr, ul_size, dir)) {
@@ -834,6 +840,8 @@ int proc_end_dma(void *hprocessor, void *pmpu_addr, u32
ul_size,
goto err_out;
Mutex is not released in this case as it is released only at no_map.
}
+no_map:
+ mutex_unlock(proc_lock);
err_out:
return status;
}
@@ -1726,9 +1734,8 @@ int proc_un_map(void *hprocessor, void *map_addr,
(p_proc_object-hbridge_context, va_align, size_align);
}
- mutex_unlock(proc_lock);
if (status)
- goto func_end;
+ goto unmap_failed;
/*
* A successful unmap should be followed by removal of map_obj
@@ -1737,6 +1744,9 @@ int proc_un_map(void *hprocessor, void *map_addr,
*/
remove_mapping_information(pr_ctxt, (u32) map_addr, size_align);
+unmap_failed:
+ mutex_unlock(proc_lock);
+
func_end:
dev_dbg(bridge, %s: hprocessor: 0x%p map_addr: 0x%p status: 0x%x\n,
__func__, hprocessor, map_addr, status);
--
1.7.3.3
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--
Thank you,
Best regards,
Hari Kanigeri
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Re: [PATCH] staging: tidspbridge: protect dmm_map properly
Hi,
On Mon, Dec 20, 2010 at 8:30 PM, Kanigeri, Hari h-kanige...@ti.com wrote:
On Mon, Dec 20, 2010 at 11:12 AM, Felipe Contreras
felipe.contre...@nokia.com wrote:
We need to protect not only the dmm_map list, but the individual
map_obj's, otherwise, we might be building the scatter-gather list with
garbage. So, use the existing proc_lock for that.
I observed race conditions which caused kernel panics while running
stress tests. This patch fixes those.
Signed-off-by: Felipe Contreras felipe.contre...@nokia.com
---
drivers/staging/tidspbridge/rmgr/proc.c | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/tidspbridge/rmgr/proc.c
b/drivers/staging/tidspbridge/rmgr/proc.c
index b47d7aa..21052e3 100644
--- a/drivers/staging/tidspbridge/rmgr/proc.c
+++ b/drivers/staging/tidspbridge/rmgr/proc.c
@@ -781,12 +781,14 @@ int proc_begin_dma(void *hprocessor, void *pmpu_addr,
u32 ul_size,
(u32)pmpu_addr,
ul_size, dir);
+ mutex_lock(proc_lock);
May be you should use mutex_lock_interruptable instead of mutex_lock.
Right, but I think that should be a separate patch since
mutex_lock(proc_lock) is already being used.
@@ -819,12 +823,14 @@ int proc_end_dma(void *hprocessor, void *pmpu_addr,
u32 ul_size,
(u32)pmpu_addr,
ul_size, dir);
+ mutex_lock(proc_lock);
+
/* find requested memory are in cached mapping information */
map_obj = find_containing_mapping(pr_ctxt, (u32) pmpu_addr, ul_size);
if (!map_obj) {
pr_err(%s: find_containing_mapping failed\n, __func__);
status = -EFAULT;
- goto err_out;
+ goto no_map;
}
if (memory_regain_ownership(map_obj, (u32) pmpu_addr, ul_size, dir)) {
@@ -834,6 +840,8 @@ int proc_end_dma(void *hprocessor, void *pmpu_addr, u32
ul_size,
goto err_out;
Mutex is not released in this case as it is released only at no_map.
Oops! I didn't test proc_end_dma() and quickly added those locks after
I noticed it. I'll resend with the fix.
--
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[PATCH v2] staging: tidspbridge: protect dmm_map properly
We need to protect not only the dmm_map list, but the individual
map_obj's, otherwise, we might be building the scatter-gather list with
garbage. So, use the existing proc_lock for that.
I observed race conditions which caused kernel panics while running
stress tests. This patch fixes those.
Signed-off-by: Felipe Contreras felipe.contre...@nokia.com
---
drivers/staging/tidspbridge/rmgr/proc.c | 19 ++-
1 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/tidspbridge/rmgr/proc.c
b/drivers/staging/tidspbridge/rmgr/proc.c
index b47d7aa..e2fe165 100644
--- a/drivers/staging/tidspbridge/rmgr/proc.c
+++ b/drivers/staging/tidspbridge/rmgr/proc.c
@@ -781,12 +781,14 @@ int proc_begin_dma(void *hprocessor, void *pmpu_addr, u32
ul_size,
(u32)pmpu_addr,
ul_size, dir);
+ mutex_lock(proc_lock);
+
/* find requested memory are in cached mapping information */
map_obj = find_containing_mapping(pr_ctxt, (u32) pmpu_addr, ul_size);
if (!map_obj) {
pr_err(%s: find_containing_mapping failed\n, __func__);
status = -EFAULT;
- goto err_out;
+ goto no_map;
}
if (memory_give_ownership(map_obj, (u32) pmpu_addr, ul_size, dir)) {
@@ -795,6 +797,8 @@ int proc_begin_dma(void *hprocessor, void *pmpu_addr, u32
ul_size,
status = -EFAULT;
}
+no_map:
+ mutex_unlock(proc_lock);
err_out:
return status;
@@ -819,21 +823,24 @@ int proc_end_dma(void *hprocessor, void *pmpu_addr, u32
ul_size,
(u32)pmpu_addr,
ul_size, dir);
+ mutex_lock(proc_lock);
+
/* find requested memory are in cached mapping information */
map_obj = find_containing_mapping(pr_ctxt, (u32) pmpu_addr, ul_size);
if (!map_obj) {
pr_err(%s: find_containing_mapping failed\n, __func__);
status = -EFAULT;
- goto err_out;
+ goto no_map;
}
if (memory_regain_ownership(map_obj, (u32) pmpu_addr, ul_size, dir)) {
pr_err(%s: InValid address parameters %p %x\n,
__func__, pmpu_addr, ul_size);
status = -EFAULT;
- goto err_out;
}
+no_map:
+ mutex_unlock(proc_lock);
err_out:
return status;
}
@@ -1726,9 +1733,8 @@ int proc_un_map(void *hprocessor, void *map_addr,
(p_proc_object-hbridge_context, va_align, size_align);
}
- mutex_unlock(proc_lock);
if (status)
- goto func_end;
+ goto unmap_failed;
/*
* A successful unmap should be followed by removal of map_obj
@@ -1737,6 +1743,9 @@ int proc_un_map(void *hprocessor, void *map_addr,
*/
remove_mapping_information(pr_ctxt, (u32) map_addr, size_align);
+unmap_failed:
+ mutex_unlock(proc_lock);
+
func_end:
dev_dbg(bridge, %s: hprocessor: 0x%p map_addr: 0x%p status: 0x%x\n,
__func__, hprocessor, map_addr, status);
--
1.7.3.3
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Re: [PATCH v2] ARM: OMAP: Power on EHCI, serial, camera and DVI on beagleboard-xM
Koen Kooi koen.k...@gmail.com writes:
Signed-off-by: Koen Kooi k...@beagleboard.org
-ENO_DESCRIPTIVE_CHANGELOG
Also, please Cc linux-arm-kernel for patches intended for upstream.
Thanks,
Kevin
---
Changes since v1:
* Reenable the PMU stat LED
arch/arm/mach-omap2/board-omap3beagle.c | 26 --
1 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c
b/arch/arm/mach-omap2/board-omap3beagle.c
index f1a8ede..4756ac7 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -297,13 +297,35 @@ static int beagle_twl_gpio_setup(struct device *dev,
gpio_request(gpio + 1, EHCI_nOC);
gpio_direction_input(gpio + 1);
- /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
+ /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
+ * high / others active low) */
gpio_request(gpio + TWL4030_GPIO_MAX, nEN_USB_PWR);
- gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+ if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM)
+ gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1);
+ else
+ gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+
+ /* DVI reset GPIO is different between revisions */
+ if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM)
+ beagle_dvi_device.reset_gpio = 129;
+ else
+ beagle_dvi_device.reset_gpio = 170;
+
+ /* Power on DVI, Serial and PWR led */
+ if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
+ gpio_request(gpio + 1, nDVI_PWR_EN);
+ gpio_direction_output(gpio + 1, 0);
+ }
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
+ /* Power on camera interface on P7/P8 or DVI on A2 and beyond */
+ if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
+ gpio_request(gpio + 2, CAM_EN);
+ gpio_direction_output(gpio + 2, 1);
+ }
+
return 0;
}
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Re: [PATCH v2] Keyboard: omap-keypad: use matrix_keypad.h
Monday 20 December 2010 19:02:08 Dmitry Torokhov wrote:
Not sure why exactly your sparse does not pick it up (too old maybe?)
but the following:
--- linux-2.6.37-rc5/arch/arm/mach-omap1/board-ams-delta.c.orig 2010-12-09
23:07:35.0 +0100
+++ linux-2.6.37-rc5/arch/arm/mach-omap1/board-ams-delta.c 2010-12-18
16:23:29.0 +0100
@@ -46,81 +46,79 @@ static u16 ams_delta_latch2_reg;
static int ams_delta_keymap[] = {
KEY(0, 0, KEY_F1), /* Advert*/
should be
static const unisgned int ams_delta_keymap[] = {
Same goes for the rest of keymaps.
Sure, thanks.
Janusz
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RE: [PATCH v2] Keyboard: omap-keypad: use matrix_keypad.h
Hi, From: Janusz Krzysztofik [jkrzy...@tis.icnet.pl] Monday 20 December 2010 16:29:32 Aaro Koskinen wrote: You should update the ams_delta_keymap type as well, otherwise this patch will introduce the following sparse warning: CHECK arch/arm/mach-omap1/board-ams-delta.c arch/arm/mach-omap1/board-ams-delta.c:191:27: warning: incorrect type in initializer (different signedness) arch/arm/mach-omap1/board-ams-delta.c:191:27:expected unsigned int const [usertype] *keymap arch/arm/mach-omap1/board-ams-delta.c:191:27:got int static [toplevel] *noident Hi Aaro, How did you get this output? I'm using OpenEmbedded as my development environment. Running make with C=1 (EXTRA_OEMAKE= C=1 ) displays a lot but the above. Running sparse by hand breaks with unable to open 'linux/init.h'. Any advice? I'm using the latest sparse from: git://git.kernel.org/pub/scm/devel/sparse/sparse.git I don't know about OpenEmbedded, but I've noticed that at least Debian ships with some old version that is missing many checks... A. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if ES1.2
Nishanth Menon n...@ti.com writes:
From: Eduardo Valentin eduardo.valen...@nokia.com
Limitation i583: Self_Refresh Exit issue after OFF mode
Issue:
When device is waking up from OFF mode, then SDRC state machine sends
inappropriate sequence violating JEDEC standards.
Impact:
OMAP3630 ES1.2 is impacted as follows depending on the platform:
CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable, while
for all other sysclk frequencies, varied levels of instability
seen based on varied parameters.
CS1: impacted
This patch takes option #3 as recommended by the Silicon erratum:
Avoid core power domain transitioning to OFF mode. Power consumption
impact is expected in this case.
To do this, we route core OFF requests to RET request on the impacted
revisions of silicon.
[...@ti.com: rebased the code to 2.6.37-rc2- short circuit code changed a bit]
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Eduardo Valentin eduardo.valen...@nokia.com
---
v4: idle state control changed a bit -we wont register or enable
the states which cannot be enabled.
I like this version. Thanks.
v3: http://marc.info/?t=129140247800027r=1w=2
no functional change in erratum wa implementation, just registration of
erratum is collated to a single cpu detection and version check
v2: https://patchwork.kernel.org/patch/365262/
rebased to this patch series instead of depending on hs changes
fix typo for macro definition
v1: http://marc.info/?l=linux-omapm=129013173425266w=2
arch/arm/mach-omap2/cpuidle34xx.c | 10 ++
arch/arm/mach-omap2/pm.h |1 +
arch/arm/mach-omap2/pm34xx.c | 24 +---
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index f80d3f6..1b32e98 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -453,6 +453,16 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
+
+ /*
+ * Erratum i583: implementation for ES rev Es1.2 on 3630. We cannot
+ * enable OFF mode in a stable form for previous revisions.
+ * we disable C7 state as a result.
+ */
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
+ omap3_power_states[OMAP3_STATE_C7].valid = 0;
+ cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
+ }
}
struct cpuidle_driver omap3_idle_driver = {
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 92ef400..9032d09 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
#define PM_RTA_ERRATUM_i608 (1 0)
+#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 1)
#if defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 21cd36e..7faea55 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
- omap3_cpuidle_update_states(state, state);
+ /*
+ * Erratum i583: implementation for ES rev Es1.2 on 3630. We cannot
+ * enable OFF mode in a stable form for previous revisions, restrict
+ * instead to RET
+ */
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
+ omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
+ else
+ omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst, pwrst_list, node) {
- pwrst-next_state = state;
- omap_set_pwrdm_state(pwrst-pwrdm, state);
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)
+ pwrst-pwrdm == core_pwrdm
+ state == PWRDM_POWER_OFF) {
+ pwrst-next_state = PWRDM_POWER_RET;
+ pr_err(%s: Core OFF disabled due to errata i583\n,
+ __func__);
This is a warning, not an error condition, so should probably be
pr_warning().
That being said, this could be noisy if enable_off_mode is being toggled
repeatedly, so using WARN_ONCE() might be more appropriate as suggested
by others.
Kevin
+ } else {
+ pwrst-next_state = state;
+ }
+ omap_set_pwrdm_state(pwrst-pwrdm, pwrst-next_state);
}
}
@@ -1011,6 +1027,8 @@ static void __init pm_errata_configure(void)
pm34xx_errata |= PM_RTA_ERRATUM_i608;
/* Enable the l2 cache
Re: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if ES1.2
Kevin Hilman had written, on 12/20/2010 01:05 PM, the following:
[..]
struct cpuidle_driver omap3_idle_driver = {
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 92ef400..9032d09 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
#define PM_RTA_ERRATUM_i608 (1 0)
+#define PM_SDRC_WAKEUP_ERRATUM_i583(1 1)
#if defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 21cd36e..7faea55 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
- omap3_cpuidle_update_states(state, state);
+ /*
+* Erratum i583: implementation for ES rev Es1.2 on 3630. We cannot
+* enable OFF mode in a stable form for previous revisions, restrict
+* instead to RET
+*/
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
+ omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
+ else
+ omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst, pwrst_list, node) {
- pwrst-next_state = state;
- omap_set_pwrdm_state(pwrst-pwrdm, state);
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)
+ pwrst-pwrdm == core_pwrdm
+ state == PWRDM_POWER_OFF) {
+ pwrst-next_state = PWRDM_POWER_RET;
+ pr_err(%s: Core OFF disabled due to errata i583\n,
+ __func__);
This is a warning, not an error condition, so should probably be
pr_warning().
That being said, this could be noisy if enable_off_mode is being toggled
repeatedly, so using WARN_ONCE() might be more appropriate as suggested
by others.
ok WARN_ONCE it is then.. :) next rev coming right up in a few more mins..
--
Regards,
Nishanth Menon
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[PATCH v5 7/7] OMAP3630: PM: Erratum i583: disable coreoff if ES1.2
From: Eduardo Valentin eduardo.valen...@nokia.com
Limitation i583: Self_Refresh Exit issue after OFF mode
Issue:
When device is waking up from OFF mode, then SDRC state machine sends
inappropriate sequence violating JEDEC standards.
Impact:
OMAP3630 ES1.2 is impacted as follows depending on the platform:
CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable, while
for all other sysclk frequencies, varied levels of instability
seen based on varied parameters.
CS1: impacted
This patch takes option #3 as recommended by the Silicon erratum:
Avoid core power domain transitioning to OFF mode. Power consumption
impact is expected in this case.
To do this, we route core OFF requests to RET request on the impacted
revisions of silicon.
Acked-by: Jean Pihet j-pi...@ti.com
[...@ti.com: rebased the code to 2.6.37-rc2- short circuit code changed a bit]
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Eduardo Valentin eduardo.valen...@nokia.com
---
v5: used WARN_ONCE to warn user for the required paths
v4: idle state control changed a bit -we wont register or enable
the states which cannot be enabled.
v3: http://marc.info/?t=129140247800027r=1w=2
no functional change in erratum wa implementation, just registration of
erratum is collated to a single cpu detection and version check
v2: https://patchwork.kernel.org/patch/365262/
rebased to this patch series instead of depending on hs changes
fix typo for macro definition
v1: http://marc.info/?l=linux-omapm=129013173425266w=2
arch/arm/mach-omap2/cpuidle34xx.c | 12
arch/arm/mach-omap2/pm.h |1 +
arch/arm/mach-omap2/pm34xx.c | 25 ++---
3 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index f80d3f6..ab4c862 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -453,6 +453,18 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
+
+ /*
+* Erratum i583: implementation for ES rev Es1.2 on 3630. We cannot
+* enable OFF mode in a stable form for previous revisions.
+* we disable C7 state as a result.
+*/
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
+ omap3_power_states[OMAP3_STATE_C7].valid = 0;
+ cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
+ WARN_ONCE(1, %s: core off state C7 disabled due to i583\n,
+ __func__);
+ }
}
struct cpuidle_driver omap3_idle_driver = {
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 2c1cbbd..ed2357a 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
#define PM_RTA_ERRATUM_i608(1 0)
+#define PM_SDRC_WAKEUP_ERRATUM_i583(1 1)
#if defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index ca3b134..652d6f5 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -928,12 +928,29 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
- omap3_cpuidle_update_states(state, state);
+ /*
+* Erratum i583: implementation for ES rev Es1.2 on 3630. We cannot
+* enable OFF mode in a stable form for previous revisions, restrict
+* instead to RET
+*/
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
+ omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
+ else
+ omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst, pwrst_list, node) {
- pwrst-next_state = state;
- omap_set_pwrdm_state(pwrst-pwrdm, state);
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)
+ pwrst-pwrdm == core_pwrdm
+ state == PWRDM_POWER_OFF) {
+ pwrst-next_state = PWRDM_POWER_RET;
+ WARN_ONCE(1,
+ %s: Core OFF disabled due to errata i583\n,
+ __func__);
+ } else {
+ pwrst-next_state = state;
+ }
+ omap_set_pwrdm_state(pwrst-pwrdm, pwrst-next_state);
}
}
@@ -1011,6 +1028,8 @@ static void __init pm_errata_configure(void)
pm34xx_errata |= PM_RTA_ERRATUM_i608;
/* Enable the l2 cache toggling in sleep logic */
enable_omap3630_toggle_l2_on_restore();
+
[PATCH v5 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode
Currently omap3_cpuidle_update_states makes whole sale decision
on which C states to update based on enable_off_mode variable
Instead, achieve the same functionality by independently providing
mpu and core deepest states the system is allowed to achieve and
update the idle states accordingly.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Jean Pihet j-pi...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
v2: proto is used as (u32, u32) + added the acks collected
v1: original version
arch/arm/mach-omap2/cpuidle34xx.c | 19 ++-
arch/arm/mach-omap2/pm.h |2 +-
arch/arm/mach-omap2/pm34xx.c |2 +-
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index 0d50b45..f80d3f6 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -293,25 +293,26 @@ select_state:
DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
/**
- * omap3_cpuidle_update_states - Update the cpuidle states.
+ * omap3_cpuidle_update_states() - Update the cpuidle states
+ * @mpu_deepest_state: Enable states upto and including this for mpu domain
+ * @core_deepest_state:Enable states upto and including this for core
domain
*
- * Currently, this function toggles the validity of idle states based upon
- * the flag 'enable_off_mode'. When the flag is set all states are valid.
- * Else, states leading to OFF state set to be invalid.
+ * This goes through the list of states available and enables and disables the
+ * validity of C states based on deepest state that can be achieved for the
+ * variable domain
*/
-void omap3_cpuidle_update_states(void)
+void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
{
int i;
for (i = OMAP3_STATE_C1; i OMAP3_MAX_STATES; i++) {
struct omap3_processor_cx *cx = omap3_power_states[i];
- if (enable_off_mode) {
+ if ((cx-mpu_state = mpu_deepest_state)
+ (cx-core_state = core_deepest_state)) {
cx-valid = 1;
} else {
- if ((cx-mpu_state == PWRDM_POWER_OFF) ||
- (cx-core_state == PWRDM_POWER_OFF))
- cx-valid = 0;
+ cx-valid = 0;
}
}
}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 5e0bee9..29663cc 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -58,7 +58,7 @@ extern u32 sleep_while_idle;
#endif
#if defined(CONFIG_CPU_IDLE)
-extern void omap3_cpuidle_update_states(void);
+extern void omap3_cpuidle_update_states(u32, u32);
#endif
#if defined(CONFIG_PM_DEBUG) defined(CONFIG_DEBUG_FS)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index feb1bd9..ca3b134 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -928,7 +928,7 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
- omap3_cpuidle_update_states();
+ omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst, pwrst_list, node) {
--
1.6.3.3
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[PATCH v5 4/7] OMAP3630: PM: Erratum i608: disable RTA
Erratum id: i608
RTA (Retention Till Access) feature is not supported and leads to device
stability issues when enabled. This impacts modules with embedded memories
on OMAP3630
Workaround is to disable RTA on boot and coming out of core off.
For disabling RTA coming out of off mode, we do this by overriding the
restore pointer for 3630 as the first point of entry before caches are
touched and is common for GP and HS devices. To disable earlier than
this could be possible by modifying the PPA for HS devices, but not for
GP devices.
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: Tony Lindgren t...@atomide.com
Acked-by: Jean Pihet j-pi...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
[ambr...@ti.com: co-developer]
Signed-off-by: Ambresh K ambr...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
v5: minor correction in commit message, RTA is used with caps
v4:
control register handling moved to control.c
errata handling framework introduction split out
into a separate patch
v3: http://marc.info/?t=129140247800026r=1w=2
additional comment to explain Ambresh's contrib
removed the redundant check for cpu_is34xx - it is already
done by pm_init
pm_errata_configure is __init
v2: https://patchwork.kernel.org/patch/365242/
fixed missing b restore for 3430 es3.1 code.
introduced erratum handling logic here splitting it out of uart errata
typo fixes for erratum
v1: http://marc.info/?l=linux-omapm=129013172825240w=2
arch/arm/mach-omap2/control.c | 13 -
arch/arm/mach-omap2/control.h |7 ++-
arch/arm/mach-omap2/pm.h|2 ++
arch/arm/mach-omap2/pm34xx.c| 10 ++
arch/arm/mach-omap2/sleep34xx.S | 26 ++
5 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 1fa3294..27ed558 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -241,7 +241,10 @@ void omap3_save_scratchpad_contents(void)
/* Populate the Scratchpad contents */
scratchpad_contents.boot_config_ptr = 0x0;
- if (omap_rev() != OMAP3430_REV_ES3_0
+ if (cpu_is_omap3630())
+ scratchpad_contents.public_restore_ptr =
+ virt_to_phys(get_omap3630_restore_pointer());
+ else if (omap_rev() != OMAP3430_REV_ES3_0
omap_rev() != OMAP3430_REV_ES3_1)
scratchpad_contents.public_restore_ptr =
virt_to_phys(get_restore_pointer());
@@ -474,4 +477,12 @@ void omap3_control_restore_context(void)
omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
return;
}
+
+void omap3630_ctrl_disable_rta(void)
+{
+ if (!cpu_is_omap3630())
+ return;
+ omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
+}
+
#endif /* CONFIG_ARCH_OMAP3 CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b6c6b7c..ec98dd7 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -204,6 +204,10 @@
#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
+/* 36xx-only RTA - Retention till Accesss control registers and bits */
+#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
+#define OMAP36XX_RTA_DISABLE 0x0
+
/* 34xx D2D idle-related pins, handled by PM core */
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK0x254
@@ -347,10 +351,11 @@ extern void omap3_save_scratchpad_contents(void);
extern void omap3_clear_scratchpad_contents(void);
extern u32 *get_restore_pointer(void);
extern u32 *get_es3_restore_pointer(void);
+extern u32 *get_omap3630_restore_pointer(void);
extern u32 omap3_arm_context[128];
extern void omap3_control_save_context(void);
extern void omap3_control_restore_context(void);
-
+extern void omap3630_ctrl_disable_rta(void);
#else
#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0348fd7..8d9aa3e 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -85,6 +85,8 @@ extern unsigned int save_secure_ram_context_sz;
extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
+#define PM_RTA_ERRATUM_i608(1 0)
+
#if defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
#define IS_PM34XX_ERRATUM(id) (pm34xx_errata (id))
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 5702f41..a404387 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -1007,6 +1007,8 @@ void omap_push_sram_idle(void)
static void __init pm_errata_configure(void)
{
[PATCH v5 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
From: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com Erratum i581 impacts OMAP3 platforms. PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing the DPLL not to be locked at times. IMPORTANT: *) This is not a complete workaround implementation as recommended by the silicon erratum. This is a support logic for detecting lockups and attempting to recover where possible and is known to provide stability in multiple platforms. *) This code is mostly important for inactive and retention. The ROM code waits for the maximum DLL lock time when resuming from off mode. So for off mode this code isn't really needed. *) counters are introduced here for eventual export to userspace once the cleanups are completed. This should eventually get refactored as part of cleanups to sleep34xx.S Cc: Kevin Hilman khil...@deeprootsystems.com Cc: Tony Lindgren t...@atomide.com Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com --- v3: additional comment on the TODO of exposing the counters eventually after the sram34xx.S cleanups are completed. v2: https://patchwork.kernel.org/patch/365252/ typo correction- erratum, support, added comment from Peter from the thread to commit message v1: http://marc.info/?l=linux-omapm=129013172525234w=2 arch/arm/mach-omap2/sleep34xx.S | 55 +++--- 1 files changed, 50 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index aa43da5..24ecb0a 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -42,6 +42,7 @@ OMAP3430_PM_PREPWSTST) #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) +#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) #define SRAM_BASE_P0x4020 #define CONTROL_STAT 0x480022F0 #define SCRATCHPAD_MEM_OFFS0x310 /* Move this as correct place is @@ -555,31 +556,67 @@ skip_l2_inval: /* Make sure SDRC accesses are ok */ wait_sdrc_ok: + +/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */ + ldr r4, cm_idlest_ckgen +wait_dpll3_lock: + ldr r5, [r4] + tst r5, #1 + beq wait_dpll3_lock + ldr r4, cm_idlest1_core +wait_sdrc_ready: ldr r5, [r4] -and r5, r5, #0x2 -cmp r5, #0 -bne wait_sdrc_ok +tst r5, #0x2 +bne wait_sdrc_ready + /* allow DLL powerdown upon hw idle req */ ldr r4, sdrc_power ldr r5, [r4] bic r5, r5, #0x40 str r5, [r4] -wait_dll_lock: +is_dll_in_lock_mode: + /* Is dll in lock mode? */ ldr r4, sdrc_dlla_ctrl ldr r5, [r4] tst r5, #0x4 bxnelr /* wait till dll locks */ -ldr r4, sdrc_dlla_status +wait_dll_lock_timed: + ldr r4, wait_dll_lock_counter + add r4, r4, #1 + str r4, wait_dll_lock_counter + ldr r4, sdrc_dlla_status +movr6, #8 /* Wait 20uS for lock */ +wait_dll_lock: + subsr6, r6, #0x1 + beq kick_dll ldr r5, [r4] and r5, r5, #0x4 cmp r5, #0x4 bne wait_dll_lock bx lr + /* disable/reenable DLL if not locked */ +kick_dll: + ldr r4, sdrc_dlla_ctrl + ldr r5, [r4] + mov r6, r5 + bic r6, #(13) /* disable dll */ + str r6, [r4] + dsb + orr r6, r6, #(13) /* enable dll */ + str r6, [r4] + dsb + ldr r4, kick_counter + add r4, r4, #1 + str r4, kick_counter + b wait_dll_lock_timed + cm_idlest1_core: .word CM_IDLEST1_CORE_V +cm_idlest_ckgen: + .word CM_IDLEST_CKGEN_V sdrc_dlla_status: .word SDRC_DLLA_STATUS_V sdrc_dlla_ctrl: @@ -616,5 +653,13 @@ control_stat: .word CONTROL_STAT kernel_flush: .word v7_flush_dcache_all + /* +* When exporting to userspace while the counters are in SRAM, +* these 2 words need to be at the end to facilitate retrival! +*/ +kick_counter: + .word 0 +wait_dll_lock_counter: + .word 0 ENTRY(omap34xx_cpu_suspend_sz) .word . - omap34xx_cpu_suspend -- 1.6.3.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
From: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com
While coming out of MPU OSWR/OFF states, L2 controller is reseted.
The reset behavior is implementation specific as per ARMv7 TRM and
hence $L2 needs to be invalidated before it's use. Since the
AUXCTRL register is also reconfigured, disable L2 cache before
invalidating it and re-enables it afterwards. This is as per
Cortex-A8 ARM documentation.
Currently this is identified as being needed on OMAP3630 as the
disable/enable is done from public side while, on OMAP3430, this
is done in the secure side.
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: Tony Lindgren t...@atomide.com
Acked-by: Jean Pihet j-pi...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
[...@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630]
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Eduardo Valentin eduardo.valen...@nokia.com
Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com
---
v5: Change in commit message - Thanks to Santosh on the same
v4: rebased only. no functional change
v3: http://marc.info/?l=linux-omapm=129139583519221w=2
collate all silicon specific errata under a single cpu detection code
making it elegant and more maintainable.
v2: https://patchwork.kernel.org/patch/365232/
rebased out to this series independent of HS bugfixes
v1: http://marc.info/?l=linux-omapm=129013171125204w=2
arch/arm/mach-omap2/pm.h|2 ++
arch/arm/mach-omap2/pm34xx.c|5 -
arch/arm/mach-omap2/sleep34xx.S | 30 ++
3 files changed, 36 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 8d9aa3e..5e0bee9 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -90,8 +90,10 @@ extern unsigned int omap34xx_cpu_suspend_sz;
#if defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
#define IS_PM34XX_ERRATUM(id) (pm34xx_errata (id))
+extern void enable_omap3630_toggle_l2_on_restore(void);
#else
#define IS_PM34XX_ERRATUM(id) 0
+static inline void enable_omap3630_toggle_l2_on_restore(void) { }
#endif /* defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3) */
#endif
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a404387..feb1bd9 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -1007,8 +1007,11 @@ void omap_push_sram_idle(void)
static void __init pm_errata_configure(void)
{
- if (cpu_is_omap3630())
+ if (cpu_is_omap3630()) {
pm34xx_errata |= PM_RTA_ERRATUM_i608;
+ /* Enable the l2 cache toggling in sleep logic */
+ enable_omap3630_toggle_l2_on_restore();
+ }
}
static int __init omap3_pm_init(void)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 4abf447..50887c7 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -111,6 +111,19 @@ ENTRY(get_omap3630_restore_pointer_sz)
.word . - get_omap3630_restore_pointer
.text
+/*
+ * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
+ * This function sets up a fflag that will allow for this toggling to take
+ * place on 3630. Hopefully some version in the future maynot need this
+ */
+ENTRY(enable_omap3630_toggle_l2_on_restore)
+stmfd sp!, {lr} @ save registers on stack
+ /* Setup so that we will disable and enable l2 */
+ mov r1, #0x1
+ str r1, l2dis_3630
+ldmfd sp!, {pc} @ restore regs and return
+
+ .text
/* Function call to get the restore pointer for for ES3 to resume from OFF */
ENTRY(get_es3_restore_pointer)
stmfd sp!, {lr} @ save registers on stack
@@ -283,6 +296,14 @@ restore:
moveq r9, #0x3@ MPU OFF = L1 and L2 lost
movne r9, #0x1@ Only L1 and L2 lost = avoid L2 invalidation
bne logic_l1_restore
+
+ ldr r0, l2dis_3630
+ cmp r0, #0x1@ should we disable L2 on 3630?
+ bne skipl2dis
+ mrc p15, 0, r0, c1, c0, 1
+ bic r0, r0, #2 @ disable L2 cache
+ mcr p15, 0, r0, c1, c0, 1
+skipl2dis:
ldr r0, control_stat
ldr r1, [r0]
and r1, #0x700
@@ -343,6 +364,13 @@ smi:.word 0xE1600070 @ Call SMI monitor
(smieq)
mov r12, #0x2
.word 0xE1600070@ Call SMI monitor (smieq)
logic_l1_restore:
+ ldr r1, l2dis_3630
+ cmp r1, #0x1@ Do we need to re-enable L2 on 3630?
+ bne skipl2reen
+ mrc p15, 0, r1, c1, c0, 1
+ orr r1, r1, #2 @ re-enable L2 cache
+ mcr p15, 0, r1, c1, c0, 1
+skipl2reen:
mov r1, #0
/* Invalidate all instruction caches to PoU
* and flush branch target cache */
@@ -679,6 +707,8 @@ control_mem_rta:
[PATCH v5 1/7] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
From: Richard Woodruff r-woodru...@ti.com Analysis in TI kernel with ETM showed that using cache mapped flush in kernel instead of SO mapped flush cost drops by 65% (3.39mS down to 1.17mS) for clean_l2 which is used during sleep sequences. Overall: - speed up - unfortunately there isn't a good alternative flush method today - code reduction and less maintenance and potential bug in unmaintained code This also fixes the bug with the clean_l2 function usage. Reported-by: Tony Lindgren t...@atomide.com Cc: Kevin Hilman khil...@deeprootsystems.com Cc: Tony Lindgren t...@atomide.com Acked-by: Santosh Shilimkar santosh.shilim...@ti.com Acked-by: Jean Pihet j-pi...@ti.com [...@ti.com: ported rkw's proposal to 2.6.37-rc2] Signed-off-by: Nishanth Menon n...@ti.com Signed-off-by: Richard Woodruff r-woodru...@ti.com --- v3: modified comment to add remark that lr is used since we are running in SRAM currently - this is to help developers transition this code eventually to SDRAM. v2: https://patchwork.kernel.org/patch/365222/ arch/arm/mach-omap2/sleep34xx.S | 80 +++ 1 files changed, 14 insertions(+), 66 deletions(-) diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 2fb205a..aa43da5 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -520,72 +520,18 @@ clean_caches: cmp r9, #1 /* Check whether L2 inval is required or not*/ bne skip_l2_inval clean_l2: - /* read clidr */ - mrc p15, 1, r0, c0, c0, 1 - /* extract loc from clidr */ - andsr3, r0, #0x700 - /* left align loc bit field */ - mov r3, r3, lsr #23 - /* if loc is 0, then no need to clean */ - beq finished - /* start clean at cache level 0 */ - mov r10, #0 -loop1: - /* work out 3x current cache level */ - add r2, r10, r10, lsr #1 - /* extract cache type bits from clidr*/ - mov r1, r0, lsr r2 - /* mask of the bits for current cache only */ - and r1, r1, #7 - /* see what cache we have at this level */ - cmp r1, #2 - /* skip if no cache, or just i-cache */ - blt skip - /* select current cache level in cssr */ - mcr p15, 2, r10, c0, c0, 0 - /* isb to sych the new cssrcsidr */ - isb - /* read the new csidr */ - mrc p15, 1, r1, c0, c0, 0 - /* extract the length of the cache lines */ - and r2, r1, #7 - /* add 4 (line length offset) */ - add r2, r2, #4 - ldr r4, assoc_mask - /* find maximum number on the way size */ - andsr4, r4, r1, lsr #3 - /* find bit position of way size increment */ - clz r5, r4 - ldr r7, numset_mask - /* extract max number of the index size*/ - andsr7, r7, r1, lsr #13 -loop2: - mov r9, r4 - /* create working copy of max way size*/ -loop3: - /* factor way and cache number into r11 */ - orr r11, r10, r9, lsl r5 - /* factor index number into r11 */ - orr r11, r11, r7, lsl r2 - /*clean invalidate by set/way */ - mcr p15, 0, r11, c7, c10, 2 - /* decrement the way*/ - subsr9, r9, #1 - bge loop3 - /*decrement the index */ - subsr7, r7, #1 - bge loop2 -skip: - add r10, r10, #2 - /* increment cache number */ - cmp r3, r10 - bgt loop1 -finished: - /*swith back to cache level 0 */ - mov r10, #0 - /* select current cache level in cssr */ - mcr p15, 2, r10, c0, c0, 0 - isb + /* +* Jump out to kernel flush routine +* - reuse that code is better +* - it executes in a cached space so is faster than refetch per-block +* - should be faster and will change with kernel +* - 'might' have to copy address, load and jump to it +* - lr is used since we are running in SRAM currently. +*/ + ldr r1, kernel_flush + mov lr, pc + bx r1 + skip_l2_inval: /* Data memory barrier and Data sync barrier */ mov r1, #0 @@ -668,5 +614,7 @@ cache_pred_disable_mask: .word 0xE7FB control_stat: .word CONTROL_STAT +kernel_flush: + .word v7_flush_dcache_all ENTRY(omap34xx_cpu_suspend_sz) .word . - omap34xx_cpu_suspend -- 1.6.3.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 3/7] OMAP3: pm: introduce errata handling
Introduce errata handling for OMAP3. This patch introduces
errata variable and stub for initialization which will be
filled up by follow-on patches.
Signed-off-by: Nishanth Menon n...@ti.com
---
v2: Minor commit message typo corrections
v1: Splitting the errata introduction out into it's own separate patch
arch/arm/mach-omap2/pm.h |7 +++
arch/arm/mach-omap2/pm34xx.c |9 +
2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0d75bfd..0348fd7 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -85,4 +85,11 @@ extern unsigned int save_secure_ram_context_sz;
extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
+#if defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3)
+extern u16 pm34xx_errata;
+#define IS_PM34XX_ERRATUM(id) (pm34xx_errata (id))
+#else
+#define IS_PM34XX_ERRATUM(id) 0
+#endif /* defined(CONFIG_PM) defined(CONFIG_ARCH_OMAP3) */
+
#endif
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 648b8c5..5702f41 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -68,6 +68,9 @@ static inline bool is_suspending(void)
#define OMAP343X_TABLE_VALUE_OFFSET 0xc0
#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
+/* pm34xx errata defined in pm.h */
+u16 pm34xx_errata;
+
struct power_state {
struct powerdomain *pwrdm;
u32 next_state;
@@ -1002,6 +1005,10 @@ void omap_push_sram_idle(void)
save_secure_ram_context_sz);
}
+static void __init pm_errata_configure(void)
+{
+}
+
static int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
@@ -1011,6 +1018,8 @@ static int __init omap3_pm_init(void)
if (!cpu_is_omap34xx())
return -ENODEV;
+ pm_errata_configure();
+
printk(KERN_ERR Power Management for TI OMAP3.\n);
/* XXX prcm_setup_regs needs to be before enabling hw
--
1.6.3.3
--
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[PATCH v5 0/7] OMAP: idle path errata fixes
Hi, as discussed in [1], here is step 2 - idle path errata fixes. this is the next rev incorporating comments from V4 of this series. Rebased to: 2.6.37-rc6 (k.org vanilla) Tested: this series: SDP3430 SDP3630 this series + ASM cleanup series[2] SDP3430 SDP3630 Test Script: http://elinux.org/OMAP_Power_Management#Quick_verification_of_suspend-idle_functionality v4: http://marc.info/?l=linux-omapm=129271283307741w=2 V3: http://marc.info/?t=129140247800030r=1w=2 V2: http://marc.info/?l=linux-omapm=129106200408109w=2 Major change in V5: comment updates, minor typo cleanups collated acks Eduardo Valentin (1): OMAP3630: PM: Erratum i583: disable coreoff if ES1.2 Nishanth Menon(3): OMAP3: pm: introduce errata handling OMAP3630: PM: Erratum i608: disable RTA OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode Peter 'p2' De Schrijver (2): OMAP3: PM: Erratum i581 support: dll kick strategy OMAP3630: PM: Disable L2 cache while invalidating L2 cache Richard Woodruff (1): OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all arch/arm/mach-omap2/control.c | 13 +++- arch/arm/mach-omap2/control.h |7 +- arch/arm/mach-omap2/cpuidle34xx.c | 31 -- arch/arm/mach-omap2/pm.h | 15 +++- arch/arm/mach-omap2/pm34xx.c | 47 +- arch/arm/mach-omap2/sleep34xx.S | 191 +++-- 6 files changed, 218 insertions(+), 86 deletions(-) bloat-o-meter report Vs 2.6.37-rc6 add/remove: 2/0 grow/shrink: 8/1 up/down: 330/-1 (329) function old new delta omap3_pm_off_mode_enable 80 192+112 omap3_pm_init 17921872 +80 omap3630_ctrl_disable_rta - 44 +44 omap3_save_scratchpad_contents 732 760 +28 static.__func__13783 13808 +25 vermagic 45 60 +15 linux_banner 132 147 +15 prcm_interrupt_handler 268 276 +8 pm34xx_errata - 2 +2 static.__warned 238 239 +1 kernel_config_data 13718 13717 -1 [1] http://marc.info/?l=linux-omapm=129045338806957w=2 [2] http://marc.info/?l=linux-omapm=129268746417556w=2 Cc: Charulatha Varadarajan ch...@ti.com Cc: Jean Pihet jean.pi...@newoldbits.com Cc: Kevin Hilman khil...@deeprootsystems.com Cc: Santosh Shilimkar santosh.shilim...@ti.com Cc: Tao Hu tgh...@motorola.com Cc: Tony Lindgren t...@atomide.com Cc: Vishwanath Sripathy vishwanath...@ti.com --- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] Keyboard: omap-keypad: use matrix_keypad.h
Monday 20 December 2010 20:03:58 aaro.koski...@nokia.com wrote: I'm using the latest sparse from: git://git.kernel.org/pub/scm/devel/sparse/sparse.git I don't know about OpenEmbedded, but I've noticed that at least Debian ships with some old version that is missing many checks... Aaro, Both you and Dmitry were right: an old sparse version. Once upgraded from 0.4.1 to 0.4.2 (Gentoo ebuild - OpenEmbedded doesn't build its own sparse binary, but uses a host provided one), now I get that issue reported. No more sparse warnings from me, I hope (until my sparse gets too old again ;). Thanks, Janusz -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3] Keyboard: omap-keypad: use matrix_keypad.h
Most keypad drivers make use of the linux/input/matrix_keypad.h
defined macros, structures and inline functions.
Convert omap-keypad driver to use those as well, as suggested by a
compile time warning, hardcoded into the OMAP palt/keypad.h.
Created against linux-2.6.37-rc5.
Tested on Amstrad Delta.
Compile tested with omap1_defconfig and omap2plus_defconfig shrinked to
board-h4.
Signed-off-by: Janusz Krzysztofik jkrzy...@tis.icnet.pl
---
v2 - v3 changes:
- update all board's keymap tables type to match the struct
matrix_keymap_data .keymap member; thanks to Aaro Koskinen for
pointing this out,
- while being at it, correct one sparse reported issue found (3 times)
in omap-keypad.c (Using plain integer as NULL pointer), and an
omap-keypad related one found in board-htcherald.c
(symbol 'htcherald_kp_data' was not declared. Should it be static?).
v1 - v2 changes, both requested by Dmitry Torokhov (thanks!):
- while updating all boards, change rep and dbounce to bool,
- put keycodes at the end of struct omap_kp and allocate it in one shot.
arch/arm/mach-omap1/board-ams-delta.c| 130 +++
arch/arm/mach-omap1/board-fsample.c | 67 ---
arch/arm/mach-omap1/board-h2.c | 75 +
arch/arm/mach-omap1/board-h3.c | 75 +
arch/arm/mach-omap1/board-htcherald.c| 98 ---
arch/arm/mach-omap1/board-innovator.c| 21 ++---
arch/arm/mach-omap1/board-nokia770.c | 29 +++---
arch/arm/mach-omap1/board-osk.c | 21 ++---
arch/arm/mach-omap1/board-palmte.c | 28 +++---
arch/arm/mach-omap1/board-palmtt.c | 28 +++---
arch/arm/mach-omap1/board-palmz71.c | 30 ---
arch/arm/mach-omap1/board-perseus2.c | 69
arch/arm/mach-omap1/board-sx1.c | 57 +++--
arch/arm/mach-omap2/board-h4.c | 63 +++
arch/arm/plat-omap/include/plat/keypad.h | 35
drivers/input/keyboard/omap-keypad.c | 41 -
include/linux/input/matrix_keypad.h |2
17 files changed, 458 insertions(+), 411 deletions(-)
--- linux-2.6.37-rc5/arch/arm/plat-omap/include/plat/keypad.h.orig
2010-12-09 23:07:38.0 +0100
+++ linux-2.6.37-rc5/arch/arm/plat-omap/include/plat/keypad.h 2010-12-20
18:15:11.0 +0100
@@ -10,16 +10,18 @@
#ifndef ASMARM_ARCH_KEYPAD_H
#define ASMARM_ARCH_KEYPAD_H
-#warning: Please update the board to use matrix_keypad.h instead
+#ifndef CONFIG_ARCH_OMAP1
+#warning Please update the board to use matrix-keypad driver
+#endif
+#include linux/input/matrix_keypad.h
struct omap_kp_platform_data {
int rows;
int cols;
- int *keymap;
- unsigned int keymapsize;
- unsigned int rep:1;
+ const struct matrix_keymap_data *keymap_data;
+ bool rep;
unsigned long delay;
- unsigned int dbounce:1;
+ bool dbounce;
/* specific to OMAP242x*/
unsigned int *row_gpios;
unsigned int *col_gpios;
@@ -28,18 +30,21 @@ struct omap_kp_platform_data {
/* Group (0..3) -- when multiple keys are pressed, only the
* keys pressed in the same group are considered as pressed. This is
* in order to workaround certain crappy HW designs that produce ghost
- * keypresses. */
-#define GROUP_0(0 16)
-#define GROUP_1(1 16)
-#define GROUP_2(2 16)
-#define GROUP_3(3 16)
+ * keypresses. Two free bits, not used by neither row/col nor keynum,
+ * must be available for use as group bits. The below GROUP_SHIFT
+ * macro definition is based on some prior knowledge of the
+ * matrix_keypad defined KEY() macro internals.
+ */
+#define GROUP_SHIFT14
+#define GROUP_0(0 GROUP_SHIFT)
+#define GROUP_1(1 GROUP_SHIFT)
+#define GROUP_2(2 GROUP_SHIFT)
+#define GROUP_3(3 GROUP_SHIFT)
#define GROUP_MASK GROUP_3
+#if KEY_MAX GROUP_MASK
+#error Group bits in conflict with keynum bits
+#endif
-#define KEY_PERSISTENT 0x0080
-#define KEYNUM_MASK0x00EF
-#define KEY(col, row, val) (((col) 28) | ((row) 24) | (val))
-#define PERSISTENT_KEY(col, row) (((col) 28) | ((row) 24) | \
- KEY_PERSISTENT)
#endif
--- linux-2.6.37-rc5/include/linux/input/matrix_keypad.h.orig 2010-12-09
23:09:05.0 +0100
+++ linux-2.6.37-rc5/include/linux/input/matrix_keypad.h2010-12-20
18:15:11.0 +0100
@@ -9,7 +9,7 @@
#define KEY(row, col, val) row) (MATRIX_MAX_ROWS - 1)) 24) |\
(((col) (MATRIX_MAX_COLS - 1)) 16) |\
-(val 0x))
+((val) 0x))
#define KEY_ROW(k) (((k) 24) 0xff)
#define KEY_COL(k) (((k) 16) 0xff)
---
[PATCH] staging: tidspbridge: remove code referred by OPT_ZERO_COPY_LOADER
Remove code referred by OPT_ZERO_COPY_LOADER since it is
not used.
Signed-off-by: Ernesto Ramos erne...@ti.com
---
drivers/staging/tidspbridge/dynload/cload.c | 60 +--
1 files changed, 20 insertions(+), 40 deletions(-)
diff --git a/drivers/staging/tidspbridge/dynload/cload.c
b/drivers/staging/tidspbridge/dynload/cload.c
index a5cdfa1..7713e76 100644
--- a/drivers/staging/tidspbridge/dynload/cload.c
+++ b/drivers/staging/tidspbridge/dynload/cload.c
@@ -1133,9 +1133,6 @@ static void dload_data(struct dload_state *dlthis)
u16 curr_sect;
struct doff_scnhdr_t *sptr = dlthis-sect_hdrs;
struct ldr_section_info *lptr = dlthis-ldr_sections;
-#ifdef OPT_ZERO_COPY_LOADER
- bool zero_copy = false;
-#endif
u8 *dest;
struct {
@@ -1194,17 +1191,6 @@ static void dload_data(struct dload_state *dlthis)
return;
}
dest = ibuf.bufr;
-#ifdef OPT_ZERO_COPY_LOADER
- zero_copy = false;
- if (!dload_check_type(sptr, DLOAD_CINIT) {
- dlthis-myio-writemem(dlthis-myio,
- dest,
- lptr-load_addr +
- image_offset,
- lptr, 0);
- zero_copy = (dest != ibuf.bufr);
- }
-#endif
/* End of determination */
if (dlthis-strm-read_buffer(dlthis-strm,
@@ -1268,33 +1254,27 @@ static void dload_data(struct dload_state *dlthis)
ibuf.ipacket);
cinit_processed = true;
} else {
-#ifdef OPT_ZERO_COPY_LOADER
- if (!zero_copy) {
-#endif
- /* FIXME */
- if (!dlthis-myio-
- writemem(dlthis-
- myio,
- ibuf.bufr,
- lptr-
- load_addr +
- image_offset,
- lptr,
- BYTE_TO_HOST
- (ibuf.
- ipacket.
- packet_size))) {
- DL_ERROR
- (Write to
- FMT_UI32
- failed,
- lptr-
- load_addr +
- image_offset);
- }
-#ifdef OPT_ZERO_COPY_LOADER
+ /* FIXME */
+ if (!dlthis-myio-
+ writemem(dlthis-
+ myio,
+ ibuf.bufr,
+ lptr-
+ load_addr +
+ image_offset,
+ lptr,
+ BYTE_TO_HOST
+ (ibuf.
+ ipacket.
+ packet_size))) {
+ DL_ERROR
+ (Write to
+ FMT_UI32
+ failed,
+ lptr-
+ load_addr +
+
Huge ubi or ubifs sync slowdown since 2.6.32
Hi All I've been looking into a ubifs performance regression on linux-omap 2.6.37. My test is pretty simple, copy a 2Mbyte file and sync. # sync; date; cp 2Mbyte-file foo; sync; date On 2.6.32 and earler, the time between the two dates was around 3 seconds. On linux-omap master it is around 14 seconds. Ouch! At first I thought the problem was due to changes in the OMAP nand drivers, but raw randwrite speed is actually a bit faster. This suggest the finger should be pointed at ubi or ubifs. I then thought that perhaps the layout of my ubinized image might be a contributing factor so I erased the partition, ubiformatted and ubimkvoled. The problem persisted, Any suggestions as to what might be broken or how to debug this deeper? Thanks Charles -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/40] Complete set of clocksource/sched_clock patches
On Mon, Dec 20, 2010 at 11:32:21AM +0800, Eric Miao wrote: On Fri, Dec 17, 2010 at 7:32 PM, Russell King - ARM Linux li...@arm.linux.org.uk wrote: Here is the entire set of clocksource and sched_clock patches which have been previously posted. There's a couple of small tweaks in a few of the patches (such as adding notrace to OMAP clocksource read functions), and this also shows the proper ordering of these patches. Still looking for acks or tested-by's for these patches. Hi Russell, Sorry for late feedback. Tested the branch 'clksrc' on Littleton/PXA3xx, seems to be good. Tested-by: Eric Miao eric.y.m...@gmail.com Ok, I'll add that to the PXA and generic patches, thanks. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Debugging failure to get MMC2 IRQ 86
Hi,
I get an error when attempting to obtain an IRQ (86) for MMC2 controller,
which is connected to a Murata TI WL1271 wlan module, using the TI proprietary
driver.
TIWLAN: 2769.576375: pInitParams-RoamingScanning_2_4G_enable 0
SDIO clock Configuration is now set to 24Mhz
After sdioDrv_ConnectBus, iStatus=0
After SD_IO_GO_IDLE_STATE, iStatus=0
sdioDrv_ExecuteCmd() SDIO Command error status = 0x18000
After VDD_VOLTAGE_WINDOW, iStatus=-1
TIWLAN: 2770.045094: Try to SDBus Connect again...
SDIO clock Configuration is now set to 24Mhz
sdioDrv_InitHw() - request_irq FAILED!!
More specifically, in file
ti_wlan_driver/external_drivers/omap3530/Linux/sdio/SdioDrv.c
line 201:
#define INT_MMC2_IRQ 86
#define OMAP_MMC_IRQ INT_MMC2_IRQ
It fails in the following function call:
line 778: in function sdioDrv_InitHw():
rc = request_irq(OMAP_MMC_IRQ,
sdiodrv_irq,
0,
SDIO_DRIVER_NAME,
g_drv);
if (rc != 0)
{
PERR (sdioDrv_InitHw() - request_irq FAILED!!\n);
goto err;
}
What could the reason be for not being able to obtain this IRQ 86 for MMC2
controller? Its pretty standard, and shouldn't have a problem getting allocated.
Best regards,
Elvis Dowson
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Re: [PATCH v7 12/12] OMAP2: dmtimer: set wakeup enable explicitly in plat
Hi Tarun,
On 12/20/2010 11:05 PM, DebBarma, Tarun Kanti wrote:
For some reason the wakeup enable bit is not getting set on OMAP2430,
OMAP2420. This is inspite of the fact that SYSC_HAS_ENAWAKEUP flag is
present in the hwmod database.
This is indeed strange. Did you observe that on OMAP3 4?
Did you use the patch that Kevin did recently to fix an issue with the
ENAWAKEUP bit?
http://git.kernel.org/?p=linux/kernel/git/khilman/linux-omap-pm.git;a=commit;h=d15ae13fc7428a95b02c1935ebf92324fcb80a5f
The point is that this fix is not really acceptable for my point of view:-(
You really have to check what is going on in the hwmod _enable_wakeup
function.
Regards,
Benoit
I am not sure if there is already a patch to fix this problem. Until the
reason is found we need this patch to boot on the above platforms.
Signed-off-by: Tarun Kanti DebBarmatarun.ka...@ti.com
---
arch/arm/plat-omap/dmtimer.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index f4aa4a1..007b754 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -227,6 +227,7 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer
*timer, u32 reg,
static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
{
+ u32 l;
struct dmtimer_platform_data *pdata = timer-pdev-dev.platform_data;
if (!pdata-is_omap16xx) {
@@ -243,6 +244,18 @@ static void omap_dm_timer_prepare(struct omap_dm_timer
*timer)
if (pdata-dm_timer_reset)
pdata-dm_timer_reset(timer);
+ /*
+* Enable wake-up on OMAP2420, OMAP2430 CPUs.
+* FIXME: SYSC_HAS_ENAWAKEUP flag is already set in hwmod database.
+* But the setting does not seem to work. Need to investigate why
+* this is happening.
+*/
+ if (cpu_is_omap2430() || cpu_is_omap2420()) {
+ l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
+ l |= 1 2;
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
+ }
+
omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
/* Match hardware reset default of posted mode */
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Re: [PATCH v5 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode
Nishanth Menon n...@ti.com writes:
Currently omap3_cpuidle_update_states makes whole sale decision
on which C states to update based on enable_off_mode variable
Instead, achieve the same functionality by independently providing
mpu and core deepest states the system is allowed to achieve and
update the idle states accordingly.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Jean Pihet j-pi...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
This patch doesnt' compile with CPUidle enabled.
You missed one other caller of the update_states function inside
cpuidle34xx.c which is only there when CONFIG_CPU_IDLE=y
Kevin
---
v2: proto is used as (u32, u32) + added the acks collected
v1: original version
arch/arm/mach-omap2/cpuidle34xx.c | 19 ++-
arch/arm/mach-omap2/pm.h |2 +-
arch/arm/mach-omap2/pm34xx.c |2 +-
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index 0d50b45..f80d3f6 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -293,25 +293,26 @@ select_state:
DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
/**
- * omap3_cpuidle_update_states - Update the cpuidle states.
+ * omap3_cpuidle_update_states() - Update the cpuidle states
+ * @mpu_deepest_state: Enable states upto and including this for mpu
domain
+ * @core_deepest_state: Enable states upto and including this for core
domain
*
- * Currently, this function toggles the validity of idle states based upon
- * the flag 'enable_off_mode'. When the flag is set all states are valid.
- * Else, states leading to OFF state set to be invalid.
+ * This goes through the list of states available and enables and disables
the
+ * validity of C states based on deepest state that can be achieved for the
+ * variable domain
*/
-void omap3_cpuidle_update_states(void)
+void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32
core_deepest_state)
{
int i;
for (i = OMAP3_STATE_C1; i OMAP3_MAX_STATES; i++) {
struct omap3_processor_cx *cx = omap3_power_states[i];
- if (enable_off_mode) {
+ if ((cx-mpu_state = mpu_deepest_state)
+ (cx-core_state = core_deepest_state)) {
cx-valid = 1;
} else {
- if ((cx-mpu_state == PWRDM_POWER_OFF) ||
- (cx-core_state == PWRDM_POWER_OFF))
- cx-valid = 0;
+ cx-valid = 0;
}
}
}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 5e0bee9..29663cc 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -58,7 +58,7 @@ extern u32 sleep_while_idle;
#endif
#if defined(CONFIG_CPU_IDLE)
-extern void omap3_cpuidle_update_states(void);
+extern void omap3_cpuidle_update_states(u32, u32);
#endif
#if defined(CONFIG_PM_DEBUG) defined(CONFIG_DEBUG_FS)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index feb1bd9..ca3b134 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -928,7 +928,7 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
- omap3_cpuidle_update_states();
+ omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst, pwrst_list, node) {
--
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Re: [PATCH v7 12/12] OMAP2: dmtimer: set wakeup enable explicitly in plat
Cousson, Benoit b-cous...@ti.com writes: Hi Tarun, On 12/20/2010 11:05 PM, DebBarma, Tarun Kanti wrote: For some reason the wakeup enable bit is not getting set on OMAP2430, OMAP2420. This is inspite of the fact that SYSC_HAS_ENAWAKEUP flag is present in the hwmod database. This is indeed strange. Did you observe that on OMAP3 4? Did you use the patch that Kevin did recently to fix an issue with the ENAWAKEUP bit? http://git.kernel.org/?p=linux/kernel/git/khilman/linux-omap-pm.git;a=commit;h=d15ae13fc7428a95b02c1935ebf92324fcb80a5f The point is that this fix is not really acceptable for my point of view:-( You really have to check what is going on in the hwmod _enable_wakeup function. I completely agree with Benoit. We cannot merge a fix like this without understanding the root cause. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v1] OMAP: GPIO: Correct IP version message during boot
Varadarajan, Charulatha ch...@ti.com writes: Kevin, On Thu, Dec 16, 2010 at 11:49, Kevin Hilman khil...@deeprootsystems.com wrote: Varadarajan, Charulatha ch...@ti.com writes: With the commit 9a748053f5f58a77cd71864f1d7b804175b0e47d whose subject is OMAP: GPIO: Make omap_gpio_show_rev bank specific (see [1]), the IP version information for all the banks are shown during bootup, but it does not show the bank number. Use dev_info instead of printk in omap_gpio_show_rev() so that the bank id is displayed along with the IP version [1] http://www.spinics.net/lists/arm-kernel/msg105872.html A related question, the commit above also changed the GPIO revision display from one-time to once per bank. Do we need to know the GPIO HW revision for each bank, or can we assume it's the same for all banks? The IP version is the same for all the gpio banks in all OMAP2+ CPUs. But I am not sure about OMAP16xx. OK, then I suggest we switch this back to just printing the GPIO revision once. Maybe after all banks are found, just print the revision for bank 1. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode
Kevin Hilman khil...@deeprootsystems.com writes:
Nishanth Menon n...@ti.com writes:
Currently omap3_cpuidle_update_states makes whole sale decision
on which C states to update based on enable_off_mode variable
Instead, achieve the same functionality by independently providing
mpu and core deepest states the system is allowed to achieve and
update the idle states accordingly.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Jean Pihet j-pi...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
This patch doesnt' compile with CPUidle enabled.
You missed one other caller of the update_states function inside
cpuidle34xx.c which is only there when CONFIG_CPU_IDLE=y
Something like the following folded into this patch makes it compile and
work as before.
If this looks OK to you, I'll fold it in.
Kevin
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx
index ab4c862..0fb619c 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -517,7 +517,10 @@ int __init omap3_idle_init(void)
return -EINVAL;
dev-state_count = count;
- omap3_cpuidle_update_states();
+ if (enable_off_mode)
+ omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
+ else
+ omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
if (cpuidle_register_device(dev)) {
printk(KERN_ERR %s: CPUidle register device failed\n,
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Re: [PATCH v6 00/10] OMAP: Adding Smartreflex and Voltage driver support
Thara Gopinath th...@ti.com writes: This patch series introduces smartreflex and voltage driver support for OMAP3430 and OMAP3630. SmartReflex modules do adaptive voltage control for real-time voltage adjustments. Thanks Thara, these are looking good for 2.6.38. Tony, unless there are major objections, I'll be queuing these two SR series for 2.6.38. They have dependencies on Paul's integration branch so will wait 'til that stabilizies before sending pull request. Kevin Originally all the functionalities introduced in this patch were present in arch/arm/mach-omap2/smartreflex.c file in Kevin's pm tree. This patch series does a major rewrite of this file and introduces a separate voltage driver. Major contributors to the original driver are Eduardo Valentin (1): OMAP3: PM: SmartReflex: Fix scheduled while atomic problem Kalle Jokiniemi (1): OMAP3: PM: SmartReflex driver integration Kevin Hilman (2): temp: SR: IO_ADDRESS conversion OMAP: SR: OPP interfaces removed from OMAP PM layer Nishanth Menon (1): omap3: pm: sr: replace get_opp with freq_to_opp Paul Walmsley (2): OMAP SR: use opp_find_opp_by_opp_id() OMAP SR: use OPP API for OPP ID, remove direct access Phil Carmody (2): OMAP3: PM: Don't do unnecessary searches in omap_sr_vdd*_autocomp_store OMAP3: PM: Early exit on invalid parameters Rajendra Nayak (9): OMAP3: SR: Fix init voltage on OPP change OMAP3: SR: Update VDD1/2 voltages at boot OMAP3: SR: Use sysclk for SR CLKLENGTH calc OMAP3: SR: Reset voltage level on SR disable OMAP3: SR: Replace printk's with pr_* calls OMAP3: SR: Remove redundant defines OMAP3: SR: Fix SR driver to check for omap-pm return values OMAP3: PM: Put optimal SMPS stabilization delay OMAP3: SR: Wait for VP idle before a VP disable Roger Quadros (4): OMAP3: PM: Fix Smartreflex when used with PM_NOOP layer OMAP3: PM: Make Smartreflex driver independent of SRF OMAP3: PM: Do not Enable SmartReflex if OPP tables not defined OMAP3: PM: Smartreflex: Fix VDD2 OPP determining logic Romit Dasgupta (1): omap: pm: SR: use enum for OPP types Teerth Reddy (1): OMAP3: SR: Replace SR_PASS/FAIL,SR_TRUE/FALSE Tero Kristo (1): Smartreflex: Avoid unnecessary spam This patch series is against pm-core branch of Kevin Hilman's OMAP PM tree with the following additional patch applied. https://patchwork.kernel.org/patch/421351/ The entire series with the dependencies are available at http://dev.omapzoom.org/?p=thara/omap-dvfs.git;a=summary head: kevin-pm-sr This patch series has been tested on OMAP3430 SDP with omap2plus_defconfig with the following menuconfig options enabled. System type - TI OMAP Implementations - Smartreflex Support System type - TI OMAP Implementations - Class 3 mode of Smartreflex Implementation Major Changes in v6 -Rebased to pm-core branch of Kevin Hilman's OMAP PM tree. Major Changes in v5 - Rebased to k.org 2.6.37-rc3 - Rebased to Nishant Menon's latest opp patches - Voltage pmic info structure extended to include a vast set of PMIC dependent parameters. - Smartreflex software n-target values support removed from the kernel. Instead n-target values are exposed as debugfs entries which can be written into by the user if needed. - Introduced a new file arch/arm/mach-omap2/omap_twl.c for specifying OMAP and TWL related info for the voltage layer. - Remove default enabling of smartreflex autocompensation during boot on OMAP3430 ES3.1 chips. Instead an API is provided that can be called from board files in case autocompensation needs to be enabled during boot up itself. - Other review comments on v4 Thara Gopinath (10): OMAP3: PM: Adding voltage driver support. OMAP: Introduce voltage domain information in the hwmod structures OMAP3: PM: Adding smartreflex driver support. OMAP3: PM: Adding smartreflex device file. OMAP3: PM: Adding smartreflex hwmod data OMAP3: PM: Adding smartreflex class3 driver OMAP3: PM: Adding T2 enabling of smartreflex support OMAP3: PM: Register TWL4030 pmic info with the voltage driver. OMAP3: PM: Adding debug support to Voltage and Smartreflex drivers OMAP3: PM: Program correct init voltages for VDD1 and VDD2 arch/arm/mach-omap2/Makefile |7 +- arch/arm/mach-omap2/control.h | 17 + arch/arm/mach-omap2/omap_hwmod_3xxx_data.c| 176 arch/arm/mach-omap2/omap_twl.c| 111 +++ arch/arm/mach-omap2/pm.c | 90 ++ arch/arm/mach-omap2/pm.h | 23 + arch/arm/mach-omap2/smartreflex-class3.c | 59 ++
Re: [PATCHv2] omap: rx51: Switch rx51_tpa6130a2_data __initdata to __initdata_or_module
* Jarkko Nikula jhnik...@gmail.com [101218 10:17]: If the TPA6130 is compiled as module the id and power_gpio values are arbitrary at module probing time since the rx51_tpa6130a2_data was marked as __initdata. Fix this by using __initdata_or_module. Then __initdata is defined only if the kernel is built without CONFIG_MODULES and omitted otherwise. Thanks applying. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] omap: pandora: fix wifi support
* Grazvydas Ignotas nota...@gmail.com [101219 14:33]: After commit ed919b0 mmc: sdio: fix runtime PM anomalies by introducing MMC_CAP_POWER_OFF_CARD it is required to specify MMC_CAP_POWER_OFF_CARD to have runtime PM support. As the wl1251 driver expects card to be powered down when it's not used, wifi will no longer work after interface is brought down at least once without functioning runtime PM. Fix this by declaring MMC_CAP_POWER_OFF_CARD for MMC3. Signed-off-by: Grazvydas Ignotas nota...@gmail.com --- this is a fix but can go for 2.6.38 as wl1251 runtime PM support is only queued for .38 . Thanks queuing for the merge window. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] I2C: i2c-omap: Change device name: i2c_omap - omap_i2c
* Kevin Hilman khil...@deeprootsystems.com [101220 08:07]: Tony Lindgren t...@atomide.com writes: * Cousson, Benoit b-cous...@ti.com [101210 00:29]: On 12/9/2010 11:18 PM, aaro.koski...@nokia.com wrote: Hi, Kevin Hilman [khil...@deeprootsystems.com]: Ben Dooksben-...@fluff.org writes: Renaming stuff like this is going to have an impact on the userspace as anyone looking through /sys's driver heirarchy is going to miss the old name... It all depends if you really want to go ahead with this... Yes, we are aware of the userspace impact, but this name change makes all devices on OMAP have consistent names and actually improves the ability to have userspace tools have consistent naming as well. So there are no imporant users, or if there is, they are prepared for this change? Well, I do not know any user of that today. Do you have some in mind? Sounds like it's safe for me to take these two. These should probably go via Paul's integration branch to avoid conflicts with the other omap_device/omap_hwmod code. Well Paul acked it.. Will check with him what he wants to do. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT] pull request: DMA hwmod changes
Hi Tony, Benoit comments are taken care and new pull request is generated as below. The omap4 hwmod database for dma is rearranged as per Benoit's convention + no idlest flag entry is removed + sysc_flags are barrowed from latest omap4 hwmod data base. The changes are aligned and benoit has agreed for these changes. Tested again on OMAP4 SDP(boot and DMA tests) and here is pull request against linux omap master branch. The following changes since commit 205e4d6e8d892176d791b77a974efe7f561ca4c3: Merge branch 'for-next' (2010-12-17 19:32:47 -0800) are available in the git repository at: git://dev.omapzoom.org/pub/scm/manju/kernel-omap3-dev.git dma_for_2.6.38 Benoit Cousson (1): OMAP4: hwmod data: add system DMA G, Manjunath Kondaiah (8): OMAP: DMA: Replace read/write macros with functions OMAP: DMA: Introduce errata handling feature OMAP2420: hwmod data: add system DMA OMAP2430: hwmod data: add system DMA OMAP3: hwmod data: add system DMA OMAP1: DMA: Implement in platform device model OMAP2+: DMA: hwmod: Device registration OMAP: DMA: Convert DMA library into platform driver arch/arm/mach-omap1/Makefile |2 +- arch/arm/mach-omap1/dma.c | 390 arch/arm/mach-omap2/Makefile |2 +- arch/arm/mach-omap2/dma.c | 297 arch/arm/mach-omap2/omap_hwmod_2420_data.c | 86 arch/arm/mach-omap2/omap_hwmod_2430_data.c | 86 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 97 arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 102 arch/arm/plat-omap/dma.c | 697 arch/arm/plat-omap/include/plat/dma.h | 232 -- 10 files changed, 1451 insertions(+), 540 deletions(-) create mode 100644 arch/arm/mach-omap1/dma.c create mode 100644 arch/arm/mach-omap2/dma.c -Manjunath On Mon, Dec 20, 2010 at 11:45:29AM +0100, Cousson, Benoit wrote: Hi Manju, I still have 2 comments on the patch #6: OMAP4: hwmod data: add system DMA. I'll sent them in a couple of minutes. Regards, Benoit On 12/19/2010 4:59 AM, G, Manjunath Kondaiah wrote: Hi Tony, Please pull the following dma hwmod changes into linux omap master branch. This pull request includes v2[http://thread.gmane.org/gmane.linux.ports.arm.omap/48695] + paul's sidle mode comments incorporated + acks for patch 3 and 4. The final series is boot tested on: OMAP3530(Beagle) N800 SDP2430 OMAP4430SDP(ES2.1) Full testing is done once again for SDP2430 and logs can be accessed at: http://pastebin.com/aJZGjdar The following changes since commit 205e4d6e8d892176d791b77a974efe7f561ca4c3: Merge branch 'for-next' (2010-12-17 19:32:47 -0800) are available in the git repository at: git://dev.omapzoom.org/pub/scm/manju/kernel-omap3-dev.git dma_hwmod Benoit Cousson (1): OMAP4: hwmod data: add system DMA G, Manjunath Kondaiah (8): OMAP: DMA: Replace read/write macros with functions OMAP: DMA: Introduce errata handling feature OMAP2420: hwmod data: add system DMA OMAP2430: hwmod data: add system DMA OMAP3: hwmod data: add system DMA OMAP1: DMA: Implement in platform device model OMAP2+: DMA: hwmod: Device registration OMAP: DMA: Convert DMA library into platform driver arch/arm/mach-omap1/Makefile |2 +- arch/arm/mach-omap1/dma.c | 390 arch/arm/mach-omap2/Makefile |2 +- arch/arm/mach-omap2/dma.c | 297 arch/arm/mach-omap2/omap_hwmod_2420_data.c | 86 arch/arm/mach-omap2/omap_hwmod_2430_data.c | 86 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 97 arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 101 arch/arm/plat-omap/dma.c | 697 arch/arm/plat-omap/include/plat/dma.h | 232 -- 10 files changed, 1450 insertions(+), 540 deletions(-) create mode 100644 arch/arm/mach-omap1/dma.c create mode 100644 arch/arm/mach-omap2/dma.c -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode
Kevin Hilman wrote, on 12/20/2010 06:44 PM:
Kevin Hilmankhil...@deeprootsystems.com writes:
Nishanth Menonn...@ti.com writes:
Currently omap3_cpuidle_update_states makes whole sale decision
on which C states to update based on enable_off_mode variable
Instead, achieve the same functionality by independently providing
mpu and core deepest states the system is allowed to achieve and
update the idle states accordingly.
Acked-by: Santosh Shilimkarsantosh.shilim...@ti.com
Acked-by: Jean Pihetj-pi...@ti.com
Signed-off-by: Nishanth Menonn...@ti.com
This patch doesnt' compile with CPUidle enabled.
You missed one other caller of the update_states function inside
cpuidle34xx.c which is only there when CONFIG_CPU_IDLE=y
Something like the following folded into this patch makes it compile and
work as before.
If this looks OK to you, I'll fold it in.
Kevin,
thanks. apologies on missing this. looks fine to me.
Kevin
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx
index ab4c862..0fb619c 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -517,7 +517,10 @@ int __init omap3_idle_init(void)
return -EINVAL;
dev-state_count = count;
- omap3_cpuidle_update_states();
+ if (enable_off_mode)
+ omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
+ else
+ omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
if (cpuidle_register_device(dev)) {
printk(KERN_ERR %s: CPUidle register device failed\n,
--
Regards,
Nishanth Menon
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Re: [PATCH v6 00/10] OMAP: Adding Smartreflex and Voltage driver support
* Kevin Hilman khil...@deeprootsystems.com [101220 17:05]: Thara Gopinath th...@ti.com writes: This patch series introduces smartreflex and voltage driver support for OMAP3430 and OMAP3630. SmartReflex modules do adaptive voltage control for real-time voltage adjustments. Thanks Thara, these are looking good for 2.6.38. Tony, unless there are major objections, I'll be queuing these two SR series for 2.6.38. They have dependencies on Paul's integration branch Well looking at patch 3/6 I think it should live under drivers somewhere and mostly be compiled as a module. Probably the only change needed for that is to not call cpu_is_omap but instead use some flags passed in the platform_data. Otherwise the whole series looks OK to me. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] adding gpmc configuration functions, west bridge related
This patch adds and exports gpmc configuration functions.
'gpmc' configuration functions will be used by
westbridge device controller driver in staging tree.
This patch is part of the work to get westbridge device controller driver
out of staging tree.
Signed-off-by: Sutharsan Ramamoorthy s...@cypress.com
---
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff
linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile
linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile 2010-11-29
20:42:04.0 -0800
+++ linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile 2010-12-13
16:04:08.378446603 -0800
@@ -182,6 +182,7 @@ obj-y += $(usbfs-m)
$(usbfs-y)
obj-y += usb-musb.o
obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
obj-y += usb-ehci.o
+obj-$(CONFIG_WESTBRIDGE_ASTORIA)+= usb-cywb-pnand.o
onenand-$(CONFIG_MTD_ONENAND_OMAP2):= gpmc-onenand.o
obj-y += $(onenand-m) $(onenand-y)
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff
linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c
linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c 1969-12-31
16:00:00.0 -0800
+++ linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c 2010-12-20
17:33:23.822251855 -0800
@@ -0,0 +1,170 @@
+/*
+ * linux /arch/arm/mach-omap2/usb-cywb-pnand.c
+ *
+ * Copyright (C) 2010 Cypress Semiconductor
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License.
+ */
+
+#include linux/module.h
+
+#include plat/gpmc.h
+
+/*
+ * chip select number on GPMC ( 0..7 )
+ */
+#define AST_GPMC_CS 4
+
+/*
+ * for use by gpmc_set_timings api, measured in ns, not clocks
+ */
+#define WB_GPMC_BUSCYC_t(7 * 6)
+#define WB_GPMC_CS_t_o_n(0)
+#define WB_GPMC_ADV_t_o_n (0)
+#define WB_GPMC_OE_t_o_n(0)
+#define WB_GPMC_OE_t_o_f_f (5 * 6)
+#define WB_GPMC_WE_t_o_n(1 * 6)
+#define WB_GPMC_WE_t_o_f_f (5 * 6)
+#define WB_GPMC_RDS_ADJ (2 * 6)
+#define WB_GPMC_RD_t_a_c_c (WB_GPMC_OE_t_o_f_f + WB_GPMC_RDS_ADJ)
+#define WB_GPMC_WR_t_a_c_c (WB_GPMC_BUSCYC_t)
+
+#define GPMC_16BIT_MODE 0
+#define GPMC_RETIME 1
+
+/*
+ * GPMC_CONFIG7[cs] register bit fields
+ * AS_CS_MASK - 3 bit mask for A26,A25,A24,
+ * AS_CS_BADDR - 6 BIT VALUE A29 ...A24
+ * CSVALID_B - CSVALID bit on GPMC_CONFIG7[cs] register
+ */
+#define AS_CS_MASK (0X7 8)
+#define AS_CS_BADDR 0x02
+#define CSVALID_B (1 6)
+
+#define BLKSZ_4K 0x1000
+
+/*
+ * switch GPMC DATA bus mode
+ */
+void cywb_gpmc_enable_16bit_bus(bool dbus16_enabled)
+{
+ u32 tmp32;
+
+ /*
+* disable gpmc CS4 operation 1st
+*/
+ tmp32 = gpmc_cs_read_reg(AST_GPMC_CS,
+ GPMC_CS_CONFIG7) ~GPMC_CONFIG7_CSVALID;
+ gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
+
+ /*
+* GPMC NAND data bus can be 8 or 16 bit wide
+*/
+ if (dbus16_enabled) {
+ dev_dbg(KERN_INFO gpmc: enabling 16 bit bus\n);
+ gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+ (GPMC_CONFIG1_DEVICETYPE(2) |
+ GPMC_CONFIG1_WAIT_PIN_SEL(2) |
+ GPMC_CONFIG1_DEVICESIZE_16));
+ } else {
+ dev_dbg(KERN_INFO gpmc: enabling 8 bit bus\n);
+ gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+ (GPMC_CONFIG1_DEVICETYPE(2) |
+ GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+ }
+
+ /*
+* re-enable astoria CS operation on GPMC
+*/
+gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+ (tmp32 | GPMC_CONFIG7_CSVALID));
+}
+
+int cywb_pnand_platform_retime(int action, bool dbus16_enabled)
+{
+ u32 tmp32;
+ struct gpmc_timings timings;
+ int retval;
+
+ switch (action) {
+
+ case GPMC_16BIT_MODE:
+ cywb_gpmc_enable_16bit_bus(dbus16_enabled);
+ retval = 0;
+ break;
+ case GPMC_RETIME:
+ gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+ (GPMC_CONFIG1_DEVICETYPE(2) |
+ GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+
+ memset(timings, 0, sizeof(timings));
+
+ /* cs timing */
+ timings.cs_on = WB_GPMC_CS_t_o_n;
+ timings.cs_wr_off = WB_GPMC_BUSCYC_t;
+ timings.cs_rd_off = WB_GPMC_BUSCYC_t;
+
+ /* adv timing */
+ timings.adv_on = WB_GPMC_ADV_t_o_n;
+ timings.adv_rd_off =
Re: [PATCH v6 00/10] OMAP: Adding Smartreflex and Voltage driver support
* Tony Lindgren t...@atomide.com [101220 18:31]: * Kevin Hilman khil...@deeprootsystems.com [101220 17:05]: Thara Gopinath th...@ti.com writes: This patch series introduces smartreflex and voltage driver support for OMAP3430 and OMAP3630. SmartReflex modules do adaptive voltage control for real-time voltage adjustments. Thanks Thara, these are looking good for 2.6.38. Tony, unless there are major objections, I'll be queuing these two SR series for 2.6.38. They have dependencies on Paul's integration branch Well looking at patch 3/6 I think it should live under drivers somewhere and mostly be compiled as a module. Probably the only change needed for that is to not call cpu_is_omap but instead use some flags passed in the platform_data. Otherwise the whole series looks OK to me. Considering the short time left, maybe you can leave out the driver part for now and merge all the platform related part for smartreflex? Sorry I really should have made that driver comment way earlier.. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 03/17] OMAP3: hwmod data: add DSS DISPC RFBI DSI VENC
Benoit, -Original Message- From: Taneja, Archit Sent: Monday, December 20, 2010 10:14 PM To: Tomi Valkeinen; Guruswamy, Senthilvadivu Cc: khil...@deeprootsystems.com; p...@pwsan.com; Hiremath, Vaibhav; linux- o...@vger.kernel.org Subject: RE: [PATCH v2 03/17] OMAP3: hwmod data: add DSS DISPC RFBI DSI VENC Hi, linux-omap-ow...@vger.kernel.org wrote: Hi, On Mon, 2010-11-29 at 17:21 +0530, ext Guruswamy Senthilvadivu wrote: From: Senthilvadivu Guruswamy svad...@ti.com Database generated for Display Sub System applicable for OMAP3430-ES2 onwards and OMAP36xx. dss is also considered as an IP as dispc,rfbi, and named as dss_dss. For all the IP modules in DSS, same clock is needed for enabling. hwmod sees as independent IPs, so same clock has to be repeated as .mainclk in each IP. OMAP3430ES1 do not have IDLEST bit to poll on for dss IP. So this hwmod is not applicable for 3430ES1. I'm not so familiar with hwmods, so I cannot comment much on the first three patches in this series. I'll continue going through the latter patches. One question though: what does the mainclk do? If it means a clock which enables access to the registers, I'm not sure it's entirely correct. The DSS clocking can be changed to get the functional clock from DSI PLL. On OMAP4 there are MODULEMODE bits for DSS and other domains, these need to be enabled to use the module, I think that's what mainclk represents here. You can have a look at the CM_DSS_DSS_CLKCTRL register in the OMAP4 TRM to get a better idea. So, instead of explicitly enabling/disabling the interface clocks like we did for DSS in omap3, we just need to ensure that MODULEMODE bits are set, setting this will take care of enabling/gating interface clocks based on the state of the clock domain. I think we consider the DSS1_ALWAYSON_FCK as the mainclk. Others, please correct me if I am wrong. [Senthil] I too have the same understanding. Its ensured that .main_clk should be with DSS1_ALWAYSON_FCK in the static database because it is necessary before switch to DSI PLL could happen. The main point to consider from Tomi's query is that DSS functional clock could be changed dynamically to that of DSI PLL. Can this change be accommodated dynamically in hwmod database so that further pm_runtime_get_sync/put_sync could address DSI PLL instead of DSS_FCK? Benoit should be able to answer this query. Regards, Archit Then a general comment about all the patches in the series: The commit descriptions do not seem to be of very high quality. They are short and poorly formatted. The descriptions are almost as important as the patch itself. Here's a nice text about commit messages: http://who-t.blogspot.com/2009/12/on-commit-messages.html And some comments of my own: - Use capital letters for DSS, DISPC, etc. when not spesifically referring to some variable or similar. - Use space after comma. - Wrap the lines consistently. Now it looks like the lines are wrapped at random points in some commits. - Use an empty line between paragraphs - While I understand that you (me neither) are not native english speaker, try to spend some time to be sure that there are no errors due to carelessness. - Remember that the 00 patch is not saved in git, so it should only be an intro, and all the relevant information should be found in the actual commit messages. Tomi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT] pull request: DMA hwmod changes
Hi, * G, Manjunath Kondaiah manj...@ti.com [101220 18:11]: Hi Tony, Benoit comments are taken care and new pull request is generated as below. The omap4 hwmod database for dma is rearranged as per Benoit's convention + no idlest flag entry is removed + sysc_flags are barrowed from latest omap4 hwmod data base. OK great, I've applied them now. The following changes since commit 205e4d6e8d892176d791b77a974efe7f561ca4c3: Merge branch 'for-next' (2010-12-17 19:32:47 -0800) I ended up cherry picking them. For next time, note that you should not do any git branches to pull against anything but mainline tags. Otherwise tons of non-mainline history would get merged.. If you cannot base your branch on some recent mainline tag because of conflicts, then you should use some branch that will stay around, like what we have queued into omap-for-linus. Cheers, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] adding gpmc configuration functions, west bridge related
On Mon, Dec 20, 2010 at 06:42:06PM -0800, Sutharsan R wrote:
This patch adds and exports gpmc configuration functions.
'gpmc' configuration functions will be used by
westbridge device controller driver in staging tree.
This patch is part of the work to get westbridge device controller driver
out of staging tree.
Signed-off-by: Sutharsan Ramamoorthy s...@cypress.com
---
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff
linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile
linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/Makefile 2010-11-29
20:42:04.0 -0800
+++ linux-2.6.37-cywb/arch/arm/mach-omap2/Makefile2010-12-13
16:04:08.378446603 -0800
Your patch is linewrapped :(
@@ -182,6 +182,7 @@ obj-y += $(usbfs-m)
$(usbfs-y)
obj-y+= usb-musb.o
obj-$(CONFIG_MACH_OMAP2_TUSB6010)+= usb-tusb6010.o
obj-y+= usb-ehci.o
+obj-$(CONFIG_WESTBRIDGE_ASTORIA)+= usb-cywb-pnand.o
onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
obj-y+= $(onenand-m) $(onenand-y)
diff -uprN -X linux-2.6.37_vanilla/Documentation/dontdiff
linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c
linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c
--- linux-2.6.37_vanilla/arch/arm/mach-omap2/usb-cywb-pnand.c 1969-12-31
16:00:00.0 -0800
+++ linux-2.6.37-cywb/arch/arm/mach-omap2/usb-cywb-pnand.c2010-12-20
17:33:23.822251855 -0800
@@ -0,0 +1,170 @@
+/*
+ * linux /arch/arm/mach-omap2/usb-cywb-pnand.c
+ *
+ * Copyright (C) 2010 Cypress Semiconductor
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License.
Either, or what?
+ */
+
+#include linux/module.h
+
+#include plat/gpmc.h
Why the extra lines inbetween the #includes?
+
+/*
+ * chip select number on GPMC ( 0..7 )
+ */
+#define AST_GPMC_CS 4
+
+/*
+ * for use by gpmc_set_timings api, measured in ns, not clocks
+ */
+#define WB_GPMC_BUSCYC_t(7 * 6)
What's with the lowercase values in #defines?
+#define WB_GPMC_CS_t_o_n(0)
+#define WB_GPMC_ADV_t_o_n (0)
+#define WB_GPMC_OE_t_o_n(0)
+#define WB_GPMC_OE_t_o_f_f (5 * 6)
+#define WB_GPMC_WE_t_o_n(1 * 6)
+#define WB_GPMC_WE_t_o_f_f (5 * 6)
+#define WB_GPMC_RDS_ADJ (2 * 6)
+#define WB_GPMC_RD_t_a_c_c (WB_GPMC_OE_t_o_f_f + WB_GPMC_RDS_ADJ)
+#define WB_GPMC_WR_t_a_c_c (WB_GPMC_BUSCYC_t)
+
+#define GPMC_16BIT_MODE 0
+#define GPMC_RETIME 1
+
+/*
+ * GPMC_CONFIG7[cs] register bit fields
+ * AS_CS_MASK - 3 bit mask for A26,A25,A24,
+ * AS_CS_BADDR - 6 BIT VALUE A29 ...A24
+ * CSVALID_B - CSVALID bit on GPMC_CONFIG7[cs] register
+ */
+#define AS_CS_MASK (0X7 8)
+#define AS_CS_BADDR 0x02
+#define CSVALID_B (1 6)
+
+#define BLKSZ_4K 0x1000
+
+/*
+ * switch GPMC DATA bus mode
+ */
+void cywb_gpmc_enable_16bit_bus(bool dbus16_enabled)
+{
+ u32 tmp32;
+
+ /*
+ * disable gpmc CS4 operation 1st
+ */
+ tmp32 = gpmc_cs_read_reg(AST_GPMC_CS,
+ GPMC_CS_CONFIG7) ~GPMC_CONFIG7_CSVALID;
+ gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7, tmp32);
+
+ /*
+ * GPMC NAND data bus can be 8 or 16 bit wide
+ */
+ if (dbus16_enabled) {
+ dev_dbg(KERN_INFO gpmc: enabling 16 bit bus\n);
+ gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+ (GPMC_CONFIG1_DEVICETYPE(2) |
+ GPMC_CONFIG1_WAIT_PIN_SEL(2) |
+ GPMC_CONFIG1_DEVICESIZE_16));
+ } else {
+ dev_dbg(KERN_INFO gpmc: enabling 8 bit bus\n);
+ gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+ (GPMC_CONFIG1_DEVICETYPE(2) |
+ GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+ }
+
+ /*
+ * re-enable astoria CS operation on GPMC
+ */
+ gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG7,
+ (tmp32 | GPMC_CONFIG7_CSVALID));
+}
+
+int cywb_pnand_platform_retime(int action, bool dbus16_enabled)
+{
+ u32 tmp32;
+ struct gpmc_timings timings;
+ int retval;
Set retval to 0 first, then you don't have to set it for when things go
right, only when things go wrong.
+
+ switch (action) {
+
+ case GPMC_16BIT_MODE:
+ cywb_gpmc_enable_16bit_bus(dbus16_enabled);
+ retval = 0;
+ break;
+ case GPMC_RETIME:
+ gpmc_cs_write_reg(AST_GPMC_CS, GPMC_CS_CONFIG1,
+ (GPMC_CONFIG1_DEVICETYPE(2) |
+ GPMC_CONFIG1_WAIT_PIN_SEL(2)));
+
+
[PATCH v1 1/2] OMAP: hwmod: API to handle autoidle mode
Create a new API that forms a wrapper to _set_module_autoidle()
to modify the AUTOIDLE bit.
This API is intended to be used by drivers that requires direct
manipulation of the AUTOIDLE bits in SYSCONFIG register.
McBSP driver requires autoidle bit to be enabled/disabled while
using sidetone feature.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Benoit Cousson b-cous...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 35 ++
arch/arm/plat-omap/include/plat/omap_hwmod.h |1 +
2 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5a30658..e016cd9 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1251,6 +1251,41 @@ int _omap_hwmod_idle(struct omap_hwmod *oh)
}
/**
+ * omap_hwmod_set_slave_autoidle - set the hwmod's OCP slave autoidle
+ * @oh: struct omap_hwmod *
+ * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
+ *
+ * Sets the IP block's OCP slave autoidle in hardware, and updates our
+ * local copy. Intended to be used by drivers that requires
+ * direct manipulation of the AUTOIDLE bits.
+ * Returns -EINVAL if @oh is null, or passes along the return value
+ * from _set_module_autoidle().
+ *
+ * Any users of this function should be scrutinized carefully.
+ */
+int omap_hwmod_set_slave_autoidle(struct omap_hwmod *oh, u8 autoidle)
+{
+ u32 v;
+ int retval = 0;
+
+ if (!oh)
+ return -EINVAL;
+
+ mutex_lock(omap_hwmod_mutex);
+
+ v = oh-_sysc_cache;
+
+ retval = _set_module_autoidle(oh, autoidle, v);
+
+ if (!retval)
+ _write_sysconfig(v, oh);
+
+ mutex_unlock(omap_hwmod_mutex);
+
+ return retval;
+}
+
+/**
* _shutdown - shutdown an omap_hwmod
* @oh: struct omap_hwmod *
*
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h
b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 7eaa8ed..1871b5a 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -525,6 +525,7 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
+int omap_hwmod_set_slave_autoidle(struct omap_hwmod *oh, u8 autoidle);
int omap_hwmod_reset(struct omap_hwmod *oh);
void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
--
1.7.0.4
--
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