[PATCH v2 RFC] clk: add gpio controlled clock
The added clk-gpio is a basic clock that can be enabled and disabled
trough a gpio output. The DT binding document for the clock is also
added.
Signed-off-by: Jyri Sarha jsa...@ti.com
---
.../devicetree/bindings/clock/gpio-clock.txt | 21 +++
drivers/clk/Makefile |1 +
drivers/clk/clk-gpio.c | 155
include/linux/clk-provider.h | 25
4 files changed, 202 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/gpio-clock.txt
create mode 100644 drivers/clk/clk-gpio.c
diff --git a/Documentation/devicetree/bindings/clock/gpio-clock.txt
b/Documentation/devicetree/bindings/clock/gpio-clock.txt
new file mode 100644
index 000..54fea39
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/gpio-clock.txt
@@ -0,0 +1,21 @@
+Binding for simple gpio controlled clock.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be gpio-clock.
+- #clock-cells : from common clock binding; shall be set to 0.
+- enable-gpios : GPIO reference for enabling and disabling the clock.
+
+Optional properties:
+- clocks: Maximum of one parent clock is supported.
+
+Example:
+ clock {
+ compatible = gpio-clock;
+ clocks = parentclk;
+ #clock-cells = 0;
+ enable-gpios = gpio 1 GPIO_ACTIVE_HIGH;
+ };
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7d74d06..81b65a3 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-rate.o
obj-$(CONFIG_COMMON_CLK) += clk-gate.o
obj-$(CONFIG_COMMON_CLK) += clk-mux.o
obj-$(CONFIG_COMMON_CLK) += clk-composite.o
+obj-$(CONFIG_COMMON_CLK) += clk-gpio.o
# SoCs specific
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c
new file mode 100644
index 000..ff24567
--- /dev/null
+++ b/drivers/clk/clk-gpio.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2012 Texas Instruments
+ * Author: Jyri Sarha jsa...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Gpio controlled clock implementation
+ */
+
+#include linux/clk-provider.h
+#include linux/module.h
+#include linux/slab.h
+#include linux/gpio.h
+#include linux/of_gpio.h
+#include linux/err.h
+#include linux/device.h
+
+/**
+ * DOC: basic gpio controlled clock which can be enabled and disabled
+ * with gpio output
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent is (un)prepared
+ * enable - clk_enable and clk_disable are functional control gpio
+ * rate - inherits rate from parent. No clk_set_rate support
+ * parent - fixed parent. No clk_set_parent support
+ */
+
+#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
+
+static int clk_gpio_enable(struct clk_hw *hw)
+{
+ struct clk_gpio *gpio = to_clk_gpio(hw);
+ int value = gpio-active_low ? 0 : 1;
+
+ gpio_set_value(gpio-gpio, value);
+
+ return 0;
+}
+
+static void clk_gpio_disable(struct clk_hw *hw)
+{
+ struct clk_gpio *gpio = to_clk_gpio(hw);
+ int value = gpio-active_low ? 1 : 0;
+
+ gpio_set_value(gpio-gpio, value);
+}
+
+static int clk_gpio_is_enabled(struct clk_hw *hw)
+{
+ struct clk_gpio *gpio = to_clk_gpio(hw);
+ int value = gpio_get_value(gpio-gpio);
+
+ return gpio-active_low ? !value : value;
+}
+
+const struct clk_ops clk_gpio_ops = {
+ .enable = clk_gpio_enable,
+ .disable = clk_gpio_disable,
+ .is_enabled = clk_gpio_is_enabled,
+};
+EXPORT_SYMBOL_GPL(clk_gpio_ops);
+
+/**
+ * clk_register_gpio - register a gpip clock with the clock framework
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_name: name of this clock's parent
+ * @flags: framework-specific flags for this clock
+ * @gpio: gpio to control this clock
+ * @active_low: gpio polarity
+ */
+struct clk *clk_register_gpio(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ unsigned int gpio, bool active_low)
+{
+ struct clk_gpio *clk_gpio;
+ struct clk *clk;
+ struct clk_init_data init = { NULL };
+ unsigned long gpio_flags;
+ int err;
+
+ if (active_low)
+ gpio_flags = GPIOF_OUT_INIT_LOW;
+ else
+ gpio_flags = GPIOF_OUT_INIT_HIGH;
+
+ err = gpio_request_one(gpio, gpio_flags, name);
+ if (err) {
+ pr_err(%s: Error requesting clock control gpio %u\n,
+ __func__, gpio);
+ return ERR_PTR(err);
+ }
+
+ clk_gpio = devm_kzalloc(dev,
Re: [PATCHv9 07/43] CLK: TI: add autoidle support
On 11/04/2013 04:59 PM, Nishanth Menon wrote: On 11/04/2013 04:00 AM, Tero Kristo wrote: On 11/01/2013 09:16 PM, Nishanth Menon wrote: On 11/01/2013 04:18 AM, Tero Kristo wrote: [...] one other thing I missed, will be nice to introduce a common bindings for autoidle which tends to be reused in other drivers.. You mean documentation or? Autoidle from this patch is only used by two clock drivers (divider + fixed-factor.) DPLLs use completely different setup. Converting the interface clocks to use the same might be rather nasty thing to do. The definitions are common - so, yes, it will be nice to have autoidle.txt which is then pointed to by divider, fixed-clock etc.. Ok can add that. -Tero -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv9 13/43] clk: ti: add support for basic mux clock
On 11/01/2013 11:01 PM, Nishanth Menon wrote:
On 10/25/2013 10:57 AM, Tero Kristo wrote:
[...]
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
new file mode 100644
index 000..9c5259a
--- /dev/null
+++ b/drivers/clk/ti/mux.c
[...]
+/**
+ * of_mux_clk_setup() - Setup function for simple mux rate clock
+ */
+static int of_mux_clk_setup(struct device_node *node, struct regmap *regmap)
$ ./scripts/kernel-doc drivers/clk/ti/mux.c /dev/null
Warning(drivers/clk/ti/mux.c:29): No description found for parameter
'node'
Warning(drivers/clk/ti/mux.c:29): No description found for parameter
'regmap'
I suggest in the next rev we do a verification if we have kernel doc
errors as well..
+{
+ struct clk *clk;
+ const char *clk_name = node-name;
+ void __iomem *reg;
+ int num_parents;
+ const char **parent_names;
+ int i;
+ u8 clk_mux_flags = 0;
+ u32 mask = 0;
+ u32 shift = 0;
+ u32 flags = 0;
+ u32 val;
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents 1) {
+ pr_err(%s: mux-clock %s must have parent(s)\n,
+ __func__, node-name);
+ return -EINVAL;
+ }
+ parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
+ if (!parent_names) {
+ pr_err(%s: memory alloc failed\n, __func__);
as discussed, could be dropped.
Yep.
+ return -ENOMEM;
+ }
+
+ for (i = 0; i num_parents; i++)
+ parent_names[i] = of_clk_get_parent_name(node, i);
+
+ of_property_read_u32(node, reg, val);
is'nt this mandatory? error check?
Will add.
+ reg = (void *)val;
+
+ if (of_property_read_u32(node, ti,bit-shift, shift)) {
+ pr_debug(%s: bit-shift property defaults to 0x%x for %s\n,
+__func__, shift, node-name);
why a debug if this is optional?
Well, it might be good for debugging if someone forgets the shift when
he was supposed to add one. I could also make this a required property,
but this will increase the dtb size slightly, there are quite a few
mux-clocks around with 0 bit-shift atm.
+ }
+
+ if (of_property_read_bool(node, ti,index-starts-at-one))
+ clk_mux_flags |= CLK_MUX_INDEX_ONE;
+
+ if (of_property_read_bool(node, ti,set-rate-parent))
+ flags |= CLK_SET_RATE_PARENT;
+
+ /* Generate bit-mask based on parent info */
+ mask = num_parents;
+ if (!(clk_mux_flags CLK_MUX_INDEX_ONE))
+ mask--;
we are assuming there wont be holes in the map (like reserved mux option?)
Yes. Currently this is the case at least, but we can add more beef to
the binding to handle holes if this comes up in future. Or alternatively
just add dummy-ck as mux parent and cover the holes that way.
+
+ mask = (1 fls(mask)) - 1;
+
+ clk = clk_register_mux_table_regmap(NULL, clk_name, parent_names,
+ num_parents, flags, reg, regmap,
+ shift, mask, clk_mux_flags, NULL,
+ NULL);
+
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return 0;
+ }
+
kfree(parent_names)?
Yea, will add.
+ return PTR_ERR(clk);
+}
+CLK_OF_DECLARE(mux_clk, ti,mux-clock, of_mux_clk_setup);
+
+static int __init of_ti_composite_mux_clk_setup(struct device_node *node,
+ struct regmap *regmap)
+{
+ struct clk_mux *mux;
+ int num_parents;
+ int ret;
+ u32 val;
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return -ENOMEM;
+
+ of_property_read_u32(node, reg, val);
is'nt this mandatory? error check?
Will add.
+
+ mux-reg = (void *)val;
+ mux-regmap = regmap;
+
+ if (of_property_read_u32(node, ti,bit-shift, val)) {
+ pr_debug(%s: no bit-shift for %s, default=0\n,
+__func__, node-name);
+ val = 0;
+ }
+ mux-shift = val;
+
+ num_parents = of_clk_get_parent_count(node);
mandatory parameter without check?
Will add.
ti,index-starts-at-one, ti,set-rate-parent
these seem not supported here even though the bindings dont tell us that.
Yeah, composite-mux-clock documentation is somewhat broken at the
moment, will look at that.
+
+ mux-mask = num_parents - 1;
+ mux-mask = (1 fls(mux-mask)) - 1;
+
+ ret = ti_clk_add_component(node, mux-hw, CLK_COMPONENT_TYPE_MUX);
+ if (!ret)
+ return 0;
+
+ kfree(mux);
+ return -ret;
+}
+CLK_OF_DECLARE(ti_composite_mux_clk_setup, ti,composite-mux-clock,
+ of_ti_composite_mux_clk_setup);
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Re: [PATCHv9 32/43] ARM: dts: AM35xx: use DT clock data
On 11/01/2013 11:18 PM, Nishanth Menon wrote:
On 10/25/2013 10:57 AM, Tero Kristo wrote:
[...]
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
new file mode 100644
index 000..c555443
--- /dev/null
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Device Tree Source for AM3517 SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed as is without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include omap3.dtsi
+
+/ {
+ cpus {
+ cpu@0 {
+ /* OMAP343x/OMAP35xx variants OPP1-5 */
^^ you could fix the comment since this is OMAP35xx variant :)
Ok. :)
+ operating-points =
+ /* kHzuV */
+ 125000 975000
+ 25 1075000
+ 50 120
+ 55 127
+ 60 135
+ ;
+ clock-latency = 30; /* From legacy driver */
+ };
+ };
+};
[..]
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Re: [PATCHv9 38/43] ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT
On 11/01/2013 11:07 PM, Nishanth Menon wrote:
On 10/25/2013 10:57 AM, Tero Kristo wrote:
[...]
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 228b850..6fa74c6 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
[...]
+/*
+ * XXX: implementation for the regmap read/write should be moved to
+ * individual PRCM IP drivers, once those are available.
+ */
+static int ti_clk_regmap_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ void __iomem *mem = context;
+ *val = __raw_readl(mem + reg);
+ return 0;
+}
+
+static int ti_clk_regmap_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ void __iomem *mem = context;
+ __raw_writel(val, mem + reg);
+ return 0;
+}
+
+static struct regmap_config ti_clk_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .reg_read = ti_clk_regmap_read,
+ .reg_write = ti_clk_regmap_write,
+ .fast_io = true,
+ .cache_type = REGCACHE_NONE,
+ .reg_format_endian = REGMAP_ENDIAN_NATIVE,
+ .val_format_endian = REGMAP_ENDIAN_NATIVE,
+};
why not use regmap_mmio?
I was thinking about using it, however this will allow us to route
everything to their individual driver APIs. Anyway, I guess that is
rather moot point so I will look at this again.
-Tero
[...]
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[PATCH RESEND] arm: omap2plus_defconfig: enable AM33xx SOC EVM audio
Modifying the omap2plus_defconfig to enable the audio support for AM335x EVM and other AM33xx based devices with TLV320AIC3X connected to McASP. Signed-off-by: Jyri Sarha jsa...@ti.com --- arch/arm/configs/omap2plus_defconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 254cf05..4443b92 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -210,6 +210,8 @@ CONFIG_SND_DEBUG=y CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=m CONFIG_SND_OMAP_SOC=m +CONFIG_SND_AM33XX_SOC_EVM=m +CONFIG_SND_DAVINCI_SOC=m CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RESEND] arm: omap2plus_defconfig: enable AM33xx SOC EVM audio
Hi Tony, The audio support for am335x-emv and am335x-evmsk has been merged: http://www.spinics.net/lists/linux-omap/msg99282.html http://www.spinics.net/lists/linux-omap/msg99135.html Best regards, Jyri Jyri Sarha (1): arm: omap2plus_defconfig: enable AM33xx SOC EVM audio arch/arm/configs/omap2plus_defconfig |2 ++ 1 file changed, 2 insertions(+) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/4] wl1251: split wl251 platform data to a separate structure
On Sun 2013-10-27 17:14:26, Sebastian Reichel wrote: From: Luciano Coelho coe...@ti.com Move the wl1251 part of the wl12xx platform data structure into a new structure specifically for wl1251. Change the platform data built-in block and board files accordingly. Cc: Tony Lindgren t...@atomide.com Signed-off-by: Luciano Coelho coe...@ti.com Acked-by: Tony Lindgren t...@atomide.com Reviewed-by: Felipe Balbi ba...@ti.com Reviewed-by: Pavel Machek pa...@ucw.cz -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/4] wl1251: move power GPIO handling into the driver
On Sun 2013-10-27 17:14:27, Sebastian Reichel wrote: Move the power GPIO handling from the board code into the driver. This is a dependency for device tree support. Signed-off-by: Sebastian Reichel s...@debian.org Reviewed-by: Pavel Machek pa...@ucw.cz -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/4] wl1251: spi: add vio regulator support
On Sun 2013-10-27 17:14:28, Sebastian Reichel wrote: This patch adds support for requesting the regulator powering the vio pin. The patch also adds the regulator for the all boards using the wl1251 in spi mode (only the Nokia N900). Signed-off-by: Sebastian Reichel s...@debian.org Reviewed-by: Pavel Machek pa...@ucw.cz -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V3 0/7] DRIVERS: IRQCHIP: Add support for crossbar IP
Some socs have a large number of interrupts requests to service the needs of its many peripherals and subsystems. All of the interrupt requests lines from the subsystems are not needed at the same time, so they have to be muxed to the controllers appropriately. In such places a interrupt controllers are preceded by an IRQ CROSSBAR that provides flexibility in muxing the device interrupt requests to the controller inputs. This series models the peripheral interrupts that can be routed through the crossbar to the GIC as 'routable-irqs'. The routable irqs are added in a separate linear domain inside the GIC. The registered routable domain's callback are invoked as a part of the GIC's callback, which in turn should allocate a free irq line and configure the IP accordingly. So every peripheral in the dts files mentions the fixed crossbar number as its interrupt. A free gic line for that gets allocated and configured when the peripheral interrupts are mapped. The minimal crossbar driver to track and allocate free GIC lines and configure the crossbar is added here, along with the DT bindings. V3: Addressed few more comments from Thomas Gleixner t...@linutronix.de Rebased patches 3,4,5,7 which updates the DTS file on top of below branch git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.13/dts Rebased patches 1,2,6 on top of 3.12 mainline Updated Commit tags V2: Addressed Thomas Gleixner t...@linutronix.de comments and Kumar Gala ga...@codeaurora.org Split updating the DRA7.dtsi file for adding the routable-irqs Previous discussions that led to this is at https://lkml.org/lkml/2013/9/18/540 The V1,V2 post of these patches is at [V1] https://lkml.org/lkml/2013/9/30/283 [V2] http://www.spinics.net/lists/linux-omap/msg99540.html Sricharan R (7): DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP ARM: DTS: DRA: Add crossbar device binding ARM: DTS: DRA: Replace peripheral interrupt numbers with crossbar inputs ARM: DTS: DRA7: Add routable-irqs property for gic node ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number ARM: DRA: Enable Crossbar IP support for DRA7XX Documentation/devicetree/bindings/arm/gic.txt |6 + .../devicetree/bindings/arm/omap/crossbar.txt | 27 +++ arch/arm/boot/dts/dra7.dtsi| 95 + arch/arm/mach-omap2/Kconfig|1 + arch/arm/mach-omap2/omap-wakeupgen.c |4 +- arch/arm/mach-omap2/omap4-common.c |4 + drivers/irqchip/Kconfig|8 + drivers/irqchip/Makefile |1 + drivers/irqchip/irq-crossbar.c | 206 drivers/irqchip/irq-gic.c | 81 +++- include/linux/irqchip/arm-gic.h|8 +- include/linux/irqchip/irq-crossbar.h | 11 ++ 12 files changed, 396 insertions(+), 56 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt create mode 100644 drivers/irqchip/irq-crossbar.c create mode 100644 include/linux/irqchip/irq-crossbar.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V3 7/7] ARM: DRA: Enable Crossbar IP support for DRA7XX
Enable the crossbar IP support for DRA7xx soc.
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/mach-omap2/Kconfig|1 +
arch/arm/mach-omap2/omap4-common.c |4
2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b5fb5f7..2086c65 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -141,6 +141,7 @@ config SOC_DRA7XX
select ARM_GIC
select HAVE_SMP
select COMMON_CLK
+ select IRQ_CROSSBAR
comment OMAP Core Type
depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch/arm/mach-omap2/omap4-common.c
index 5791143..274cbfa 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -22,6 +22,7 @@
#include linux/of_platform.h
#include linux/export.h
#include linux/irqchip/arm-gic.h
+#include linux/irqchip/irq-crossbar.h
#include linux/of_address.h
#include linux/reboot.h
@@ -282,9 +283,12 @@ void __init omap_gic_of_init(void)
skip_errata_init:
omap_wakeupgen_init();
+ if (soc_is_dra7xx())
+ crossbar_init();
irqchip_init();
}
+
#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
static int omap4_twl6030_hsmmc_late_init(struct device *dev)
{
--
1.7.9.5
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[PATCH V3 6/7] ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
The wakeup gen mask/unmask callback uses the irq element of the irq_data to setup. The irq is the linux virtual irq number and is same as the hardware irq number only when the parent irqchip is setup as a legacy domain. When it is used as a linear domain, the virtual irqs are allocated dynamically and wakeup gen code cannot rely on these numbers to access the irq registers. Instead use the hwirq element of the irq_data which represent the physical irq number. Cc: Santosh Shilimkar santosh.shilim...@ti.com Cc: Rajendra Nayak rna...@ti.com Cc: Tony Lindgren t...@atomide.com Signed-off-by: Sricharan R r.sricha...@ti.com --- arch/arm/mach-omap2/omap-wakeupgen.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 813c615..b813f4b 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -134,7 +134,7 @@ static void wakeupgen_mask(struct irq_data *d) unsigned long flags; raw_spin_lock_irqsave(wakeupgen_lock, flags); - _wakeupgen_clear(d-irq, irq_target_cpu[d-irq]); + _wakeupgen_clear(d-hwirq, irq_target_cpu[d-hwirq]); raw_spin_unlock_irqrestore(wakeupgen_lock, flags); } @@ -146,7 +146,7 @@ static void wakeupgen_unmask(struct irq_data *d) unsigned long flags; raw_spin_lock_irqsave(wakeupgen_lock, flags); - _wakeupgen_set(d-irq, irq_target_cpu[d-irq]); + _wakeupgen_set(d-hwirq, irq_target_cpu[d-hwirq]); raw_spin_unlock_irqrestore(wakeupgen_lock, flags); } -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V3 5/7] ARM: DTS: DRA7: Add routable-irqs property for gic node
There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Cc: Benoit Cousson bcous...@baylibre.com Cc: Santosh Shilimkar santosh.shilim...@ti.com Cc: Rajendra Nayak rna...@ti.com Cc: Tony Lindgren t...@atomide.com Signed-off-by: Sricharan R r.sricha...@ti.com --- arch/arm/boot/dts/dra7.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 8b93b7a..fd58a09 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -67,6 +67,7 @@ compatible = arm,cortex-a15-gic; interrupt-controller; #interrupt-cells = 3; + arm,routable-irqs = 160; reg = 0x48211000 0x1000, 0x48212000 0x1000, 0x48214000 0x2000, -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V3 2/7] DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are preceded by an CROSSBAR
that provides flexibility in muxing the device requests to the controller
inputs.
This driver takes care a allocating a free irq and then configuring the
crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should
be called right before the irqchip_init, so that it is setup to handle the
irqchip callbacks.
Cc: Thomas Gleixner t...@linutronix.de
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Tony Lindgren t...@atomide.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Sricharan R r.sricha...@ti.com
Acked-by: Kumar Gala ga...@codeaurora.org (for DT binding portion)
---
[V2] Addressed Thomas Gleixner t...@linutronix.de comments
and renamed the bindings as per Kumar Gala ga...@codeaurora.org
comments.
[V3] Changed static inline const to static inline int and removed
unnecessary variable initialization as per
Thomas Gleixner t...@linutronix.de. Updated commit tags
.../devicetree/bindings/arm/omap/crossbar.txt | 27 +++
drivers/irqchip/Kconfig|8 +
drivers/irqchip/Makefile |1 +
drivers/irqchip/irq-crossbar.c | 206
include/linux/irqchip/irq-crossbar.h | 11 ++
5 files changed, 253 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/omap/crossbar.txt
create mode 100644 drivers/irqchip/irq-crossbar.c
create mode 100644 include/linux/irqchip/irq-crossbar.h
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
new file mode 100644
index 000..fb88585
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -0,0 +1,27 @@
+Some socs have a large number of interrupts requests to service
+the needs of its many peripherals and subsystems. All of the
+interrupt lines from the subsystems are not needed at the same
+time, so they have to be muxed to the irq-controller appropriately.
+In such places a interrupt controllers are preceded by an CROSSBAR
+that provides flexibility in muxing the device requests to the controller
+inputs.
+
+Required properties:
+- compatible : Should be ti,irq-crossbar
+- reg: Base address and the size of the crossbar registers.
+- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- ti,reg-size: Size of a individual register in bytes. Every individual
+ register is assumed to be of same size. Valid sizes are 1, 2, 4.
+- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
+crossbar. These interrupt lines are reserved in the soc,
+so crossbar bar driver should not consider them as free
+lines.
+
+Examples:
+ crossbar_mpu: @4a02 {
+ compatible = ti,irq-crossbar;
+ reg = 0x4a002a48 0x130;
+ ti,max-irqs = 160;
+ ti,reg-size = 2;
+ ti,irqs-reserved = 0 1 2 3 5 6 131 132 139 140;
+ };
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3792a1a..2efcde6 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -61,3 +61,11 @@ config VERSATILE_FPGA_IRQ_NR
int
default 4
depends on VERSATILE_FPGA_IRQ
+
+config IRQ_CROSSBAR
+ bool
+ help
+ Support for a CROSSBAR ip that preceeds the main interrupt controller.
+ The primary irqchip invokes the crossbar's callback which inturn
allocates
+ a free irq and configures the IP. Thus the peripheral interrupts are
+ routed to one of the free irqchip interrupt lines.
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index c60b901..2edead9 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_RENESAS_IRQC)+= irq-renesas-irqc.o
obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o
obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
+obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
new file mode 100644
index 000..0af209e
--- /dev/null
+++ b/drivers/irqchip/irq-crossbar.c
@@ -0,0 +1,206 @@
+/*
+ * drivers/irqchip/irq-crossbar.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated -
[PATCH V3 4/7] ARM: DTS: DRA: Replace peripheral interrupt numbers with crossbar inputs
Now with the crossbar IP in picture, the peripherals do not have the
fixed interrupt lines. Instead they rely on the crossbar irqchip to
allocate and map a free interrupt line to its crossbar input. So replacing
all the peripheral interrupt numbers with its fixed crossbar input lines.
Cc: Benoit Cousson bcous...@baylibre.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 86 +--
1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index cf0d6ca..8b93b7a 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -122,10 +122,10 @@
sdma: dma-controller@4a056000 {
compatible = ti,omap4430-sdma;
reg = 0x4a056000 0x1000;
- interrupts = GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
#dma-cells = 1;
#dma-channels = 32;
#dma-requests = 127;
@@ -134,7 +134,7 @@
gpio1: gpio@4ae1 {
compatible = ti,omap4-gpio;
reg = 0x4ae1 0x200;
- interrupts = GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio1;
gpio-controller;
#gpio-cells = 2;
@@ -145,7 +145,7 @@
gpio2: gpio@48055000 {
compatible = ti,omap4-gpio;
reg = 0x48055000 0x200;
- interrupts = GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio2;
gpio-controller;
#gpio-cells = 2;
@@ -156,7 +156,7 @@
gpio3: gpio@48057000 {
compatible = ti,omap4-gpio;
reg = 0x48057000 0x200;
- interrupts = GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio3;
gpio-controller;
#gpio-cells = 2;
@@ -167,7 +167,7 @@
gpio4: gpio@48059000 {
compatible = ti,omap4-gpio;
reg = 0x48059000 0x200;
- interrupts = GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio4;
gpio-controller;
#gpio-cells = 2;
@@ -178,7 +178,7 @@
gpio5: gpio@4805b000 {
compatible = ti,omap4-gpio;
reg = 0x4805b000 0x200;
- interrupts = GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio5;
gpio-controller;
#gpio-cells = 2;
@@ -189,7 +189,7 @@
gpio6: gpio@4805d000 {
compatible = ti,omap4-gpio;
reg = 0x4805d000 0x200;
- interrupts = GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio6;
gpio-controller;
#gpio-cells = 2;
@@ -200,7 +200,7 @@
gpio7: gpio@48051000 {
compatible = ti,omap4-gpio;
reg = 0x48051000 0x200;
- interrupts = GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio7;
gpio-controller;
#gpio-cells = 2;
@@ -211,7 +211,7 @@
gpio8: gpio@48053000 {
compatible = ti,omap4-gpio;
reg = 0x48053000 0x200;
- interrupts = GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio8;
gpio-controller;
[PATCH V3 3/7] ARM: DTS: DRA: Add crossbar device binding
This adds the irq crossbar device node.
There is a IRQ crossbar device in the soc, which
maps the irq requests from the peripherals to the
mpu interrupt controller's inputs. The Peripheral irq
requests are connected to only one crossbar
input and the output of the crossbar is connected to only one
controller's input line. The crossbar device is used to map
a peripheral input to a free mpu's interrupt controller line.
Cc: Benoit Cousson bcous...@baylibre.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d0df4c4..cf0d6ca 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -583,4 +583,12 @@
status = disabled;
};
};
+
+ crossbar_mpu: crossbar@4a02 {
+ compatible = ti,irq-crossbar;
+ reg = 0x4a002a48 0x130;
+ ti,max-irqs = 160;
+ ti,reg-size = 2;
+ ti,irqs-reserved = 0 1 2 3 5 6 131 132 139 140;
+ };
};
--
1.7.9.5
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[PATCH V3 1/7] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input line.
The DT entries for peripherals provides the fixed crossbar input line
as its interrupt number and the mapping code should associate this with
a free gic input line. This patch adds the support inside the gic irqchip
to handle such routable irqs. The routable irqs are registered in a linear
domain. The registered routable domain's callback should be implemented
to get a free irq and to configure the IP to route it.
Cc: Thomas Gleixner t...@linutronix.de
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Tony Lindgren t...@atomide.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Sricharan R r.sricha...@ti.com
---
[V2] Added default routable-irqs functions to avoid
unnecessary if checks as per Thomas Gleixner comments
and renamed routable-irq binding as per
Kumar Gala ga...@codeaurora.org comments.
[V3] Addressed unnecessary warn-on and updated default
xlate function as per Thomas Gleixner comments
Documentation/devicetree/bindings/arm/gic.txt |6 ++
drivers/irqchip/irq-gic.c | 81 ++---
include/linux/irqchip/arm-gic.h |8 ++-
3 files changed, 84 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 3dfb0c0..5357745 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -49,6 +49,11 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
+- arm,routable-irqs : Total number of gic irq inputs which are not directly
+ connected from the peripherals, but are routed dynamically
+ by a crossbar/multiplexer preceding the GIC. The GIC irq
+ input line is assigned dynamically when the corresponding
+ peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -56,6 +61,7 @@ Example:
#interrupt-cells = 3;
#address-cells = 1;
interrupt-controller;
+ arm,routable-irqs = 160;
reg = 0xfff11000 0x1000,
0xfff10100 0x100;
};
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d0e9480..07be228 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -681,16 +681,25 @@ static int gic_irq_domain_map(struct irq_domain *d,
unsigned int irq,
irq_set_chip_and_handler(irq, gic_chip,
handle_fasteoi_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+ gic_routable_irq_domain_ops-map(d, irq, hw);
}
irq_set_chip_data(irq, d-host_data);
return 0;
}
+static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
+{
+ gic_routable_irq_domain_ops-unmap(d, irq);
+}
+
static int gic_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq, unsigned int
*out_type)
{
+ unsigned long ret = 0;
+
if (d-of_node != controller)
return -EINVAL;
if (intsize 3)
@@ -700,11 +709,20 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
- if (!intspec[0])
- *out_hwirq += 16;
+ if (!intspec[0]) {
+ ret = gic_routable_irq_domain_ops-xlate(d, controller,
+intspec,
+intsize,
+out_hwirq,
+out_type);
+
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ }
*out_type = intspec[2] IRQ_TYPE_SENSE_MASK;
- return 0;
+
+ return ret;
}
#ifdef CONFIG_SMP
@@ -728,9 +746,41 @@ static struct notifier_block gic_cpu_notifier = {
const struct irq_domain_ops gic_irq_domain_ops = {
.map = gic_irq_domain_map,
+ .unmap = gic_irq_domain_unmap,
.xlate = gic_irq_domain_xlate,
};
+/* Default functions for routable irq domain */
+static int gic_routable_irq_domain_map(struct irq_domain *d,
Re: [PATCH] typo fixes (coordiante - coordinate) in am335x
On Tue, 2013-10-22 at 10:05 +0100, Lee Jones wrote: This is the first time this patch has been sent to me. I need Dmitry's input (no pun intended) on how he's like to deal with this. At a bare minimum I'd like his Ack. Is there anything I can do to push this forward? The earlier we get the typo fixed in the documentation, the less chance that someone will use it that way. Regards, Jan -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] typo fixes (coordiante - coordinate) in am335x
On Tue, 05 Nov 2013, Jan Lübbe wrote: On Tue, 2013-10-22 at 10:05 +0100, Lee Jones wrote: This is the first time this patch has been sent to me. I need Dmitry's input (no pun intended) on how he's like to deal with this. At a bare minimum I'd like his Ack. Is there anything I can do to push this forward? The earlier we get the typo fixed in the documentation, the less chance that someone will use it that way. I think you should sent it again, but this time Cc the Device Tree list, Dmitry and myself when you submit. -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] typo fixes (coordiante - coordinate) in am335x
On Tue, 2013-11-05 at 17:15 +, Lee Jones wrote: On Tue, 05 Nov 2013, Jan Lübbe wrote: On Tue, 2013-10-22 at 10:05 +0100, Lee Jones wrote: This is the first time this patch has been sent to me. I need Dmitry's input (no pun intended) on how he's like to deal with this. At a bare minimum I'd like his Ack. Is there anything I can do to push this forward? The earlier we get the typo fixed in the documentation, the less chance that someone will use it that way. I think you should sent it again, but this time Cc the Device Tree list, Dmitry and myself when you submit. The original patch was not from me. But sure, I can resend it. Jan -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] typo fixes (coordiante - coordinate) in am335x
On Tue, 05 Nov 2013, Jan Lübbe wrote: On Tue, 2013-11-05 at 17:15 +, Lee Jones wrote: On Tue, 05 Nov 2013, Jan Lübbe wrote: On Tue, 2013-10-22 at 10:05 +0100, Lee Jones wrote: This is the first time this patch has been sent to me. I need Dmitry's input (no pun intended) on how he's like to deal with this. At a bare minimum I'd like his Ack. Is there anything I can do to push this forward? The earlier we get the typo fixed in the documentation, the less chance that someone will use it that way. I think you should sent it again, but this time Cc the Device Tree list, Dmitry and myself when you submit. The original patch was not from me. But sure, I can resend it. I'm not worried about who re-sends the patch. Just make sure whoever does sends in correctly with regards to the $SUBJECT line etc. The one on this patch looks odd. -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/7] usb: dwc3: get usb_phy only if the platform indicates the presence of PHY's
On Tue, Nov 5, 2013 at 11:41 PM, Vivek Gautam gautamvivek1...@gmail.com wrote:
Dear Kishon, Roger
On Wed, Oct 16, 2013 at 6:40 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
Hi roger,
On Wednesday 16 October 2013 06:33 PM, Roger Quadros wrote:
Hi Kishon,
Apologies for missing this thread for so long.
On 10/15/2013 10:54 PM, Kishon Vijay Abraham I wrote:
There can be systems which does not have a external usb_phy, so get
usb_phy only if dt data indicates the presence of PHY in the case of dt
boot or
if platform_data indicates the presence of PHY. Also remove checking if
return value is -ENXIO since it's now changed to always enable usb_phy
layer.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
In usb_get_phy_by_phandle, index 0 always refers to usb2 phy and index 1
always
refers to usb3 phy. Since we've lived so long with this, this patch will
make
an assumption that if only one entry is populated in *usb-phy* property,
it will
be usb2 phy and the next entry will be usb3 phy.
drivers/usb/dwc3/Kconfig |1 +
drivers/usb/dwc3/core.c | 72
--
drivers/usb/dwc3/platform_data.h |2 ++
3 files changed, 41 insertions(+), 34 deletions(-)
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 70fc430..8e385b4 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -1,6 +1,7 @@
config USB_DWC3
tristate DesignWare USB3 DRD Core Support
depends on (USB || USB_GADGET) HAS_DMA
+select USB_PHY
select USB_XHCI_PLATFORM if USB_SUPPORT USB_XHCI_HCD
help
Say Y or M here if your system has a Dual Role SuperSpeed
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 474162e..cb91d70 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -354,6 +354,7 @@ static int dwc3_probe(struct platform_device *pdev)
struct device_node *node = dev-of_node;
struct resource *res;
struct dwc3 *dwc;
+int count;
int ret = -ENOMEM;
@@ -387,16 +388,49 @@ static int dwc3_probe(struct platform_device *pdev)
if (node) {
dwc-maximum_speed = of_usb_get_maximum_speed(node);
-dwc-usb2_phy = devm_usb_get_phy_by_phandle(dev, usb-phy,
0);
-dwc-usb3_phy = devm_usb_get_phy_by_phandle(dev, usb-phy,
1);
+count = of_count_phandle_with_args(node, usb-phy, NULL);
+switch (count) {
+case 2:
+dwc-usb3_phy = devm_usb_get_phy_by_phandle(dev,
+usb-phy, 1);
+if (IS_ERR(dwc-usb3_phy)) {
+dev_err(dev, usb3 phy not found\n);
+return PTR_ERR(dwc-usb3_phy);
+}
+case 1:
+dwc-usb2_phy = devm_usb_get_phy_by_phandle(dev,
+usb-phy, 0);
+if (IS_ERR(dwc-usb2_phy)) {
+dev_err(dev, usb2 phy not found\n);
+return PTR_ERR(dwc-usb2_phy);
+}
+break;
In the Exynos case, there is only 1 phy and it is the USB3 phy. This code
will wrongly treat it as usb2_phy.
Thank you Roger for your concern regarding Exynos case.
It's true that, Exynos5 series of SoCs have got only one IP block for
DWC3'c PHY.
This block is actually a combo of USB2 phy (UTMI+) as well as USB3 phy
(PIPE3).
And the same is served by a single USB phy driver. This is also
clarified in the thread : https://lkml.org/lkml/2013/11/5/160
That was the case even before this patch no? Unfortunately the old USB PHY
library doesn't have APIs to get PHYs in a better way. If we try modifying
the
USB PHY library, it'll be kind of duplicating what is already there in the
Generic PHY library. I'd rather prefer Exynos guys to use the new framework.
we have tried moving Samsung's USB phy controller driver for DWC3, to
generic phy framework
so that things look clearer on Samsung's side too. The necessary
patches are availble at:
https://lkml.org/lkml/2013/10/31/79
Thanks
Kishon
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Best Regards
Vivek Gautam
Samsung RD Institute, Bangalore
India
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Best Regards
Vivek Gautam
Samsung RD Institute, Bangalore
India
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Re: [PATCHv9 01/43] clk: Add support for regmap register read/write
On Thu, Oct 31, 2013 at 16:40 +0200, Tero Kristo wrote:
On 10/31/2013 04:03 PM, Nishanth Menon wrote:
On 10/25/2013 10:56 AM, Tero Kristo wrote:
[...]
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7e59253..63ff78c 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
[...]
-static inline u32 clk_readl(u32 __iomem *reg)
+static inline u32 clk_readl(u32 __iomem *reg, struct regmap *regmap)
{
- return readl(reg);
+ u32 val;
+
+ if (regmap)
+ regmap_read(regmap, (u32)reg, val);
+ else
+ val = readl(reg);
+ return val;
}
-static inline void clk_writel(u32 val, u32 __iomem *reg)
+static inline void clk_writel(u32 val, u32 __iomem *reg, struct regmap
*regmap)
{
- writel(val, reg);
+ if (regmap)
+ regmap_write(regmap, (u32)reg, val);
+ else
+ writel(val, reg);
}
#endif /* CONFIG_COMMON_CLK */
Might it not be better to introduce regmap variants?
static inline void clk_regmap_writel(u32 val, u32 reg, struct regmap
*regmap)
and corresponding readl? that allows cleaner readability for clk
drivers that use regmap and those that dont.
Well, doing that will introduce a lot of redundant code, as the
checks for the presence of regmap must be copied all over the place.
With this patch, all the generic clock drivers support internally
both regmap or non-regmap register accesses.
Please keep in mind that the identity of clk_readl() and
readl() only applies in the current source code (ARM only use of
common CCF primitives), while patches are pending (currently
under review and receiving further improvement) which introduce
several alternative implementations of clk_readl() depending on
the platform. Making all of them duplicate the regmap vs direct
register access branch would be as bad. Keeping one set of
clk_readl() and clk_writel() routines and adding #ifdefs around
the direct register access would be rather ugly, and I understand
that preprocessor ifdef counts should get reduced instead of
introduced.
virtually yours
Gerhard Sittig
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