Re: [PATCH v2 0/9] unshare and simplify omap_hsmmc platform struct
On 29 September 2014 11:32, Andreas Fenkart wrote: > v2: > - replace erroneous mmci by omap1/2 > - add description to all patches > - full compile check with: > CONFIG_MACH_OMAP3_BEAGLE=y > CONFIG_MACH_DEVKIT8000=y > CONFIG_MACH_OMAP_LDP=y > CONFIG_MACH_OMAP3530_LV_SOM=y > CONFIG_MACH_OMAP3_TORPEDO=y > CONFIG_MACH_OVERO=y > CONFIG_MACH_OMAP3517EVM=y > CONFIG_MACH_CRANEBOARD=y > CONFIG_MACH_OMAP3_PANDORA=y > CONFIG_MACH_TOUCHBOOK=y > CONFIG_MACH_OMAP_3430SDP=y > CONFIG_MACH_NOKIA_RX51=y > CONFIG_MACH_CM_T35=y > CONFIG_MACH_CM_T3517=y > CONFIG_MACH_CM_T3730=y > CONFIG_MACH_SBC3530=y > - reorganized and added more patches, hence no blank ack added > > > Andreas Fenkart (9): > omap_hsmmc: use separate platform data for ompa3 and omap 1/2 driver > omap_hsmmc: remove unused fields in platform_data > omap_hsmmc: remove un-initialized callbacks from platform data > omap_hsmmc: remove un-ready power_saving field in omap2_hsmmc_info > omap_hsmmc: remove unused get_context_loss_count callback > omap_hsmmc: remove unnecessary omap_hsmmc_slot_data indirection > omap_hsmmc: pass mmc_priv struct to gpio init / free > omap_hsmmc: Remove unnecessary callbacks from platform data > omap_hsmmc: remove unused slot_id parameter > > arch/arm/mach-omap2/board-rx51-peripherals.c | 4 +- > arch/arm/mach-omap2/hsmmc.c| 155 +-- > arch/arm/mach-omap2/hsmmc.h| 9 +- > arch/arm/mach-omap2/mmc.h | 6 +- > .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 6 +- > arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 6 +- > drivers/mmc/host/omap_hsmmc.c | 282 > ++--- > include/linux/platform_data/hsmmc-omap.h | 88 +++ > 8 files changed, 299 insertions(+), 257 deletions(-) > create mode 100644 include/linux/platform_data/hsmmc-omap.h > > -- > 2.1.0 > Thanks! Applied for next! Kind regards Uffe -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/13 v10] omap 8250 based UART + DMA
On 09/29/2014 02:06 PM, Sebastian Andrzej Siewior wrote: > The queue is getting smaller. The highlights of v9…v10 > - the DMA stall Frans Klaver reported which popped up in yocto is gone. It > also seems that the "ack the err-irq even if nothing happened" in EDMA > can be dropped. > - the RX- and TX-DMA callbacks are now OMAP-only and no "bugs" flags are > introduced into the generic DMA code. This also means that there is > custom IRQ routine in case of DMA. For the series: Reviewed-by: Peter Hurley -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/5] ARM: OMAP3+: DPLL: fix set_rate logic
Hi, OMAP3+ DPLL code is currently using set_rate op to change DPLL rates. This is kind of wrong, as it also involves changing DPLL parent in certain cases (switch between locked mode <-> bypass mode.) This set fixes these issues by introducing the support of determine_rate and set_rate_and_parent ops for the DPLL clocks. Also introduces support for set_parent, which just switches a DPLL between locked <-> bypass modes. Testing branch pushed at my tree: https://github.com/t-kristo/linux-pm.git branch: 3.17-rc1-dpll-fixes Testing done: - omap2430-sdp : boot - am335x-bone : boot - am43xx-gpevm : boot - dra7-evm : boot - omap5-uevm : boot - omap4-panda-es : boot - omap3-beagle : boot - omap3-beagle-xm : boot -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/5] ARM: OMAP3+: DPLL: use determine_rate() and set_rate_and_parent()
Currently, DPLLs are hiding the gory details of switching parent
within set_rate, which confuses the common clock code and is wrong.
Fixed by applying the new determine_rate() and set_rate_and_parent()
functionality to any clock-ops previously using the broken approach.
This patch also removes the broken legacy code.
Signed-off-by: Tero Kristo
---
arch/arm/mach-omap2/cclock3xxx_data.c |6 +++
arch/arm/mach-omap2/dpll3xxx.c| 96 ++---
drivers/clk/ti/dpll.c | 15 ++
3 files changed, 25 insertions(+), 92 deletions(-)
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c
b/arch/arm/mach-omap2/cclock3xxx_data.c
index eb8c75e..5c5ebb4 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -257,6 +257,9 @@ static const struct clk_ops dpll1_ck_ops = {
.get_parent = &omap2_init_dpll_parent,
.recalc_rate= &omap3_dpll_recalc,
.set_rate = &omap3_noncore_dpll_set_rate,
+ .set_parent = &omap3_noncore_dpll_set_parent,
+ .set_rate_and_parent= &omap3_noncore_dpll_set_rate_and_parent,
+ .determine_rate = &omap3_noncore_dpll_determine_rate,
.round_rate = &omap2_dpll_round_rate,
};
@@ -367,6 +370,9 @@ static const struct clk_ops dpll4_ck_ops = {
.get_parent = &omap2_init_dpll_parent,
.recalc_rate= &omap3_dpll_recalc,
.set_rate = &omap3_dpll4_set_rate,
+ .set_parent = &omap3_noncore_dpll_set_parent,
+ .set_rate_and_parent= &omap3_dpll4_set_rate_and_parent,
+ .determine_rate = &omap3_noncore_dpll_determine_rate,
.round_rate = &omap2_dpll_round_rate,
};
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index cfe7c30..20e120d 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -460,93 +460,6 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
/* Non-CORE DPLL rate set code */
/**
- * omap3_noncore_dpll_set_rate - set non-core DPLL rate
- * @clk: struct clk * of DPLL to set
- * @rate: rounded target rate
- *
- * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
- * low-power bypass, and the target rate is the bypass source clock
- * rate, then configure the DPLL for bypass. Otherwise, round the
- * target rate if it hasn't been done already, then program and lock
- * the DPLL. Returns -EINVAL upon error, or 0 upon success.
- */
-int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
-{
- struct clk_hw_omap *clk = to_clk_hw_omap(hw);
- struct clk *new_parent = NULL;
- unsigned long rrate;
- u16 freqsel = 0;
- struct dpll_data *dd;
- int ret;
-
- if (!hw || !rate)
- return -EINVAL;
-
- dd = clk->dpll_data;
- if (!dd)
- return -EINVAL;
-
- if (__clk_get_rate(dd->clk_bypass) == rate &&
- (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
- pr_debug("%s: %s: set rate: entering bypass.\n",
-__func__, __clk_get_name(hw->clk));
-
- __clk_prepare(dd->clk_bypass);
- clk_enable(dd->clk_bypass);
- ret = _omap3_noncore_dpll_bypass(clk);
- if (!ret)
- new_parent = dd->clk_bypass;
- clk_disable(dd->clk_bypass);
- __clk_unprepare(dd->clk_bypass);
- } else {
- __clk_prepare(dd->clk_ref);
- clk_enable(dd->clk_ref);
-
- /* XXX this check is probably pointless in the CCF context */
- if (dd->last_rounded_rate != rate) {
- rrate = __clk_round_rate(hw->clk, rate);
- if (rrate != rate) {
- pr_warn("%s: %s: final rate %lu does not match
desired rate %lu\n",
- __func__, __clk_get_name(hw->clk),
- rrate, rate);
- rate = rrate;
- }
- }
-
- if (dd->last_rounded_rate == 0)
- return -EINVAL;
-
- /* Freqsel is available only on OMAP343X devices */
- if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
- freqsel = _omap3_dpll_compute_freqsel(clk,
- dd->last_rounded_n);
- WARN_ON(!freqsel);
- }
-
- pr_debug("%s: %s: set rate: locking rate to %lu.\n",
-__func__, __clk_get_name(hw->clk), rate);
-
- ret = omap3_noncore_dpll_program(clk, freqsel);
- if (!ret)
- new_parent = dd->clk_ref;
- clk_disable(dd->clk_ref);
- __clk_unprepare(dd->clk_ref);
- }
-
[PATCH 2/5] ARM: OMAP3: clock: add new rate changing logic support for noncore DPLLs
Currently, DPLL code hides the re-parenting within its internals, which
is wrong. This needs to be exposed to the common clock code via
determine_rate and set_rate_and_parent APIs. This patch adds support
for these, which will be taken into use in the following patches.
Signed-off-by: Tero Kristo
---
arch/arm/mach-omap2/dpll3xxx.c | 147
include/linux/clk/ti.h |9 +++
2 files changed, 156 insertions(+)
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index ac3d789..cfe7c30 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -546,6 +546,153 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw,
unsigned long rate,
return 0;
}
+/**
+ * omap3_noncore_dpll_determine_rate - determine rate for a DPLL
+ * @hw: pointer to the clock to determine rate for
+ * @rate: target rate for the DPLL
+ * @best_parent_rate: pointer for returning best parent rate
+ * @best_parent_clk: pointer for returning best parent clock
+ *
+ * Determines which DPLL mode to use for reaching a desired target rate.
+ * Checks whether the DPLL shall be in bypass or locked mode, and if
+ * locked, calculates the M,N values for the DPLL via round-rate.
+ * Returns a positive clock rate with success, negative error value
+ * in failure.
+ */
+long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate,
+ struct clk **best_parent_clk)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ struct dpll_data *dd;
+
+ if (!hw || !rate)
+ return -EINVAL;
+
+ dd = clk->dpll_data;
+ if (!dd)
+ return -EINVAL;
+
+ if (__clk_get_rate(dd->clk_bypass) == rate &&
+ (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
+ *best_parent_clk = dd->clk_bypass;
+ } else {
+ rate = omap2_dpll_round_rate(hw, rate, best_parent_rate);
+ *best_parent_clk = dd->clk_ref;
+ }
+
+ *best_parent_rate = rate;
+
+ return rate;
+}
+
+/**
+ * omap3_noncore_dpll_set_parent - set parent for a DPLL clock
+ * @hw: pointer to the clock to set parent for
+ * @index: parent index to select
+ *
+ * Sets parent for a DPLL clock. This sets the DPLL into bypass or
+ * locked mode. Returns 0 with success, negative error value otherwise.
+ */
+int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ int ret;
+
+ if (!hw)
+ return -EINVAL;
+
+ if (index)
+ ret = _omap3_noncore_dpll_bypass(clk);
+ else
+ ret = _omap3_noncore_dpll_lock(clk);
+
+ return ret;
+}
+
+/**
+ * omap3_noncore_dpll_set_rate_new - set rate for a DPLL clock
+ * @hw: pointer to the clock to set parent for
+ * @rate: target rate for the clock
+ * @parent_rate: rate of the parent clock
+ *
+ * Sets rate for a DPLL clock. First checks if the clock parent is
+ * reference clock (in bypass mode, the rate of the clock can't be
+ * changed) and proceeds with the rate change operation. Returns 0
+ * with success, negative error value otherwise.
+ */
+static int omap3_noncore_dpll_set_rate_new(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ struct dpll_data *dd;
+ u16 freqsel = 0;
+ int ret;
+
+ if (!hw || !rate)
+ return -EINVAL;
+
+ dd = clk->dpll_data;
+ if (!dd)
+ return -EINVAL;
+
+ if (__clk_get_parent(hw->clk) != dd->clk_ref)
+ return -EINVAL;
+
+ if (dd->last_rounded_rate == 0)
+ return -EINVAL;
+
+ /* Freqsel is available only on OMAP343X devices */
+ if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
+ freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
+ WARN_ON(!freqsel);
+ }
+
+ pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,
+__clk_get_name(hw->clk), rate);
+
+ ret = omap3_noncore_dpll_program(clk, freqsel);
+
+ return ret;
+}
+
+/**
+ * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL
clock
+ * @hw: pointer to the clock to set rate and parent for
+ * @rate: target rate for the DPLL
+ * @parent_rate: clock rate of the DPLL parent
+ * @index: new parent index for the DPLL, 0 - reference, 1 - bypass
+ *
+ * Sets rate and parent for a DPLL clock. If new parent is the bypass
+ * clock, only selects the parent. Otherwise proceeds with a rate
+ * change, as this will effectively also change the parent as the
+ * DPLL is put into locked mode. Returns 0 with success, negative error
+ * value otherwise.
+ */
+int omap3_non
[PATCH 1/5] ARM: OMAP3: clock: use clk_features flags for omap3 DPLL4 checks
DPLL4 can't be reprogrammed on OMAP3430 ES1.0 due to hardware limitation.
Currently, the code does runtime omap_rev() check to see the chip it is
being executed on, instead, change this to use clk_features flags.
This avoids need for runtime omap_rev() checks.
Signed-off-by: Tero Kristo
---
arch/arm/mach-omap2/clock.c |4
arch/arm/mach-omap2/clock.h |1 +
arch/arm/mach-omap2/clock3xxx.c |2 +-
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 500530d..c2b2398 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -771,4 +771,8 @@ void __init ti_clk_init_features(void)
ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
else if (cpu_is_omap34xx())
ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
+
+ /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
+ if (omap_rev() == OMAP3430_REV_ES1_0)
+ ti_clk_features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 4592a27..641337c 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -234,6 +234,7 @@ struct ti_clk_features {
};
#define TI_CLK_DPLL_HAS_FREQSEL(1 << 0)
+#define TI_CLK_DPLL4_DENY_REPROGRAM(1 << 1)
extern struct ti_clk_features ti_clk_features;
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 0b02b41..9a25601 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -46,7 +46,7 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long
rate,
* on 3430ES1 prevents us from changing DPLL multipliers or dividers
* on DPLL4.
*/
- if (omap_rev() == OMAP3430_REV_ES1_0) {
+ if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
pr_err("clock: DPLL4 cannot change rate due to silicon
'Limitation 2.5' on 3430ES1.\n");
return -EINVAL;
}
--
1.7.9.5
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[PATCH 4/5] ARM: OMAP3: clock: add support for dpll4_set_rate_and_parent
Expand the support of omap4 per-dpll to provide set_rate_and_parent.
This is required for proper behavior of clk_change_rate with
determine_rate support.
Signed-off-by: Tero Kristo
---
arch/arm/mach-omap2/clock3xxx.c | 36
include/linux/clk/ti.h |2 ++
2 files changed, 38 insertions(+)
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 9a25601..a9e86db 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -38,6 +38,18 @@
/* needed by omap3_core_dpll_m2_set_rate() */
struct clk *sdrc_ick_p, *arm_fck_p;
+
+/**
+ * omap3_dpll4_set_rate - set rate for omap3 per-dpll
+ * @hw: clock to change
+ * @rate: target rate for clock
+ * @parent_rate: rate of the parent clock
+ *
+ * Check if the current SoC supports the per-dpll reprogram operation
+ * or not, and then do the rate change if supported. Returns -EINVAL
+ * if not supported, 0 for success, and potential error codes from the
+ * clock rate change.
+ */
int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -54,6 +66,30 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long
rate,
return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
}
+/**
+ * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
+ * @hw: clock to change
+ * @rate: target rate for clock
+ * @parent_rate: rate of the parent clock
+ * @index: parent index, 0 - reference clock, 1 - bypass clock
+ *
+ * Check if the current SoC support the per-dpll reprogram operation
+ * or not, and then do the rate + parent change if supported. Returns
+ * -EINVAL if not supported, 0 for success, and potential error codes
+ * from the clock rate change.
+ */
+int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate, u8 index)
+{
+ if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
+ pr_err("clock: DPLL4 cannot change rate due to silicon
'Limitation 2.5' on 3430ES1.\n");
+ return -EINVAL;
+ }
+
+ return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,
+ index);
+}
+
void __init omap3_clk_lock_dpll5(void)
{
struct clk *dpll5_clk;
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 541dc33..57242ba 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -291,6 +291,8 @@ int omap2_clk_disable_autoidle_all(void);
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
+int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate, u8 index);
int omap2_dflt_clk_enable(struct clk_hw *hw);
void omap2_dflt_clk_disable(struct clk_hw *hw);
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
--
1.7.9.5
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[PATCH 3/5] ARM: OMAP4: clock: add support for determine_rate for omap4 regm4xen DPLL
Similarly to OMAP3 noncore DPLL, the implementation of this DPLL clock
type is wrong. This patch adds basic functionality for determine_rate
for this clock type which will be taken into use in the patches following
later.
Signed-off-by: Tero Kristo
---
arch/arm/mach-omap2/dpll44xx.c | 41
include/linux/clk/ti.h |4
2 files changed, 45 insertions(+)
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 4613f1e..535822f 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -207,3 +207,44 @@ out:
return dd->last_rounded_rate;
}
+
+/**
+ * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
+ * @hw: pointer to the clock to determine rate for
+ * @rate: target rate for the DPLL
+ * @best_parent_rate: pointer for returning best parent rate
+ * @best_parent_clk: pointer for returning best parent clock
+ *
+ * Determines which DPLL mode to use for reaching a desired rate.
+ * Checks whether the DPLL shall be in bypass or locked mode, and if
+ * locked, calculates the M,N values for the DPLL via round-rate.
+ * Returns a positive clock rate with success, negative error value
+ * in failure.
+ */
+long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate,
+ struct clk **best_parent_clk)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ struct dpll_data *dd;
+
+ if (!hw || !rate)
+ return -EINVAL;
+
+ dd = clk->dpll_data;
+ if (!dd)
+ return -EINVAL;
+
+ if (__clk_get_rate(dd->clk_bypass) == rate &&
+ (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
+ *best_parent_clk = dd->clk_bypass;
+ } else {
+ rate = omap4_dpll_regm4xen_round_rate(hw, rate,
+ best_parent_rate);
+ *best_parent_clk = dd->clk_ref;
+ }
+
+ *best_parent_rate = rate;
+
+ return rate;
+}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 47d0c63..541dc33 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -270,6 +270,10 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
unsigned long target_rate,
unsigned long *parent_rate);
+long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *best_parent_rate,
+ struct clk **best_parent_clk);
u8 omap2_init_dpll_parent(struct clk_hw *hw);
unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
--
1.7.9.5
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Re: [PATCH 00/26] ARM: OMAP2+: PRCM cleanups for 3.18 merge window
On Thu, Oct 02, 2014 at 04:59:30PM -0500, Felipe Balbi wrote: > Hi, > > On Thu, Oct 02, 2014 at 02:19:08PM -0700, Tony Lindgren wrote: > > * Felipe Balbi [141002 13:18]: > > > On Thu, Oct 02, 2014 at 12:52:38PM -0700, Tony Lindgren wrote: > > > > * Tony Lindgren [141002 09:36]: > > > > > * Tero Kristo [140924 02:04]: > > > > > > On 09/19/2014 08:27 PM, Paul Walmsley wrote: > > > > > > >On Fri, 19 Sep 2014, Paul Walmsley wrote: > > > > > > > > > > > > > >>However, I saw the following crash at boot on 37xxevm during one > > > > > > >>of > > > > > > >>the boot test. Ran thirty more boot tests afterwards on that > > > > > > >>board > > > > > > >>and it did not recur. It seems unlikely that the problem is > > > > > > >>related > > > > > > >>to this series, but looks like we may have some intermittent boot > > > > > > >>failure or race on 37xx :-( > > > > > > > > > > > > > >... > > > > > > > > > > > > > >>[4.892211] Unhandled fault: external abort on non-linefetch > > > > > > >>(0x1028) at 0xfa318034 > > > > > > >>[4.900299] Internal error: : 1028 [#1] SMP ARM > > > > > > >>[4.905090] Modules linked in: > > > > > > >>[4.908325] CPU: 0 PID: 0 Comm: swapper/0 Not tainted > > > > > > >>3.17.0-rc5-12866-g0164b2d #1 > > > > > > >>[4.916320] task: c0835db0 ti: c082a000 task.ti: c082a000 > > > > > > >>[4.922027] PC is at omap2_gp_timer_set_next_event+0x24/0x78 > > > > > > >>[4.928009] LR is at clockevents_program_event+0xc0/0x148 > > > > > > >>[4.933715] pc : []lr : []psr: > > > > > > >>0193 > > > > > > >>[4.933715] sp : c082bed8 ip : fp : > > > > > > >>[4.945800] r10: r9 : 24101100 r8 : c0839080 > > > > > > >>[4.951324] r7 : 0001 r6 : 237bc339 r5 : 009f r4 : > > > > > > >>3d9759e7 > > > > > > >>[4.958190] r3 : fa318034 r2 : c08cb920 r1 : 0003 r0 : > > > > > > >>fec1 > > > > > > >>[4.965087] Flags: nzcv IRQs off FIQs on Mode SVC_32 ISA > > > > > > >>ARM Segment kernel > > > > > > >>[4.972900] Control: 10c5387d Table: 80004019 DAC: 0015 > > > > > > >>[4.978942] Process swapper/0 (pid: 0, stack limit = > > > > > > >>0xc082a248) > > > > > > >>[4.985290] Stack: (0xc082bed8 to 0xc082c000) > > > > > > >>[4.989868] bec0: > > > > > > >> 237bc339 0001 > > > > > > >>[4.998504] bee0: 0001 24101100 0001 cfc7d6c8 0001 > > > > > > >>cfc7da50 cfc7d720 c00a4780 > > > > > > >>[5.007141] bf00: c00962b0 cfc7d720 c0096180 0001 > > > > > > >> 0001 c08256c8 > > > > > > >>[5.015777] bf20: c082a000 c08256c8 c00962b0 237b4c04 > > > > > > >>0001 0002 a193 > > > > > > >>[5.024414] bf40: 00989680 24101100 0001 > > > > > > >>cfc7da50 c108cc78 > > > > > > >>[5.033020] bf60: c00962b0 0002 0001 > > > > > > >> c108cc78 c00a56f0 > > > > > > >>[5.041656] bf80: 0002 237b4c04 0001 c08c8ce8 > > > > > > >>c082a000 c08c8ce8 > > > > > > >>[5.050292] bfa0: c08329dc c0832978 cfc7f0f8 c0072808 c0559928 > > > > > > >>c08270f0 c08caf40 c080fdc0 > > > > > > >>[5.058929] bfc0: c07c3b74 c07c35f0 > > > > > > >> c080fdc0 > > > > > > >>[5.067535] bfe0: c08cb154 c0832968 c080fdbc c083763c 80004059 > > > > > > >>80008074 > > > > > > >>[5.076171] [] (omap2_gp_timer_set_next_event) from > > > > > > >>[] (clockevents_program_event+0xc0/0x148) > > > > > > >>[5.087005] [] (clockevents_program_event) from > > > > > > >>[] (tick_program_event+0x44/0x54) > > > > > > >>[5.096771] [] (tick_program_event) from > > > > > > >>[] (__hrtimer_start_range_ns+0x3c0/0x4a0) > > > > > > >>[5.106597] [] (__hrtimer_start_range_ns) from > > > > > > >>[] (hrtimer_start_range_ns+0x24/0x2c) > > > > > > >>[5.116577] [] (hrtimer_start_range_ns) from > > > > > > >>[] (tick_nohz_idle_exit+0x140/0x1ec) > > > > > > >>[5.126342] [] (tick_nohz_idle_exit) from > > > > > > >>[] (cpu_startup_entry+0xf4/0x2d0) > > > > > > >>[5.135528] [] (cpu_startup_entry) from [] > > > > > > >>(start_kernel+0x340/0x3a8) > > > > > > >>[5.144165] [] (start_kernel) from [<80008074>] > > > > > > >>(0x80008074) > > > > > > >>[5.151031] Code: 13a0c000 0a04 ee07cfba e592301c > > > > > > >>(e5931000) > > > > > > >>[5.157470] ---[ end trace f92de024d996d904 ]--- > > > > > > >>[5.162353] Kernel panic - not syncing: Attempted to kill the > > > > > > >>idle task! > > > > > > >>[5.169433] ---[ end Kernel panic - not syncing: Attempted to > > > > > > >>kill the idle task! > > > > > > > > > > > > > >Actually it just occurred to me that if something broke > > > > > > >*wait_target_ready(), we'd expect to see intermittent failures > > > > > > >like this, > > > > > > >and this series touches *wait_target_ready().
Re: [PATCH 00/26] ARM: OMAP2+: PRCM cleanups for 3.18 merge window
* Felipe Balbi [141003 07:53]: > On Thu, Oct 02, 2014 at 04:59:30PM -0500, Felipe Balbi wrote: > > On Thu, Oct 02, 2014 at 02:19:08PM -0700, Tony Lindgren wrote: > > > * Felipe Balbi [141002 13:18]: > > > > On Thu, Oct 02, 2014 at 12:52:38PM -0700, Tony Lindgren wrote: > > > > > > > > > > Hmm here seems to be a link to similar issues from 2011: > > > > > > > > > > http://e2e.ti.com/support/arm/sitara_arm/f/791/p/113593/628790.aspx > > > > > > > > > > Looks like the issue can be potentially reproduced with: > > > > > > > > > > # cyclictest -l1 -m -a0 -t1 -n -p99 -i200 -h200 -q > > > > > > > > running here on am335x and am437x. On that same post, on person > > > > mentions he reproduced on beagle bone. > > > > > > OK I'll run it here too on my am37xx evm. Looks like Stanley was > > > running both cyclictest and hackbench the same time. > > > > yeah I did that. > > > > BTW, just got the following on BBB, AM437x SK is still running. > > > > [ 3952.432262] Kernel panic - not syncing: Attempted to kill the idle > > task!752763 > > [ 3952.442403] CPU: 0 PID: 0 Comm: hackbench Not tainted > > 3.17.0-rc6-00456-gd8da063 #222 > > [ 3952.450517] [] (unwind_backtrace) from [] > > (show_stack+0x20/0x24) > > [ 3952.458620] [] (show_stack) from [] > > (dump_stack+0x8c/0xa4) > > [ 3952.466168] [] (dump_stack) from [] > > (panic+0xa4/0x224) > > [ 3952.473358] [] (panic) from [] (do_exit+0x924/0x9d8) > > [ 3952.480358] [] (do_exit) from [] > > (do_group_exit+0x50/0xc0) > > [ 3952.487903] [] (do_group_exit) from [] > > (__wake_up_parent+0x0/0x30) > > [ 3952.496179] [] (__wake_up_parent) from [] > > (ret_fast_syscall+0x0/0x48) > > [ 3952.504875] drm_kms_helper: panic occurred, switching back to text > > console > > [ 3952.517844] ---[ end Kernel panic - not syncing: Attempted to kill the > > idle task! > > > > > > > And I'll also queue the following patch during the -rc cycle to > > > avoid apps segfaulting occasionally at random on omap3. > > > > and maybe this will fix BBB :-) I'll add that locally. If I survive > > until tomorrow, I'll add a Tested-by. > > BBB died again with the same behavior as above, but I think it's > unrelated to this errata. Therefore: > > Tested-by: Felipe Balbi BTW, I have revision r3p2: CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d And it still seems to need 430973. Looks like my 37xx evm produced no errors overnight running cyclictest and hackbench the same time. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] CLK: TI: Remove unused includes of linux/clk-private.h
Signed-off-by: Tomeu Vizoso --- drivers/clk/ti/clk-44xx.c | 1 - drivers/clk/ti/clk-54xx.c | 1 - drivers/clk/ti/clk-7xx.c | 1 - include/linux/clk/ti.h| 1 + 4 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c index 02517a8..8ea705e 100644 --- a/drivers/clk/ti/clk-44xx.c +++ b/drivers/clk/ti/clk-44xx.c @@ -12,7 +12,6 @@ #include #include -#include #include #include diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index 5e18399..e823d0b 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -12,7 +12,6 @@ #include #include -#include #include #include #include diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 62ac8f6..afd61a6 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -12,7 +12,6 @@ #include #include -#include #include #include diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index e8d8a35..ced953a 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -16,6 +16,7 @@ #define __LINUX_CLK_TI_H__ #include +#include /** * struct dpll_data - DPLL registers and integration data -- 1.9.3 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] clk: Make clk API return per-user struct clk instances
On 10/02, Tomeu Vizoso wrote:
> Moves clock state to struct clk_core, but takes care to change as little API
> as
> possible.
>
> struct clk_hw still has a pointer to a struct clk, which is the
> implementation's per-user clk instance, for backwards compatibility.
>
> The struct clk that clk_get_parent() returns isn't owned by the caller, but by
> the clock implementation, so the former shouldn't call clk_put() on it.
>
> Because some boards in mach-omap2 still register clocks statically, their
> clock
> registration had to be updated to take into account that the clock information
> is stored in struct clk_core now.
>
> Signed-off-by: Tomeu Vizoso
> ---
We should s/provider/core/ when we're dealing with clk_core
structures in the function signature. The providers are hardware
drivers and the core structures are for the framework, not the
same. Furthermore, the provider drivers should only be dealing
with clk_hw structures. The only place that clk_core should be in
clk-provider.h is in struct clk_hw because there's no way to get
around it.
This way, provider drivers should only be including
clk-provider.h because they only care about dealing with struct
clk_hw. Consumers should only be including linux/clk.h where they
only know about struct clk as an opaque pointer. Once we get OMAP
to stop using clk-private.h we can kill off that header entirely
(I see there are some other bogus users of that header outside of
OMAP that we should nuke). Then the framework can include
clk-provider.h and clk.h to map between the hw cookie and the
consumer cookie.
This is the end goal. I understand that the provider API is sort
of a mess with us allowing drivers to use the underscore and
non-underscore functions and the mixture of struct clk and struct
ckl_hw throughout.
struct clk_hw <--> struct clk_core <> struct clk
\-> struct clk
|-> struct clk
providers
-
struct clk_hw {
struct clk_core *
...
};
consumers
-
struct clk;
hidden in core framework
struct clk {
struct clk_core *;
...
}
struct clk_core {
struct clk_hw *;
...
}
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 4eeb8de..b216b13 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -37,6 +37,13 @@ static HLIST_HEAD(clk_root_list);
> static HLIST_HEAD(clk_orphan_list);
> static LIST_HEAD(clk_notifier_list);
>
> +static void clk_provider_put(struct clk_core *clk);
Does this need to be forward declared?
> +static long clk_provider_get_accuracy(struct clk_core *clk);
> +static bool clk_provider_is_prepared(struct clk_core *clk);
> +static bool clk_provider_is_enabled(struct clk_core *clk);
> +static long clk_provider_round_rate(struct clk_core *clk, unsigned long
> rate);
> @@ -356,7 +363,7 @@ out:
> *
> * Caller must hold prepare_lock.
> */
> -static void clk_debug_unregister(struct clk *clk)
> +static void clk_debug_unregister(struct clk_core *clk)
> {
> debugfs_remove_recursive(clk->dentry);
> }
> @@ -366,8 +373,8 @@ struct dentry *clk_debugfs_add_file(struct clk *clk, char
> *name, umode_t mode,
We should pass struct clk_hw here instead of struct clk. Let's do
it soon before we get any users.
> {
> struct dentry *d = NULL;
>
> - if (clk->dentry)
> - d = debugfs_create_file(name, mode, clk->dentry, data, fops);
> + if (clk->core->dentry)
> + d = debugfs_create_file(name, mode, clk->core->dentry, data,
> fops);
>
> return d;
> }
> @@ -545,53 +553,67 @@ late_initcall_sync(clk_disable_unused);
>
> const char *__clk_get_name(struct clk *clk)
> {
> - return !clk ? NULL : clk->name;
> + return !clk ? NULL : clk->core->name;
> }
> EXPORT_SYMBOL_GPL(__clk_get_name);
>
> struct clk_hw *__clk_get_hw(struct clk *clk)
> {
> - return !clk ? NULL : clk->hw;
> + return !clk ? NULL : clk->core->hw;
> }
> EXPORT_SYMBOL_GPL(__clk_get_hw);
>
> u8 __clk_get_num_parents(struct clk *clk)
> {
> - return !clk ? 0 : clk->num_parents;
> + return !clk ? 0 : clk->core->num_parents;
> }
> EXPORT_SYMBOL_GPL(__clk_get_num_parents);
>
> struct clk *__clk_get_parent(struct clk *clk)
> {
> - return !clk ? NULL : clk->parent;
> + /* TODO: Create a per-user clk and change callers to call clk_put */
More like replace all callers with a function that returns their
parent's hw pointer.
struct clk_hw *clk_provider_get_parent(struct clk_hw *hw)
> + return !clk ? NULL : clk->core->parent->hw->clk;
> }
> EXPORT_SYMBOL_GPL(__clk_get_parent);
>
> -struct clk *clk_get_parent_by_index(struct clk *clk, u8 index)
> +static struct clk_core *clk_provider_get_parent_by_index(struct clk_core
> *clk,
> + u8 index)
> {
> if (!clk || index >= clk->num_parents)
> return NULL;
