Re: [PATCH v2 0/2] dmaengine: ti-dma-crossbar: Support for eDMA
On 07/02/2015 06:56 PM, Vinod Koul wrote: > On Wed, Jul 01, 2015 at 03:41:26PM +0300, Peter Ujfalusi wrote: >> Hi, >> >> On 06/08/2015 04:22 PM, Peter Ujfalusi wrote: >>> Hi, >>> >>> Changes since v01: >>> - Drop change in compatible for the crossbar driver and do the configuration >>> based on the DT structure. >>> >>> The ti-dma-crossbar driver in it's current form can work when it is used >>> with >>> sDMA (omap-dma). On DRA7x class of devices we have both sDMA and eDMA >>> available. >>> The sDMA driver expects to get the DMA request line with offset 1. The eDMA >>> stack does not need the offset. >>> The crosbbar itself is identical for sDMA and eDMA. >>> At probe time the driver will do a match to figure out which dma engine it >>> is >>> connected to and based on that information it will configure the offset >>> needed >>> by the DMA driver. >> >> Gentle ping, it has been almost a month ago this series has been sent. > Sorry I seem to have missed this series. I relooked at this and it looks > fine. I will apply it once rc1 is out. If it needs rebase please resend No problem, the patch still applies cleanly. Thanks, Péter -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] PCI: host: pci-dra7xx: add pm support to pci dra7xx
Hi Kishon,
On 07/03/2015 02:03 PM, Kishon Vijay Abraham I wrote:
Add PM support to pci-dra7xx so that PCI clocks can be disabled
during suspend and enabled back during resume without affecting
PCI functionality.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/host/pci-dra7xx.c | 74 +
1 file changed, 74 insertions(+)
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index d8b6d66..1f5c039 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -433,6 +433,79 @@ static int __exit dra7xx_pcie_remove(struct
platform_device *pdev)
return 0;
}
+#ifdef CONFIG_PM_SLEEP
[...]
+
+static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
+ .suspend_noirq = dra7xx_pcie_suspend_noirq,
+ .suspend = dra7xx_pcie_suspend,
+ .resume_noirq = dra7xx_pcie_resume_noirq,
+ .resume = dra7xx_pcie_resume,
Could you use here SET_SYSTEM_SLEEP_PM_OPS()
and SET_NOIRQ_SYSTEM_SLEEP_PM_OPS() macro, pls?
+};
+#define DEV_PM_OPS (&dra7xx_pcie_pm_ops)
+#else
+#define DEV_PM_OPS NULL
+#endif
+
static const struct of_device_id of_dra7xx_pcie_match[] = {
{ .compatible = "ti,dra7-pcie", },
{},
@@ -444,6 +517,7 @@ static struct platform_driver dra7xx_pcie_driver = {
.driver = {
.name = "dra7-pcie",
.of_match_table = of_dra7xx_pcie_match,
+ .pm = DEV_PM_OPS,
},
};
--
regards,
-grygorii
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[PATCH 2/3] PCI: host: pcie-designware: add support for suspend and resume
Certain platforms require MSE bit to be cleared to set the master
in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe
Controller Master Standby Behavior advises to use the clearing
of the local MSE bit to set the master in standby. Without this
some of the clocks do not idle).
Cleared the MSE bit on suspend and enabled it back on resume.
This is required to get suspend/resume working.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sekhar Nori
---
drivers/pci/host/pcie-designware.c | 20
drivers/pci/host/pcie-designware.h |2 ++
2 files changed, 22 insertions(+)
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index 69486be..cfb2bd6 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -811,6 +811,26 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_writel_rc(pp, val, PCI_COMMAND);
}
+void dw_pcie_suspend_rc(struct pcie_port *pp)
+{
+ u32 val;
+
+ /* clear MSE */
+ dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
+ val &= ~PCI_COMMAND_MEMORY;
+ dw_pcie_writel_rc(pp, val, PCI_COMMAND);
+}
+
+void dw_pcie_resume_rc(struct pcie_port *pp)
+{
+ u32 val;
+
+ /* set MSE */
+ dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
+ val |= PCI_COMMAND_MEMORY;
+ dw_pcie_writel_rc(pp, val, PCI_COMMAND);
+}
+
MODULE_AUTHOR("Jingoo Han ");
MODULE_DESCRIPTION("Designware PCIe host controller driver");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/host/pcie-designware.h
b/drivers/pci/host/pcie-designware.h
index d0bbd27..0df2dfa 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -83,5 +83,7 @@ void dw_pcie_msi_init(struct pcie_port *pp);
int dw_pcie_link_up(struct pcie_port *pp);
void dw_pcie_setup_rc(struct pcie_port *pp);
int dw_pcie_host_init(struct pcie_port *pp);
+void dw_pcie_suspend_rc(struct pcie_port *pp);
+void dw_pcie_resume_rc(struct pcie_port *pp);
#endif /* _PCIE_DESIGNWARE_H */
--
1.7.9.5
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[PATCH 1/3] PCI: host: pci-dra7xx: Disable pm_runtime on get_sync failure
Fix the error handling code in case pm_runtime_get_sync fails. Now
when pm_runtime_get_sync fails pm_runtime_disable is invoked so that
there is no unbalanced pm_runtime_enable calls.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/host/pci-dra7xx.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 80db09e..d8b6d66 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -384,7 +384,7 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
ret = pm_runtime_get_sync(dev);
if (IS_ERR_VALUE(ret)) {
dev_err(dev, "pm_runtime_get_sync failed\n");
- goto err_phy;
+ goto err_get_sync;
}
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
@@ -401,6 +401,8 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
err_add_port:
pm_runtime_put(dev);
+
+err_get_sync:
pm_runtime_disable(dev);
err_phy:
--
1.7.9.5
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[PATCH 3/3] PCI: host: pci-dra7xx: add pm support to pci dra7xx
Add PM support to pci-dra7xx so that PCI clocks can be disabled
during suspend and enabled back during resume without affecting
PCI functionality.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/host/pci-dra7xx.c | 74 +
1 file changed, 74 insertions(+)
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index d8b6d66..1f5c039 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -433,6 +433,79 @@ static int __exit dra7xx_pcie_remove(struct
platform_device *pdev)
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+static int dra7xx_pcie_suspend(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ struct pcie_port *pp = &dra7xx->pp;
+
+ dw_pcie_suspend_rc(pp);
+
+ return 0;
+}
+
+static int dra7xx_pcie_resume(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ struct pcie_port *pp = &dra7xx->pp;
+
+ dw_pcie_resume_rc(pp);
+
+ return 0;
+}
+static int dra7xx_pcie_suspend_noirq(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ int count = dra7xx->phy_count;
+
+ while (count--) {
+ phy_power_off(dra7xx->phy[count]);
+ phy_exit(dra7xx->phy[count]);
+ }
+
+ return 0;
+}
+static int dra7xx_pcie_resume_noirq(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ int phy_count = dra7xx->phy_count;
+ int ret;
+ int i;
+
+ for (i = 0; i < phy_count; i++) {
+ ret = phy_init(dra7xx->phy[i]);
+ if (ret < 0)
+ goto err_phy;
+
+ ret = phy_power_on(dra7xx->phy[i]);
+ if (ret < 0) {
+ phy_exit(dra7xx->phy[i]);
+ goto err_phy;
+ }
+ }
+
+ return 0;
+
+err_phy:
+ while (--i >= 0) {
+ phy_power_off(dra7xx->phy[i]);
+ phy_exit(dra7xx->phy[i]);
+ }
+
+ return ret;
+}
+
+static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
+ .suspend_noirq = dra7xx_pcie_suspend_noirq,
+ .suspend = dra7xx_pcie_suspend,
+ .resume_noirq = dra7xx_pcie_resume_noirq,
+ .resume = dra7xx_pcie_resume,
+};
+#define DEV_PM_OPS (&dra7xx_pcie_pm_ops)
+#else
+#define DEV_PM_OPS NULL
+#endif
+
static const struct of_device_id of_dra7xx_pcie_match[] = {
{ .compatible = "ti,dra7-pcie", },
{},
@@ -444,6 +517,7 @@ static struct platform_driver dra7xx_pcie_driver = {
.driver = {
.name = "dra7-pcie",
.of_match_table = of_dra7xx_pcie_match,
+ .pm = DEV_PM_OPS,
},
};
--
1.7.9.5
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[PATCH 0/3] J6/J6Eco: Add PM support to PCIe
This series adds PM support to pci-dra7xx so that PCI clocks can be disabled during suspend and enabled back during resume without affecting PCI functionality. This series is dependent on [1] for proper PM functionality. [1] -> http://newscentral.exsees.com/item/595269de5c35c59c386b91ce8efd9872-eedf6742bb6159c3b1a90625c4d43407 Kishon Vijay Abraham I (3): PCI: host: pci-dra7xx: Disable pm_runtime if get_sync failure PCI: host: pcie-designware: add support for suspend and resume PCI: host: pci-dra7xx: add pm support to pci dra7xx drivers/pci/host/pci-dra7xx.c | 78 +++- drivers/pci/host/pcie-designware.c | 20 + drivers/pci/host/pcie-designware.h |2 + 3 files changed, 99 insertions(+), 1 deletion(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] drm/tilcdc: Allocate register storage based on the actual number registers
Allocate suspend/resume register storage based on the actual number
registers the driver is aware of. The static allocation for register
storage had falen behind badly.
Reported-by: Michael Bode
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 20 +++-
drivers/gpu/drm/tilcdc/tilcdc_drv.h | 2 +-
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 4908c1f..2f87263 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -139,11 +139,14 @@ static int tilcdc_unload(struct drm_device *dev)
pm_runtime_disable(dev->dev);
+ kfree(priv->saved_register);
kfree(priv);
return 0;
}
+static size_t tilcdc_num_regs(void);
+
static int tilcdc_load(struct drm_device *dev, unsigned long flags)
{
struct platform_device *pdev = dev->platformdev;
@@ -155,7 +158,11 @@ static int tilcdc_load(struct drm_device *dev, unsigned
long flags)
int ret;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
- if (!priv) {
+ if (priv)
+ priv->saved_register = kcalloc(sizeof(*priv->saved_register),
+ tilcdc_num_regs(), GFP_KERNEL);
+ if (!priv || !priv->saved_register) {
+ kfree(priv);
dev_err(dev->dev, "failed to allocate private data\n");
return -ENOMEM;
}
@@ -345,6 +352,7 @@ fail_free_wq:
fail_free_priv:
dev->dev_private = NULL;
+ kfree(priv->saved_register);
kfree(priv);
return ret;
}
@@ -467,6 +475,16 @@ static const struct {
REG(2, true, LCDC_INT_ENABLE_SET_REG),
#undef REG
};
+
+static size_t tilcdc_num_regs(void)
+{
+ return ARRAY_SIZE(registers);
+}
+#else
+static size_t tilcdc_num_regs(void)
+{
+ return 0;
+}
#endif
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
index e863ad0..bc94835 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
@@ -67,7 +67,7 @@ struct tilcdc_drm_private {
uint32_t max_width;
/* register contents saved across suspend/resume: */
- u32 saved_register[12];
+ u32 *saved_register;
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
--
1.9.1
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