Re: [PATCH v2 4/7] ARM: davinci: Add support for an L3RAM gen_pool
On Tue, Oct 2, 2012 at 7:13 AM, Sekhar Nori nsek...@ti.com wrote: On 10/1/2012 7:20 PM, Ben Gardiner wrote: On Mon, Oct 1, 2012 at 8:32 AM, Matt Porter mpor...@ti.com wrote: On Mon, Oct 01, 2012 at 05:34:02PM +0530, Sekhar Nori wrote: Hi Matt, On 9/29/2012 1:07 AM, Matt Porter wrote: L3RAM (shared SRAM) is needed for use by several drivers. This creates a genalloc pool and a hook for the platform code to provide the struct gen_pool * in platform data. Signed-off-by: Matt Porter mpor...@ti.com I am not sure if any of the DaVinci devices have a need to allocate from *both* ARM RAM and shared RAM. Shared RAM is not present on all DaVinci devices AFAIR, and on DA850, there is just 8KB ARM RAM so I am not sure if there is much point in trying to allocate from there. Can you instead see if Ben's earlier patch[1] to use shared RAM for SRAM allocation on DA850 makes sense for your case? If yes, can you repost with Ben's patch included in your series instead of this patch? I would prefer that over creating a new pool for shared RAM. Hrm, I did look at Ben's earlier patch. The reason I added a separate pool mostly was so I didn't have to touch the PM code at all. That can continue using the private SRAM API with the ARM RAM as it is now. The idea here was to allow that to be separate since no other bus masters can access the ARM RAM anyway and do something that didn't require regression testing PM. Also, I figured there's really no reason to use even a tiny bit of the shared SRAM on PM if we have that ARM RAM there and working fine for that use case. [...] I agree with Matt. Preserving the use of the ARM RAM (8K on L138 -- as you said, Sekhar) in any fashion is preferable to moving suspend support into shared RAM. There is more of it (128K on L138) but also more pressure on allocations there since there are more clients. There is where I would like to see more information on who the potential clients are. Even if DSP takes away 64K of the shared RAM on OMAP-L138, there should be more than enough for PM, Audio and PRU. I haven't checked the PM code size lately but it should be fairly small and I can check the actual number if that helps. So, adding a new pool just to save on those bytes doesn't sound like helping a lot. Good points. I suppose that the list would decrease also on L138 if davinci-pcm ping-pong buffers were removed from SRAM. I appreciate that you are trying to preserve prior efforts in attempted merging of SRAM support -- thank you for that; however, that patch [1] was just an import of Subashish Ghosh's patch [2] -- I chose _that_ implementation option then mainly because I imagined it would be the least risky to get accepted upstream and not because of any particular technical merits. Its not a question of prior effort since Matt has already put in the effort too. I am yet unconvinced that we need to add support to manage two blocks of SoC internal RAM on DA850 in the kernel today. That's all. Understood. Thank you, Sekhar. Best Regards, Ben Gardiner --- Nanometrics Inc. http://www.nanometrics.ca -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 4/7] ARM: davinci: Add support for an L3RAM gen_pool
On Mon, Oct 1, 2012 at 8:32 AM, Matt Porter mpor...@ti.com wrote: On Mon, Oct 01, 2012 at 05:34:02PM +0530, Sekhar Nori wrote: Hi Matt, On 9/29/2012 1:07 AM, Matt Porter wrote: L3RAM (shared SRAM) is needed for use by several drivers. This creates a genalloc pool and a hook for the platform code to provide the struct gen_pool * in platform data. Signed-off-by: Matt Porter mpor...@ti.com I am not sure if any of the DaVinci devices have a need to allocate from *both* ARM RAM and shared RAM. Shared RAM is not present on all DaVinci devices AFAIR, and on DA850, there is just 8KB ARM RAM so I am not sure if there is much point in trying to allocate from there. Can you instead see if Ben's earlier patch[1] to use shared RAM for SRAM allocation on DA850 makes sense for your case? If yes, can you repost with Ben's patch included in your series instead of this patch? I would prefer that over creating a new pool for shared RAM. Hrm, I did look at Ben's earlier patch. The reason I added a separate pool mostly was so I didn't have to touch the PM code at all. That can continue using the private SRAM API with the ARM RAM as it is now. The idea here was to allow that to be separate since no other bus masters can access the ARM RAM anyway and do something that didn't require regression testing PM. Also, I figured there's really no reason to use even a tiny bit of the shared SRAM on PM if we have that ARM RAM there and working fine for that use case. [...] I agree with Matt. Preserving the use of the ARM RAM (8K on L138 -- as you said, Sekhar) in any fashion is preferable to moving suspend support into shared RAM. There is more of it (128K on L138) but also more pressure on allocations there since there are more clients. I appreciate that you are trying to preserve prior efforts in attempted merging of SRAM support -- thank you for that; however, that patch [1] was just an import of Subashish Ghosh's patch [2] -- I chose _that_ implementation option then mainly because I imagined it would be the least risky to get accepted upstream and not because of any particular technical merits. Best Regards, Ben Gardiner [1] https://patchwork.kernel.org/patch/840552/ [2] https://patchwork.kernel.org/patch/549351/ --- Nanometrics Inc. http://www.nanometrics.ca -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: dspbridge and the omapl1x
On Thu, Aug 12, 2010 at 8:28 PM, Hari Kanigeri hari.kanig...@gmail.com wrote: Also I believe that the new Contiguous Memory Allocation (CMA) framework was developed specifically for systems that need to allocate physically contiguous memory because they don't have an MMU. What (edit) ... because they don't have an _IO_MMU. would say to avoiding the IOMMU requirement and keeping DMM by using physically contiguous dynamically allocated memory regions like those provided by the new CMA [2]? Just curious as how CMA is different from Android's pmem. I'm not really sure, but based on the discussion in one of the pmem patches proposed on lkml [1] they seem to provide similar functionality. Perhaps the difference is that pmem has made it to staging whereas CMA is only a proposed feature so far? Best Regards, Ben Gardiner [1] https://patchwork.kernel.org/patch/47513/ --- Nanometrics Inc. http://www.nanometrics.ca -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: dspbridge and the omapl1x
Hari and Mugdha, On Wed, Aug 11, 2010 at 7:35 PM, Hari Kanigeri hari.kanig...@gmail.com wrote: On Wed, Aug 11, 2010 at 2:25 PM, Ben Gardiner bengardi...@nanometrics.ca wrote: On Wed, Aug 11, 2010 at 12:55 PM, Hari Kanigeri hari.kanig...@gmail.com wrote: We are working on making some of core functionalities such as DMM, resource Management, reset Management of co-processors generic for any IPC to use. So if DSPLink is missing DMM functionality then it should be just the matter of DSPLink adapting to this. I don't get what you're trying to say here, sorry. Would DSPLink be one of the IPCs for which the 'core functionalities' could be adapted? May be let's re-visit this point when the RFC is send on my above mentioned features. Could you explain an example of how DMM being made generic for any IPC to use could be applied to DSPLink? Basically today the Dynamic memory management is handled by DSPBridge. So the userspace clients talk to DSPBridge, and DSPBridge in turn talks to IOMMU to map the user passed Buffers. DSPBridge is managing the virtual address space of DSP in this case. So basically where we are going is replacing DSPBridge's DMM module with a generic Kernel module that can handle the DMM for any given number of Co-Processors. OMAP3 has only Co-Processor, where as OMAP4 has 2 Co-Processors. The solution should be generic to handle any number of Devices. I will try to send an RFC of this implementation and I would love to get feedback from you. I would be happy to review the RFC. In case if you want to get some information on how the Dynamic memory mapping works, you can refer pages 12-15 of this presentation https://gforge.ti.com/gf/download/docmanfileversion/17/674/OMAP3430_Bridge_overview.pdf Thank you for the link; the diagram on page 13 was most helpful in solidifying my understanding of the IOMMU to which your are referring in your explanation of DMM above and in the roadmap below. On a high level, this is what needs to be done to provide support for OMAP1. 1. Adapt to iommu. Add support if the support is not present for OMAP1. Gulp. This could be a problem. Thanks to your link above I now understand that the iommu which is controlled by dspbridge and facilitates the use by the DSP of scattered pages allocated on the ARM side is an MMU _separate_ from that of the ARM. The OMAP3430 obviously has an MMU for the DSP Side [1] but I can't find any documentation indicating that the OMAP L138 has a DSP-side MMU. On Thu, Aug 12, 2010 at 2:16 AM, Kamoolkar, Mugdha mug...@ti.com wrote: One thing I would like to mention is that the DMM feature does require the slave DSP to have an MMU. The OMAPL1xx devices do not have MMU for the DSP. DMM cannot be implemented without the DSP having an MMU. Hence, even if you ported DSPBridge to OMAPL1xx devices, you could not make use of the DMM feature. Thank you, Mugdha, for reading my mind and confirming that there is no MMU on the omapL1x -- I saved a draft of this email last night and was going to do some more research to confirm myself but you saved me the trouble. On Thu, Aug 12, 2010 at 2:16 AM, Kamoolkar, Mugdha mug...@ti.com wrote: You are correct that dynamic linking and loading is a feature that is available in DSPBridge, and which is missing in DSPLink, which could work on OMAPL1xx if you ported DSPBridge to OMAPL1xx I imagined that the lack of MMU would be a blocker in porting dspbridge since it would be impossible to support scattered (in PAs) pages on the DSP-side. But Mugdha makes it sound like the port could be accomplished with DMM omitted. Also I believe that the new Contiguous Memory Allocation (CMA) framework was developed specifically for systems that need to allocate physically contiguous memory because they don't have an MMU. What would say to avoiding the IOMMU requirement and keeping DMM by using physically contiguous dynamically allocated memory regions like those provided by the new CMA [2]? On Wed, Aug 11, 2010 at 7:35 PM, Hari Kanigeri hari.kanig...@gmail.com wrote: 2. Adapt to mailbox On Thu, Aug 12, 2010 at 2:16 AM, Kamoolkar, Mugdha mug...@ti.com wrote: Also, OMAPL1xx devices do not use mailbox interrupts. They have a different type of IPC interrupt, which is not mailbox. So a different kind of abstraction would be required to be able to use either mailbox or this different IPC interrupt. Good point. I believe that currently it is DSPLink which provides a mailbox implemented on top of the available IPC interrupt on the L13x. If re-using DSPLink in the dspbridge's baseimage is still overkill then we at least have code in DSPLink from which to base the standalone driver code. On Wed, Aug 11, 2010 at 7:35 PM, Hari Kanigeri hari.kanig...@gmail.com wrote: 3. Reset and Power management adaptation for OMAP1. Thanks for the roadmap. This doesn't sound too daunting, but that could be because I am ignorant of the details. :) I forgot to add item 4. Surprises
Re: dspbridge and the omapl1x
Hello Hari, Thank you for reading and replying to our email. On Tue, Aug 10, 2010 at 6:12 PM, Hari Kanigeri hari.kanig...@gmail.com wrote: Do you mean dynamic memory management ? Can you please elaborate on what feature you are referring to ? Yes, dynamic memory management. With DSP Link on the OMAPL138 the memory allocated to the DSP must be specified as a 'hole' in Linux memory at boot-time [1[2][3]. It seems (perhaps this is wishful thinking) that dspbridge does not have this limitation. Also dynamic application loading. With DSP Link it is possible to run multiple linux processes concurrently communicating with DSP tasks but the image loaded and executed on the DSP side must contain the code for all of the tasks at load time [4]. It seems that dspbridge does not have this limitation. I am very interested in learning details about both dsplink and dspbridge; please reply with more details or corrections as you see fit. Best Regards, Ben Gardiner [1] http://processors.wiki.ti.com/index.php/Changing_DSPLink_Memory_Map [2] http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/29571.aspx [3] http://code.google.com/p/rowboat/wiki/DSP [4] http://processors.wiki.ti.com/index.php/Using_DSPLink_from_multiple_processes --- Nanometrics Inc. http://www.nanometrics.ca -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: dspbridge and the omapl1x
Hello Felipe, On Wed, Aug 11, 2010 at 10:01 AM, Felipe Contreras felipe.contre...@gmail.com wrote: Hi, On Wed, Aug 11, 2010 at 3:56 PM, Ben Gardiner bengardi...@nanometrics.ca wrote: Yes, dynamic memory management. With DSP Link on the OMAPL138 the memory allocated to the DSP must be specified as a 'hole' in Linux memory at boot-time [1[2][3]. It seems (perhaps this is wishful thinking) that dspbridge does not have this limitation. The dsp-bridge can map scattered user-space pages just fine. Also dynamic application loading. With DSP Link it is possible to run multiple linux processes concurrently communicating with DSP tasks but the image loaded and executed on the DSP side must contain the code for all of the tasks at load time [4]. It seems that dspbridge does not have this limitation. Indeed, you can dynamically load socket-nodes. Thank you kindly for the confirmations. It's good to know our comprehension of the current state of dspbridge is correct. I am very interested in learning details about both dsplink and dspbridge; please reply with more details or corrections as you see fit. Have you looked into dsp-gateway[1]? The code is very simple and AFAIK it was close to getting merged upstream, but it's unmaintained nowadays. It was used on OMAP1 and OMAP2 by Nokia, and shares code with dsp-bridge, like mailbox and soon iommu. So it might be possible to port the OMAP1 stuff from dsp-gateway into dsp-bridge. That's a good suggestion, thanks. Now that you mention it the OMAP1 and OMAPL1x have similarities other than their names [1]: they both have ARM9 cores for GPP but the OMAP1 has a C55x where the L1x has a C67x for DSP. I must admit that I'm not sure how I could extract the platform specific information from the files made available by the dspgateway project [2] yet. Nevertheless, I appreciate you pointing out this similarity and I hope I can make use of it in the future. Best Regards, Ben Gardiner [1] http://en.wikipedia.org/wiki/Texas_Instruments_OMAP [2] http://sourceforge.net/projects/dspgateway/files/ --- Nanometrics Inc. http://www.nanometrics.ca -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: dspbridge and the omapl1x
Hi Deepali, On Wed, Aug 11, 2010 at 9:48 AM, Uppal, Deepali deep...@ti.com wrote: Hello Ben, I am Deepali, DSPLink engineering manager from DSPLink team in TI India. I have removed the linux omap mailing list as my mailing client is not correctly setup to send mails to community. I will respond to the community mailing list later. Thank you for reading and replying. Note to the list: With his permission, I am replying on-list with Deepali's reply in-line. To answer your questions: 1) Specifying shared memory for DSPLink does involve setting aside memory for Linux using the mem variable in kernel bootargs. 2) DSPLink does not support dynamic linking and loading. All the DSP code must be available in the DSP image loaded at PROC_load API time itself. Thank you for confirming these points. 3) There are no plans of putting DSPLink (which is currently available into mainstream kernel). However there are plans of putting the next generation of DSPLink for newer generation of devices onto the community. But this may be too late for your needs. However we do support build against the git kernels in the newer versions of DSPLink. This is good news, Deepali. Are there any current DSPLink interfaces that are guaranteed to be stable into the 'next generation' ? You also make a good point that the ARM-side DSPLink component is an out-of-tree kernel module which builds against recent kernels. This is great support for us developers that are using very recent kernels and I think that it is a valuable feature that you have provided with DSPLink. Thanks for that. Information about DSPLink is available at http://processors.wiki.ti.com/index.php/Category:DSPLink DSPLink Webex trainings are at http://processors.wiki.ti.com/index.php/DSPBIOS_LINK_WebEx_Presentations To give a brief overview: DSPLink provides foundation software for the inter-processor communication i.e. IPC across the GPP-DSP boundary. It differs from DSPBridge that it does not provide any framework infrastructure but focuses more on the IPC. It does provide support for Codec Engine which is a codecs management framework which sits on top of DSPLink. I think that Hari Kanigeri points it out in his later post; it sounds like I am trying to compare apples and oranges by comparing dspbrige and DSP Link. Would a more equatable comparison be between Codec Engine + DSP Link vs. dspbridge? DSPLink provides * PROC: Boot Loading of DSP It is this feature category where it seems that DSP Link falls short of the features afforded by dspbridge. But I'm started to see that this because DSPLink alone is not intended to be feature complete here. When combined with Code Engine is it possible to get dynamic memory management and dynamic application loading ? * Inter-Processor Communication protocols o Complete protocols for different types of data transfer between the processors o Each protocol meets a different data transfer need + MSGQ: Message Queue + CHNL: SIO/streaming based on issue-reclaim model + RingIO: Circular ring buffer based data streaming * Inter-Processor Communication building blocks o Low-level building blocks used by the protocols o Each building block is also exposed as APIs to allow framework writers to define their own application-specific protocols + POOL: Memory Manager: shared/non-shared + NOTIFY: Interrupt abstraction and de-multiplexing for notification of user events + MPCS: Multi-processor critical section for mutually exclusive access to shared objects + MPLIST: Multi-processor doubly linked circular list + PROC_read/PROC_write: Read from or write to DSP memory DSPLink is also available on different OS (WinCE and PrOS) and platforms (DM6446, DM6467 etc) combinations. This enables to you port your application to any other platform OS combination seamlessly. DSPLink+Codec Engine is also portable across all recent DaVinci and OMAP platforms correct? This is itself an attractive feature. Best Regards, Ben Gardiner --- Nanometrics Inc. http://www.nanometrics.ca -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: dspbridge and the omapl1x
Hello Hari, On Wed, Aug 11, 2010 at 12:55 PM, Hari Kanigeri hari.kanig...@gmail.com wrote: Ben, Yes, dynamic memory management. With DSP Link on the OMAPL138 the memory allocated to the DSP must be specified as a 'hole' in Linux memory at boot-time [1[2][3]. It seems (perhaps this is wishful thinking) that dspbridge does not have this limitation. DSPBridge doesn't has this requirement. Thank you for confirming. Also dynamic application loading. With DSP Link it is possible to run multiple linux processes concurrently communicating with DSP tasks but the image loaded and executed on the DSP side must contain the code for all of the tasks at load time [4]. It seems that dspbridge does not have this limitation. I am very interested in learning details about both dsplink and dspbridge; please reply with more details or corrections as you see fit. DSPBridge and DSPLink IPCs are for 2 different purposes. So before you make a switch to one of the IPC, I would recommend to you to make sure your requirements are met. To check the differences between DSPBridge and DSPLink, please check this email thread contributed by Richard W. http://linux.omap.com/pipermail/linux-omap-open-source/2007-May/009850.html. Good point. Thank you for making that clear to me. And for the link to the post, I'm regret that I missed that in my initial research. I'm starting to think that maybe a direct comparison between DSPLink and dspbridge is not a fair one. We are working on making some of core functionalities such as DMM, resource Management, reset Management of co-processors generic for any IPC to use. So if DSPLink is missing DMM functionality then it should be just the matter of DSPLink adapting to this. I don't get what you're trying to say here, sorry. Would DSPLink be one of the IPCs for which the 'core functionalities' could be adapted? Could you explain an example of how DMM being made generic for any IPC to use could be applied to DSPLink? I am not aware of the official word from T.I to support dspbridge on OMAP1, but as the community you will have the support in case you want to go with dspbridge option. On a high level, this is what needs to be done to provide support for OMAP1. 1. Adapt to iommu. Add support if the support is not present for OMAP1. 2. Adapt to mailbox 3. Reset and Power management adaptation for OMAP1. Thanks for the roadmap. This doesn't sound too daunting, but that could be because I am ignorant of the details. :) It is good to know that the community (at least you) would be interested in reviewing and picking up patches that integrate dspbridge support for the omapl1x. I'm still not sure about the iommu features required by dspbridge, I will need to look into this. But 2+3 sound like they could be provided by DSPLink itself. Would it be sane to put dspbridge on top of DSPLink? Just to sound it out, the DSP-side base image could be DSPBios + DSPLink (DSP-side) and the ARM-side would be made of dspbridge where the IPC is DSP Link 'compatible'. This could avoid a rewrite of the DSP-side of dspbridge maybe? All crazy ideas aside. We are very pleased with all the help you (Hari), Felipe and Deepali have offered us in trying to understand dspbridge and its relationship to DSP Link. Many thanks again and we look forward to any more insights you have to offer. Best Regards, Ben Gardiner --- Nanometrics Inc. http://www.nanometrics.ca -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
dspbridge and the omapl1x
Hello authors of staging/tidspbridge patches, We have been watching the progress in staging/dspbridge with great excitement. Unfortunately we are using the OMAPL138 which is a davinci family member which has support for DSPLink not DSPBridge. We are attracted to DSPBridge over DSPLink because it appears to have better dynamic resource management and it is headed for mainline (fingers crossed). Is omapl1x support part of the roadmap for dspbridge? Is there anything we can do to help? Are there interfaces to which we can program that would insulate us from changes during a future migration from DSPLink to DSPBridge? Best Regards, Ben Gardiner --- Nanometrics Inc. http://www.nanometrics.ca -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
