[PATCH 1/1] OMAP3: CLOCK: Remove few unnecessary clocks
dpllx_m2x2_ck parent is dpllx_m2_ck. So remove few useless clocks and
and use right parent for dpllx_m2x2_ck.
Signed-off-by: Jouni Hogander jouni.hogan...@nokia.com
---
arch/arm/mach-omap2/clock34xx.h | 31 ++-
1 files changed, 2 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 179ea17..4f462ea 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -427,18 +427,6 @@ static struct clk dpll3_ck = {
.recalc = omap3_dpll_recalc,
};
-/*
- * This virtual clock provides the CLKOUTX2 output from the DPLL if the
- * DPLL isn't bypassed
- */
-static struct clk dpll3_x2_ck = {
- .name = dpll3_x2_ck,
- .parent = dpll3_ck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = dpll3_clkdm },
- .recalc = omap3_clkoutx2_recalc,
-};
-
static const struct clksel_rate div31_dpll3_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
{ .div = 2, .val = 2, .flags = RATE_IN_343X },
@@ -505,10 +493,10 @@ static struct clk core_ck = {
static struct clk dpll3_m2x2_ck = {
.name = dpll3_m2x2_ck,
- .parent = dpll3_x2_ck,
+ .parent = dpll3_m2_ck,
.flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
.clkdm = { .name = dpll3_clkdm },
- .recalc = followparent_recalc,
+ .recalc = omap3_clkoutx2_recalc,
};
/* The PWRDN bit is apparently only available on 3430ES2 and above */
@@ -590,19 +578,6 @@ static struct clk dpll4_ck = {
.recalc = omap3_dpll_recalc,
};
-/*
- * This virtual clock provides the CLKOUTX2 output from the DPLL if the
- * DPLL isn't bypassed --
- * XXX does this serve any downstream clocks?
- */
-static struct clk dpll4_x2_ck = {
- .name = dpll4_x2_ck,
- .parent = dpll4_ck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = dpll4_clkdm },
- .recalc = omap3_clkoutx2_recalc,
-};
-
static const struct clksel div16_dpll4_clksel[] = {
{ .parent = dpll4_ck, .rates = div16_dpll_rates },
{ .parent = NULL }
@@ -3355,14 +3330,12 @@ static struct clk *onchip_34xx_clks[] __initdata = {
dpll2_m2_ck,
dpll3_ck,
core_ck,
- dpll3_x2_ck,
dpll3_m2_ck,
dpll3_m2x2_ck,
dpll3_m3_ck,
dpll3_m3x2_ck,
emu_core_alwon_ck,
dpll4_ck,
- dpll4_x2_ck,
omap_96m_alwon_fck,
omap_96m_fck,
cm_96m_fck,
--
1.6.0.1
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[PATCH PM 0/1] OMAP3: PM: Fix to prcm save/restore
This patch should fix the problem in locking DPLL2 after wake-up from OFF mode: clock: dpll2_ck failed transition to 'locked' clock: dpll2_ck failed transition to 'locked' clock: dpll2_ck failed transition to 'locked' clock: dpll2_ck failed transition to 'locked' prcm.c |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH PM 1/1] OMAP3: PM: Save and restore also CM_CLKSEL1_PLL_IVA2
CM_CLKSEL1_PLL_IVA2 is not saved/restored currently. This patch is
adding save and restore for it.
Signed-off-by: Jouni Hogander jouni.hogan...@nokia.com
---
arch/arm/mach-omap2/prcm.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index c64b668..7ccaf7f 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -36,6 +36,7 @@ static void __iomem *cm_base;
struct omap3_prcm_regs {
u32 control_padconf_sys_nirq;
+ u32 iva2_cm_clksel1;
u32 iva2_cm_clksel2;
u32 cm_sysconfig;
u32 sgx_cm_clksel;
@@ -218,6 +219,8 @@ void omap3_prcm_save_context(void)
{
prcm_context.control_padconf_sys_nirq =
omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
+ prcm_context.iva2_cm_clksel1 =
+cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
prcm_context.iva2_cm_clksel2 =
cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
@@ -371,6 +374,8 @@ void omap3_prcm_restore_context(void)
{
omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
OMAP343X_CONTROL_PADCONF_SYSNIRQ);
+ cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
+CM_CLKSEL1);
cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
CM_CLKSEL2);
__raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
--
1.6.0.1
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[PATCH PM 0/1] OMAP3: MCSPI: Fix to spi save/restore
There is a bug in SPI save/restore. This patch is supposed to fix that. omap2_mcspi.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH PM 1/1] OMAP3 McSPI: Fix to restore chconf for all CSs
This patch saves/restores chconf0 for all CSs instead of only for CS0
Signed-off-by: Jouni Hogander jouni.hogan...@nokia.com
---
drivers/spi/omap2_mcspi.c | 14 +++---
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index a7ee3b7..45632dd 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -142,7 +142,7 @@ struct omap2_mcspi_cs {
struct omap2_mcspi_regs {
u32 sysconfig;
u32 modulctrl;
- u32 chconf0;
+ u32 chconf0[4];
u32 wakeupenable;
};
@@ -238,8 +238,8 @@ static void omap2_mcspi_set_master_mode(struct spi_master
*master)
static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
{
- struct spi_master *spi_cntrl;
- spi_cntrl = mcspi-master;
+ struct spi_master *spi_cntrl = mcspi-master;
+ int i;
/* McSPI: context restore */
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
@@ -248,9 +248,9 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi
*mcspi)
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
omap2_mcspi_ctx[spi_cntrl-bus_num - 1].sysconfig);
- mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_CHCONF0,
- omap2_mcspi_ctx[spi_cntrl-bus_num - 1].chconf0);
-
+ for (i = 0; i spi_cntrl-num_chipselect; i++)
+ mcspi_write_reg(spi_cntrl, i * 0x14 + OMAP2_MCSPI_CHCONF0,
+ omap2_mcspi_ctx[spi_cntrl-bus_num -
1].chconf0[i]);
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
omap2_mcspi_ctx[spi_cntrl-bus_num - 1].wakeupenable);
@@ -593,7 +593,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device
*spi,
mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
- omap2_mcspi_ctx[spi_cntrl-bus_num - 1].chconf0 = l;
+ omap2_mcspi_ctx[spi_cntrl-bus_num - 1].chconf0[spi-chip_select] = l;
dev_dbg(spi-dev, setup: speed %d, sample %s edge, clk %s\n,
OMAP2_MCSPI_MAX_FREQ / (1 div),
--
1.6.0.1
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[PATCH 1/2] SDTI: Fix sdti to use right clocks from clockfw
SDTI uses pclk and pclkx2 instead of emu_per_alwon_ck. This patch
fixes sdti to use those clocks.
Signed-off-by: Jouni Hogander jouni.hogan...@nokia.com
---
drivers/misc/sti/sdti.c | 47 +--
1 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/drivers/misc/sti/sdti.c b/drivers/misc/sti/sdti.c
index 92ce57b..8c27504 100644
--- a/drivers/misc/sti/sdti.c
+++ b/drivers/misc/sti/sdti.c
@@ -34,7 +34,7 @@
#define SDTI_SYSCONFIG_SOFTRESET (1 1)
#define SDTI_SYSCONFIG_AUTOIDLE(1 0)
-static struct clk *sdti_ck;
+static struct clk *sdti_fck, *sdti_ick;
void __iomem *sti_base, *sti_channel_base;
static DEFINE_SPINLOCK(sdti_lock);
@@ -70,14 +70,30 @@ static void omap_sdti_reset(void)
static int __init omap_sdti_init(void)
{
char buf[64];
- int i;
+ int i, ret = 0;
- sdti_ck = clk_get(NULL, emu_per_alwon_ck);
- if (IS_ERR(sdti_ck)) {
- printk(KERN_ERR Cannot get clk emu_per_alwon_ck\n);
- return PTR_ERR(sdti_ck);
+ sdti_fck = clk_get(NULL, pclk_fck);
+ if (IS_ERR(sdti_fck)) {
+ printk(KERN_ERR Cannot get clk pclk_fck\n);
+ ret = PTR_ERR(sdti_fck);
+ goto err0;
+ }
+ sdti_ick = clk_get(NULL, pclkx2_fck);
+ if (IS_ERR(sdti_ick)) {
+ printk(KERN_ERR Cannot get clk pclkx2_fck\n);
+ ret = PTR_ERR(sdti_ick);
+ goto err1;
+ }
+ ret = clk_enable(sdti_fck);
+ if (ret) {
+ printk(KERN_ERR Cannot enable sdti_fck\n);
+ goto err2;
+ }
+ ret = clk_enable(sdti_ick);
+ if (ret) {
+ printk(KERN_ERR Cannot enable sdti_ick\n);
+ goto err3;
}
- clk_enable(sdti_ck);
omap_sdti_reset();
sti_writel(0xC5ACCE55, SDTI_LOCK_ACCESS);
@@ -107,14 +123,25 @@ static int __init omap_sdti_init(void)
printk(KERN_INFO %s, buf);
sti_channel_write_trace(strlen(buf), 0xc3, buf, 239);
- return 0;
+ return ret;
+
+err3:
+ clk_disable(sdti_fck);
+err2:
+ clk_put(sdti_ick);
+err1:
+ clk_put(sdti_fck);
+err0:
+ return ret;
}
static void omap_sdti_exit(void)
{
sti_writel(0, SDTI_WINCTRL);
- clk_disable(sdti_ck);
- clk_put(sdti_ck);
+ clk_disable(sdti_fck);
+ clk_disable(sdti_ick);
+ clk_put(sdti_fck);
+ clk_put(sdti_ick);
}
static int __devinit omap_sdti_probe(struct platform_device *pdev)
--
1.6.0.1
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[PATCH PM] OMAP: UART: Add sysfs interface for adjusting UART sleep timeout
This patch makes it possible to change uart sleep timeout. New sysfs
entry is added (/sys/devices/platform/serial8250.0/sleep_timeout)
Also default timeout is increased to 5 second to make serial console
more usable.
Original patch was written by Tero Kristo some time ago.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/serial.c | 45 +++--
1 files changed, 42 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 7635038..c0a913a 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -31,7 +31,7 @@
#include pm.h
#include prm-regbits-34xx.h
-#define DEFAULT_TIMEOUT (2 * HZ)
+#define DEFAULT_TIMEOUT (5 * HZ)
struct omap_uart_state {
int num;
@@ -330,6 +330,8 @@ static irqreturn_t omap_uart_interrupt(int irq, void
*dev_id)
return IRQ_NONE;
}
+static u32 sleep_timeout = DEFAULT_TIMEOUT;
+
static void omap_uart_idle_init(struct omap_uart_state *uart)
{
u32 v;
@@ -337,7 +339,7 @@ static void omap_uart_idle_init(struct omap_uart_state
*uart)
int ret;
uart-can_sleep = 0;
- uart-timeout = DEFAULT_TIMEOUT;
+ uart-timeout = sleep_timeout;
setup_timer(uart-timer, omap_uart_idle_timer,
(unsigned long) uart);
mod_timer(uart-timer, jiffies + uart-timeout);
@@ -418,6 +420,34 @@ static void omap_uart_pm(struct uart_port *port,
break;
}
}
+
+static ssize_t sleep_timeout_show(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, %u\n, sleep_timeout / HZ);
+}
+
+static ssize_t sleep_timeout_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t n)
+{
+ struct omap_uart_state *uart;
+ unsigned int value;
+
+ if (sscanf(buf, %u, value) != 1) {
+ printk(KERN_ERR sleep_timeout_store: Invalid value\n);
+ return -EINVAL;
+ }
+ sleep_timeout = value * HZ;
+ list_for_each_entry(uart, uart_list, node)
+ uart-timeout = sleep_timeout;
+ return n;
+}
+
+static struct kobj_attribute sleep_timeout_attr =
+ __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
+
#else
static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
static inline void omap_uart_pm(struct uart_port *port,
@@ -490,6 +520,15 @@ static struct platform_device serial_device = {
static int __init omap_init(void)
{
- return platform_device_register(serial_device);
+ int ret;
+
+ ret = platform_device_register(serial_device);
+
+#ifdef CONFIG_PM
+ if (!ret)
+ ret = sysfs_create_file(serial_device.dev.kobj,
+ sleep_timeout_attr.attr);
+#endif
+ return ret;
}
arch_initcall(omap_init);
--
1.6.0.1
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[PATCH PM-20081119] OMAP: PM: Check both, IOPAD and UART wakeup always
Uart RX might not always generate IOPAD wake-up. E.g. IOPAD is not enabled or core was not in sleep state. Signed-off-by: Jouni Hogander [EMAIL PROTECTED] --- arch/arm/mach-omap2/serial.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 745ae5c..8d2f0b1 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -281,7 +281,7 @@ void omap_uart_resume_idle(int num) } /* Check for normal UART wakeup */ - else if (__raw_readl(uart-wk_st) uart-wk_mask) + if (__raw_readl(uart-wk_st) uart-wk_mask) omap_uart_block_sleep(uart); return; -- 1.6.0.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH PM-20081106] OMAP: PM: Few fixes to uart clock handling
Omap3_can_sleep is not inside part of idle loop which is protected
with irg disable. If some irq handler is trying dump out something
after omap3_can_sleep and before irqs are disabled. It causes oops
because uart clocks are disabled.
Remove also some unused extra code from omap_uart_can_sleep
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/serial.c | 11 +--
1 files changed, 1 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index ef30d8d..b06b797 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -314,21 +314,13 @@ void omap_uart_check_wakeup(void)
int omap_uart_can_sleep(void)
{
struct omap_uart_state *uart;
- int can_sleep = 1;
list_for_each_entry(uart, uart_list, node) {
- if (!uart-clocked)
+ if (!uart-clocked || !uart-can_sleep)
continue;
- if (!uart-can_sleep) {
- can_sleep = 0;
- continue;
- }
-
/* This UART can now safely sleep. */
omap_uart_allow_sleep(uart);
- if (clocks_off_while_idle)
- omap_uart_disable_clocks(uart);
}
return 1;
@@ -435,7 +427,6 @@ static void omap_uart_pm(struct uart_port *port,
break;
case 3: /* suspend */
omap_uart_allow_sleep(uart);
- omap_uart_disable_clocks(uart);
break;
}
}
--
1.6.0.1
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[PATCH PM-20081106 3/3] OMAP2: PM: Fix omap2 build
This patch fixes build in case of omap2.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm.h |4
arch/arm/mach-omap2/pm24xx.c |4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 91431f9..4b1ba7c 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -32,7 +32,11 @@ extern void *omap3_secure_ram_storage;
extern void omap2_block_sleep(void);
extern void omap2_allow_sleep(void);
+#ifdef CONFIG_ARCH_OMAP3
extern void omap3_pm_off_mode_enable(int);
+#else
+#define omap3_pm_off_mode_enable(int) do {} while (0);
+#endif
extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 4a19804..b385f3c 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -338,7 +338,7 @@ static struct platform_suspend_ops omap_pm_ops = {
.valid = suspend_valid_only_mem,
};
-static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm)
+static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm, void *unused)
{
omap2_clkdm_allow_idle(clkdm);
return 0;
@@ -390,7 +390,7 @@ static void __init prcm_setup_regs(void)
omap2_clkdm_sleep(gfx_clkdm);
/* Enable clockdomain hardware-supervised control for all clkdms */
- clkdm_for_each(_pm_clkdm_enable_hwsup);
+ clkdm_for_each(_pm_clkdm_enable_hwsup, NULL);
/* Enable clock autoidle for all domains */
cm_write_mod_reg(OMAP24XX_AUTO_CAM |
--
1.6.0.1
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[PATCH PM-20081106 1/3] OMAP3: PM: Do not build suspend code if SUSPEND is not enabled
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index d2330c4..d499dc7 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -67,7 +67,9 @@
struct power_state {
struct powerdomain *pwrdm;
u32 next_state;
+#ifdef CONFIG_SUSPEND
u32 saved_state;
+#endif
struct list_head node;
};
@@ -511,6 +513,7 @@ out:
local_irq_enable();
}
+#ifdef CONFIG_SUSPEND
static int omap3_pm_prepare(void)
{
saved_idle = pm_idle;
@@ -584,6 +587,7 @@ static struct platform_suspend_ops omap_pm_ops = {
.finish = omap3_pm_finish,
.valid = suspend_valid_only_mem,
};
+#endif /* CONFIG_SUSPEND */
static void __init prcm_setup_regs(void)
{
@@ -862,7 +866,10 @@ int __init omap3_pm_init(void)
core_pwrdm = pwrdm_lookup(core_pwrdm);
omap_push_sram_idle();
+
+#ifdef CONFIG_SUSPEND
suspend_set_ops(omap_pm_ops);
+#endif /* CONFIG_SUSPEND */
pm_idle = omap3_pm_idle;
omap3_idle_init();
--
1.6.0.1
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[PATCH PM-20081106 2/3] OMAP: PM: Build fails if PM is not enabled
This patch fixes build in case if PM is not enabled
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/control.c |6 --
arch/arm/mach-omap2/serial.c | 32 +++-
arch/arm/plat-omap/Kconfig |3 ++-
arch/arm/plat-omap/include/mach/sram.h |5 +
arch/arm/plat-omap/sram.c |2 ++
5 files changed, 32 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 743b57e..d28b823 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -26,6 +26,7 @@
static void __iomem *omap2_ctrl_base;
+#if defined(CONFIG_ARCH_OMAP3) defined(CONFIG_PM)
struct omap3_scratchpad {
u32 boot_config_ptr;
u32 public_restore_ptr;
@@ -133,6 +134,7 @@ struct omap3_control_regs {
};
static struct omap3_control_regs control_context;
+#endif /* CONFIG_ARCH_OMAP3 CONFIG_PM */
#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
@@ -176,7 +178,7 @@ void omap_ctrl_writel(u32 val, u16 offset)
__raw_writel(val, OMAP_CTRL_REGADDR(offset));
}
-#ifdef CONFIG_ARCH_OMAP3
+#if defined(CONFIG_ARCH_OMAP3) defined(CONFIG_PM)
/*
* Clears the scratchpad contents in case of cold boot-
* called during bootup
@@ -425,4 +427,4 @@ void omap3_control_restore_context(void)
omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
return;
}
-#endif /* CONFIG_ARCH_OMAP3 */
+#endif /* CONFIG_ARCH_OMAP3 CONFIG_PM */
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 65cce87..95a2299 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -51,7 +51,7 @@ struct omap_uart_state {
struct plat_serial8250_port *p;
struct list_head node;
-#ifdef CONFIG_ARCH_OMAP3
+#if defined(CONFIG_ARCH_OMAP3) defined(CONFIG_PM)
int context_valid;
/* Registers to be saved/restored for OFF-mode */
@@ -126,7 +126,7 @@ static inline void __init omap_uart_reset(struct
omap_uart_state *uart)
serial_write_reg(p, UART_OMAP_SYSC, (0x02 3) | (1 2) | (1 0));
}
-#ifdef CONFIG_ARCH_OMAP3
+#if defined(CONFIG_ARCH_OMAP3) defined(CONFIG_PM)
static void omap_uart_save_context(struct omap_uart_state *uart)
{
u16 lcr = 0;
@@ -186,6 +186,18 @@ static inline void omap_uart_save_context(struct
omap_uart_state *uart) {}
static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
#endif /* CONFIG_ARCH_OMAP3 */
+static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
+{
+ if (uart-clocked)
+ return;
+
+ clk_enable(uart-ick);
+ clk_enable(uart-fck);
+ uart-clocked = 1;
+ omap_uart_restore_context(uart);
+}
+
+#ifdef CONFIG_PM
static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
int enable)
{
@@ -201,17 +213,6 @@ static void omap_uart_smart_idle_enable(struct
omap_uart_state *uart,
serial_write_reg(p, UART_OMAP_SYSC, sysc);
}
-static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
-{
- if (uart-clocked)
- return;
-
- clk_enable(uart-ick);
- clk_enable(uart-fck);
- uart-clocked = 1;
- omap_uart_restore_context(uart);
-}
-
static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
{
if (!uart-clocked)
@@ -409,6 +410,11 @@ static void omap_uart_pm(struct uart_port *port,
break;
}
}
+#else
+static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
+static inline void omap_uart_pm(struct uart_port *port,
+ unsigned int state, unsigned int old_state) {}
+#endif /* CONFIG_PM */
void __init omap_serial_init(void)
{
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 0ee0985..ca67862 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -58,7 +58,7 @@ config OMAP_DEBUG_CLOCKDOMAIN
config OMAP_SMARTREFLEX
bool SmartReflex support
- depends on ARCH_OMAP34XX TWL4030_CORE
+ depends on ARCH_OMAP34XX TWL4030_CORE PM
help
Say Y if you want to enable SmartReflex.
@@ -264,6 +264,7 @@ config OMAP_PM_NOOP
bool No-op/debug PM layer
config OMAP_PM_SRF
+ depends on PM
bool PM layer implemented using SRF
endchoice
diff --git a/arch/arm/plat-omap/include/mach/sram.h
b/arch/arm/plat-omap/include/mach/sram.h
index 87f4567..0c0b45f 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -63,6 +63,11 @@ extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2);
extern unsigned long omap3_sram_configure_core_dpll_sz;
+
+#ifdef CONFIG_PM
extern void
[PATCH] OMAP: MCSPI: Enable mcspi wake-up
Currently mcspi wake-ups are not enabled. This might cause case where
OMAP is not waking up on mcspi events.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
drivers/spi/omap2_mcspi.c | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index 454a271..4bd330c 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -59,6 +59,8 @@
/* per-register bitmasks: */
+#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE(0x2 3)
+#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP(0x1 2)
#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE (1 0)
#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET(1 1)
@@ -90,6 +92,7 @@
#define OMAP2_MCSPI_CHCTRL_EN (1 0)
+#define OMAP2_MCSPI_WAKEUPENABLE_WKEN (1 0)
/* We have 2 DMA channels per CS, one for RX and one for TX */
struct omap2_mcspi_dma {
@@ -884,8 +887,12 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi
*mcspi)
} while (!(tmp OMAP2_MCSPI_SYSSTATUS_RESETDONE));
mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
- /* (3 8) | (2 3) | */
- OMAP2_MCSPI_SYSCONFIG_AUTOIDLE);
+ OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
+ OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
+ OMAP2_MCSPI_SYSCONFIG_SMARTIDLE);
+
+ mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
+ OMAP2_MCSPI_WAKEUPENABLE_WKEN);
omap2_mcspi_set_master_mode(master);
--
1.6.0.1
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[PATCH] OMAP: MCSPI: Enable mcspi wake-up v2.
Currently mcspi wake-ups are not enabled. This might cause case where
OMAP is not waking up on mcspi events.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
drivers/spi/omap2_mcspi.c | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index 454a271..d7e519c 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -59,6 +59,8 @@
/* per-register bitmasks: */
+#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE(2 3)
+#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP(1 2)
#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE (1 0)
#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET(1 1)
@@ -90,6 +92,7 @@
#define OMAP2_MCSPI_CHCTRL_EN (1 0)
+#define OMAP2_MCSPI_WAKEUPENABLE_WKEN (1 0)
/* We have 2 DMA channels per CS, one for RX and one for TX */
struct omap2_mcspi_dma {
@@ -884,8 +887,12 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi
*mcspi)
} while (!(tmp OMAP2_MCSPI_SYSSTATUS_RESETDONE));
mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
- /* (3 8) | (2 3) | */
- OMAP2_MCSPI_SYSCONFIG_AUTOIDLE);
+ OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
+ OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
+ OMAP2_MCSPI_SYSCONFIG_SMARTIDLE);
+
+ mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
+ OMAP2_MCSPI_WAKEUPENABLE_WKEN);
omap2_mcspi_set_master_mode(master);
--
1.6.0.1
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[PATCH] OMAP3: PM: Check in set_pwrdm_state that target state is supported by pwrdm v2
Check that wanted sleep state is supported by powerdomain. If it is
not supported, then use next lowest supported state.
Check also on suspend that state of pwrdm was lower or equal.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index da098d2..9f5a544 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -239,8 +239,13 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32
state)
if (pwrdm == NULL || IS_ERR(pwrdm))
return -EINVAL;
- cur_state = pwrdm_read_next_pwrst(pwrdm);
+ while (!(pwrdm-pwrsts (1 state))) {
+ if (state == PWRDM_POWER_OFF)
+ return ret;
+ state--;
+ }
+ cur_state = pwrdm_read_next_pwrst(pwrdm);
if (cur_state == state)
return ret;
@@ -314,7 +319,7 @@ restore:
list_for_each_entry(pwrst, pwrst_list, node) {
set_pwrdm_state(pwrst-pwrdm, pwrst-saved_state);
state = pwrdm_read_prev_pwrst(pwrst-pwrdm);
- if (state != pwrst-next_state) {
+ if (state pwrst-next_state) {
printk(KERN_INFO Powerdomain (%s) didn't enter
target state %d\n,
pwrst-pwrdm-name, pwrst-next_state);
--
1.6.0.1
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[PATCH] OMAP3: PM: Check in set_pwrdm_state that target state is supported by pwrdm
Check that wanted sleep state is supported by powerdomain. If it is
not supported, then use next lowest supported state.
Check also on suspend that state of pwrdm was lower or equal.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index da098d2..babead5 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -239,8 +239,13 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32
state)
if (pwrdm == NULL || IS_ERR(pwrdm))
return -EINVAL;
- cur_state = pwrdm_read_next_pwrst(pwrdm);
+ while (!(pwrdm-pwrsts (1 state))) {
+ if (state PWRDM_POWER_OFF)
+ return ret;
+ state--;
+ }
+ cur_state = pwrdm_read_next_pwrst(pwrdm);
if (cur_state == state)
return ret;
@@ -314,7 +319,7 @@ restore:
list_for_each_entry(pwrst, pwrst_list, node) {
set_pwrdm_state(pwrst-pwrdm, pwrst-saved_state);
state = pwrdm_read_prev_pwrst(pwrst-pwrdm);
- if (state != pwrst-next_state) {
+ if (state pwrst-next_state) {
printk(KERN_INFO Powerdomain (%s) didn't enter
target state %d\n,
pwrst-pwrdm-name, pwrst-next_state);
--
1.6.0.1
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[PATCH PM-20081106] OMAP3: UART: Make sure that uart clocks are enabled when needed
Current implementation makes it possible that printouts are
written into UART while its clocks are disabled. This causes freeze.
This patch contains possible fix for this.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c |6 ++
arch/arm/mach-omap2/serial.c | 30 ++
arch/arm/plat-omap/include/mach/serial.h |2 ++
3 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index d480c39..3838a19 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -320,6 +320,7 @@ void omap_sram_idle(void)
/* PER */
per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
if (per_next_state PWRDM_POWER_ON) {
+ omap_uart_prepare_idle(2);
omap2_gpio_prepare_for_retention();
if (per_next_state == PWRDM_POWER_OFF)
omap3_per_save_context();
@@ -328,6 +329,8 @@ void omap_sram_idle(void)
/* CORE */
core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
if (core_next_state PWRDM_POWER_ON) {
+ omap_uart_prepare_idle(0);
+ omap_uart_prepare_idle(1);
if (core_next_state == PWRDM_POWER_OFF) {
prm_set_mod_reg_bits(OMAP3430_AUTO_OFF,
OMAP3430_GR_MOD,
@@ -386,6 +389,8 @@ void omap_sram_idle(void)
prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF,
OMAP3430_GR_MOD,
OMAP3_PRM_VOLTCTRL_OFFSET);
+ omap_uart_resume_idle(0);
+ omap_uart_resume_idle(1);
}
/* PER */
@@ -394,6 +399,7 @@ void omap_sram_idle(void)
if (per_prev_state == PWRDM_POWER_OFF)
omap3_per_restore_context();
omap2_gpio_resume_after_retention();
+ omap_uart_resume_idle(2);
}
/* Enable smartreflex after WFI */
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 65cce87..ef30d8d 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -249,6 +249,36 @@ static void omap_uart_idle_timer(unsigned long data)
omap_uart_allow_sleep(uart);
}
+void omap_uart_prepare_idle(int num)
+{
+ struct omap_uart_state *uart;
+
+ if (!clocks_off_while_idle)
+ return;
+
+ list_for_each_entry(uart, uart_list, node) {
+ if (num == uart-num uart-can_sleep) {
+ omap_uart_disable_clocks(uart);
+ return;
+ }
+ }
+}
+
+void omap_uart_resume_idle(int num)
+{
+ struct omap_uart_state *uart;
+
+ if (!clocks_off_while_idle)
+ return;
+
+ list_for_each_entry(uart, uart_list, node) {
+ if (num == uart-num) {
+ omap_uart_enable_clocks(uart);
+ return;
+ }
+ }
+}
+
void omap_uart_check_wakeup(void)
{
struct omap_uart_state *uart;
diff --git a/arch/arm/plat-omap/include/mach/serial.h
b/arch/arm/plat-omap/include/mach/serial.h
index 11ff540..254a775 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -44,6 +44,8 @@
extern void omap_serial_init(void);
extern int omap_uart_can_sleep(void);
extern void omap_uart_check_wakeup(void);
+extern void omap_uart_prepare_idle(int num);
+extern void omap_uart_resume_idle(int num);
#endif
#endif
--
1.6.0.1
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[PATCH PM-0] OMAP3: PM: Remove extra prcm save from idle loop
Prcm registers are saved two times in case of core OFF. First one can be removed. Signed-off-by: Jouni Hogander [EMAIL PROTECTED] --- arch/arm/mach-omap2/pm34xx.c |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 1b0272d..e8a47a5 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -304,7 +304,6 @@ void omap_sram_idle(void) OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET); omap3_save_core_ctx(); - omap3_save_prcm_ctx(); omap_save_uart_ctx(0); omap_save_uart_ctx(1); } -- 1.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH PM-0] OMAP3: I2C: Implement i2c save/restore
Save and restore needed registers instead of re-init.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
drivers/i2c/busses/i2c-omap.c | 47 +++--
1 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index a661ed3..211d7b5 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -147,6 +147,10 @@ struct omap_i2c_dev {
unsignedb_hw:1; /* bad h/w fixes */
unsignedidle:1;
u16 iestate;/* Saved interrupt register */
+ u16 pscstate;
+ u16 scllstate;
+ u16 sclhstate;
+ u16 bufstate;
};
static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
@@ -209,16 +213,22 @@ static void omap_i2c_unidle(struct omap_i2c_dev *dev)
if (dev-iclk != NULL)
clk_enable(dev-iclk);
clk_enable(dev-fclk);
+
+ if (cpu_is_omap34xx()) {
+ omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev-pscstate);
+ omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev-scllstate);
+ omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev-sclhstate);
+ omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev-bufstate);
+ }
+
dev-idle = 0;
- if (dev-iestate)
- omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev-iestate);
+ omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev-iestate);
}
static void omap_i2c_idle(struct omap_i2c_dev *dev)
{
u16 iv;
- dev-iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
if (dev-rev1)
iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
@@ -238,7 +248,7 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev)
static int omap_i2c_init(struct omap_i2c_dev *dev)
{
- u16 psc = 0, scll = 0, sclh = 0;
+ u16 psc = 0, scll = 0, sclh = 0, buf = 0;
u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
unsigned long fclk_rate = 1200;
unsigned long timeout;
@@ -327,23 +337,30 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
- if (dev-fifo_size)
- /* Note: setup required fifo size - 1 */
- omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
- (dev-fifo_size - 1) 8 | /* RTRSH */
- OMAP_I2C_BUF_RXFIF_CLR |
- (dev-fifo_size - 1) | /* XTRSH */
- OMAP_I2C_BUF_TXFIF_CLR);
+ if (dev-fifo_size) {
+ /* Note: setup required fifo size - 1. RTRSH and XTRSH */
+ buf = (dev-fifo_size - 1) 8 | OMAP_I2C_BUF_RXFIF_CLR |
+ (dev-fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
+ omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
+ }
/* Take the I2C module out of reset: */
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
/* Enable interrupts */
- omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
- (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
+ dev-iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
OMAP_I2C_IE_AL) | ((dev-fifo_size) ?
- (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
+ (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
+ omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev-iestate);
+
+ if (cpu_is_omap34xx()) {
+ dev-pscstate = psc;
+ dev-scllstate = scll;
+ dev-sclhstate = sclh;
+ dev-bufstate = buf;
+ }
+
return 0;
}
@@ -503,8 +520,6 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
omap_i2c_unidle(dev);
- omap_i2c_init(dev);
-
if ((r = omap_i2c_wait_for_bb(dev)) 0)
goto out;
--
1.5.5
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[PATCH] OMAP3: GPIO: Enable debounce clock only when debounce is enabled v3.
This patch changes gpio driver to enable debounce clock for
gpio-bank only when debounce is enabled for some gpio in that bank.
Gpio functional clocks are also renamed in clock tree, gpioX_fck -
gpioX_dbck.
This patch triggers problem with gpio wake-up and Omap3. Gpios in PER
domain aren't capable to generate wake-up if PER domain is in sleep
state. For this iopad wake-up should be used and needed pad
configuration should be done. Enabling iopad wake-up for gpio pads is
left for bootloader or omap mux configuration in kernel.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.h | 36 ++--
arch/arm/plat-omap/gpio.c | 26 +++---
2 files changed, 33 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 41f91f8..b81b69b 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2399,8 +2399,8 @@ static struct clk wkup_32k_fck = {
.recalc = followparent_recalc,
};
-static struct clk gpio1_fck = {
- .name = gpio1_fck,
+static struct clk gpio1_dbck = {
+ .name = gpio1_dbck,
.parent = wkup_32k_fck,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
@@ -2643,8 +2643,8 @@ static struct clk per_32k_alwon_fck = {
.recalc = followparent_recalc,
};
-static struct clk gpio6_fck = {
- .name = gpio6_fck,
+static struct clk gpio6_dbck = {
+ .name = gpio6_dbck,
.parent = per_32k_alwon_fck,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
@@ -2653,8 +2653,8 @@ static struct clk gpio6_fck = {
.recalc = followparent_recalc,
};
-static struct clk gpio5_fck = {
- .name = gpio5_fck,
+static struct clk gpio5_dbck = {
+ .name = gpio5_dbck,
.parent = per_32k_alwon_fck,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
@@ -2663,8 +2663,8 @@ static struct clk gpio5_fck = {
.recalc = followparent_recalc,
};
-static struct clk gpio4_fck = {
- .name = gpio4_fck,
+static struct clk gpio4_dbck = {
+ .name = gpio4_dbck,
.parent = per_32k_alwon_fck,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
@@ -2673,8 +2673,8 @@ static struct clk gpio4_fck = {
.recalc = followparent_recalc,
};
-static struct clk gpio3_fck = {
- .name = gpio3_fck,
+static struct clk gpio3_dbck = {
+ .name = gpio3_dbck,
.parent = per_32k_alwon_fck,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
@@ -2683,8 +2683,8 @@ static struct clk gpio3_fck = {
.recalc = followparent_recalc,
};
-static struct clk gpio2_fck = {
- .name = gpio2_fck,
+static struct clk gpio2_dbck = {
+ .name = gpio2_dbck,
.parent = per_32k_alwon_fck,
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
@@ -3290,7 +3290,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
usim_fck,
gpt1_fck,
wkup_32k_fck,
- gpio1_fck,
+ gpio1_dbck,
wdt2_fck,
wkup_l4_ick,
usim_ick,
@@ -3312,11 +3312,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
gpt8_fck,
gpt9_fck,
per_32k_alwon_fck,
- gpio6_fck,
- gpio5_fck,
- gpio4_fck,
- gpio3_fck,
- gpio2_fck,
+ gpio6_dbck,
+ gpio5_dbck,
+ gpio4_dbck,
+ gpio3_dbck,
+ gpio2_dbck,
wdt3_fck,
per_l4_ick,
gpio6_ick,
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index ac55616..2d63023 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -151,6 +151,7 @@ struct gpio_bank {
u32 level_mask;
spinlock_t lock;
struct gpio_chip chip;
+ struct clk *dbck;
};
#define METHOD_MPUIO 0
@@ -483,10 +484,15 @@ void omap_set_gpio_debounce(int gpio, int enable)
reg += OMAP24XX_GPIO_DEBOUNCE_EN;
val = __raw_readl(reg);
- if (enable)
+ if (enable !(val l))
val |= l;
- else
+ else if (!enable val l)
val = ~l;
+ else
+ return;
+
+ if (cpu_is_omap34xx())
+ enable ? clk_enable(bank-dbck) : clk_disable(bank-dbck);
__raw_writel(val, reg);
}
@@ -1298,7 +1304,6 @@ static struct clk * gpio5_fck
[PATCH 1/4] 34XX: PM: Workaround to check wether any fck is active before entering sleep
This workaround shouldn't be needed when all drivers are configuring
their sysconfig registers properly and using their clocks properly.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 37 +
1 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a57cf41..5c37cbd 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -174,10 +174,47 @@ static void omap_sram_idle(void)
omap2_gpio_resume_after_retention();
}
+/* XXX This workaround shouldn't be needed when all drivers are configuring
+ * their sysconfig registers properly and using their clocks
+ * properly. */
+static int omap3_fclks_active(void)
+{
+ u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
+ fck_cam = 0, fck_per = 0, fck_usbhost = 0;
+
+ fck_core1 = cm_read_mod_reg(CORE_MOD,
+ CM_FCLKEN1);
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ fck_core3 = cm_read_mod_reg(CORE_MOD,
+ OMAP3430ES2_CM_FCLKEN3);
+ fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+ CM_FCLKEN);
+ fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+ CM_FCLKEN);
+ } else
+ fck_sgx = cm_read_mod_reg(GFX_MOD,
+ OMAP3430ES2_CM_FCLKEN3);
+ fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
+ CM_FCLKEN);
+ fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
+ CM_FCLKEN);
+ fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
+ CM_FCLKEN);
+ if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
+ fck_cam | fck_per | fck_usbhost)
+ return 1;
+ return 0;
+}
+
static int omap3_can_sleep(void)
{
if (!enable_dyn_sleep)
return 0;
+ /* XXX This workaround shouldn't be needed when all drivers are
configuring
+* their sysconfig registers properly and using their clocks
+* properly. */
+ if (omap3_fclks_active())
+ return 0;
if (atomic_read(sleep_block) 0)
return 0;
return 1;
--
1.5.5
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[PATCH 4/4] 34XX: PM: Workaround to enable autoidle for clocks and plls
From: ext Jouni Hogander [EMAIL PROTECTED]
This workaround enables autoidle for interface clocks and plls. Also
automatic control of external oscillator through sys_clkreq is
enabled.
Proper fix to this is to generalize omap3_dpll_allow_idle,
omap3_dpll_deny_idle, omap3_dpll_autoidle_read and call it for each
clock on init.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 120 ++
1 files changed, 120 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 8fb8ba7..def77ad 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -438,6 +438,126 @@ static void __init prcm_setup_regs(void)
} else
prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
+ /* XXX Enable interface clock autoidle for all modules. This
+* should be done by clockfw */
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_MMC3 |
+ OMAP3430ES2_AUTO_ICR |
+ OMAP3430_AUTO_AES2 |
+ OMAP3430_AUTO_SHA12 |
+ OMAP3430_AUTO_DES2 |
+ OMAP3430_AUTO_MMC2 |
+ OMAP3430_AUTO_MMC1 |
+ OMAP3430_AUTO_MSPRO |
+ OMAP3430_AUTO_HDQ |
+ OMAP3430_AUTO_MCSPI4 |
+ OMAP3430_AUTO_MCSPI3 |
+ OMAP3430_AUTO_MCSPI2 |
+ OMAP3430_AUTO_MCSPI1 |
+ OMAP3430_AUTO_I2C3 |
+ OMAP3430_AUTO_I2C2 |
+ OMAP3430_AUTO_I2C1 |
+ OMAP3430_AUTO_UART2 |
+ OMAP3430_AUTO_UART1 |
+ OMAP3430_AUTO_GPT11 |
+ OMAP3430_AUTO_GPT10 |
+ OMAP3430_AUTO_MCBSP5 |
+ OMAP3430_AUTO_MCBSP1 |
+ OMAP3430ES1_AUTO_FAC | /* This is es1 only */
+ OMAP3430_AUTO_MAILBOXES |
+ OMAP3430_AUTO_OMAPCTRL |
+ OMAP3430ES1_AUTO_FSHOSTUSB |
+ OMAP3430_AUTO_HSOTGUSB |
+ OMAP3430ES1_AUTO_D2D | /* This is es1 only */
+ OMAP3430_AUTO_SSI,
+ CORE_MOD, CM_AUTOIDLE1);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_PKA |
+ OMAP3430_AUTO_AES1 |
+ OMAP3430_AUTO_RNG |
+ OMAP3430_AUTO_SHA11 |
+ OMAP3430_AUTO_DES1,
+ CORE_MOD, CM_AUTOIDLE2);
+
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_USBTLL,
+ CORE_MOD, CM_AUTOIDLE3);
+ }
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_WDT2 |
+ OMAP3430_AUTO_WDT1 |
+ OMAP3430_AUTO_GPIO1 |
+ OMAP3430_AUTO_32KSYNC |
+ OMAP3430_AUTO_GPT12 |
+ OMAP3430_AUTO_GPT1 ,
+ WKUP_MOD, CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_DSS,
+ OMAP3430_DSS_MOD,
+ CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_CAM,
+ OMAP3430_CAM_MOD,
+ CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_GPIO6 |
+ OMAP3430_AUTO_GPIO5 |
+ OMAP3430_AUTO_GPIO4 |
+ OMAP3430_AUTO_GPIO3 |
+ OMAP3430_AUTO_GPIO2 |
+ OMAP3430_AUTO_WDT3 |
+ OMAP3430_AUTO_UART3 |
+ OMAP3430_AUTO_GPT9 |
+ OMAP3430_AUTO_GPT8 |
+ OMAP3430_AUTO_GPT7 |
+ OMAP3430_AUTO_GPT6 |
+ OMAP3430_AUTO_GPT5 |
+ OMAP3430_AUTO_GPT4 |
+ OMAP3430_AUTO_GPT3 |
+ OMAP3430_AUTO_GPT2 |
+ OMAP3430_AUTO_MCBSP4 |
+ OMAP3430_AUTO_MCBSP3 |
+ OMAP3430_AUTO_MCBSP2,
+ OMAP3430_PER_MOD,
+ CM_AUTOIDLE);
+
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_USBHOST,
+ OMAP3430ES2_USBHOST_MOD,
+ CM_AUTOIDLE);
+ }
+
+ /* XXX Set all plls to autoidle. This is needed until autoidle is
+* enabled by clockfw */
+ cm_write_mod_reg(1 OMAP3430_CLKTRCTRL_IVA2_SHIFT,
+OMAP3430_IVA2_MOD,
+CM_AUTOIDLE2);
+ cm_write_mod_reg(1 OMAP3430_AUTO_MPU_DPLL_SHIFT,
+MPU_MOD,
+CM_AUTOIDLE2);
+ cm_write_mod_reg((1 OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
+(1 OMAP3430_AUTO_CORE_DPLL_SHIFT),
+PLL_MOD,
+CM_AUTOIDLE);
+ cm_write_mod_reg(1 OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
+PLL_MOD,
+CM_AUTOIDLE2);
+
+ /* XXX Enable control of expternal oscillator through
+* sys_clkreq. I think
[PATCH 4/4] 34XX: PM: Workaround to enable autoidle for clocks and plls
From: ext Jouni Hogander [EMAIL PROTECTED]
This workaround enables autoidle for interface clocks and plls. Also
automatic control of external oscillator through sys_clkreq is
enabled.
Proper fix to this is to generalize omap3_dpll_allow_idle,
omap3_dpll_deny_idle, omap3_dpll_autoidle_read and call it for each
clock on init.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 120 ++
1 files changed, 120 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 29b4eee..cc2ab70 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -438,6 +438,126 @@ static void __init prcm_setup_regs(void)
} else
prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
+ /* XXX Enable interface clock autoidle for all modules. This
+* should be done by clockfw */
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_MMC3 |
+ OMAP3430ES2_AUTO_ICR |
+ OMAP3430_AUTO_AES2 |
+ OMAP3430_AUTO_SHA12 |
+ OMAP3430_AUTO_DES2 |
+ OMAP3430_AUTO_MMC2 |
+ OMAP3430_AUTO_MMC1 |
+ OMAP3430_AUTO_MSPRO |
+ OMAP3430_AUTO_HDQ |
+ OMAP3430_AUTO_MCSPI4 |
+ OMAP3430_AUTO_MCSPI3 |
+ OMAP3430_AUTO_MCSPI2 |
+ OMAP3430_AUTO_MCSPI1 |
+ OMAP3430_AUTO_I2C3 |
+ OMAP3430_AUTO_I2C2 |
+ OMAP3430_AUTO_I2C1 |
+ OMAP3430_AUTO_UART2 |
+ OMAP3430_AUTO_UART1 |
+ OMAP3430_AUTO_GPT11 |
+ OMAP3430_AUTO_GPT10 |
+ OMAP3430_AUTO_MCBSP5 |
+ OMAP3430_AUTO_MCBSP1 |
+ OMAP3430ES1_AUTO_FAC | /* This is es1 only */
+ OMAP3430_AUTO_MAILBOXES |
+ OMAP3430_AUTO_OMAPCTRL |
+ OMAP3430ES1_AUTO_FSHOSTUSB |
+ OMAP3430_AUTO_HSOTGUSB |
+ OMAP3430ES1_AUTO_D2D | /* This is es1 only */
+ OMAP3430_AUTO_SSI,
+ CORE_MOD, CM_AUTOIDLE1);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_PKA |
+ OMAP3430_AUTO_AES1 |
+ OMAP3430_AUTO_RNG |
+ OMAP3430_AUTO_SHA11 |
+ OMAP3430_AUTO_DES1,
+ CORE_MOD, CM_AUTOIDLE2);
+
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_USBTLL,
+ CORE_MOD, CM_AUTOIDLE3);
+ }
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_WDT2 |
+ OMAP3430_AUTO_WDT1 |
+ OMAP3430_AUTO_GPIO1 |
+ OMAP3430_AUTO_32KSYNC |
+ OMAP3430_AUTO_GPT12 |
+ OMAP3430_AUTO_GPT1 ,
+ WKUP_MOD, CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_DSS,
+ OMAP3430_DSS_MOD,
+ CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_CAM,
+ OMAP3430_CAM_MOD,
+ CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_GPIO6 |
+ OMAP3430_AUTO_GPIO5 |
+ OMAP3430_AUTO_GPIO4 |
+ OMAP3430_AUTO_GPIO3 |
+ OMAP3430_AUTO_GPIO2 |
+ OMAP3430_AUTO_WDT3 |
+ OMAP3430_AUTO_UART3 |
+ OMAP3430_AUTO_GPT9 |
+ OMAP3430_AUTO_GPT8 |
+ OMAP3430_AUTO_GPT7 |
+ OMAP3430_AUTO_GPT6 |
+ OMAP3430_AUTO_GPT5 |
+ OMAP3430_AUTO_GPT4 |
+ OMAP3430_AUTO_GPT3 |
+ OMAP3430_AUTO_GPT2 |
+ OMAP3430_AUTO_MCBSP4 |
+ OMAP3430_AUTO_MCBSP3 |
+ OMAP3430_AUTO_MCBSP2,
+ OMAP3430_PER_MOD,
+ CM_AUTOIDLE);
+
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_USBHOST,
+ OMAP3430ES2_USBHOST_MOD,
+ CM_AUTOIDLE);
+ }
+
+ /* XXX Set all plls to autoidle. This is needed until autoidle is
+* enabled by clockfw */
+ cm_write_mod_reg(1 OMAP3430_CLKTRCTRL_IVA2_SHIFT,
+OMAP3430_IVA2_MOD,
+CM_AUTOIDLE2);
+ cm_write_mod_reg(1 OMAP3430_AUTO_MPU_DPLL_SHIFT,
+MPU_MOD,
+CM_AUTOIDLE2);
+ cm_write_mod_reg((1 OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
+(1 OMAP3430_AUTO_CORE_DPLL_SHIFT),
+PLL_MOD,
+CM_AUTOIDLE);
+ cm_write_mod_reg(1 OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
+PLL_MOD,
+CM_AUTOIDLE2);
+
+ /* XXX Enable control of expternal oscillator through
+* sys_clkreq. I think
[PATCH 2/4] PM: Workaround for taking care of gpio clocks
In omap3 gpios 2-6 are in per domain. Functional clocks for these
should be disabled. This patch is needed until gpio driver disables
gpio clocks.
GPIO modules in PER domain are not able to act as a wake up source if
PER domain is in retention. PER domain sleep transition before MPU is
prevented by leaving icks active. PER domain still enters retention
together with MPU. When this happens IOPAD wake up mechanism is used
for gpios.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 54 +-
1 files changed, 53 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index f30fa9e..7d5d461 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -53,6 +53,36 @@ static void (*saved_idle)(void);
static struct powerdomain *mpu_pwrdm;
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+#define NUM_OF_PERGPIOS 5
+static struct clk *gpio_fcks[NUM_OF_PERGPIOS];
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void per_gpio_clk_enable(void)
+{
+ int i;
+ for (i = 1; i NUM_OF_PERGPIOS + 1; i++)
+ clk_enable(gpio_fcks[i-1]);
+}
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void per_gpio_clk_disable(void)
+{
+ int i;
+ for (i = 1; i NUM_OF_PERGPIOS + 1; i++)
+ clk_disable(gpio_fcks[i-1]);
+}
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void gpio_fclk_mask(u32 *fclk)
+{
+ *fclk = ~(0x1f 13);
+}
+
/* PRCM Interrupt Handler for wakeups */
static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
{
@@ -169,8 +199,18 @@ static void omap_sram_idle(void)
omap2_gpio_prepare_for_retention();
+ /* XXX This is for gpio fclk hack. Will be removed as gpio driver
+* handles fcks correctly */
+ if (clocks_off_while_idle)
+ per_gpio_clk_disable();
+
_omap_sram_idle(NULL, save_state);
+ /* XXX This is for gpio fclk hack. Will be removed as gpio driver
+* handles fcks correctly */
+ if (clocks_off_while_idle)
+ per_gpio_clk_enable();
+
omap2_gpio_resume_after_retention();
}
@@ -200,6 +240,10 @@ static int omap3_fclks_active(void)
CM_FCLKEN);
fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
CM_FCLKEN);
+
+ if (clocks_off_while_idle)
+ gpio_fclk_mask(fck_per);
+
if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
fck_cam | fck_per | fck_usbhost)
return 1;
@@ -418,7 +462,8 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm)
int __init omap3_pm_init(void)
{
struct power_state *pwrst;
- int ret;
+ char clk_name[11];
+ int ret, i;
printk(KERN_ERR Power Management for TI OMAP3.\n);
@@ -454,6 +499,13 @@ int __init omap3_pm_init(void)
pm_idle = omap3_pm_idle;
+ /* XXX This is for gpio fclk hack. Will be removed as gpio driver
+* handles fcks correctly */
+ for (i = 1; i NUM_OF_PERGPIOS + 1; i++) {
+ sprintf(clk_name, gpio%d_fck, i + 1);
+ gpio_fcks[i-1] = clk_get(NULL, clk_name);
+ }
+
err1:
return ret;
err2:
--
1.5.5
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[PATCH] OMAP: DISPC: Fix to disable also interface clocks.
Leaving interface clocks enabled causes dss pwrdm to stay in active
state when mpu is in active state. This fix puts dss to sleep state
when it is not needed.
Earlier version broke framebuffer on 24xx. This is fixed by enabling
clocks before trying to access DISPC_IRQSTATUS register.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
drivers/video/omap/dispc.c | 23 ++-
1 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
index 3d64314..99bf355 100644
--- a/drivers/video/omap/dispc.c
+++ b/drivers/video/omap/dispc.c
@@ -858,8 +858,11 @@ EXPORT_SYMBOL(omap_dispc_free_irq);
static irqreturn_t omap_dispc_irq_handler(int irq, void *dev)
{
- u32 stat = dispc_read_reg(DISPC_IRQSTATUS);
+ u32 stat;
+ enable_lcd_clocks(1);
+
+ stat = dispc_read_reg(DISPC_IRQSTATUS);
if (stat DISPC_IRQ_FRAMEMASK)
complete(dispc.frame_done);
@@ -875,6 +878,8 @@ static irqreturn_t omap_dispc_irq_handler(int irq, void
*dev)
dispc_write_reg(DISPC_IRQSTATUS, stat);
+ enable_lcd_clocks(0);
+
return IRQ_HANDLED;
}
@@ -915,18 +920,13 @@ static void put_dss_clocks(void)
static void enable_lcd_clocks(int enable)
{
- if (enable)
+ if (enable) {
+ clk_enable(dispc.dss_ick);
clk_enable(dispc.dss1_fck);
- else
+ } else {
clk_disable(dispc.dss1_fck);
-}
-
-static void enable_interface_clocks(int enable)
-{
- if (enable)
- clk_enable(dispc.dss_ick);
- else
clk_disable(dispc.dss_ick);
+ }
}
static void enable_digit_clocks(int enable)
@@ -1362,7 +1362,6 @@ static int omap_dispc_init(struct omapfb_device *fbdev,
int ext_mode,
if ((r = get_dss_clocks()) 0)
return r;
- enable_interface_clocks(1);
enable_lcd_clocks(1);
#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
@@ -1466,7 +1465,6 @@ fail2:
free_irq(INT_24XX_DSS_IRQ, fbdev);
fail1:
enable_lcd_clocks(0);
- enable_interface_clocks(0);
put_dss_clocks();
return r;
@@ -1483,7 +1481,6 @@ static void omap_dispc_cleanup(void)
cleanup_fbmem();
free_palette_ram();
free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
- enable_interface_clocks(0);
put_dss_clocks();
}
--
1.5.5
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[PATCH] OMAP: DISPC: Enable dispc wake up capability
Without wakeup enable omap doesn't wake up on dispc interrupts. This causes problems in a case where mpu is in sleep state and dispc interrupt fires. Signed-off-by: Jouni Hogander [EMAIL PROTECTED] --- drivers/video/omap/dispc.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c index 3d64314..d232ea9 100644 --- a/drivers/video/omap/dispc.c +++ b/drivers/video/omap/dispc.c @@ -1393,10 +1393,10 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode, enable_digit_clocks(0); } - /* Enable smart idle and autoidle */ + /* Enable smart standby/idle, autoidle and wakeup */ l = dispc_read_reg(DISPC_SYSCONFIG); l = ~((3 12) | (3 3)); - l |= (2 12) | (2 3) | (1 0); + l |= (2 12) | (2 3) | (1 2) | (1 0); dispc_write_reg(DISPC_SYSCONFIG, l); omap_writel(1 0, DSS_BASE + DSS_SYSCONFIG); -- 1.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC] OMAP3: CPUIDLE PM: Fix slow serial-console
This patch fixes slowness on serial console. This patch superseeds
OMAP3: CPUIDLE PM: check_bm fix.
---
arch/arm/mach-omap2/cpuidle34xx.c |3 ++-
arch/arm/mach-omap2/pm34xx.c |2 --
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index c14152f..b227d9b 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -30,6 +30,7 @@
#include asm/arch/gpio.h
#include asm/arch/gpmc.h
#include asm/arch/control.h
+#include asm/arch/common.h
#include linux/sched.h
#include cpuidle34xx.h
#include cm.h
@@ -430,7 +431,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
current_cx_state = *cx;
- if (cx-type == OMAP3_STATE_C0) {
+ if (cx-type == OMAP3_STATE_C0 || !omap_serial_can_sleep()) {
/* Do nothing for C0, not even a wfi */
return 0;
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 9f73e5c..9bb0fba 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -385,8 +385,6 @@ int omap3_can_sleep(void)
return 0;
if (atomic_read(sleep_block) 0)
return 0;
- if (!omap_serial_can_sleep())
- return 0;
return 1;
}
--
1.5.5
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[RFC] OMAP3: CPUIDLE PM: Modifications and fixes
With this patch cpuidle boot problem with cpuidle doesn't exist. Also hang on
wake-up seems to
disappear (haven't seen this far).
Main points in this patch are:
1. Add wkdep between neon and mpu
2. Add wkdep between per and core
3. Deny hwsup mode before writing next pwrst state
3. Make sure that order in idle loop is such that clocks are _really_
enabled before accessing registers (serial gpio).
This patch is meant to be applied on top of OMAP3 CPUidle patches
patch set and OMAP3 CPUidle patches - fixes patch sent by Rajendra
Nayak.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/cpuidle34xx.c | 82 ++--
arch/arm/mach-omap2/pm34xx.c | 109 +++--
2 files changed, 108 insertions(+), 83 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index 6440515..c14152f 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -404,8 +404,6 @@ void omap3_save_core_ctx(void)
omap_save_gpmc_ctx();
/* Save the system control module context, padconf already save above*/
omap_save_control_ctx();
- omap_save_uart_ctx(0);
- omap_save_uart_ctx(1);
}
void omap3_restore_core_ctx(void)
@@ -416,11 +414,10 @@ void omap3_restore_core_ctx(void)
omap_restore_gpmc_ctx();
/* Restore the interrupt controller context */
omap_restore_intc_ctx();
- omap_restore_uart_ctx(0);
- omap_restore_uart_ctx(1);
padconf_saved = 0;
}
+int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
/* omap3_enter_idle - Programs OMAP3 to enter the specified state.
* returns the total time during which the system was idle.
*/
@@ -429,8 +426,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
{
struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
struct timespec ts_preidle, ts_postidle, ts_idle;
- struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;
- int per_pwrst, neon_pwrst;
+ struct powerdomain *mpu_pd, *core_pd;
current_cx_state = *cx;
@@ -450,49 +446,9 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
mpu_pd = pwrdm_lookup(mpu_pwrdm);
core_pd = pwrdm_lookup(core_pwrdm);
- per_pd = pwrdm_lookup(per_pwrdm);
- neon_pd = pwrdm_lookup(neon_pwrdm);
-
- /* Reset previous power state registers */
- pwrdm_clear_all_prev_pwrst(mpu_pd);
- pwrdm_clear_all_prev_pwrst(neon_pd);
- pwrdm_clear_all_prev_pwrst(core_pd);
- pwrdm_clear_all_prev_pwrst(per_pd);
-
- per_pwrst = pwrdm_read_pwrst(per_pd);
- neon_pwrst = pwrdm_read_pwrst(neon_pd);
-
- /* Do this before any changes to PRCM registers */
- if (cx-core_state == PWRDM_POWER_OFF)
- omap3_save_prcm_ctx();
-
- /* Program MPU to target state */
- if (cx-mpu_state PWRDM_POWER_ON) {
- pwrdm_set_next_pwrst(neon_pd, cx-mpu_state);
- pwrdm_set_next_pwrst(mpu_pd, cx-mpu_state);
- }
- /* Program CORE and PER to target state */
- if (cx-core_state PWRDM_POWER_ON) {
- omap2_gpio_prepare_for_retention();
- if (clocks_off_while_idle) {
- omap3_save_per_ctx();
- per_gpio_clk_disable();
- omap_save_uart_ctx(2);
- omap_serial_enable_clocks(0, 2);
- }
- if (cx-core_state == PWRDM_POWER_OFF)
- omap3_save_core_ctx();
- /* Disable UART1/UART2 clocks here. Done using direct register
- * writes as using clock f/w calls results in a hang in prcm_
- * interrupt_handler trying to clear WKST for CORE
- */
- cm_clear_mod_reg_bits(0x6000, CORE_MOD, CM_ICLKEN1);
- cm_clear_mod_reg_bits(0x6000, CORE_MOD, CM_FCLKEN1);
- pwrdm_set_next_pwrst(core_pd, cx-core_state);
- }
-
- *(scratchpad_restore_addr) = restore_pointer_address;
+set_pwrdm_state(mpu_pd, cx-mpu_state);
+ set_pwrdm_state(core_pd, cx-core_state);
if (omap_irq_pending())
goto return_sleep_time;
@@ -500,34 +456,6 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
/* Execute ARM wfi */
omap_sram_idle();
- *(scratchpad_restore_addr) = 0x0;
-
- if (cx-core_state PWRDM_POWER_ON) {
- cm_set_mod_reg_bits(0x6000, CORE_MOD, CM_ICLKEN1);
- cm_set_mod_reg_bits(0x6000, CORE_MOD, CM_FCLKEN1);
- if ((cx-core_state == PWRDM_POWER_OFF)
-(pwrdm_read_prev_pwrst(core_pd) == PWRDM_POWER_OFF)) {
- omap3_restore_core_ctx();
- omap3_restore_prcm_ctx();
- omap3_restore_sram_ctx();
- }
- pwrdm_set_next_pwrst(core_pd
[RFC] OMAP3: CPUIDLE PM: Modifications and fixes. Suspend part.
With this suspend also works.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 32 ++--
1 files changed, 6 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 1f9c58a..9f73e5c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -503,29 +503,8 @@ static int omap3_pm_suspend(void)
goto restore;
}
- omap2_gpio_prepare_for_retention();
-
- if (clocks_off_while_idle) {
- omap_serial_enable_clocks(0, 0);
- omap_serial_enable_clocks(0, 1);
- omap_serial_enable_clocks(0, 2);
- /* XXX This is for gpio fclk hack. Will be removed as
-* gpio driver * handles fcks correctly */
- per_gpio_clk_disable();
- }
-
omap_sram_idle();
- if (clocks_off_while_idle) {
- omap_serial_enable_clocks(1, 0);
- omap_serial_enable_clocks(1, 1);
- omap_serial_enable_clocks(1, 2);
- /* XXX This is for gpio fclk hack. Will be removed as
-* gpio driver * handles fcks correctly */
- per_gpio_clk_enable();
- }
-
- omap2_gpio_resume_after_retention();
restore:
/* Restore next_pwrsts */
list_for_each_entry(pwrst, pwrst_list, node) {
@@ -748,16 +727,17 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm)
if (!pwrst)
return -ENOMEM;
pwrst-pwrdm = pwrdm;
- if (!strcmp(pwrst-pwrdm-name, core_pwrdm) ||
!strcmp(pwrst-pwrdm-name, mpu_pwrdm) || !strcmp(pwrst-pwrdm-name,
mpu_pwrdm))
- pwrst-next_state = PWRDM_POWER_ON;
- else
- pwrst-next_state = PWRDM_POWER_OFF;
+ pwrst-next_state = PWRDM_POWER_OFF;
list_add(pwrst-node, pwrst_list);
if (pwrdm_has_hdwr_sar(pwrdm))
pwrdm_enable_hdwr_sar(pwrdm);
- return set_pwrdm_state(pwrst-pwrdm, pwrst-next_state);
+ if (!strcmp(pwrst-pwrdm-name, core_pwrdm) ||
!strcmp(pwrst-pwrdm-name, mpu_pwrdm) ||
+ !strcmp(pwrst-pwrdm-name, mpu_pwrdm))
+ return set_pwrdm_state(pwrst-pwrdm, PWRDM_POWER_ON);
+ else
+ return set_pwrdm_state(pwrst-pwrdm, pwrst-next_state);
}
void omap_push_sram_idle()
--
1.5.5
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[PATCH] OMAP: DISPC: Fix to disable also interface clocks
Leaving interface clocks enabled causes dss pwrdm to stay in active
state when mpu is in active state. This fix puts dss to sleep state
when it is not needed.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
drivers/video/omap/dispc.c | 17 +
1 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
index 6aff476..ad436f5 100644
--- a/drivers/video/omap/dispc.c
+++ b/drivers/video/omap/dispc.c
@@ -914,18 +914,14 @@ static void put_dss_clocks(void)
static void enable_lcd_clocks(int enable)
{
- if (enable)
+ if (enable) {
+ clk_enable(dispc.dss_ick);
clk_enable(dispc.dss1_fck);
- else
+ }
+ else {
clk_disable(dispc.dss1_fck);
-}
-
-static void enable_interface_clocks(int enable)
-{
- if (enable)
- clk_enable(dispc.dss_ick);
- else
clk_disable(dispc.dss_ick);
+ }
}
static void enable_digit_clocks(int enable)
@@ -1361,7 +1357,6 @@ static int omap_dispc_init(struct omapfb_device *fbdev,
int ext_mode,
if ((r = get_dss_clocks()) 0)
return r;
- enable_interface_clocks(1);
enable_lcd_clocks(1);
#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
@@ -1465,7 +1460,6 @@ fail2:
free_irq(INT_24XX_DSS_IRQ, fbdev);
fail1:
enable_lcd_clocks(0);
- enable_interface_clocks(0);
put_dss_clocks();
return r;
@@ -1482,7 +1476,6 @@ static void omap_dispc_cleanup(void)
cleanup_fbmem();
free_palette_ram();
free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
- enable_interface_clocks(0);
put_dss_clocks();
}
--
1.5.5
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[PATCH 3/6] OMAP: PM: Add new sysfs option for disabling clocks when entering idle
There are drivers that are not disabling their clocks (gpio
uart). These clocks need to be disabled if retention/off state is
wanted when idling. Before disabling them in idle loop this option
needs to be checked.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm.c | 37 +++--
arch/arm/mach-omap2/pm.h |1 +
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index bef58d7..b7434df 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -31,30 +31,51 @@
#include pm.h
unsigned short enable_dyn_sleep;
+unsigned short clocks_off_while_idle;
atomic_t sleep_block = ATOMIC_INIT(0);
+static ssize_t idle_show(struct kobject *, struct kobj_attribute *, char *);
+static ssize_t idle_store(struct kobject *k, struct kobj_attribute *,
+ const char *buf, size_t n);
+
+static struct kobj_attribute sleep_while_idle_attr =
+ __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
+
+static struct kobj_attribute clocks_off_while_idle_attr =
+ __ATTR(clocks_off_while_idle, 0644, idle_show, idle_store);
+
static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
char *buf)
{
- return sprintf(buf, %hu\n, enable_dyn_sleep);
+ if (attr == sleep_while_idle_attr)
+ return sprintf(buf, %hu\n, enable_dyn_sleep);
+ else if (attr == clocks_off_while_idle_attr)
+ return sprintf(buf, %hu\n, clocks_off_while_idle);
+ else
+ return -EINVAL;
}
static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
const char *buf, size_t n)
{
unsigned short value;
+
if (sscanf(buf, %hu, value) != 1 ||
(value != 0 value != 1)) {
- printk(KERN_ERR idle_sleep_store: Invalid value\n);
+ printk(KERN_ERR idle_store: Invalid value\n);
return -EINVAL;
}
- enable_dyn_sleep = value;
+
+ if (attr == sleep_while_idle_attr)
+ enable_dyn_sleep = value;
+ else if (attr == clocks_off_while_idle_attr)
+ clocks_off_while_idle = value;
+ else
+ return -EINVAL;
+
return n;
}
-static struct kobj_attribute sleep_while_idle_attr =
- __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
-
void omap2_block_sleep(void)
{
atomic_inc(sleep_block);
@@ -86,6 +107,10 @@ int __init omap_pm_init(void)
error = sysfs_create_file(power_kobj, sleep_while_idle_attr.attr);
if (error)
printk(KERN_ERR sysfs_create_file failed: %d\n, error);
+ error = sysfs_create_file(power_kobj,
+ clocks_off_while_idle_attr.attr);
+ if (error)
+ printk(KERN_ERR sysfs_create_file failed: %d\n, error);
return error;
}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 351456e..0aeb461 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -17,6 +17,7 @@ extern int omap2_pm_init(void);
extern int omap3_pm_init(void);
extern unsigned short enable_dyn_sleep;
+extern unsigned short clocks_off_while_idle;
extern atomic_t sleep_block;
#ifdef CONFIG_PM_DEBUG
--
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[PATCH 5/6] Added sleep support to UART
From: Tero Kristo [EMAIL PROTECTED]
UART usage (e.g. serial console) now denies sleep for 5 seconds. This
makes it possible to use serial console when dynamic idle is
enabled. Write 1 to /sys/power/clocks_off_while_sleep to enable uart
clock disable on idle. Without this omap won't enter retention.
Also moved code from pm-debug.c to serial.c, and made pm24xx.c use
this new implementation.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm-debug.c | 132
arch/arm/mach-omap2/pm.h |8 --
arch/arm/mach-omap2/pm24xx.c | 57 --
arch/arm/mach-omap2/pm34xx.c | 26 +--
arch/arm/mach-omap2/serial.c | 148
include/asm-arm/arch-omap/common.h |3 +
6 files changed, 204 insertions(+), 170 deletions(-)
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index a32f11f..61d4501 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -37,138 +37,6 @@
#ifdef CONFIG_PM_DEBUG
int omap2_pm_debug = 0;
-static int serial_console_clock_disabled;
-static int serial_console_uart;
-static unsigned int serial_console_next_disable;
-
-static struct clk *console_iclk, *console_fclk;
-
-static void serial_console_kick(void)
-{
- serial_console_next_disable = omap2_read_32k_sync_counter();
- /* Keep the clocks on for 4 secs */
- serial_console_next_disable += 4 * 32768;
-}
-
-static void serial_wait_tx(void)
-{
- static const unsigned long uart_bases[3] = {
- 0x4806a000, 0x4806c000, 0x4806e000
- };
- unsigned long lsr_reg;
- int looped = 0;
-
- /* Wait for TX FIFO and THR to get empty */
- lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 2));
- while ((__raw_readb(lsr_reg) 0x60) != 0x60)
- looped = 1;
- if (looped)
- serial_console_kick();
-}
-
-u32 omap2_read_32k_sync_counter(void)
-{
-return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
-}
-
-void serial_console_fclk_mask(u32 *f1, u32 *f2)
-{
- switch (serial_console_uart) {
- case 1:
- *f1 = ~(1 21);
- break;
- case 2:
- *f1 = ~(1 22);
- break;
- case 3:
- *f2 = ~(1 2);
- break;
- }
-}
-
-void serial_console_sleep(int enable)
-{
- if (console_iclk == NULL || console_fclk == NULL)
- return;
-
- if (enable) {
- BUG_ON(serial_console_clock_disabled);
- if (clk_get_usecount(console_fclk) == 0)
- return;
- if ((int) serial_console_next_disable - (int)
omap2_read_32k_sync_counter() = 0)
- return;
- serial_wait_tx();
- clk_disable(console_iclk);
- clk_disable(console_fclk);
- serial_console_clock_disabled = 1;
- } else {
- int serial_wakeup = 0;
- u32 l;
-
- switch (serial_console_uart) {
- case 1:
- l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (l OMAP24XX_ST_UART1)
- serial_wakeup = 1;
- break;
- case 2:
- l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (l OMAP24XX_ST_UART2)
- serial_wakeup = 1;
- break;
- case 3:
- l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
- if (l OMAP24XX_ST_UART3)
- serial_wakeup = 1;
- break;
- }
- if (serial_wakeup)
- serial_console_kick();
- if (!serial_console_clock_disabled)
- return;
- clk_enable(console_iclk);
- clk_enable(console_fclk);
- serial_console_clock_disabled = 0;
- }
-}
-
-void pm_init_serial_console(void)
-{
- const struct omap_serial_console_config *conf;
- char name[16];
-
- conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
- struct omap_serial_console_config);
- if (conf == NULL)
- return;
- if (conf-console_uart 3 || conf-console_uart 1)
- return;
- serial_console_uart = conf-console_uart;
- sprintf(name, uart%d_fck, conf-console_uart);
- console_fclk = clk_get(NULL, name);
- if (IS_ERR(console_fclk))
- console_fclk = NULL;
- name[6] = 'i';
- console_iclk = clk_get(NULL, name);
- if (IS_ERR(console_fclk))
- console_iclk = NULL;
- if (console_fclk == NULL || console_iclk == NULL) {
- serial_console_uart = 0;
- return
[PATCH 2/6] 34XX: PM: Workaround to check wether any fck is active before entering sleep
This workaround shouldn't be needed when all drivers are configuring
their sysconfig registers properly and using their clocks properly.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 31 +++
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 449e7b5..92e56cd 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -174,10 +174,41 @@ static void omap_sram_idle(void)
omap2_gpio_resume_after_retention();
}
+static int omap3_fclks_active(void)
+{
+ u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
+ fck_cam = 0, fck_per = 0, fck_usbhost = 0;
+
+ fck_core1 = cm_read_mod_reg(CORE_MOD,
+ CM_FCLKEN1);
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ fck_core3 = cm_read_mod_reg(CORE_MOD,
+ OMAP3430ES2_CM_FCLKEN3);
+ fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+ CM_FCLKEN);
+ fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+ CM_FCLKEN);
+ } else
+ fck_sgx = cm_read_mod_reg(GFX_MOD,
+ OMAP3430ES2_CM_FCLKEN3);
+ fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
+ CM_FCLKEN);
+ fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
+ CM_FCLKEN);
+ fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
+ CM_FCLKEN);
+ if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
+ fck_cam | fck_per | fck_usbhost)
+ return 1;
+ return 0;
+}
+
static int omap3_can_sleep(void)
{
if (!enable_dyn_sleep)
return 0;
+ if (omap3_fclks_active())
+ return 0;
if (atomic_read(sleep_block) 0)
return 0;
return 1;
--
1.5.5
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[PATCH 4/6] 34XX: PM: Workaround for taking care of gpio clocks
In omap3 gpios 2-6 are in per domain. Functional clocks for these
should be disabled. This patch is needed until gpio driver disables
gpio clocks.
GPIO modules in PER domain are not able to act as a wake up source if
PER domain is in retention. PER domain sleep transition before MPU is
prevented by leaving icks active. PER domain still enters retention
together with MPU. When this happens IOPAD wake up mechanism is used
for gpios.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 58 +++--
1 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 92e56cd..2b7ca5f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -47,12 +47,42 @@ struct power_state {
static LIST_HEAD(pwrst_list);
-void (*_omap_sram_idle)(u32 *addr, int save_state);
+void (*_omap_sram_idle)(u32 *addr, int save_state, int disable_clocks);
static void (*saved_idle)(void);
static struct powerdomain *mpu_pwrdm;
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+#define NUM_OF_PERGPIOS 5
+static struct clk *gpio_fcks[NUM_OF_PERGPIOS];
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void per_gpio_clk_enable(void)
+{
+ int i;
+ for (i = 1; i NUM_OF_PERGPIOS + 1; i++)
+ clk_enable(gpio_fcks[i-1]);
+}
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void per_gpio_clk_disable(void)
+{
+ int i;
+ for (i = 1; i NUM_OF_PERGPIOS + 1; i++)
+ clk_disable(gpio_fcks[i-1]);
+}
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void gpio_fclk_mask(u32 *fclk)
+{
+ *fclk = ~(0x1f 13);
+}
+
/* PRCM Interrupt Handler for wakeups */
static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
{
@@ -169,7 +199,17 @@ static void omap_sram_idle(void)
omap2_gpio_prepare_for_retention();
- _omap_sram_idle(NULL, save_state);
+ /* XXX This is for gpio fclk hack. Will be removed as gpio driver
+* handles fcks correctly */
+ if (clocks_off_while_idle)
+ per_gpio_clk_disable();
+
+ _omap_sram_idle(NULL, save_state, clocks_off_while_idle);
+
+ /* XXX This is for gpio fclk hack. Will be removed as gpio driver
+* handles fcks correctly */
+ if (clocks_off_while_idle)
+ per_gpio_clk_enable();
omap2_gpio_resume_after_retention();
}
@@ -197,6 +237,10 @@ static int omap3_fclks_active(void)
CM_FCLKEN);
fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
CM_FCLKEN);
+
+ if (clocks_off_while_idle)
+ gpio_fclk_mask(fck_per);
+
if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
fck_cam | fck_per | fck_usbhost)
return 1;
@@ -412,7 +456,8 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm)
int __init omap3_pm_init(void)
{
struct power_state *pwrst;
- int ret;
+ char clk_name[11];
+ int ret, i;
printk(KERN_ERR Power Management for TI OMAP3.\n);
@@ -448,6 +493,13 @@ int __init omap3_pm_init(void)
pm_idle = omap3_pm_idle;
+ /* XXX This is for gpio fclk hack. Will be removed as gpio driver
+* handles fcks correctly */
+ for (i = 1; i NUM_OF_PERGPIOS + 1; i++) {
+ sprintf(clk_name, gpio%d_fck, i + 1);
+ gpio_fcks[i-1] = clk_get(NULL, clk_name);
+ }
+
err1:
return ret;
err2:
--
1.5.5
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[PATCH 1/6] 34XX: PM: Workaround to reset all wkdeps
This workaround is needed until powerdomain code resets wkdeps.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 20 ++--
1 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 202c269..449e7b5 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -332,6 +332,20 @@ static struct platform_suspend_ops omap_pm_ops = {
static void __init prcm_setup_regs(void)
{
+ /* XXX Reset all wkdeps. This should be done when initializing
+* powerdomains */
+ prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
+ } else
+ prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
+
/* setup wakup source */
prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1,
WKUP_MOD, PM_WKEN);
@@ -371,6 +385,10 @@ int __init omap3_pm_init(void)
printk(KERN_ERR Power Management for TI OMAP3.\n);
+ /* XXX prcm_setup_regs needs to be before enabling hw
+* supervised mode for powerdomains */
+ prcm_setup_regs();
+
ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
(irq_handler_t)prcm_interrupt_handler,
IRQF_DISABLED, prcm, NULL);
@@ -397,8 +415,6 @@ int __init omap3_pm_init(void)
suspend_set_ops(omap_pm_ops);
- prcm_setup_regs();
-
pm_idle = omap3_pm_idle;
err1:
--
1.5.5
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[PATCH 0/7] 34XX: PM: Workarounds to get omap3 to retention 3rd.
Hi, This patch set contains all workarounds that are needed to get omap3 to retention. Also patch from Tero Kristo to get PM to work if using serial console is included in this set. Basically all patches in this set should be reverted one by one as correct fixes are implemented and applied. This patch set superseeds earlier version sent 2008-06-17 7:28:35. To get Omap into retention, this patch set still depends on: 1. ARCH: OMAP: MUSB: Do not block sleep (Felipe Balbi) 2. ARM: OMAP: SmartReflex driver: enable in omap_3430sdp_defconfig (Kalle Jokiniemi) 3. PRCM: 34XX: Fix wrong shift value used in dpll4_m4x2_ck enable bit 4. Patch which removes control of usbhost_sar_fck from clock tree (Paul Walmsley will send this soon) Test: 1. Apply dependency patches and workaround set on top of them 2. Enable disabling/enabling of gpio2-6 and uart clocks on idle: $ echo 1 /sys/power/clocks_off_while_idle 3. Try out static suspend: $ echo mem /sys/power/state Wake up from suspend by entering character to serial console. This should print out: Successfully put all powerdomains to target state 4. Try out dynamic sleep: $ echo 1 /sys/power/sleep_while_idle On Omap3430 SDP board VCORE_EN led can be used as an indicator. If it starts to blink after a while then Omap enters retention on idle. To make this work also display needs to be blanked. -- Jouni Högander -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/7] 34XX: PM: Workaround to reset all wkdeps
This workaround is needed until powerdomain code resets wkdeps.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 20 ++--
1 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2dccd0b..dc2e57d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -332,6 +332,20 @@ static struct platform_suspend_ops omap_pm_ops = {
static void __init prcm_setup_regs(void)
{
+ /* XXX Reset all wkdeps. This should be done when initializing
+* powerdomains */
+ prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
+ } else
+ prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
+
/* XXX Enable interface clock autoidle for all modules. This
* should be done by clockfw */
cm_write_mod_reg(
@@ -487,6 +501,10 @@ int __init omap3_pm_init(void)
printk(KERN_ERR Power Management for TI OMAP3.\n);
+ /* XXX prcm_setup_regs needs to be before enabling hw
+* supervised mode for powerdomains */
+ prcm_setup_regs();
+
ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
(irq_handler_t)prcm_interrupt_handler,
IRQF_DISABLED, prcm, NULL);
@@ -513,8 +531,6 @@ int __init omap3_pm_init(void)
suspend_set_ops(omap_pm_ops);
- prcm_setup_regs();
-
pm_idle = omap3_pm_idle;
err1:
--
1.5.5
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[PATCH 1/7] 34XX: PM: Workaround to build omap hsmmc as a module
Current omap hsmmc driver is not pm friendly. Build it as a module because it prevents omap3 retention. Signed-off-by: Jouni Hogander [EMAIL PROTECTED] --- arch/arm/configs/omap_3430sdp_defconfig |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig index 947c25f..5672a6e 100644 --- a/arch/arm/configs/omap_3430sdp_defconfig +++ b/arch/arm/configs/omap_3430sdp_defconfig @@ -1058,7 +1058,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y # # MMC/SD Host Controller Drivers # -CONFIG_MMC_OMAP_HS=y +CONFIG_MMC_OMAP_HS=m # CONFIG_MMC_SPI is not set # CONFIG_NEW_LEDS is not set CONFIG_RTC_LIB=y -- 1.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 6/7] 34XX: PM: Workaround for taking care of gpio clocks
In omap3 gpios 2-6 are in per domain. Clocks for these should be
disabled. This patch is needed until gpio driver disables gpio clocks.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c| 15 +++-
arch/arm/mach-omap2/sleep34xx.S | 74 +++
2 files changed, 87 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index edde254..9c7b7be 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -47,12 +47,19 @@ struct power_state {
static LIST_HEAD(pwrst_list);
-void (*_omap_sram_idle)(u32 *addr, int save_state);
+void (*_omap_sram_idle)(u32 *addr, int save_state, int disable_clocks);
static void (*saved_idle)(void);
static struct powerdomain *mpu_pwrdm;
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void gpio_fclk_mask(u32 *fclk)
+{
+ *fclk = ~(0x1f 13);
+}
+
/* PRCM Interrupt Handler for wakeups */
static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
{
@@ -169,7 +176,7 @@ static void omap_sram_idle(void)
omap2_gpio_prepare_for_retention();
- _omap_sram_idle(NULL, save_state);
+ _omap_sram_idle(NULL, save_state, clocks_off_while_idle);
omap2_gpio_resume_after_retention();
}
@@ -197,6 +204,10 @@ static int omap3_fclks_active(void)
CM_FCLKEN);
fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
CM_FCLKEN);
+
+ if (clocks_off_while_idle)
+ gpio_fclk_mask(fck_per);
+
if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
fck_cam | fck_per | fck_usbhost)
return 1;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index ebc7eb3..1f7009a 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -32,6 +32,8 @@
#include prm.h
#include sdrc.h
+#include cm.h
+#include cm-regbits-34xx.h
#define PM_PREPWSTST_CORE_VOMAP34XX_PRM_REGADDR(CORE_MOD, \
OMAP3430_PM_PREPWSTST)
@@ -45,6 +47,15 @@
SCRATCHPAD_MEM_OFFS)
#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
+/* XXX gpio fclk workaround */
+#define CM_FCLKEN_PER_VOMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, \
+ CM_FCLKEN)
+#define CM_FCLKEN_PER_Pio_v2p(CM_FCLKEN_PER_V)
+
+#define GPIO_FCLK_MASK OMAP3430_EN_GPIO6 | OMAP3430_EN_GPIO5 | \
+ OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO3 | \
+ OMAP3430_EN_GPIO2
+
.text
/* Function call to get the restore pointer for resume from OFF */
ENTRY(get_restore_pointer)
@@ -68,14 +79,41 @@ loop:
/*b loop*/ @Enable to debug by stepping through code
/* r0 contains restore pointer in sdram */
/* r1 contains information about saving context */
+ /* r2 contains information whether clocks should be disabled */
ldr r4, sdrc_power @ read the SDRC_POWER register
ldr r5, [r4]@ read the contents of SDRC_POWER
orr r5, r5, #0x40 @ enable self refresh on idle req
str r5, [r4]@ write back to SDRC_POWER register
+ /* XXX gpio fclk workaround */
+ /* Check if per fclken needs to be saved */
+ cmp r2, #0x0
+ beq skip_per_fclken_save
+
+ /* XXX gpio fclk workaround */
+ /* Save current value of per fclken reg */
+ ldr r4, cm_fclken_per_v
+ ldr r5, [r4]
+ str r5, cm_fclken_per_val
+skip_per_fclken_save:
+
cmp r1, #0x0
/* If context save is required, do that and execute wfi */
bne save_context_wfi
+
+ /* XXX gpio fclk workaround */
+ /* Check if gpio clocks needs to be disabled */
+ ldr r5, cm_fclken_per_val
+ cmp r5, #0x0
+ beq skip_gpio_clk_disable
+
+ /* XXX gpio fclk workaround */
+ /* Disable gpio clocks */
+ ldr r4, cm_fclken_per_v
+ bic r5, r5, #GPIO_FCLK_MASK
+ str r5, [r4]
+skip_gpio_clk_disable:
+
/* Data memory barrier and Data sync barrier */
mov r1, #0
mcr p15, 0, r1, c7, c10, 4
@@ -93,6 +131,14 @@ loop:
nop
nop
nop
+
+ /* XXX gpio fclk workaround */
+ ldr r5, cm_fclken_per_val
+ cmp r5, #0x0
+ beq skip_per_fclken_restore
+ str r5, [r4]
+skip_per_fclken_restore:
+
bl i_dll_wait
ldmfd sp!, {r0-r12, pc} @ restore regs and return
@@ -483,6 +529,20 @@ finished:
mcr p15, 2, r10, c0, c0, 0
isb
skip_l2_inval:
+
+ /* XXX gpio fclk workaround */
+ /* Check if gpio clocks needs to be disabled */
+ ldr
[PATCH 2/7] 34XX: PM: Workaround to enable autoidle for clocks and plls
This workaround enables autoidle for interface clocks and plls. Also
automatic control of external oscillator through sys_clkreq is
enabled. I think these should be done by clockfw.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 120 ++
1 files changed, 120 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c7493f5..2dccd0b 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -332,6 +332,126 @@ static struct platform_suspend_ops omap_pm_ops = {
static void __init prcm_setup_regs(void)
{
+ /* XXX Enable interface clock autoidle for all modules. This
+* should be done by clockfw */
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_MMC3 |
+ OMAP3430ES2_AUTO_ICR |
+ OMAP3430_AUTO_AES2 |
+ OMAP3430_AUTO_SHA12 |
+ OMAP3430_AUTO_DES2 |
+ OMAP3430_AUTO_MMC2 |
+ OMAP3430_AUTO_MMC1 |
+ OMAP3430_AUTO_MSPRO |
+ OMAP3430_AUTO_HDQ |
+ OMAP3430_AUTO_MCSPI4 |
+ OMAP3430_AUTO_MCSPI3 |
+ OMAP3430_AUTO_MCSPI2 |
+ OMAP3430_AUTO_MCSPI1 |
+ OMAP3430_AUTO_I2C3 |
+ OMAP3430_AUTO_I2C2 |
+ OMAP3430_AUTO_I2C1 |
+ OMAP3430_AUTO_UART2 |
+ OMAP3430_AUTO_UART1 |
+ OMAP3430_AUTO_GPT11 |
+ OMAP3430_AUTO_GPT10 |
+ OMAP3430_AUTO_MCBSP5 |
+ OMAP3430_AUTO_MCBSP1 |
+ OMAP3430ES1_AUTO_FAC | /* This is es1 only */
+ OMAP3430_AUTO_MAILBOXES |
+ OMAP3430_AUTO_OMAPCTRL |
+ OMAP3430ES1_AUTO_FSHOSTUSB |
+ OMAP3430_AUTO_HSOTGUSB |
+ OMAP3430ES1_AUTO_D2D | /* This is es1 only */
+ OMAP3430_AUTO_SSI,
+ CORE_MOD, CM_AUTOIDLE1);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_PKA |
+ OMAP3430_AUTO_AES1 |
+ OMAP3430_AUTO_RNG |
+ OMAP3430_AUTO_SHA11 |
+ OMAP3430_AUTO_DES1,
+ CORE_MOD, CM_AUTOIDLE2);
+
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_USBTLL,
+ CORE_MOD, CM_AUTOIDLE3);
+ }
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_WDT2 |
+ OMAP3430_AUTO_WDT1 |
+ OMAP3430_AUTO_GPIO1 |
+ OMAP3430_AUTO_32KSYNC |
+ OMAP3430_AUTO_GPT12 |
+ OMAP3430_AUTO_GPT1 ,
+ WKUP_MOD, CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_DSS,
+ OMAP3430_DSS_MOD,
+ CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_CAM,
+ OMAP3430_CAM_MOD,
+ CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_GPIO6 |
+ OMAP3430_AUTO_GPIO5 |
+ OMAP3430_AUTO_GPIO4 |
+ OMAP3430_AUTO_GPIO3 |
+ OMAP3430_AUTO_GPIO2 |
+ OMAP3430_AUTO_WDT3 |
+ OMAP3430_AUTO_UART3 |
+ OMAP3430_AUTO_GPT9 |
+ OMAP3430_AUTO_GPT8 |
+ OMAP3430_AUTO_GPT7 |
+ OMAP3430_AUTO_GPT6 |
+ OMAP3430_AUTO_GPT5 |
+ OMAP3430_AUTO_GPT4 |
+ OMAP3430_AUTO_GPT3 |
+ OMAP3430_AUTO_GPT2 |
+ OMAP3430_AUTO_MCBSP4 |
+ OMAP3430_AUTO_MCBSP3 |
+ OMAP3430_AUTO_MCBSP2,
+ OMAP3430_PER_MOD,
+ CM_AUTOIDLE);
+
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_USBHOST,
+ OMAP3430ES2_USBHOST_MOD,
+ CM_AUTOIDLE);
+ }
+
+ /* XXX Set all plls to autoidle. This is needed until autoidle is
+* enabled by clockfw */
+ cm_write_mod_reg(1 OMAP3430_CLKTRCTRL_IVA2_SHIFT,
+OMAP3430_IVA2_MOD,
+CM_AUTOIDLE2);
+ cm_write_mod_reg(1 OMAP3430_AUTO_MPU_DPLL_SHIFT,
+MPU_MOD,
+CM_AUTOIDLE2);
+ cm_write_mod_reg((1 OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
+(1 OMAP3430_AUTO_CORE_DPLL_SHIFT),
+PLL_MOD,
+CM_AUTOIDLE);
+ cm_write_mod_reg(1 OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
+PLL_MOD,
+CM_AUTOIDLE2);
+
+ /* XXX Enable control of expternal oscillator through
+* sys_clkreq. I think clockfw should provide means to do this
+*/
+ prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
+1 OMAP_AUTOEXTCLKMODE_SHIFT
[PATCH 4/7] 34XX: PM: Workaround to check wether any fck is active before entering sleep
This workaround shouldn't be needed when all drivers are configuring
their sysconfig registers properly and using their clocks properly.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 31 +++
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index dc2e57d..edde254 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -174,10 +174,41 @@ static void omap_sram_idle(void)
omap2_gpio_resume_after_retention();
}
+static int omap3_fclks_active(void)
+{
+ u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
+ fck_cam = 0, fck_per = 0, fck_usbhost = 0;
+
+ fck_core1 = cm_read_mod_reg(CORE_MOD,
+ CM_FCLKEN1);
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ fck_core3 = cm_read_mod_reg(CORE_MOD,
+ OMAP3430ES2_CM_FCLKEN3);
+ fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+ CM_FCLKEN);
+ fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+ CM_FCLKEN);
+ } else
+ fck_sgx = cm_read_mod_reg(GFX_MOD,
+ OMAP3430ES2_CM_FCLKEN3);
+ fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
+ CM_FCLKEN);
+ fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
+ CM_FCLKEN);
+ fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
+ CM_FCLKEN);
+ if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
+ fck_cam | fck_per | fck_usbhost)
+ return 1;
+ return 0;
+}
+
static int omap3_can_sleep(void)
{
if (!enable_dyn_sleep)
return 0;
+ if (omap3_fclks_active())
+ return 0;
if (atomic_read(sleep_block) 0)
return 0;
return 1;
--
1.5.5
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[PATCH 5/7] OMAP: PM: Add new sysfs option for disabling clocks when entering idle
There are drivers that are not disabling their clocks (gpio
uart). These clocks need to be disabled if retention/off state is
wanted when idling. Before disabling them in idle loop this option
needs to be checked.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm.c | 37 +++--
arch/arm/mach-omap2/pm.h |1 +
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index bef58d7..b7434df 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -31,30 +31,51 @@
#include pm.h
unsigned short enable_dyn_sleep;
+unsigned short clocks_off_while_idle;
atomic_t sleep_block = ATOMIC_INIT(0);
+static ssize_t idle_show(struct kobject *, struct kobj_attribute *, char *);
+static ssize_t idle_store(struct kobject *k, struct kobj_attribute *,
+ const char *buf, size_t n);
+
+static struct kobj_attribute sleep_while_idle_attr =
+ __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
+
+static struct kobj_attribute clocks_off_while_idle_attr =
+ __ATTR(clocks_off_while_idle, 0644, idle_show, idle_store);
+
static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
char *buf)
{
- return sprintf(buf, %hu\n, enable_dyn_sleep);
+ if (attr == sleep_while_idle_attr)
+ return sprintf(buf, %hu\n, enable_dyn_sleep);
+ else if (attr == clocks_off_while_idle_attr)
+ return sprintf(buf, %hu\n, clocks_off_while_idle);
+ else
+ return -EINVAL;
}
static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
const char *buf, size_t n)
{
unsigned short value;
+
if (sscanf(buf, %hu, value) != 1 ||
(value != 0 value != 1)) {
- printk(KERN_ERR idle_sleep_store: Invalid value\n);
+ printk(KERN_ERR idle_store: Invalid value\n);
return -EINVAL;
}
- enable_dyn_sleep = value;
+
+ if (attr == sleep_while_idle_attr)
+ enable_dyn_sleep = value;
+ else if (attr == clocks_off_while_idle_attr)
+ clocks_off_while_idle = value;
+ else
+ return -EINVAL;
+
return n;
}
-static struct kobj_attribute sleep_while_idle_attr =
- __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
-
void omap2_block_sleep(void)
{
atomic_inc(sleep_block);
@@ -86,6 +107,10 @@ int __init omap_pm_init(void)
error = sysfs_create_file(power_kobj, sleep_while_idle_attr.attr);
if (error)
printk(KERN_ERR sysfs_create_file failed: %d\n, error);
+ error = sysfs_create_file(power_kobj,
+ clocks_off_while_idle_attr.attr);
+ if (error)
+ printk(KERN_ERR sysfs_create_file failed: %d\n, error);
return error;
}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 351456e..0aeb461 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -17,6 +17,7 @@ extern int omap2_pm_init(void);
extern int omap3_pm_init(void);
extern unsigned short enable_dyn_sleep;
+extern unsigned short clocks_off_while_idle;
extern atomic_t sleep_block;
#ifdef CONFIG_PM_DEBUG
--
1.5.5
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[PATCH 7/7] Added sleep support to UART
From: Tero Kristo [EMAIL PROTECTED]
UART usage (e.g. serial console) now denies sleep for 5 seconds. This
makes it possible to use serial console when dynamic idle is
enabled. Write 1 to /sys/power/clocks_off_while_sleep to enable uart
clock disable on idle. Without this omap won't enter retention.
Also moved code from pm-debug.c to serial.c, and made pm24xx.c use
this new implementation.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm-debug.c | 132
arch/arm/mach-omap2/pm.h |8 --
arch/arm/mach-omap2/pm24xx.c | 57 --
arch/arm/mach-omap2/pm34xx.c | 16 -
arch/arm/mach-omap2/serial.c | 148
include/asm-arm/arch-omap/common.h |3 +
6 files changed, 200 insertions(+), 164 deletions(-)
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index a32f11f..61d4501 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -37,138 +37,6 @@
#ifdef CONFIG_PM_DEBUG
int omap2_pm_debug = 0;
-static int serial_console_clock_disabled;
-static int serial_console_uart;
-static unsigned int serial_console_next_disable;
-
-static struct clk *console_iclk, *console_fclk;
-
-static void serial_console_kick(void)
-{
- serial_console_next_disable = omap2_read_32k_sync_counter();
- /* Keep the clocks on for 4 secs */
- serial_console_next_disable += 4 * 32768;
-}
-
-static void serial_wait_tx(void)
-{
- static const unsigned long uart_bases[3] = {
- 0x4806a000, 0x4806c000, 0x4806e000
- };
- unsigned long lsr_reg;
- int looped = 0;
-
- /* Wait for TX FIFO and THR to get empty */
- lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 2));
- while ((__raw_readb(lsr_reg) 0x60) != 0x60)
- looped = 1;
- if (looped)
- serial_console_kick();
-}
-
-u32 omap2_read_32k_sync_counter(void)
-{
-return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
-}
-
-void serial_console_fclk_mask(u32 *f1, u32 *f2)
-{
- switch (serial_console_uart) {
- case 1:
- *f1 = ~(1 21);
- break;
- case 2:
- *f1 = ~(1 22);
- break;
- case 3:
- *f2 = ~(1 2);
- break;
- }
-}
-
-void serial_console_sleep(int enable)
-{
- if (console_iclk == NULL || console_fclk == NULL)
- return;
-
- if (enable) {
- BUG_ON(serial_console_clock_disabled);
- if (clk_get_usecount(console_fclk) == 0)
- return;
- if ((int) serial_console_next_disable - (int)
omap2_read_32k_sync_counter() = 0)
- return;
- serial_wait_tx();
- clk_disable(console_iclk);
- clk_disable(console_fclk);
- serial_console_clock_disabled = 1;
- } else {
- int serial_wakeup = 0;
- u32 l;
-
- switch (serial_console_uart) {
- case 1:
- l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (l OMAP24XX_ST_UART1)
- serial_wakeup = 1;
- break;
- case 2:
- l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (l OMAP24XX_ST_UART2)
- serial_wakeup = 1;
- break;
- case 3:
- l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
- if (l OMAP24XX_ST_UART3)
- serial_wakeup = 1;
- break;
- }
- if (serial_wakeup)
- serial_console_kick();
- if (!serial_console_clock_disabled)
- return;
- clk_enable(console_iclk);
- clk_enable(console_fclk);
- serial_console_clock_disabled = 0;
- }
-}
-
-void pm_init_serial_console(void)
-{
- const struct omap_serial_console_config *conf;
- char name[16];
-
- conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
- struct omap_serial_console_config);
- if (conf == NULL)
- return;
- if (conf-console_uart 3 || conf-console_uart 1)
- return;
- serial_console_uart = conf-console_uart;
- sprintf(name, uart%d_fck, conf-console_uart);
- console_fclk = clk_get(NULL, name);
- if (IS_ERR(console_fclk))
- console_fclk = NULL;
- name[6] = 'i';
- console_iclk = clk_get(NULL, name);
- if (IS_ERR(console_fclk))
- console_iclk = NULL;
- if (console_fclk == NULL || console_iclk == NULL) {
- serial_console_uart = 0;
- return
[PATCH] PRCM: 34XX: Fix wrong shift value used in dpll4_m4x2_ck enable bit
Enable bit for dpll4_m4x2_ck is OMAP3430_PWRDN_DSS1_SHIFT instead of
OMAP3430_PWRDN_CAM_SHIFT.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index b4dceea..4a8729a 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -819,7 +819,7 @@ static struct clk dpll4_m4x2_ck = {
.name = dpll4_m4x2_ck,
.parent = dpll4_m4_ck,
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
- .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
+ .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
.recalc = omap3_clkoutx2_recalc,
};
--
1.5.5
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[PATCH 2/8] PRCM: Workaround for pwrdn_x control
Clock path should be powered down only after all it's clients are
properly disabled. Generally we don't have working implementation for
checking wether some clock is enabled or disabled.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c | 11 ++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ed15868..9099ba6 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -329,6 +329,9 @@ void omap2_clk_disable(struct clk *clk)
{
if (clk-usecount 0 !(--clk-usecount)) {
_omap2_clk_disable(clk);
+ /* XXX Currently we don't have working code for
+* checking wether clock is really disabled */
+ udelay(10);
if (clk-parent)
omap2_clk_disable(clk-parent);
if (clk-clkdm)
@@ -974,6 +977,12 @@ void omap2_clk_disable_unused(struct clk *clk)
return;
printk(KERN_INFO Disabling unused clock \%s\\n, clk-name);
- _omap2_clk_disable(clk);
+ /* XXX In case of omap3 we need to make sure that sequence is
+* correct when disabling clocks */
+ if (cpu_is_omap34xx()) {
+ omap2_clk_enable(clk);
+ omap2_clk_disable(clk);
+ } else
+ _omap2_clk_disable(clk);
}
#endif
--
1.5.5
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[PATCH 6/8] 34XX: PM: Workaround to check wether any fck is active before entering sleep
This workaround shouldn't be needed when all drivers are configuring
their sysconfig registers properly and setting their requirements
through omap-pm-srf.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 39 +++
1 files changed, 39 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 29ef5a8..0f42de7 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -80,6 +80,13 @@ static void per_gpio_clk_disable(void)
}
}
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void gpio_fclk_mask(u32 *fclk)
+{
+ *fclk = ~(0x1f 13);
+}
+
/* PRCM Interrupt Handler for wakeups */
static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
{
@@ -209,10 +216,42 @@ static void omap_sram_idle(void)
omap2_gpio_resume_after_retention();
}
+static int omap3_fclks_active(void)
+{
+ u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
+ fck_cam = 0, fck_per = 0, fck_usbhost = 0;
+
+ fck_core1 = cm_read_mod_reg(CORE_MOD,
+ CM_FCLKEN1);
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ fck_core3 = cm_read_mod_reg(CORE_MOD,
+ OMAP3430ES2_CM_FCLKEN3);
+ fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+ CM_FCLKEN);
+ fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+ CM_FCLKEN);
+ } else
+ fck_sgx = cm_read_mod_reg(GFX_MOD,
+ OMAP3430ES2_CM_FCLKEN3);
+ fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
+ CM_FCLKEN);
+ fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
+ CM_FCLKEN);
+ fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
+ CM_FCLKEN);
+ gpio_fclk_mask(fck_per);
+ if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
+ fck_cam | fck_per | fck_usbhost)
+ return 1;
+ return 0;
+}
+
static int omap3_can_sleep(void)
{
if (!enable_dyn_sleep)
return 0;
+ if (omap3_fclks_active())
+ return 0;
if (atomic_read(sleep_block) 0)
return 0;
return 1;
--
1.5.5
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[PATCH 8/8] Added sleep support to UART
From: Tero Kristo [EMAIL PROTECTED]
UART usage (e.g. serial console) now denies sleep for 5 seconds. This
makes it possible to use serial console when dynamic idle is
enabled. Write 1 to /sys/power/uart_clocks_off_while_sleep to enable
uart clock disable on idle. Without this omap won't enter retention.
Also moved code from pm-debug.c to serial.c, and made pm24xx.c use
this new implementation.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm-debug.c | 132
arch/arm/mach-omap2/pm.c | 37 --
arch/arm/mach-omap2/pm.h |9 +--
arch/arm/mach-omap2/pm24xx.c | 57 --
arch/arm/mach-omap2/pm34xx.c | 16
arch/arm/mach-omap2/serial.c | 148
include/asm-arm/arch-omap/common.h |3 +
7 files changed, 233 insertions(+), 169 deletions(-)
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index a32f11f..61d4501 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -37,138 +37,6 @@
#ifdef CONFIG_PM_DEBUG
int omap2_pm_debug = 0;
-static int serial_console_clock_disabled;
-static int serial_console_uart;
-static unsigned int serial_console_next_disable;
-
-static struct clk *console_iclk, *console_fclk;
-
-static void serial_console_kick(void)
-{
- serial_console_next_disable = omap2_read_32k_sync_counter();
- /* Keep the clocks on for 4 secs */
- serial_console_next_disable += 4 * 32768;
-}
-
-static void serial_wait_tx(void)
-{
- static const unsigned long uart_bases[3] = {
- 0x4806a000, 0x4806c000, 0x4806e000
- };
- unsigned long lsr_reg;
- int looped = 0;
-
- /* Wait for TX FIFO and THR to get empty */
- lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 2));
- while ((__raw_readb(lsr_reg) 0x60) != 0x60)
- looped = 1;
- if (looped)
- serial_console_kick();
-}
-
-u32 omap2_read_32k_sync_counter(void)
-{
-return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
-}
-
-void serial_console_fclk_mask(u32 *f1, u32 *f2)
-{
- switch (serial_console_uart) {
- case 1:
- *f1 = ~(1 21);
- break;
- case 2:
- *f1 = ~(1 22);
- break;
- case 3:
- *f2 = ~(1 2);
- break;
- }
-}
-
-void serial_console_sleep(int enable)
-{
- if (console_iclk == NULL || console_fclk == NULL)
- return;
-
- if (enable) {
- BUG_ON(serial_console_clock_disabled);
- if (clk_get_usecount(console_fclk) == 0)
- return;
- if ((int) serial_console_next_disable - (int)
omap2_read_32k_sync_counter() = 0)
- return;
- serial_wait_tx();
- clk_disable(console_iclk);
- clk_disable(console_fclk);
- serial_console_clock_disabled = 1;
- } else {
- int serial_wakeup = 0;
- u32 l;
-
- switch (serial_console_uart) {
- case 1:
- l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (l OMAP24XX_ST_UART1)
- serial_wakeup = 1;
- break;
- case 2:
- l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (l OMAP24XX_ST_UART2)
- serial_wakeup = 1;
- break;
- case 3:
- l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
- if (l OMAP24XX_ST_UART3)
- serial_wakeup = 1;
- break;
- }
- if (serial_wakeup)
- serial_console_kick();
- if (!serial_console_clock_disabled)
- return;
- clk_enable(console_iclk);
- clk_enable(console_fclk);
- serial_console_clock_disabled = 0;
- }
-}
-
-void pm_init_serial_console(void)
-{
- const struct omap_serial_console_config *conf;
- char name[16];
-
- conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
- struct omap_serial_console_config);
- if (conf == NULL)
- return;
- if (conf-console_uart 3 || conf-console_uart 1)
- return;
- serial_console_uart = conf-console_uart;
- sprintf(name, uart%d_fck, conf-console_uart);
- console_fclk = clk_get(NULL, name);
- if (IS_ERR(console_fclk))
- console_fclk = NULL;
- name[6] = 'i';
- console_iclk = clk_get(NULL, name);
- if (IS_ERR(console_fclk))
- console_iclk = NULL;
- if (console_fclk == NULL || console_iclk == NULL
[PATCH 4/8] 34XX: PM: Workaround to enable autoidle for clocks and plls
This workaround enables autoidle for interface clocks and plls. Also
automatic control of external oscillator through sys_clkreq is
enabled. I think these should be done by clockfw.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 120 ++
1 files changed, 120 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 1476597..ee00609 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -378,6 +378,126 @@ static struct platform_suspend_ops omap_pm_ops = {
#define R_VDD2_SR_CONTROL 0x01
static void __init prcm_setup_regs(void)
{
+ /* XXX Enable interface clock autoidle for all modules. This
+* should be done by clockfw */
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_MMC3 |
+ OMAP3430ES2_AUTO_ICR |
+ OMAP3430_AUTO_AES2 |
+ OMAP3430_AUTO_SHA12 |
+ OMAP3430_AUTO_DES2 |
+ OMAP3430_AUTO_MMC2 |
+ OMAP3430_AUTO_MMC1 |
+ OMAP3430_AUTO_MSPRO |
+ OMAP3430_AUTO_HDQ |
+ OMAP3430_AUTO_MCSPI4 |
+ OMAP3430_AUTO_MCSPI3 |
+ OMAP3430_AUTO_MCSPI2 |
+ OMAP3430_AUTO_MCSPI1 |
+ OMAP3430_AUTO_I2C3 |
+ OMAP3430_AUTO_I2C2 |
+ OMAP3430_AUTO_I2C1 |
+ OMAP3430_AUTO_UART2 |
+ OMAP3430_AUTO_UART1 |
+ OMAP3430_AUTO_GPT11 |
+ OMAP3430_AUTO_GPT10 |
+ OMAP3430_AUTO_MCBSP5 |
+ OMAP3430_AUTO_MCBSP1 |
+ OMAP3430ES1_AUTO_FAC | /* This is es1 only */
+ OMAP3430_AUTO_MAILBOXES |
+ OMAP3430_AUTO_OMAPCTRL |
+ OMAP3430ES1_AUTO_FSHOSTUSB |
+ OMAP3430_AUTO_HSOTGUSB |
+ OMAP3430ES1_AUTO_D2D | /* This is es1 only */
+ OMAP3430_AUTO_SSI,
+ CORE_MOD, CM_AUTOIDLE1);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_PKA |
+ OMAP3430_AUTO_AES1 |
+ OMAP3430_AUTO_RNG |
+ OMAP3430_AUTO_SHA11 |
+ OMAP3430_AUTO_DES1,
+ CORE_MOD, CM_AUTOIDLE2);
+
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_USBTLL,
+ CORE_MOD, CM_AUTOIDLE3);
+ }
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_WDT2 |
+ OMAP3430_AUTO_WDT1 |
+ OMAP3430_AUTO_GPIO1 |
+ OMAP3430_AUTO_32KSYNC |
+ OMAP3430_AUTO_GPT12 |
+ OMAP3430_AUTO_GPT1 ,
+ WKUP_MOD, CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_DSS,
+ OMAP3430_DSS_MOD,
+ CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_CAM,
+ OMAP3430_CAM_MOD,
+ CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_GPIO6 |
+ OMAP3430_AUTO_GPIO5 |
+ OMAP3430_AUTO_GPIO4 |
+ OMAP3430_AUTO_GPIO3 |
+ OMAP3430_AUTO_GPIO2 |
+ OMAP3430_AUTO_WDT3 |
+ OMAP3430_AUTO_UART3 |
+ OMAP3430_AUTO_GPT9 |
+ OMAP3430_AUTO_GPT8 |
+ OMAP3430_AUTO_GPT7 |
+ OMAP3430_AUTO_GPT6 |
+ OMAP3430_AUTO_GPT5 |
+ OMAP3430_AUTO_GPT4 |
+ OMAP3430_AUTO_GPT3 |
+ OMAP3430_AUTO_GPT2 |
+ OMAP3430_AUTO_MCBSP4 |
+ OMAP3430_AUTO_MCBSP3 |
+ OMAP3430_AUTO_MCBSP2,
+ OMAP3430_PER_MOD,
+ CM_AUTOIDLE);
+
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_USBHOST,
+ OMAP3430ES2_USBHOST_MOD,
+ CM_AUTOIDLE);
+ }
+
+ /* XXX Set all plls to autoidle. This is needed until autoidle is
+* enabled by clockfw */
+ cm_write_mod_reg(1 OMAP3430_CLKTRCTRL_IVA2_SHIFT,
+OMAP3430_IVA2_MOD,
+CM_AUTOIDLE2);
+ cm_write_mod_reg(1 OMAP3430_AUTO_MPU_DPLL_SHIFT,
+MPU_MOD,
+CM_AUTOIDLE2);
+ cm_write_mod_reg((1 OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
+(1 OMAP3430_AUTO_CORE_DPLL_SHIFT),
+PLL_MOD,
+CM_AUTOIDLE);
+ cm_write_mod_reg(1 OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
+PLL_MOD,
+CM_AUTOIDLE2);
+
+ /* XXX Enable control of expternal oscillator through
+* sys_clkreq. I think clockfw should provide means to do this
+*/
+ prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK
[PATCH 7/8] 34XX: PM: Workaround to disable mmc
Current hsmmc is not pm friendly. Disable it because it prevents omap3 retention Signed-off-by: Jouni Hogander [EMAIL PROTECTED] --- arch/arm/configs/omap_3430sdp_defconfig |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig index 947c25f..ee902ae 100644 --- a/arch/arm/configs/omap_3430sdp_defconfig +++ b/arch/arm/configs/omap_3430sdp_defconfig @@ -1043,7 +1043,7 @@ CONFIG_USB_ZERO=y # CONFIG_USB_G_SERIAL is not set # CONFIG_USB_MIDI_GADGET is not set # CONFIG_USB_G_PRINTER is not set -CONFIG_MMC=y +# CONFIG_MMC is not set # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set -- 1.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] PRCM: OMAP3: Fix to wrongly modified omap2_clk_wait_ready
omap2_clk_wait_ready was wrongly modified to check registers contents. This fix changes it back to check addresses. Signed-off-by: Jouni Hogander [EMAIL PROTECTED] --- arch/arm/mach-omap2/clock.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index d3ab537..ed15868 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -246,8 +246,8 @@ static void omap2_clk_wait_ready(struct clk *clk) /* REVISIT: What are the appropriate exclusions for 34XX? */ /* OMAP3: ignore DSS-mod clocks */ if (cpu_is_omap34xx() - ((reg ~0xff) == cm_read_mod_reg(OMAP3430_DSS_MOD, 0) || -(((reg ~0xff) == cm_read_mod_reg(CORE_MOD, 0)) + ((reg ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) || +(((reg ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) clk-enable_bit == OMAP3430_EN_SSI_SHIFT))) return; -- 1.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/9] 24XX: PM: Move pm.c to pm24xx.c and sleep.S to sleep24xx.S
Rename filenames to prepare 34XX additions.
Compile omap2 code only if CONFIG_ARCH_OMAP2 is defined.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/Makefile|4 +-
arch/arm/mach-omap2/pm.c| 845 ---
arch/arm/mach-omap2/pm24xx.c| 845 +++
arch/arm/mach-omap2/sleep.S | 133 --
arch/arm/mach-omap2/sleep24xx.S | 133 ++
5 files changed, 981 insertions(+), 979 deletions(-)
delete mode 100644 arch/arm/mach-omap2/pm.c
create mode 100644 arch/arm/mach-omap2/pm24xx.c
delete mode 100644 arch/arm/mach-omap2/sleep.S
create mode 100644 arch/arm/mach-omap2/sleep24xx.S
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ea0cf43..462f685 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -12,7 +12,9 @@ obj-$(CONFIG_ARCH_OMAP2) += sram24xx.o
obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
# Power Management
-obj-$(CONFIG_PM) += pm.o sleep.o
+ifeq ($(CONFIG_ARCH_OMAP2),y)
+obj-$(CONFIG_PM) += pm24xx.o sleep24xx.o
+endif
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
deleted file mode 100644
index b627fe5..000
--- a/arch/arm/mach-omap2/pm.c
+++ /dev/null
@@ -1,845 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/pm.c
- *
- * OMAP2 Power Management Routines
- *
- * Copyright (C) 2005 Texas Instruments, Inc.
- * Copyright (C) 2006-2008 Nokia Corporation
- *
- * Written by:
- * Richard Woodruff [EMAIL PROTECTED]
- * Tony Lindgren
- * Juha Yrjola
- * Amit Kucheria [EMAIL PROTECTED]
- * Igor Stoppa [EMAIL PROTECTED]
- *
- * Based on pm.c for omap1
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include linux/suspend.h
-#include linux/sched.h
-#include linux/proc_fs.h
-#include linux/interrupt.h
-#include linux/sysfs.h
-#include linux/module.h
-#include linux/delay.h
-#include linux/clk.h
-#include linux/io.h
-#include linux/irq.h
-
-#include asm/atomic.h
-#include asm/mach/time.h
-#include asm/mach/irq.h
-#include asm/mach-types.h
-
-#include asm/arch/irqs.h
-#include asm/arch/clock.h
-#include asm/arch/sram.h
-#include asm/arch/control.h
-#include asm/arch/gpio.h
-#include asm/arch/pm.h
-#include asm/arch/mux.h
-#include asm/arch/dma.h
-#include asm/arch/board.h
-
-#include prm.h
-#include prm-regbits-24xx.h
-#include cm.h
-#include cm-regbits-24xx.h
-#include sdrc.h
-
-/* These addrs are in assembly language code to be patched at runtime */
-extern void *omap2_ocs_sdrc_power;
-extern void *omap2_ocs_sdrc_dlla_ctrl;
-
-static void (*omap2_sram_idle)(void);
-static void (*omap2_sram_suspend)(void __iomem *dllctrl);
-static void (*saved_idle)(void);
-
-static u32 omap2_read_32k_sync_counter(void)
-{
- return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
-}
-
-#ifdef CONFIG_PM_DEBUG
-int omap2_pm_debug = 0;
-
-static int serial_console_clock_disabled;
-static int serial_console_uart;
-static unsigned int serial_console_next_disable;
-
-static struct clk *console_iclk, *console_fclk;
-
-static void serial_console_kick(void)
-{
- serial_console_next_disable = omap2_read_32k_sync_counter();
- /* Keep the clocks on for 4 secs */
- serial_console_next_disable += 4 * 32768;
-}
-
-static void serial_wait_tx(void)
-{
- static const unsigned long uart_bases[3] = {
- 0x4806a000, 0x4806c000, 0x4806e000
- };
- unsigned long lsr_reg;
- int looped = 0;
-
- /* Wait for TX FIFO and THR to get empty */
- lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 2));
- while ((__raw_readb(lsr_reg) 0x60) != 0x60)
- looped = 1;
- if (looped)
- serial_console_kick();
-}
-
-static void serial_console_fclk_mask(u32 *f1, u32 *f2)
-{
- switch (serial_console_uart) {
- case 1:
- *f1 = ~(1 21);
- break;
- case 2:
- *f1 = ~(1 22);
- break;
- case 3:
- *f2 = ~(1 2);
- break;
- }
-}
-
-static void serial_console_sleep(int enable)
-{
- if (console_iclk == NULL || console_fclk == NULL)
- return;
-
- if (enable) {
- BUG_ON(serial_console_clock_disabled);
- if (clk_get_usecount(console_fclk) == 0)
- return;
- if ((int) serial_console_next_disable -
- (int) omap2_read_32k_sync_counter() = 0)
- return;
- serial_wait_tx();
- clk_disable(console_iclk);
- clk_disable(console_fclk);
- serial_console_clock_disabled = 1;
- } else {
- int serial_wakeup = 0;
- u32 l
[PATCH 2/9] 24XX: PM: Move debugging related code to pm-debug.c
Move debugging and serial console handling to pm-debug.c.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/Makefile |2 +
arch/arm/mach-omap2/pm-debug.c | 275
arch/arm/mach-omap2/pm.h | 31 +
arch/arm/mach-omap2/pm24xx.c | 258 +-
4 files changed, 309 insertions(+), 257 deletions(-)
create mode 100644 arch/arm/mach-omap2/pm-debug.c
create mode 100644 arch/arm/mach-omap2/pm.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 462f685..8f80382 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -16,6 +16,8 @@ ifeq ($(CONFIG_ARCH_OMAP2),y)
obj-$(CONFIG_PM) += pm24xx.o sleep24xx.o
endif
+obj-$(CONFIG_PM_DEBUG) += pm-debug.o
+
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
new file mode 100644
index 000..361e52b
--- /dev/null
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -0,0 +1,275 @@
+/*
+ * linux/arch/arm/mach-omap2/pm_debug.c
+ *
+ * OMAP Power Management debug routines
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ * Copyright (C) 2006-2008 Nokia Corporation
+ *
+ * Written by:
+ * Richard Woodruff [EMAIL PROTECTED]
+ * Tony Lindgren
+ * Juha Yrjola
+ * Amit Kucheria [EMAIL PROTECTED]
+ * Igor Stoppa [EMAIL PROTECTED]
+ * Jouni Hogander
+ *
+ * Based on pm.c for omap2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/err.h
+
+#include asm/arch/clock.h
+#include asm/arch/board.h
+
+#include prm.h
+#include pm.h
+
+#ifdef CONFIG_PM_DEBUG
+int omap2_pm_debug = 0;
+
+static int serial_console_clock_disabled;
+static int serial_console_uart;
+static unsigned int serial_console_next_disable;
+
+static struct clk *console_iclk, *console_fclk;
+
+static void serial_console_kick(void)
+{
+ serial_console_next_disable = omap2_read_32k_sync_counter();
+ /* Keep the clocks on for 4 secs */
+ serial_console_next_disable += 4 * 32768;
+}
+
+static void serial_wait_tx(void)
+{
+ static const unsigned long uart_bases[3] = {
+ 0x4806a000, 0x4806c000, 0x4806e000
+ };
+ unsigned long lsr_reg;
+ int looped = 0;
+
+ /* Wait for TX FIFO and THR to get empty */
+ lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 2));
+ while ((__raw_readb(lsr_reg) 0x60) != 0x60)
+ looped = 1;
+ if (looped)
+ serial_console_kick();
+}
+
+u32 omap2_read_32k_sync_counter(void)
+{
+return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
+}
+
+void serial_console_fclk_mask(u32 *f1, u32 *f2)
+{
+ switch (serial_console_uart) {
+ case 1:
+ *f1 = ~(1 21);
+ break;
+ case 2:
+ *f1 = ~(1 22);
+ break;
+ case 3:
+ *f2 = ~(1 2);
+ break;
+ }
+}
+
+void serial_console_sleep(int enable)
+{
+ if (console_iclk == NULL || console_fclk == NULL)
+ return;
+
+ if (enable) {
+ BUG_ON(serial_console_clock_disabled);
+ if (clk_get_usecount(console_fclk) == 0)
+ return;
+ if ((int) serial_console_next_disable - (int)
omap2_read_32k_sync_counter() = 0)
+ return;
+ serial_wait_tx();
+ clk_disable(console_iclk);
+ clk_disable(console_fclk);
+ serial_console_clock_disabled = 1;
+ } else {
+ int serial_wakeup = 0;
+ u32 l;
+
+ switch (serial_console_uart) {
+ case 1:
+ l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
+ if (l OMAP24XX_ST_UART1)
+ serial_wakeup = 1;
+ break;
+ case 2:
+ l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
+ if (l OMAP24XX_ST_UART2)
+ serial_wakeup = 1;
+ break;
+ case 3:
+ l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
+ if (l OMAP24XX_ST_UART3)
+ serial_wakeup = 1;
+ break;
+ }
+ if (serial_wakeup)
+ serial_console_kick();
+ if (!serial_console_clock_disabled)
+ return;
+ clk_enable(console_iclk);
+ clk_enable(console_fclk);
+ serial_console_clock_disabled = 0;
+ }
+}
+
+void pm_init_serial_console(void
[PATCH 6/9] 34XX: Suspend: Use same naming convention in sleep34xx.S as in sleep24XX.S
Change omap34xx_suspend to omap34xx_cpu_suspend and
omap34xx_suspend_sz to omap34xx_cpu_suspend_sz.
Do not use PRM_BASE in sleep34xx.S because it is not defined in
linux-omap tree.
Use OMAP343X_SDRC_BASE in sleep34xx.S instead of SDRC_BASE.
Convert all IO_ADDRESS style definitions to OMAP34XX_PRM_REGADDR style
definitions.
Add omap34xx_cpu_suspend and omap34xx_cpu_suspend_sz to
include/asm-arm/arch-omap/pm.h
Do necessary modifications to be able to use arch/arm/mach-omap2/prm.h
and include/asm-arm/arch-omap/control.h ins asm files.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/prm.h |7 ++-
arch/arm/mach-omap2/sleep34xx.S | 28 +++-
include/asm-arm/arch-omap/control.h |6 ++
include/asm-arm/arch-omap/pm.h |3 +++
4 files changed, 30 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index e1ce33e..f816165 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -14,9 +14,6 @@
* published by the Free Software Foundation.
*/
-#include linux/io.h
-#include linux/bitops.h
-
#include prcm-common.h
#ifndef __ASSEMBLER__
@@ -156,6 +153,8 @@ static __inline__ u32 __attribute__((unused))
prm_rmw_reg_bits(u32 mask,
#define OMAP3430_PRM_IRQSTATUS_IVA20x00f8
#define OMAP3430_PRM_IRQENABLE_IVA20x00fc
+#ifndef __ASSEMBLER__
+
/* Read-modify-write bits in a PRM register (by domain) */
static u32 __attribute__((unused)) prm_rmw_mod_reg_bits(u32 mask, u32 bits,
s16 module, s16 idx)
@@ -183,8 +182,6 @@ static u32 __attribute__((unused))
prm_clear_mod_reg_bits(u32 bits, s16 module,
#define OMAP24XX_PRCM_IRQSTATUS_IVA0x00f8
#define OMAP24XX_PRCM_IRQENABLE_IVA0x00fc
-#ifndef __ASSEMBLER__
-
/* Power/reset management domain register get/set */
static __inline__ void __attribute__((unused)) prm_write_mod_reg(u32 val,
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index c9db507..ebc7eb3 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -28,12 +28,22 @@
#include asm/assembler.h
#include asm/arch/io.h
#include asm/arch/pm.h
-
-#define PM_PREPWSTST_CORE_VIO_ADDRESS(PRM_BASE + 0xAE8)
-#define PM_PREPWSTST_MPU_V IO_ADDRESS(PRM_BASE + 0x9E8)
-#define PM_PWSTCTRL_MPU_P (PRM_BASE + 0x9E0)
-#define SCRATCHPAD_BASE_P 0x48002910
-#define SDRC_POWER_V IO_ADDRESS(SDRC_BASE + 0x070)
+#include asm/arch/control.h
+
+#include prm.h
+#include sdrc.h
+
+#define PM_PREPWSTST_CORE_VOMAP34XX_PRM_REGADDR(CORE_MOD, \
+ OMAP3430_PM_PREPWSTST)
+#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
+ OMAP3430_PM_PREPWSTST)
+#define PM_PWSTCTRL_MPU_P OMAP34XX_PRM_REGADDR(MPU_MOD, PM_PWSTCTRL)
+#define SCRATCHPAD_MEM_OFFS0x310 /* Move this as correct place is
+ * available */
+#define SCRATCHPAD_BASE_P OMAP343X_CTRL_REGADDR(\
+ OMAP343X_CONTROL_MEM_WKUP +\
+ SCRATCHPAD_MEM_OFFS)
+#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
.text
/* Function call to get the restore pointer for resume from OFF */
@@ -52,7 +62,7 @@ ENTRY(get_restore_pointer_sz)
* Note: This code get's copied to internal SRAM at boot. When the OMAP
* wakes up it continues execution at the point it went to sleep.
*/
-ENTRY(omap34xx_suspend)
+ENTRY(omap34xx_cpu_suspend)
stmfd sp!, {r0-r12, lr} @ save registers on stack
loop:
/*b loop*/ @Enable to debug by stepping through code
@@ -530,5 +540,5 @@ table_entry:
.word 0x0C02
cache_pred_disable_mask:
.word 0xE7FB
-ENTRY(omap34xx_suspend_sz)
- .word . - omap34xx_suspend
+ENTRY(omap34xx_cpu_suspend_sz)
+ .word . - omap34xx_cpu_suspend
diff --git a/include/asm-arm/arch-omap/control.h
b/include/asm-arm/arch-omap/control.h
index 0832348..1d95cc2 100644
--- a/include/asm-arm/arch-omap/control.h
+++ b/include/asm-arm/arch-omap/control.h
@@ -18,12 +18,18 @@
#include asm/arch/io.h
+#ifndef __ASSEMBLY__
#define OMAP242X_CTRL_REGADDR(reg) \
(__force void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
#define OMAP243X_CTRL_REGADDR(reg) \
(__force void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
#define OMAP343X_CTRL_REGADDR(reg) \
(__force void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#else
+#define OMAP242X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg
[PATCH 3/9] PM: Add pm.c file for omap2 and omap3 common code
Add pm.c file for common code and move handling of sleep_while_idle
attribute and sleep_block to it.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/Makefile |2 +
arch/arm/mach-omap2/pm.c | 91 ++
arch/arm/mach-omap2/pm.h |4 ++
arch/arm/mach-omap2/pm24xx.c | 49 +--
4 files changed, 98 insertions(+), 48 deletions(-)
create mode 100644 arch/arm/mach-omap2/pm.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8f80382..12f6a6f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -12,6 +12,8 @@ obj-$(CONFIG_ARCH_OMAP2) += sram24xx.o
obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
# Power Management
+obj-$(CONFIG_PM) += pm.o
+
ifeq ($(CONFIG_ARCH_OMAP2),y)
obj-$(CONFIG_PM) += pm24xx.o sleep24xx.o
endif
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
new file mode 100644
index 000..55ed75b
--- /dev/null
+++ b/arch/arm/mach-omap2/pm.c
@@ -0,0 +1,91 @@
+/*
+ * linux/arch/arm/mach-omap2/pm.c
+ *
+ * OMAP Power Management Common Routines
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ * Copyright (C) 2006-2008 Nokia Corporation
+ *
+ * Written by:
+ * Richard Woodruff [EMAIL PROTECTED]
+ * Tony Lindgren
+ * Juha Yrjola
+ * Amit Kucheria [EMAIL PROTECTED]
+ * Igor Stoppa [EMAIL PROTECTED]
+ * Jouni Hogander
+ *
+ * Based on pm.c for omap1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/suspend.h
+#include linux/time.h
+
+#include asm/arch/cpu.h
+#include asm/mach/time.h
+#include asm/atomic.h
+
+#include pm.h
+
+unsigned short enable_dyn_sleep;
+atomic_t sleep_block = ATOMIC_INIT(0);
+
+static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
+char *buf)
+{
+ return sprintf(buf, %hu\n, enable_dyn_sleep);
+}
+
+static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, size_t n)
+{
+ unsigned short value;
+ if (sscanf(buf, %hu, value) != 1 ||
+ (value != 0 value != 1)) {
+ printk(KERN_ERR idle_sleep_store: Invalid value\n);
+ return -EINVAL;
+ }
+ enable_dyn_sleep = value;
+ return n;
+}
+
+static struct kobj_attribute sleep_while_idle_attr =
+ __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
+
+void omap2_block_sleep(void)
+{
+ atomic_inc(sleep_block);
+}
+
+void omap2_allow_sleep(void)
+{
+ int i;
+
+ i = atomic_dec_return(sleep_block);
+ BUG_ON(i 0);
+}
+
+int __init omap_pm_init(void)
+{
+ int error = -1;
+
+ if (cpu_is_omap24xx())
+ error = omap2_pm_init();
+ if (error) {
+ printk(KERN_ERR omap2_pm_init failed: %d\n, error);
+ return error;
+ }
+
+ /* disabled till drivers are fixed */
+ enable_dyn_sleep = 0;
+ error = sysfs_create_file(power_kobj, sleep_while_idle_attr.attr);
+ if (error)
+ printk(KERN_ERR sysfs_create_file failed: %d\n, error);
+
+ return error;
+}
+
+late_initcall(omap_pm_init);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 541bf90..15482ba 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -13,6 +13,10 @@
* published by the Free Software Foundation.
*/
+extern int omap2_pm_init(void);
+extern unsigned short enable_dyn_sleep;
+extern atomic_t sleep_block;
+
#ifdef CONFIG_PM_DEBUG
extern u32 omap2_read_32k_sync_counter(void);
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 593f629..7bb654f 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -31,7 +31,6 @@
#include linux/io.h
#include linux/irq.h
-#include asm/atomic.h
#include asm/mach/time.h
#include asm/mach/irq.h
#include asm/mach-types.h
@@ -61,30 +60,6 @@ static void (*omap2_sram_idle)(void);
static void (*omap2_sram_suspend)(void __iomem *dllctrl);
static void (*saved_idle)(void);
-static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed
*/
-
-static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
-char *buf)
-{
- return sprintf(buf, %hu\n, enable_dyn_sleep);
-}
-
-static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- unsigned short value;
- if (sscanf(buf, %hu, value) != 1 ||
- (value != 0 value != 1)) {
- printk(KERN_ERR idle_sleep_store: Invalid value\n);
- return -EINVAL;
- }
- enable_dyn_sleep = value;
- return n;
-}
-
-static
[PATCH 7/9] 34XX: Add miscellaneous definitions related to 34xx
Signed-off-by: Jouni Hogander [EMAIL PROTECTED] --- arch/arm/mach-omap2/cm-regbits-34xx.h |7 +++ arch/arm/mach-omap2/prm-regbits-34xx.h |9 + arch/arm/mach-omap2/prm.h | 24 +--- include/asm-arm/arch-omap/irqs.h |1 + 4 files changed, 30 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 219f5c8..6ec66f4 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -208,6 +208,10 @@ #define OMAP3430ES2_ST_USBTLL_MASK (1 2) /* CM_AUTOIDLE1_CORE */ +#define OMAP3430ES2_AUTO_MMC3 (1 30) +#define OMAP3430ES2_AUTO_MMC3_SHIFT30 +#define OMAP3430ES2_AUTO_ICR (1 29) +#define OMAP3430ES2_AUTO_ICR_SHIFT 29 #define OMAP3430_AUTO_AES2 (1 28) #define OMAP3430_AUTO_AES2_SHIFT 28 #define OMAP3430_AUTO_SHA12(1 27) @@ -276,6 +280,9 @@ #define OMAP3430_AUTO_DES1_SHIFT 0 /* CM_AUTOIDLE3_CORE */ +#defineOMAP3430ES2_AUTO_USBHOST(1 0) +#defineOMAP3430ES2_AUTO_USBHOST_SHIFT 0 +#defineOMAP3430ES2_AUTO_USBTLL (1 2) #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 #define OMAP3430ES2_AUTO_USBTLL_MASK (1 2) diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 5b5ecfe..c6a7940 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -366,6 +366,7 @@ /* PM_WKEN_WKUP specific bits */ #define OMAP3430_EN_IO (1 8) +#define OMAP3430_EN_GPIO1 (1 3) /* PM_MPUGRPSEL_WKUP specific bits */ @@ -452,6 +453,14 @@ #define OMAP3430_CMDRA0_MASK (0xff 0) /* PRM_VC_CMD_VAL_0 specific bits */ +#define OMAP3430_VC_CMD_ON_SHIFT 24 +#define OMAP3430_VC_CMD_ON_MASK(0xFF 24) +#define OMAP3430_VC_CMD_ONLP_SHIFT 16 +#define OMAP3430_VC_CMD_ONLP_MASK (0xFF 16) +#define OMAP3430_VC_CMD_RET_SHIFT 8 +#define OMAP3430_VC_CMD_RET_MASK (0xFF 8) +#define OMAP3430_VC_CMD_OFF_SHIFT 0 +#define OMAP3430_VC_CMD_OFF_MASK (0xFF 0) /* PRM_VC_CMD_VAL_1 specific bits */ diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index f816165..27d44e2 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -142,6 +142,19 @@ static __inline__ u32 __attribute__((unused)) prm_rmw_reg_bits(u32 mask, #define PM_PWSTCTRL0x00e0 #define PM_PWSTST 0x00e4 +/* Omap2 specific registers */ +#define OMAP24XX_PM_WKEN2 0x00a4 +#define OMAP24XX_PM_WKST2 0x00b4 + +#define OMAP24XX_PRCM_IRQSTATUS_DSP0x00f0 /* IVA mod */ +#define OMAP24XX_PRCM_IRQENABLE_DSP0x00f4 /* IVA mod */ +#define OMAP24XX_PRCM_IRQSTATUS_IVA0x00f8 +#define OMAP24XX_PRCM_IRQENABLE_IVA0x00fc + +/* Omap3 specific registers */ +#define OMAP3430ES2_PM_WKEN3 0x00f0 +#define OMAP3430ES2_PM_WKST3 0x00b8 + #define OMAP3430_PM_MPUGRPSEL 0x00a4 #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL @@ -172,16 +185,6 @@ static u32 __attribute__((unused)) prm_clear_mod_reg_bits(u32 bits, s16 module, return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); } -/* Architecture-specific registers */ - -#define OMAP24XX_PM_WKEN2 0x00a4 -#define OMAP24XX_PM_WKST2 0x00b4 - -#define OMAP24XX_PRCM_IRQSTATUS_DSP0x00f0 /* IVA mod */ -#define OMAP24XX_PRCM_IRQENABLE_DSP0x00f4 /* IVA mod */ -#define OMAP24XX_PRCM_IRQSTATUS_IVA0x00f8 -#define OMAP24XX_PRCM_IRQENABLE_IVA0x00fc - /* Power/reset management domain register get/set */ static __inline__ void __attribute__((unused)) prm_write_mod_reg(u32 val, @@ -243,7 +246,6 @@ static __inline__ u32 __attribute__((unused)) prm_read_mod_reg(s16 module, #define OMAP_RSTTIME1_SHIFT0 #define OMAP_RSTTIME1_MASK (0xff 0) - /* PRM_RSTCTRL */ /* Named RM_RSTCTRL_WKUP on the 24xx */ /* 2420 calls RST_DPLL3 'RST_DPLL' */ diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h index 343e93e..f901e8b 100644 --- a/include/asm-arm/arch-omap
[PATCH 9/9] OMAP3430SDP: Enable config options CONFIG_OMAP_RESET_CLOCKS and CONFIG_SUSPEND
Signed-off-by: Jouni Hogander [EMAIL PROTECTED] --- arch/arm/configs/omap_3430sdp_defconfig |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig index 0fef29d..9e4af26 100644 --- a/arch/arm/configs/omap_3430sdp_defconfig +++ b/arch/arm/configs/omap_3430sdp_defconfig @@ -168,7 +168,7 @@ CONFIG_ARCH_OMAP3=y # OMAP Feature Selections # CONFIG_OMAP_DEBUG_SRAM_PATCH=y -# CONFIG_OMAP_RESET_CLOCKS is not set +CONFIG_OMAP_RESET_CLOCKS=y CONFIG_OMAP_BOOT_TAG=y CONFIG_OMAP_BOOT_REASON=y # CONFIG_OMAP_COMPONENT_VERSION is not set @@ -308,7 +308,7 @@ CONFIG_BINFMT_MISC=y CONFIG_PM=y # CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set -# CONFIG_SUSPEND is not set +CONFIG_SUSPEND=y # CONFIG_APM_EMULATION is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y -- 1.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 8/9] 34XX: PM: Initial version of suspend and dynamic retention
This is initial version of suspend and dynamic retention for
34xx. Omap is tried to put to full retention on suspend and pm_idle.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/Makefile |3 +
arch/arm/mach-omap2/pm.c |4 +-
arch/arm/mach-omap2/pm.h |2 +
arch/arm/mach-omap2/pm34xx.c | 386 ++
4 files changed, 394 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/pm34xx.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 12f6a6f..6168aa4 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -18,6 +18,9 @@ ifeq ($(CONFIG_ARCH_OMAP2),y)
obj-$(CONFIG_PM) += pm24xx.o sleep24xx.o
endif
+ifeq ($(CONFIG_ARCH_OMAP3),y)
+obj-$(CONFIG_PM) += pm34xx.o sleep34xx.o
+endif
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
# Clock framework
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 55ed75b..bef58d7 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -74,8 +74,10 @@ int __init omap_pm_init(void)
if (cpu_is_omap24xx())
error = omap2_pm_init();
+ if (cpu_is_omap34xx())
+ error = omap3_pm_init();
if (error) {
- printk(KERN_ERR omap2_pm_init failed: %d\n, error);
+ printk(KERN_ERR omap2|3_pm_init failed: %d\n, error);
return error;
}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 15482ba..351456e 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -14,6 +14,8 @@
*/
extern int omap2_pm_init(void);
+extern int omap3_pm_init(void);
+
extern unsigned short enable_dyn_sleep;
extern atomic_t sleep_block;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
new file mode 100644
index 000..a1bfb30
--- /dev/null
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -0,0 +1,386 @@
+/*
+ * linux/arch/arm/mach-omap2/pm34xx.c
+ *
+ * OMAP3 Power Management Routines
+ *
+ * Copyright (C) 2006-2008 Nokia Corporation
+ * Tony Lindgren [EMAIL PROTECTED]
+ * Jouni Hogander
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ * Richard Woodruff [EMAIL PROTECTED]
+ *
+ * Based on pm.c for omap1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/pm.h
+#include linux/suspend.h
+#include linux/interrupt.h
+#include linux/module.h
+#include linux/list.h
+#include linux/err.h
+
+#include asm/arch/gpio.h
+#include asm/arch/sram.h
+#include asm/arch/pm.h
+#include asm/arch/clockdomain.h
+#include asm/arch/powerdomain.h
+
+#include cm.h
+#include cm-regbits-34xx.h
+#include prm-regbits-34xx.h
+
+#include prm.h
+#include pm.h
+
+struct power_state {
+ struct powerdomain *pwrdm;
+ u32 next_state;
+ u32 saved_state;
+ struct list_head node;
+};
+
+static LIST_HEAD(pwrst_list);
+
+void (*_omap_sram_idle)(u32 *addr, int save_state);
+
+static void (*saved_idle)(void);
+
+static struct powerdomain *mpu_pwrdm;
+
+/* PRCM Interrupt Handler for wakeups */
+static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
+{
+ u32 wkst, irqstatus_mpu;
+ u32 fclk, iclk;
+
+ /* WKUP */
+ wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
+ if (wkst) {
+ iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
+ fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
+ cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
+ cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
+ prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
+ while (prm_read_mod_reg(WKUP_MOD, PM_WKST));
+ cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
+ cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
+ }
+
+ /* CORE */
+ wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
+ if (wkst) {
+ iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
+ fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+ cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
+ cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
+ prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
+ while (prm_read_mod_reg(CORE_MOD, PM_WKST1));
+ cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
+ cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
+ }
+ wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
+ if (wkst) {
+ iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
+ fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
+ cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
+ cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
+ prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
+ while
[PATCH 02/10] 34XX: PM: Workaround for uart clocks
This patch is needed until we have uart driver which disables uart clocks when they are not needed. Signed-off-by: Jouni Hogander [EMAIL PROTECTED] --- arch/arm/mach-omap2/pm34xx.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 1826dcd..e578503 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -29,6 +29,7 @@ #include asm/arch/pm.h #include asm/arch/clockdomain.h #include asm/arch/powerdomain.h +#include asm/arch/common.h #include cm.h #include cm-regbits-34xx.h @@ -197,8 +198,12 @@ static void omap_sram_idle(void) * handles fcks correctly */ per_gpio_clk_disable(); + omap_serial_enable_clocks(0); + _omap_sram_idle(NULL, save_state); + omap_serial_enable_clocks(1); + /* XXX This is for gpio fclk hack. Will be removed as gpio driver * handles fcks correctly */ per_gpio_clk_enable(); -- 1.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 01/10] 34XX: PM: Workaround for taking care of gpio clocks
In omap3 gpios 2-6 are in per domain. Clocks for these should be
disabled. This patch is needed until gpio driver disables gpio clocks
when they are not needed.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 48 +-
1 files changed, 47 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a1bfb30..1826dcd 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -52,6 +52,34 @@ static void (*saved_idle)(void);
static struct powerdomain *mpu_pwrdm;
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+#define NUM_OF_PERGPIOS 5
+static struct clk *gpio_fcks[NUM_OF_PERGPIOS];
+static struct clk *gpio_icks[NUM_OF_PERGPIOS];
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void per_gpio_clk_enable(void)
+{
+ int i;
+ for (i = 1; i NUM_OF_PERGPIOS + 1; i++) {
+ clk_enable(gpio_icks[i-1]);
+ clk_enable(gpio_fcks[i-1]);
+ }
+}
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void per_gpio_clk_disable(void)
+{
+ int i;
+ for (i = 1; i NUM_OF_PERGPIOS + 1; i++) {
+ clk_disable(gpio_fcks[i-1]);
+ clk_disable(gpio_icks[i-1]);
+ }
+}
+
/* PRCM Interrupt Handler for wakeups */
static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
{
@@ -165,8 +193,16 @@ static void omap_sram_idle(void)
omap2_gpio_prepare_for_retention();
+ /* XXX This is for gpio fclk hack. Will be removed as gpio driver
+* handles fcks correctly */
+ per_gpio_clk_disable();
+
_omap_sram_idle(NULL, save_state);
+ /* XXX This is for gpio fclk hack. Will be removed as gpio driver
+* handles fcks correctly */
+ per_gpio_clk_enable();
+
omap2_gpio_resume_after_retention();
}
@@ -340,7 +376,8 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm)
int __init omap3_pm_init(void)
{
struct power_state *pwrst;
- int ret;
+ char clk_name[11];
+ int ret, i;
printk(KERN_ERR Power Management for TI OMAP3.\n);
@@ -374,6 +411,15 @@ int __init omap3_pm_init(void)
pm_idle = omap3_pm_idle;
+ /* XXX This is for gpio fclk hack. Will be removed as gpio driver
+* handles fcks correctly */
+ for (i = 1; i NUM_OF_PERGPIOS + 1; i++) {
+ sprintf(clk_name, gpio%d_fck, i + 1);
+ gpio_fcks[i-1] = clk_get(NULL, clk_name);
+ sprintf(clk_name, gpio%d_ick, i + 1);
+ gpio_icks[i-1] = clk_get(NULL, clk_name);
+ }
+
err1:
return ret;
err2:
--
1.5.5
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[PATCH 03/10] 34XX: PM: Workaround for missing smartreflex driver
This workaround is needed because we don't have smartreflex
driver. These configurations are taken from TI's reference code.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 67 ++
drivers/i2c/chips/twl4030-core.c |9 +
2 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e578503..49e2989 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -346,6 +346,25 @@ static struct platform_suspend_ops omap_pm_ops = {
.valid = suspend_valid_only_mem,
};
+/* PRM_VC_CMD_VAL_0 specific bits */
+#define PRM_VC_CMD_VAL0_ON 0x30
+#define PRM_VC_CMD_VAL0_ONLP 0x18
+#define PRM_VC_CMD_VAL0_RET0x18
+#define PRM_VC_CMD_VAL0_OFF0x18
+
+/* PRM_VC_CMD_VAL_1 specific bits */
+#define PRM_VC_CMD_VAL1_ON 0x2C
+#define PRM_VC_CMD_VAL1_ONLP 0x18
+#define PRM_VC_CMD_VAL1_RET0x18
+#define PRM_VC_CMD_VAL1_OFF0x18
+
+/* PRM_VOLTCTRL */
+#define PRM_VOLTCTRL_AUTO_RET 0x2
+
+/* T2 SMART REFLEX */
+#define R_SRI2C_SLAVE_ADDR 0x12
+#define R_VDD1_SR_CONTROL 0x00
+#define R_VDD2_SR_CONTROL 0x01
static void __init prcm_setup_regs(void)
{
u32 v;
@@ -360,6 +379,54 @@ static void __init prcm_setup_regs(void)
* it is selected to mpu wakeup goup */
__raw_writel(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
OMAP3430_PRM_IRQENABLE_MPU);
+
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ /* XXX These are smartreflex related and are here as long as we
+* have working smartreflex driver in linux-omap tree */
+ __raw_writel((R_SRI2C_SLAVE_ADDR
+ OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT) |
+(R_SRI2C_SLAVE_ADDR
+ OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT),
+OMAP3430_PRM_VC_SMPS_SA);
+
+ __raw_writel((R_VDD2_SR_CONTROL
+ OMAP3430_VOLRA1_SHIFT) |
+(R_VDD1_SR_CONTROL
+ OMAP3430_VOLRA0_SHIFT),
+OMAP3430_PRM_VC_SMPS_VOL_RA);
+
+ __raw_writel((PRM_VC_CMD_VAL0_ON
+ OMAP3430_VC_CMD_ON_SHIFT) |
+(PRM_VC_CMD_VAL0_ONLP
+ OMAP3430_VC_CMD_ONLP_SHIFT) |
+(PRM_VC_CMD_VAL0_RET
+ OMAP3430_VC_CMD_RET_SHIFT) |
+(PRM_VC_CMD_VAL0_OFF
+ OMAP3430_VC_CMD_OFF_SHIFT),
+OMAP3430_PRM_VC_CMD_VAL_0);
+
+ __raw_writel((PRM_VC_CMD_VAL1_ON
+ OMAP3430_VC_CMD_ON_SHIFT) |
+(PRM_VC_CMD_VAL1_ONLP
+ OMAP3430_VC_CMD_ONLP_SHIFT) |
+(PRM_VC_CMD_VAL1_RET
+ OMAP3430_VC_CMD_RET_SHIFT) |
+(PRM_VC_CMD_VAL1_OFF
+ OMAP3430_VC_CMD_OFF_SHIFT),
+OMAP3430_PRM_VC_CMD_VAL_1);
+
+ __raw_writel(OMAP3430_CMD1 |
+OMAP3430_RAV1,
+OMAP3430_PRM_VC_CH_CONF);
+
+ __raw_writel(OMAP3430_MCODE_SHIFT |
+OMAP3430_HSEN |
+OMAP3430_SREN,
+OMAP3430_PRM_VC_I2C_CFG);
+
+ __raw_writel(PRM_VOLTCTRL_AUTO_RET,
+OMAP3430_PRM_VOLTCTRL);
+ }
}
static int __init pwrdms_setup(struct powerdomain *pwrdm)
diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
index 8822653..96e6216 100644
--- a/drivers/i2c/chips/twl4030-core.c
+++ b/drivers/i2c/chips/twl4030-core.c
@@ -119,6 +119,7 @@
/* Few power values */
#define R_CFG_BOOT 0x05
#define R_PROTECT_KEY 0x0E
+#define R_DCDC_GLOBAL_CFG 0x06
/* access control */
#define KEY_UNLOCK10xce
@@ -709,6 +710,14 @@ static int power_companion_init(void)
e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, ctrl, R_CFG_BOOT);
e |= protect_pm_master();
+ /* XXX Enable smart reflex. Voltage scaling method should be
+* passed in platform data */
+ e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER,
+ctrl, R_DCDC_GLOBAL_CFG);
+ ctrl |= 0x8;
+ e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+ ctrl, R_DCDC_GLOBAL_CFG);
+
return e;
}
--
1.5.5
--
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[PATCH 08/10] 34XX: PM: Workaround to disable mmc
Current hsmmc is not pm friendly. Disable it because it prevents omap3 retention Signed-off-by: Jouni Hogander [EMAIL PROTECTED] --- arch/arm/configs/omap_3430sdp_defconfig |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig index 9e4af26..4239b25 100644 --- a/arch/arm/configs/omap_3430sdp_defconfig +++ b/arch/arm/configs/omap_3430sdp_defconfig @@ -966,7 +966,7 @@ CONFIG_USB_ZERO=y # CONFIG_USB_G_SERIAL is not set # CONFIG_USB_MIDI_GADGET is not set # CONFIG_USB_G_PRINTER is not set -CONFIG_MMC=y +# CONFIG_MMC is not set # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set -- 1.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 05/10] 34XX: PM: Workaround to enable autoidle for clocks and plls
This workaround enables autoidle for interface clocks and plls. Also
automatic control of external oscillator through sys_clkreq is
enabled. I think these should be done by clockfw.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 120 ++
1 files changed, 120 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 49e2989..c30a218 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -369,6 +369,126 @@ static void __init prcm_setup_regs(void)
{
u32 v;
+ /* XXX Enable interface clock autoidle for all modules. This
+* should be done by clockfw */
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_MMC3 |
+ OMAP3430ES2_AUTO_ICR |
+ OMAP3430_AUTO_AES2 |
+ OMAP3430_AUTO_SHA12 |
+ OMAP3430_AUTO_DES2 |
+ OMAP3430_AUTO_MMC2 |
+ OMAP3430_AUTO_MMC1 |
+ OMAP3430_AUTO_MSPRO |
+ OMAP3430_AUTO_HDQ |
+ OMAP3430_AUTO_MCSPI4 |
+ OMAP3430_AUTO_MCSPI3 |
+ OMAP3430_AUTO_MCSPI2 |
+ OMAP3430_AUTO_MCSPI1 |
+ OMAP3430_AUTO_I2C3 |
+ OMAP3430_AUTO_I2C2 |
+ OMAP3430_AUTO_I2C1 |
+ OMAP3430_AUTO_UART2 |
+ OMAP3430_AUTO_UART1 |
+ OMAP3430_AUTO_GPT11 |
+ OMAP3430_AUTO_GPT10 |
+ OMAP3430_AUTO_MCBSP5 |
+ OMAP3430_AUTO_MCBSP1 |
+ OMAP3430ES1_AUTO_FAC | /* This is es1 only */
+ OMAP3430_AUTO_MAILBOXES |
+ OMAP3430_AUTO_OMAPCTRL |
+ OMAP3430ES1_AUTO_FSHOSTUSB |
+ OMAP3430_AUTO_HSOTGUSB |
+ OMAP3430ES1_AUTO_D2D | /* This is es1 only */
+ OMAP3430_AUTO_SSI,
+ CORE_MOD, CM_AUTOIDLE1);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_PKA |
+ OMAP3430_AUTO_AES1 |
+ OMAP3430_AUTO_RNG |
+ OMAP3430_AUTO_SHA11 |
+ OMAP3430_AUTO_DES1,
+ CORE_MOD, CM_AUTOIDLE2);
+
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_USBTLL,
+ CORE_MOD, CM_AUTOIDLE3);
+ }
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_WDT2 |
+ OMAP3430_AUTO_WDT1 |
+ OMAP3430_AUTO_GPIO1 |
+ OMAP3430_AUTO_32KSYNC |
+ OMAP3430_AUTO_GPT12 |
+ OMAP3430_AUTO_GPT1 ,
+ WKUP_MOD, CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_DSS,
+ OMAP3430_DSS_MOD,
+ CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_CAM,
+ OMAP3430_CAM_MOD,
+ CM_AUTOIDLE);
+
+ cm_write_mod_reg(
+ OMAP3430_AUTO_GPIO6 |
+ OMAP3430_AUTO_GPIO5 |
+ OMAP3430_AUTO_GPIO4 |
+ OMAP3430_AUTO_GPIO3 |
+ OMAP3430_AUTO_GPIO2 |
+ OMAP3430_AUTO_WDT3 |
+ OMAP3430_AUTO_UART3 |
+ OMAP3430_AUTO_GPT9 |
+ OMAP3430_AUTO_GPT8 |
+ OMAP3430_AUTO_GPT7 |
+ OMAP3430_AUTO_GPT6 |
+ OMAP3430_AUTO_GPT5 |
+ OMAP3430_AUTO_GPT4 |
+ OMAP3430_AUTO_GPT3 |
+ OMAP3430_AUTO_GPT2 |
+ OMAP3430_AUTO_MCBSP4 |
+ OMAP3430_AUTO_MCBSP3 |
+ OMAP3430_AUTO_MCBSP2,
+ OMAP3430_PER_MOD,
+ CM_AUTOIDLE);
+
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ cm_write_mod_reg(
+ OMAP3430ES2_AUTO_USBHOST,
+ OMAP3430ES2_USBHOST_MOD,
+ CM_AUTOIDLE);
+ }
+
+ /* XXX Set all plls to autoidle. This is needed until autoidle is
+* enabled by clockfw */
+ cm_write_mod_reg(1 OMAP3430_CLKTRCTRL_IVA2_SHIFT,
+OMAP3430_IVA2_MOD,
+CM_AUTOIDLE2);
+ cm_write_mod_reg(1 OMAP3430_AUTO_MPU_DPLL_SHIFT,
+MPU_MOD,
+CM_AUTOIDLE2);
+ cm_write_mod_reg((1 OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
+(1 OMAP3430_AUTO_CORE_DPLL_SHIFT),
+PLL_MOD,
+CM_AUTOIDLE);
+ cm_write_mod_reg(1 OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
+PLL_MOD,
+CM_AUTOIDLE2);
+
+ /* XXX Enable control of expternal oscillator through
+* sys_clkreq. I think clockfw should provide means to do this
+ */
+ v = __raw_readl(OMAP3430_PRM_CLKSRC_CTRL);
+ v = ~(OMAP_AUTOEXTCLKMODE_MASK);
+ v |= (1 OMAP_AUTOEXTCLKMODE_SHIFT
[PATCH 10/10] 34XX: PM: Workaround to mask uart clocks when checking active clocks
This workaround mask uart clocks when checking for active clocks. This has an effect that serial console stops to work as dynamic sleep is enabled. Signed-off-by: Jouni Hogander [EMAIL PROTECTED] --- arch/arm/mach-omap2/pm34xx.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index dbc3cf1..1355e0e 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -242,6 +242,8 @@ static int omap3_fclks_active(void) fck_per = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); gpio_fclk_mask(fck_per); + fck_core1 = ~(0x3 13); + fck_per = ~(0x1 11); if (fck_core1 | fck_core3 | fck_sgx | fck_dss | fck_cam | fck_per | fck_usbhost) return 1; -- 1.5.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 04/10] PRCM: Workaround for pwrdn_x control
Clock path should be powered down only after all it's clients are
properly disabled. Generally we don't have working implementation for
checking wether some clock is enabled or disabled.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0742359..443924f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -328,6 +328,7 @@ void omap2_clk_disable(struct clk *clk)
{
if (clk-usecount 0 !(--clk-usecount)) {
_omap2_clk_disable(clk);
+ udelay(10);
if (clk-parent)
omap2_clk_disable(clk-parent);
if (clk-clkdm)
@@ -968,6 +969,10 @@ void omap2_clk_disable_unused(struct clk *clk)
return;
printk(KERN_INFO Disabling unused clock \%s\\n, clk-name);
- _omap2_clk_disable(clk);
+ if (cpu_is_omap34xx()) {
+ omap2_clk_enable(clk);
+ omap2_clk_disable(clk);
+ } else
+ _omap2_clk_disable(clk);
}
#endif
--
1.5.5
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[PATCH 06/10] 34XX: PM: Workaround to reset all wkdeps
This workaround is needed until powerdomain code resets wkdeps.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 20 ++--
1 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c30a218..a5504b7 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -369,6 +369,20 @@ static void __init prcm_setup_regs(void)
{
u32 v;
+ /* XXX Reset all wkdeps. This should be done when initializing
+* powerdomains */
+ prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
+ } else
+ prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
+
/* XXX Enable interface clock autoidle for all modules. This
* should be done by clockfw */
cm_write_mod_reg(
@@ -573,6 +587,10 @@ int __init omap3_pm_init(void)
printk(KERN_ERR Power Management for TI OMAP3.\n);
+ /* XXX prcm_setup_regs needs to be before enabling hw
+* supervised mode for powerdomains */
+ prcm_setup_regs();
+
ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
(irq_handler_t)prcm_interrupt_handler,
IRQF_DISABLED, prcm, NULL);
@@ -599,8 +617,6 @@ int __init omap3_pm_init(void)
suspend_set_ops(omap_pm_ops);
- prcm_setup_regs();
-
pm_idle = omap3_pm_idle;
/* XXX This is for gpio fclk hack. Will be removed as gpio driver
--
1.5.5
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[PATCH] OMAP: SERIAL: Provide function to enable/disable uart clocks
This patch adds common function to enable/disable omap2/3 uart
clocks. Enabled uarts are passed by bootloader in atags and clocks for
these enabled uarts are touched.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/serial.c | 79 ++-
include/asm-arm/arch-omap/common.h |1 +
2 files changed, 33 insertions(+), 47 deletions(-)
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index c9697a4..54ab7af 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -3,7 +3,7 @@
*
* OMAP2 serial support.
*
- * Copyright (C) 2005 Nokia Corporation
+ * Copyright (C) 2005-2008 Nokia Corporation
* Author: Paul Mundt [EMAIL PROTECTED]
*
* Based off of arch/arm/mach-omap/omap1/serial.c
@@ -23,12 +23,8 @@
#include asm/arch/common.h
#include asm/arch/board.h
-static struct clk * uart1_ick = NULL;
-static struct clk * uart1_fck = NULL;
-static struct clk * uart2_ick = NULL;
-static struct clk * uart2_fck = NULL;
-static struct clk * uart3_ick = NULL;
-static struct clk * uart3_fck = NULL;
+static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
+static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
static struct plat_serial8250_port serial_platform_data[] = {
{
@@ -87,10 +83,24 @@ static inline void __init omap_serial_reset(struct
plat_serial8250_port *p)
serial_write_reg(p, UART_OMAP_SYSC, (0x02 3) | (1 2) | (1 0));
}
+void omap_serial_enable_clocks(int enable)
+{
+ int i;
+ for (i = 0; i OMAP_MAX_NR_PORTS; i++) {
+ if (uart_ick[i])
+ enable ? clk_enable(uart_ick[i]) :
+ clk_disable(uart_ick[i]);
+ if (uart_fck[i])
+ enable ? clk_enable(uart_fck[i]) :
+ clk_disable(uart_fck[i]);
+ }
+}
+
void __init omap_serial_init(void)
{
int i;
const struct omap_uart_config *info;
+ char name[16];
/*
* Make sure the serial ports are muxed on at this point.
@@ -112,47 +122,22 @@ void __init omap_serial_init(void)
continue;
}
- switch (i) {
- case 0:
- uart1_ick = clk_get(NULL, uart1_ick);
- if (IS_ERR(uart1_ick))
- printk(Could not get uart1_ick\n);
- else
- clk_enable(uart1_ick);
-
- uart1_fck = clk_get(NULL, uart1_fck);
- if (IS_ERR(uart1_fck))
- printk(Could not get uart1_fck\n);
- else
- clk_enable(uart1_fck);
- break;
- case 1:
- uart2_ick = clk_get(NULL, uart2_ick);
- if (IS_ERR(uart2_ick))
- printk(Could not get uart2_ick\n);
- else
- clk_enable(uart2_ick);
-
- uart2_fck = clk_get(NULL, uart2_fck);
- if (IS_ERR(uart2_fck))
- printk(Could not get uart2_fck\n);
- else
- clk_enable(uart2_fck);
- break;
- case 2:
- uart3_ick = clk_get(NULL, uart3_ick);
- if (IS_ERR(uart3_ick))
- printk(Could not get uart3_ick\n);
- else
- clk_enable(uart3_ick);
-
- uart3_fck = clk_get(NULL, uart3_fck);
- if (IS_ERR(uart3_fck))
- printk(Could not get uart3_fck\n);
- else
- clk_enable(uart3_fck);
- break;
+ sprintf(name, uart%d_ick, i+1);
+ uart_ick[i] = clk_get(NULL, name);
+ if (IS_ERR(uart_ick[i])) {
+ printk(KERN_ERR Could not get uart%d_ick\n, i+1);
+ uart_ick[i] = NULL;
+ }
+ else
+ clk_enable(uart_ick[i]);
+ sprintf(name, uart%d_fck, i+1);
+ uart_fck[i] = clk_get(NULL, name);
+ if (IS_ERR(uart_fck[i])) {
+ printk(KERN_ERR Could not get uart%d_fck\n, i+1);
+ uart_ick[i] = NULL;
}
+ else
+ clk_enable(uart_fck[i]);
omap_serial_reset(p);
}
diff --git a/include/asm-arm/arch-omap/common.h
b/include/asm-arm/arch-omap/common.h
index 36a3b62..6c072de 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -34,6 +34,7 @@ struct sys_timer;
extern void omap_map_common_io(void);
extern struct
