[PATCH 36/54] ARM: omap2: irq_data conversion.
Signed-off-by: Lennert Buytenhek buyt...@secretlab.ca
---
arch/arm/mach-omap2/irq.c | 22 --
1 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 32eeabe..3d17ef6 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -100,13 +100,14 @@ static int omap_check_spurious(unsigned int irq)
}
/* XXX: FIQ and additional INTC support (only MPU at the moment) */
-static void omap_ack_irq(unsigned int irq)
+static void omap_ack_irq(struct irq_data *d)
{
intc_bank_write_reg(0x1, irq_banks[0], INTC_CONTROL);
}
-static void omap_mask_irq(unsigned int irq)
+static void omap_mask_irq(struct irq_data *d)
{
+ unsigned int irq = d-irq;
int offset = irq (~(IRQ_BITS_PER_REG - 1));
if (cpu_is_omap34xx()) {
@@ -128,8 +129,9 @@ static void omap_mask_irq(unsigned int irq)
intc_bank_write_reg(1 irq, irq_banks[0], INTC_MIR_SET0 + offset);
}
-static void omap_unmask_irq(unsigned int irq)
+static void omap_unmask_irq(struct irq_data *d)
{
+ unsigned int irq = d-irq;
int offset = irq (~(IRQ_BITS_PER_REG - 1));
irq = (IRQ_BITS_PER_REG - 1);
@@ -137,17 +139,17 @@ static void omap_unmask_irq(unsigned int irq)
intc_bank_write_reg(1 irq, irq_banks[0], INTC_MIR_CLEAR0 + offset);
}
-static void omap_mask_ack_irq(unsigned int irq)
+static void omap_mask_ack_irq(struct irq_data *d)
{
- omap_mask_irq(irq);
- omap_ack_irq(irq);
+ omap_mask_irq(d);
+ omap_ack_irq(d);
}
static struct irq_chip omap_irq_chip = {
- .name = INTC,
- .ack= omap_mask_ack_irq,
- .mask = omap_mask_irq,
- .unmask = omap_unmask_irq,
+ .name = INTC,
+ .irq_ack= omap_mask_ack_irq,
+ .irq_mask = omap_mask_irq,
+ .irq_unmask = omap_unmask_irq,
};
static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
--
1.7.1
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[PATCH 35/54] ARM: omap1: irq_data conversion.
Signed-off-by: Lennert Buytenhek buyt...@secretlab.ca
---
arch/arm/mach-omap1/ams-delta-fiq.c |8 --
arch/arm/mach-omap1/fpga.c | 28 +++---
arch/arm/mach-omap1/irq.c | 44 +-
3 files changed, 41 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c
b/arch/arm/mach-omap1/ams-delta-fiq.c
index 6c994e2..152b32c 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.c
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -49,7 +49,7 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
irq_desc = irq_to_desc(IH_GPIO_BASE);
if (irq_desc)
- irq_chip = irq_desc-chip;
+ irq_chip = irq_desc-irq_data.chip;
/*
* For each handled GPIO interrupt, keep calling its interrupt handler
@@ -62,13 +62,15 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
while (irq_counter[gpio] fiq_count) {
if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
+ struct irq_data *d = irq_get_irq_data(irq_num);
+
/*
* It looks like handle_edge_irq() that
* OMAP GPIO edge interrupts default to,
* expects interrupt already unmasked.
*/
- if (irq_chip irq_chip-unmask)
- irq_chip-unmask(irq_num);
+ if (irq_chip irq_chip-irq_unmask)
+ irq_chip-irq_unmask(d);
}
generic_handle_irq(irq_num);
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 5cfce16..0de09fa 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -30,9 +30,9 @@
#include plat/fpga.h
#include mach/gpio.h
-static void fpga_mask_irq(unsigned int irq)
+static void fpga_mask_irq(struct irq_data *d)
{
- irq -= OMAP_FPGA_IRQ_BASE;
+ unsigned int irq = d-irq - OMAP_FPGA_IRQ_BASE;
if (irq 8)
__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
@@ -58,14 +58,14 @@ static inline u32 get_fpga_unmasked_irqs(void)
}
-static void fpga_ack_irq(unsigned int irq)
+static void fpga_ack_irq(struct irq_data *d)
{
/* Don't need to explicitly ACK FPGA interrupts */
}
-static void fpga_unmask_irq(unsigned int irq)
+static void fpga_unmask_irq(struct irq_data *d)
{
- irq -= OMAP_FPGA_IRQ_BASE;
+ unsigned int irq = d-irq - OMAP_FPGA_IRQ_BASE;
if (irq 8)
__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 irq)),
@@ -78,10 +78,10 @@ static void fpga_unmask_irq(unsigned int irq)
| (1 (irq - 16))), INNOVATOR_FPGA_IMR2);
}
-static void fpga_mask_ack_irq(unsigned int irq)
+static void fpga_mask_ack_irq(struct irq_data *d)
{
- fpga_mask_irq(irq);
- fpga_ack_irq(irq);
+ fpga_mask_irq(d);
+ fpga_ack_irq(d);
}
void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
@@ -105,17 +105,17 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct
irq_desc *desc)
static struct irq_chip omap_fpga_irq_ack = {
.name = FPGA-ack,
- .ack= fpga_mask_ack_irq,
- .mask = fpga_mask_irq,
- .unmask = fpga_unmask_irq,
+ .irq_ack= fpga_mask_ack_irq,
+ .irq_mask = fpga_mask_irq,
+ .irq_unmask = fpga_unmask_irq,
};
static struct irq_chip omap_fpga_irq = {
.name = FPGA,
- .ack= fpga_ack_irq,
- .mask = fpga_mask_irq,
- .unmask = fpga_unmask_irq,
+ .irq_ack= fpga_ack_irq,
+ .irq_mask = fpga_mask_irq,
+ .irq_unmask = fpga_unmask_irq,
};
/*
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index db913c3..c2cfb27 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -70,48 +70,48 @@ static inline void irq_bank_writel(unsigned long value, int
bank, int offset)
omap_writel(value, irq_banks[bank].base_reg + offset);
}
-static void omap_ack_irq(unsigned int irq)
+static void omap_ack_irq(struct irq_data *d)
{
- if (irq 31)
+ if (d-irq 31)
omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
}
-static void omap_mask_irq(unsigned int irq)
+static void omap_mask_irq(struct irq_data *d)
{
- int bank = IRQ_BANK(irq);
+ int bank = IRQ_BANK(d-irq);
u32 l;
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
- l |= 1 IRQ_BIT(irq);
+ l |= 1 IRQ_BIT(d-irq);
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
}
-static void
[PATCH 51/54] ARM: plat-omap: irq_data conversion.
Signed-off-by: Lennert Buytenhek buyt...@secretlab.ca
---
arch/arm/plat-omap/gpio.c | 93 ++---
1 files changed, 46 insertions(+), 47 deletions(-)
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index c05c653..1e83b6b 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -878,17 +878,17 @@ bad:
return -EINVAL;
}
-static int gpio_irq_type(unsigned irq, unsigned type)
+static int gpio_irq_type(struct irq_data *d, unsigned type)
{
struct gpio_bank *bank;
unsigned gpio;
int retval;
unsigned long flags;
- if (!cpu_class_is_omap2() irq IH_MPUIO_BASE)
- gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
+ if (!cpu_class_is_omap2() d-irq IH_MPUIO_BASE)
+ gpio = OMAP_MPUIO(d-irq - IH_MPUIO_BASE);
else
- gpio = irq - IH_GPIO_BASE;
+ gpio = d-irq - IH_GPIO_BASE;
if (check_gpio(gpio) 0)
return -EINVAL;
@@ -901,19 +901,19 @@ static int gpio_irq_type(unsigned irq, unsigned type)
(type (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
return -EINVAL;
- bank = get_irq_chip_data(irq);
+ bank = irq_data_get_irq_chip_data(d);
spin_lock_irqsave(bank-lock, flags);
retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
if (retval == 0) {
- irq_desc[irq].status = ~IRQ_TYPE_SENSE_MASK;
- irq_desc[irq].status |= type;
+ irq_desc[d-irq].status = ~IRQ_TYPE_SENSE_MASK;
+ irq_desc[d-irq].status |= type;
}
spin_unlock_irqrestore(bank-lock, flags);
if (type (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
- __set_irq_handler_unlocked(irq, handle_level_irq);
+ __set_irq_handler_unlocked(d-irq, handle_level_irq);
else if (type (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
- __set_irq_handler_unlocked(irq, handle_edge_irq);
+ __set_irq_handler_unlocked(d-irq, handle_edge_irq);
return retval;
}
@@ -1170,15 +1170,15 @@ static void _reset_gpio(struct gpio_bank *bank, int
gpio)
}
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
-static int gpio_wake_enable(unsigned int irq, unsigned int enable)
+static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
{
- unsigned int gpio = irq - IH_GPIO_BASE;
+ unsigned int gpio = d-irq - IH_GPIO_BASE;
struct gpio_bank *bank;
int retval;
if (check_gpio(gpio) 0)
return -ENODEV;
- bank = get_irq_chip_data(irq);
+ bank = irq_data_get_irq_chip_data(d);
retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
return retval;
@@ -1291,7 +1291,7 @@ static void gpio_irq_handler(unsigned int irq, struct
irq_desc *desc)
u32 retrigger = 0;
int unmasked = 0;
- desc-chip-ack(irq);
+ desc-irq_data.chip-irq_ack(desc-irq_data);
bank = get_irq_data(irq);
#ifdef CONFIG_ARCH_OMAP1
@@ -1343,7 +1343,7 @@ static void gpio_irq_handler(unsigned int irq, struct
irq_desc *desc)
configured, we could unmask GPIO bank interrupt immediately */
if (!level_mask !unmasked) {
unmasked = 1;
- desc-chip-unmask(irq);
+ desc-irq_data.chip-irq_unmask(desc-irq_data);
}
isr |= retrigger;
@@ -1378,41 +1378,40 @@ static void gpio_irq_handler(unsigned int irq, struct
irq_desc *desc)
handler(s) are executed in order to avoid spurious bank
interrupt */
if (!unmasked)
- desc-chip-unmask(irq);
-
+ desc-irq_data.chip-irq_unmask(desc-irq_data);
}
-static void gpio_irq_shutdown(unsigned int irq)
+static void gpio_irq_shutdown(struct irq_data *d)
{
- unsigned int gpio = irq - IH_GPIO_BASE;
- struct gpio_bank *bank = get_irq_chip_data(irq);
+ unsigned int gpio = d-irq - IH_GPIO_BASE;
+ struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
_reset_gpio(bank, gpio);
}
-static void gpio_ack_irq(unsigned int irq)
+static void gpio_ack_irq(struct irq_data *d)
{
- unsigned int gpio = irq - IH_GPIO_BASE;
- struct gpio_bank *bank = get_irq_chip_data(irq);
+ unsigned int gpio = d-irq - IH_GPIO_BASE;
+ struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
_clear_gpio_irqstatus(bank, gpio);
}
-static void gpio_mask_irq(unsigned int irq)
+static void gpio_mask_irq(struct irq_data *d)
{
- unsigned int gpio = irq - IH_GPIO_BASE;
- struct gpio_bank *bank = get_irq_chip_data(irq);
+ unsigned int gpio = d-irq - IH_GPIO_BASE;
+ struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
_set_gpio_irqenable(bank, gpio, 0);
_set_gpio_triggering
Re: [PATCH] ARM TLB: add v7wbi_{possible,always}_flags to {possible,always}_tlb_flags
On Mon, Aug 11, 2008 at 02:03:10PM -0600, Paul Walmsley wrote: Commit 2ccdd1e77da52ad494e9af46bf272d816830cb28 doesn't add v7wbi_possible_flags and v7wbi_always_flags to possible_tlb_flags and always_tlb_flags. This causes the L2 cache flush in clean_pmd_entry() (intended for Feroceon only) to execute on ARMv7, and the CPU hangs. This patch is required for OMAP3 boards to boot. Signed-off-by: Paul Walmsley [EMAIL PROTECTED] Cc: [EMAIL PROTECTED] Cc: [EMAIL PROTECTED] Acked-by: Lennert Buytenhek [EMAIL PROTECTED] -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] MTD: OMAP2-NAND: Fix partition reading from board info
On Mon, Aug 04, 2008 at 01:02:46PM -0700, David Brownell wrote: Looks like this driver does not exist outside linux-omap tree, care to send the whole driver to MTD list? Unless someone created a big-endian OMAP, Don't they use standard ARM ARM cores, which can all be used in both LE and BE modes? -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] MTD: OMAP2-NAND: Fix partition reading from board info
On Mon, Aug 04, 2008 at 01:26:38PM -0700, David Brownell wrote: Looks like this driver does not exist outside linux-omap tree, care to send the whole driver to MTD list? Unless someone created a big-endian OMAP, Don't they use standard ARM ARM cores, which can all be used in both LE and BE modes? And when those cores turn into silicon, the choice is usually hard-wired. I've never seen CPU endianity being hardwired in any ARM system ever -- but maybe OMAP is different. (Out of all the ARM subarchs supported in the kernel right now, I've had ep93xx'es, iop13xx'es, iop32x'es, iop33x'es, ixp2000s, ixp23xx'es, ixp4xx'es, kirkwoods, mv78xx0's, and orion5x'es all running in BE mode at some point.) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] MTD: OMAP2-NAND: Fix partition reading from board info
On Mon, Aug 04, 2008 at 04:23:35PM -0500, Woodruff, Richard wrote: The most visible BE-ARM seems to be Intel's IXP network processors. The IXPs are one of the few cases where the vendors _ships an all-BE software development environment by default_ -- but that doesn't mean that BE doesn't work on ARM CPUs where the vendor ships a LE software development environment by default (BE has certainly worked on all ARM CPUs I've ever tried it on). -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] MTD: OMAP2-NAND: Fix partition reading from board info
On Mon, Aug 04, 2008 at 02:37:34PM -0700, David Brownell wrote: I've never seen CPU endianity being hardwired in any ARM system ever -- but maybe OMAP is different. I'll let TI answer that one, since I'm not going to look at docs for all the ARM's I've ever used. My observation stands *REGARDLESS* of whether endianness was fixed in hardware, bootloader, or kernel ... and in any case, with very few exceptions (not including OMAP), Linux uses ARMs in LE mode: ~/kernel/linux-2.6/arch/arm/configs$ grep ENDIAN * | egrep -v '#' |egrep -v OHCI ixp2000_defconfig:CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y ixp2000_defconfig:CONFIG_CPU_BIG_ENDIAN=y ixp23xx_defconfig:CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y ixp23xx_defconfig:CONFIG_CPU_BIG_ENDIAN=y ixp4xx_defconfig:CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y ixp4xx_defconfig:CONFIG_CPU_BIG_ENDIAN=y ~/kernel/linux-2.6/arch/arm/configs$ ls | wc -l 105 ~/kernel/linux-2.6/arch/arm/configs$ That's just because not many people ask for BE or use BE -- not because the LE'ness would be hardwired in hardware as you asserted earlier. To repeat: there's no point in having the words byteswapped when writing, then again when reading, like this driver does. All that does is ensure slow I/O paths. Were you disagreeing with that main point? Or just quibbling about where any unusual big-endianness might come from? I was responding to your statement that ARM CPU endianity is hardwired when ARM cores are turned into silicon. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] MTD: OMAP2-NAND: Fix partition reading from board info
On Mon, Aug 04, 2008 at 04:45:19PM -0500, Woodruff, Richard wrote: The most visible BE-ARM seems to be Intel's IXP network processors. The IXPs are one of the few cases where the vendors _ships an all-BE software development environment by default_ -- but that doesn't mean that BE doesn't work on ARM CPUs where the vendor ships a LE software development environment by default (BE has certainly worked on all ARM CPUs I've ever tried it on). I wonder how many shipping systems use LE. A grep of current ARM Linux Kconfig's only shows 3 IXP systems setting CONFIG_CPU_BIG_ENDIAN. Perhaps you are correct about ability but few seem to use it. Seems like a trivia question for ARM Ltd. At any rate all OMAPs have been hardwired. Hmmm. So bit [7] of the system control register is ignored entirely, and if you write a 1 to it, nothing at all happens and the system boots as usual? (To test, add a line OBJS += big-endian.o to the top of arch/arm/boot/compressed/Makefile.) Does it also mean that the ARMv6 based OMAPs have the SETEND instruction behave as NOPs? -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
