[PATCH v1 0/3] OMAP: DSS2: Fix for DISPC core functional clock divider

2011-03-03 Thread Raghuveer Murthy 
OMAP4 has 2 LCD channels and corresponding DISPC_DIVISOR1 and DISPC_DIVISOR2
registers to configure the pixel clock frequency, for the respective LCD 
displays.

There is also DISPC_DIVISOR register, which by default has the ENABLE bit 
set to zero, for backward compatibility mode. Hence the logical clock divider of
DISPC_DIVISOR1.LCD, gets used for core func clk configuration. The default value
of DISPC_DIVISOR1.LCD is 4.

If only the secondary LCD is enabled, at high pixel resolutions the core clk 
lags behind the pixel clock, causing stair-step effect (diagonal lines with
tearing) on the display.

Hence DISPC_DIVISOR.ENABLE is set to 1, and the core functional clock is set 
independently and exclusively in DISPC_DIVISOR.LCD.

- Added the above as dss_features

-
History
---
Changes from previous version (v1)
- Fixed comments from Tomi Valkeinen tomi.valkei...@ti.com

Base

url = git://gitorious.org/linux-omap-dss2/linux.git
branch master
commit 1e0f79f1066aba3cfcaa45a0298bb24ba7bf864d 

-
Raghuveer Murthy (3):
  OMAP: DSS2: Adding dss_features for independent core clk divider
  OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch)
  OMAP4: DSS2: Using dss_features to set independent core clock divider

 drivers/video/omap2/dss/dispc.c|   51 +++
 drivers/video/omap2/dss/dss_features.c |2 +-
 drivers/video/omap2/dss/dss_features.h |2 +
 3 files changed, 41 insertions(+), 14 deletions(-)

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[PATCH v1 2/3] OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch)

2011-03-03 Thread Raghuveer Murthy 
The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK
independent of Primary and Secondary display clocks.

Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction
of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers
DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2.

Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch).
Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be
configured

OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and
DISPC_DIVISOR2

Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 drivers/video/omap2/dss/dispc.c |   27 ++-
 1 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 43f7091..11b2b04 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -73,7 +73,7 @@ struct dispc_reg { u16 idx; };
 #define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
 #define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
 #define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
-#define DISPC_DIVISOR(ch)  DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
+#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
 #define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
 #define DISPC_SIZE_DIG DISPC_REG(0x0078)
 #define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
@@ -128,6 +128,7 @@ struct dispc_reg { u16 idx; };
 
 #define DISPC_VID_PRELOAD(n)   DISPC_REG(0x230 + (n)*0x04)
 
+#define DISPC_DIVISOR  DISPC_REG(0x0804)
 
 #define DISPC_IRQ_MASK_ERROR(DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 DISPC_IRQ_OCP_ERR | \
@@ -231,7 +232,7 @@ void dispc_save_context(void)
SR(TIMING_H(0));
SR(TIMING_V(0));
SR(POL_FREQ(0));
-   SR(DIVISOR(0));
+   SR(DIVISORo(0));
SR(GLOBAL_ALPHA);
SR(SIZE_DIG);
SR(SIZE_LCD(0));
@@ -243,7 +244,7 @@ void dispc_save_context(void)
SR(TIMING_H(2));
SR(TIMING_V(2));
SR(POL_FREQ(2));
-   SR(DIVISOR(2));
+   SR(DIVISORo(2));
SR(CONFIG2);
}
 
@@ -390,7 +391,7 @@ void dispc_restore_context(void)
RR(TIMING_H(0));
RR(TIMING_V(0));
RR(POL_FREQ(0));
-   RR(DIVISOR(0));
+   RR(DIVISORo(0));
RR(GLOBAL_ALPHA);
RR(SIZE_DIG);
RR(SIZE_LCD(0));
@@ -401,7 +402,7 @@ void dispc_restore_context(void)
RR(TIMING_H(2));
RR(TIMING_V(2));
RR(POL_FREQ(2));
-   RR(DIVISOR(2));
+   RR(DIVISORo(2));
RR(CONFIG2);
}
 
@@ -2294,7 +2295,7 @@ static void dispc_set_lcd_divisor(enum omap_channel 
channel, u16 lck_div,
BUG_ON(pck_div  2);
 
enable_clocks(1);
-   dispc_write_reg(DISPC_DIVISOR(channel),
+   dispc_write_reg(DISPC_DIVISORo(channel),
FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
enable_clocks(0);
 }
@@ -2303,7 +2304,7 @@ static void dispc_get_lcd_divisor(enum omap_channel 
channel, int *lck_div,
int *pck_div)
 {
u32 l;
-   l = dispc_read_reg(DISPC_DIVISOR(channel));
+   l = dispc_read_reg(DISPC_DIVISORo(channel));
*lck_div = FLD_GET(l, 23, 16);
*pck_div = FLD_GET(l, 7, 0);
 }
@@ -2329,7 +2330,7 @@ unsigned long dispc_lclk_rate(enum omap_channel channel)
unsigned long r;
u32 l;
 
-   l = dispc_read_reg(DISPC_DIVISOR(channel));
+   l = dispc_read_reg(DISPC_DIVISORo(channel));
 
lcd = FLD_GET(l, 23, 16);
 
@@ -2344,7 +2345,7 @@ unsigned long dispc_pclk_rate(enum omap_channel channel)
unsigned long r;
u32 l;
 
-   l = dispc_read_reg(DISPC_DIVISOR(channel));
+   l = dispc_read_reg(DISPC_DIVISORo(channel));
 
lcd = FLD_GET(l, 23, 16);
pcd = FLD_GET(l, 7, 0);
@@ -2460,7 +2461,7 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_TIMING_H(0));
DUMPREG(DISPC_TIMING_V(0));
DUMPREG(DISPC_POL_FREQ(0));
-   DUMPREG(DISPC_DIVISOR(0));
+   DUMPREG(DISPC_DIVISORo(0));
DUMPREG(DISPC_GLOBAL_ALPHA);
DUMPREG(DISPC_SIZE_DIG);
DUMPREG(DISPC_SIZE_LCD(0));
@@ -2472,7 +2473,7 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_TIMING_H(2));
DUMPREG(DISPC_TIMING_V(2));
DUMPREG(DISPC_POL_FREQ(2));
-   DUMPREG(DISPC_DIVISOR(2));
+   DUMPREG(DISPC_DIVISORo(2));
DUMPREG(DISPC_SIZE_LCD(2));
}
 
@@ -2714,8 +2715,8 @@ int dispc_get_clock_div(enum omap_channel channel,
 
fck

[PATCH v3 1/3] OMAP: DSS2: Adding dss_features for independent core clk divider

2011-03-03 Thread Raghuveer Murthy 
In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div)
field. The lcd_div is common, for deciding the DISPC core functional clock
frequency, and the final pixel clock frequency for LCD display.

In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1
and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR.

The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core
functional clock configuration. For pixel clock configuration of primary and
secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used
respectively

Signed-off-by: Archit Taneja arc...@ti.com
Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 drivers/video/omap2/dss/dss_features.c |3 ++-
 drivers/video/omap2/dss/dss_features.h |2 ++
 2 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/video/omap2/dss/dss_features.c 
b/drivers/video/omap2/dss/dss_features.c
index ccae57b..dc170ad 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -234,7 +234,8 @@ static struct omap_dss_features omap4_dss_features = {
 
.has_feature=
FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
-   FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1,
+   FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
+   FEAT_CORE_CLK_DIV,
 
.num_mgrs = 3,
.num_ovls = 3,
diff --git a/drivers/video/omap2/dss/dss_features.h 
b/drivers/video/omap2/dss/dss_features.h
index 65d6de7..569d1b2 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -36,6 +36,8 @@ enum dss_feat_id {
FEAT_LINEBUFFERSPLIT= 1  8,
FEAT_ROWREPEATENABLE= 1  9,
FEAT_RESIZECONF = 1  10,
+   /* Independent core clk divider */
+   FEAT_CORE_CLK_DIV   = 1  11,
 };
 
 /* DSS register field id */
-- 
1.7.0.4

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[PATCH v3 0/3] OMAP: DSS2: Fix for DISPC core functional clock divider

2011-03-03 Thread Raghuveer Murthy 
OMAP4 has 2 LCD channels and corresponding DISPC_DIVISOR1 and DISPC_DIVISOR2
registers to configure the pixel clock frequency, for the respective LCD
displays.

There is also DISPC_DIVISOR register, which by default has the ENABLE bit
set to zero, for backward compatibility mode. Hence the logical clock divider of
DISPC_DIVISOR1.LCD, gets used for core func clk configuration. The default value
of DISPC_DIVISOR1.LCD is 4.

If only the secondary LCD is enabled, at high pixel resolutions the core clk 
lags behind the pixel clock, causing stair-step effect (diagonal lines with
tearing) on the display.

Hence DISPC_DIVISOR.ENABLE is set to 1, and the core functional clock is set 
independently and exclusively in DISPC_DIVISOR.LCD.

- Added the above as dss_features

-
History
---
Changes from previous version (v1)
- Fixed comments from Tomi Valkeinen tomi.valkei...@ti.com

Changes from previous version (v2)
- Rebased against the DSS2 master to avoid conflicts 

Base

url = git://gitorious.org/linux-omap-dss2/linux.git
branch master
commit a2792bb44d45ef97963e67565ad1e1dd5bf0cbd7

-
Raghuveer Murthy (3):
  OMAP: DSS2: Adding dss_features for independent core clk divider
  OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch)
  OMAP4: DSS2: Using dss_features to set independent core clock divider

 drivers/video/omap2/dss/dispc.c|   51 +++
 drivers/video/omap2/dss/dss_features.c |3 +-
 drivers/video/omap2/dss/dss_features.h |2 +
 3 files changed, 42 insertions(+), 14 deletions(-)

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[PATCH v3 3/3] OMAP4: DSS2: Using dss_features to set independent core clock divider

2011-03-03 Thread Raghuveer Murthy 
Using dss_features to select independent core clock divider and setting
it. Added the register used, to DISPC context save and restore group

---
In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as:

DISPC_CORE_CLK = max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...)

Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the
maximum horizontal downscaling done through MANAGERi

Based on the usecase, core clk can be increased or decreased at runtime
to save power. Such mechanism are not yet implemented. Hence, we set the
core clock divisor to 1, to support maximum range of resolutions


Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 drivers/video/omap2/dss/dispc.c |   24 
 1 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index a3dff5f..dae9686 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -375,6 +375,9 @@ void dispc_save_context(void)
SR(VID_FIR_COEF_V(1, 7));
 
SR(VID_PRELOAD(1));
+
+   if (dss_has_feature(FEAT_CORE_CLK_DIV))
+   SR(DIVISOR);
 }
 
 void dispc_restore_context(void)
@@ -534,6 +537,9 @@ void dispc_restore_context(void)
 
RR(VID_PRELOAD(1));
 
+   if (dss_has_feature(FEAT_CORE_CLK_DIV))
+   RR(DIVISOR);
+
/* enable last, because LCD  DIGIT enable are here */
RR(CONTROL);
if (dss_has_feature(FEAT_MGR_LCD2))
@@ -2380,6 +2386,7 @@ unsigned long dispc_pclk_rate(enum omap_channel channel)
 void dispc_dump_clocks(struct seq_file *s)
 {
int lcd, pcd;
+   u32 l;
enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
 
enable_clocks(1);
@@ -2392,6 +2399,14 @@ void dispc_dump_clocks(struct seq_file *s)
 
seq_printf(s, fck\t\t%-16lu\n, dispc_fclk_rate());
 
+   if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
+   seq_printf(s, - DISPC-CORE-CLK -\n);
+   l = dispc_read_reg(DISPC_DIVISOR);
+   lcd = FLD_GET(l, 23, 16);
+
+   seq_printf(s, lck\t\t%-16lulck div\t%u\n,
+   (dispc_fclk_rate()/lcd), lcd);
+   }
seq_printf(s, - LCD1 -\n);
 
dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, lcd, pcd);
@@ -3287,6 +3302,15 @@ static void _omap_dispc_initial_config(void)
l = FLD_MOD(l, 1, 0, 0);/* AUTOIDLE */
dispc_write_reg(DISPC_SYSCONFIG, l);
 
+   /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
+   if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
+   l = dispc_read_reg(DISPC_DIVISOR);
+   /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
+   l = FLD_MOD(l, 1, 0, 0);
+   l = FLD_MOD(l, 1, 23, 16);
+   dispc_write_reg(DISPC_DIVISOR, l);
+   }
+
/* FUNCGATED */
if (dss_has_feature(FEAT_FUNCGATED))
REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
-- 
1.7.0.4

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[PATCH v3 2/3] OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch)

2011-03-03 Thread Raghuveer Murthy 
The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK
independent of Primary and Secondary display clocks.

Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction
of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers
DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2.

Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch).
Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be
configured

OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and
DISPC_DIVISOR2

Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 drivers/video/omap2/dss/dispc.c |   27 ++-
 1 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 9fb11c1..a3dff5f 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -73,7 +73,7 @@ struct dispc_reg { u16 idx; };
 #define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
 #define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
 #define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
-#define DISPC_DIVISOR(ch)  DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
+#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
 #define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
 #define DISPC_SIZE_DIG DISPC_REG(0x0078)
 #define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
@@ -128,6 +128,7 @@ struct dispc_reg { u16 idx; };
 
 #define DISPC_VID_PRELOAD(n)   DISPC_REG(0x230 + (n)*0x04)
 
+#define DISPC_DIVISOR  DISPC_REG(0x0804)
 
 #define DISPC_IRQ_MASK_ERROR(DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 DISPC_IRQ_OCP_ERR | \
@@ -231,7 +232,7 @@ void dispc_save_context(void)
SR(TIMING_H(0));
SR(TIMING_V(0));
SR(POL_FREQ(0));
-   SR(DIVISOR(0));
+   SR(DIVISORo(0));
SR(GLOBAL_ALPHA);
SR(SIZE_DIG);
SR(SIZE_LCD(0));
@@ -243,7 +244,7 @@ void dispc_save_context(void)
SR(TIMING_H(2));
SR(TIMING_V(2));
SR(POL_FREQ(2));
-   SR(DIVISOR(2));
+   SR(DIVISORo(2));
SR(CONFIG2);
}
 
@@ -390,7 +391,7 @@ void dispc_restore_context(void)
RR(TIMING_H(0));
RR(TIMING_V(0));
RR(POL_FREQ(0));
-   RR(DIVISOR(0));
+   RR(DIVISORo(0));
RR(GLOBAL_ALPHA);
RR(SIZE_DIG);
RR(SIZE_LCD(0));
@@ -401,7 +402,7 @@ void dispc_restore_context(void)
RR(TIMING_H(2));
RR(TIMING_V(2));
RR(POL_FREQ(2));
-   RR(DIVISOR(2));
+   RR(DIVISORo(2));
RR(CONFIG2);
}
 
@@ -2316,7 +2317,7 @@ static void dispc_set_lcd_divisor(enum omap_channel 
channel, u16 lck_div,
BUG_ON(pck_div  2);
 
enable_clocks(1);
-   dispc_write_reg(DISPC_DIVISOR(channel),
+   dispc_write_reg(DISPC_DIVISORo(channel),
FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
enable_clocks(0);
 }
@@ -2325,7 +2326,7 @@ static void dispc_get_lcd_divisor(enum omap_channel 
channel, int *lck_div,
int *pck_div)
 {
u32 l;
-   l = dispc_read_reg(DISPC_DIVISOR(channel));
+   l = dispc_read_reg(DISPC_DIVISORo(channel));
*lck_div = FLD_GET(l, 23, 16);
*pck_div = FLD_GET(l, 7, 0);
 }
@@ -2351,7 +2352,7 @@ unsigned long dispc_lclk_rate(enum omap_channel channel)
unsigned long r;
u32 l;
 
-   l = dispc_read_reg(DISPC_DIVISOR(channel));
+   l = dispc_read_reg(DISPC_DIVISORo(channel));
 
lcd = FLD_GET(l, 23, 16);
 
@@ -2366,7 +2367,7 @@ unsigned long dispc_pclk_rate(enum omap_channel channel)
unsigned long r;
u32 l;
 
-   l = dispc_read_reg(DISPC_DIVISOR(channel));
+   l = dispc_read_reg(DISPC_DIVISORo(channel));
 
lcd = FLD_GET(l, 23, 16);
pcd = FLD_GET(l, 7, 0);
@@ -2483,7 +2484,7 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_TIMING_H(0));
DUMPREG(DISPC_TIMING_V(0));
DUMPREG(DISPC_POL_FREQ(0));
-   DUMPREG(DISPC_DIVISOR(0));
+   DUMPREG(DISPC_DIVISORo(0));
DUMPREG(DISPC_GLOBAL_ALPHA);
DUMPREG(DISPC_SIZE_DIG);
DUMPREG(DISPC_SIZE_LCD(0));
@@ -2495,7 +2496,7 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_TIMING_H(2));
DUMPREG(DISPC_TIMING_V(2));
DUMPREG(DISPC_POL_FREQ(2));
-   DUMPREG(DISPC_DIVISOR(2));
+   DUMPREG(DISPC_DIVISORo(2));
DUMPREG(DISPC_SIZE_LCD(2));
}
 
@@ -2737,8 +2738,8 @@ int dispc_get_clock_div(enum omap_channel channel,
 
fck

Re: [PATCH v1 0/3] OMAP: DSS2: Fix for DISPC core functional clock divider

2011-03-03 Thread Raghuveer Murthy 

On Thursday 03 March 2011 06:46 PM, Valkeinen, Tomi wrote:

On Thu, 2011-03-03 at 15:25 +0530, Raghuveer Murthy wrote:

OMAP4 has 2 LCD channels and corresponding DISPC_DIVISOR1 and DISPC_DIVISOR2
registers to configure the pixel clock frequency, for the respective LCD
displays.

There is also DISPC_DIVISOR register, which by default has the ENABLE bit
set to zero, for backward compatibility mode. Hence the logical clock divider of
DISPC_DIVISOR1.LCD, gets used for core func clk configuration. The default value
of DISPC_DIVISOR1.LCD is 4.

If only the secondary LCD is enabled, at high pixel resolutions the core clk
lags behind the pixel clock, causing stair-step effect (diagonal lines with
tearing) on the display.

Hence DISPC_DIVISOR.ENABLE is set to 1, and the core functional clock is set
independently and exclusively in DISPC_DIVISOR.LCD.


I think this patch set is ok. However, it doesn't apply with the latest
master branch from DSS tree, some quite trivial conflicts with dss
features. Can you rebase and post it?

Also, please send patches to my ti.com address, not iki.fi address.

  Tomi



Hi Tomi,

Resent the after re-basing.

Regards,
Raghuveer

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Re: [PATCH 0/4] OMAP4: DSS2: Adding fclk support for DPI interface

2011-02-18 Thread Raghuveer Murthy 

On Friday 18 February 2011 12:46 AM, Valkeinen, Tomi wrote:

On Thu, 2011-02-17 at 08:49 -0600, Paul Walmsley wrote:

On Wed, 16 Feb 2011, Raghuveer Murthy wrote:



snip



DPLL_PER post divider output for DSS core functional clock can be changed in
OMAP3xxx and OMAP4430, based on the requested pixel clock for a given display
resolution.

Additionally, the number of dividers available for DPLL_PER post dividors for
DSS has increased from 16 to 32, from OMAP3630 onwards.

Both these are added as dss_features.

Given the above comments from Tomi, can the same be included as part of the
clock framework?


Have you considered just calling clk_round_rate() on the DPLL_PER's output
divider and seeing if you can get a rate that you're happy with?


Hmm, yes, perhaps that would be possible.

Currently we iterate suitable clocks by going through all fck dividers,
then lck dividers and then pck dividers, and checking if one of the
resulting pixel clocks is close to the required one.

But we could start with the required pck, and go up from there with
pck dividers, lck dividers, and in the end using clk_round_rate() to see
if the set of dividers is possible.

And we know the maximum allowed fck rate, so we can use that as a
ceiling and forget any divider sets that lead to too high clocks.

This will probably need a bit more iterations, though, as we may be
trying multiple divider sets leading to the same fck rate, because the
code doesn't have any idea what the possible rates are.

I trust clk_round_rate() is quite simple function (ie. fast)?

  Tomi



I will look into this and come with a solution.

Regards,
Raghuveer
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Re: [PATCH 0/4] OMAP4: DSS2: Adding fclk support for DPI interface

2011-02-16 Thread Raghuveer Murthy 

On Monday 14 February 2011 09:32 PM, Valkeinen, Tomi wrote:

Hi,

On Thu, 2011-02-03 at 07:56 -0600, Murthy, Raghuveer wrote:

- Adding dss_feature for DPLL fclk
- Enabling pixel clock generation for DPI interface


A bit more description what the patch set is about would be nice. Also,
one line patch descriptions are a bit too short for anything else than
the most trivial patches.

Now to the actual patch contents:

DPLL is not a feature of the DSS, and I don't think we should have
dss_features for that. In fact, I think the whole DPLL code should be
moved from DSS to somewhere under arch/arm.

In a perfect world DSS could just set the dss_fck to whatever rate it
requires, but as the clock rate can only be set to certain rates, and we
need a precise control for the rate, some other method has to be in
place.

I am not sure what this method should be. Perhaps there is something in
the clock framework that could help us here, or perhaps we just need a
bunch of function pointers in the DSS's platform data which can be used
to configure the clock.

  Tomi




Hi Paul, Benoit,

DPLL_PER post divider output for DSS core functional clock can be 
changed in OMAP3xxx and OMAP4430, based on the requested pixel clock for 
a given display resolution.


Additionally, the number of dividers available for DPLL_PER post 
dividors for DSS has increased from 16 to 32, from OMAP3630 onwards.


Both these are added as dss_features.

Given the above comments from Tomi, can the same be included as part of 
the clock framework?


Regards,
Raghuveer
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Re: [3/4] OMAP: DSS2: Adding macro for DISPC_DIVISOR register

2011-02-16 Thread Raghuveer Murthy 

On Wednesday 16 February 2011 09:13 PM, Valkeinen, Tomi wrote:

On Thu, 2011-02-03 at 14:09 +, Raghuveer Murthy wrote:

Added macro for DISPC_DIVISOR. This is different from DISPC_DIVISOR1 and
DISPC_DIVISOR2. OMAP4 supports all the above 3 registers.

DISPC_DIVISOR1 and DISPC_DIVISOR2 registers are accessed through
DISPC_DIVISORo(ch) macro

Signed-off-by: Raghuveer Murthyraghuveer.mur...@ti.com

---
drivers/video/omap2/dss/dispc.c |   11 +++
  1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index e52a413..6225d12 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -132,6 +132,17 @@ struct dispc_reg { u16 idx; };

  #define DISPC_VID_PRELOAD(n)  DISPC_REG(0x230 + (n)*0x04)

+/*
+ * The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
+ * However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK.
+ * This allows DISPC_CORE_CLK to be independent of logical clock dividers (lcd)
+ * of LCD1 (primary) and LCD2 (secondary) displays.
+ *
+ * To derive pixel clocks for Primary and Secondary LCD channels, configure the
+ * lcd and pcd in DISPC_DIVISOR1 and DISPC_DIVISOR2 respectively, using the
+ * DISPC_DIVISORo(ch).
+ */
+#define DISPC_DIVISOR  DISPC_REG(0x0804)

  #define DISPC_IRQ_MASK_ERROR(DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 DISPC_IRQ_OCP_ERR | \


See my comment about comments in previous mail.

I think you should merge this and the next patch. There's not much point
in adding a single line define, which is not used (yet).

How about the debug output from debug/omapdss/clk file? Does it print
sensible things on OMAP4 after these patches?


Will verify this.


  Tomi




Acknowledge the comments for patch 2/4 and 3/4. Will merge them and post 
a new series.


Regards,
Raghuveer
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[PATCH] OMAP4: PandaBoard: Adding DVI support

2011-02-09 Thread Raghuveer Murthy 
Adding DVI support to OMAP4 PandaBoard.

PandaBoard uses TFP410 DVI Framer chip
http://focus.ti.com/lit/ds/symlink/tfp410.pdf

The TFP410 gets its power enable and display data over GPIO lines muxed
in from OMAP4430. PandaBoard supports other LCD displays through expansion
connectors, following board rework. This will disable the DVI interface.
However, the existing mux settings remain the same

PandaBoard additionally supports display over HDMI interface. It is
mutually exclusive to display over DVI. Hence the mux settings need to be
configured seperately, as and when HDMI is enabled

Also, I2C3 bus used for reading EDID data from DVI Monitors is
registered here. Since the design is similar to BeagleBoard, the code
for the same is taken from the kernel.org commit ef48dd5cb21
(omap: Adding beagle i2c eeprom driver to read EDID)

Reviewed-by: Manjunath G Kondaiah manj...@ti.com
Reviewed-by: Anand Gadiyar gadi...@ti.com 
Reviewed-by: Nishanth Menon n...@ti.com
Reviewed-by: Sumit Semwal sumit.sem...@ti.com
Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---

Base

url =
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
branch master
commit 100b33c8bd8a3235fd0b7948338d6cbb3db3c63d
tag 2.6.38-rc4

Applies over:
=
1.
v10 of OMAP2,3 DSS2 HWMOD
https://patchwork.kernel.org/patch/500191/

2.
v3 of DSS2: Generalize clock names
https://patchwork.kernel.org/patch/520191/

3.
v3 of DSS2: OMAP4 DSS HWMOD :
https://patchwork.kernel.org/patch/511211/

4.
OMAP: DSS2: Common IRQ handler for all OMAPs
https://patchwork.kernel.org/patch/526241/

5.
OMAP4: DSS2: Adding fclk support for DPI interface
https://patchwork.kernel.org/patch/529381/

6.
OMAP: DSS2: Adding dss_features for independent core clk divider
https://patchwork.kernel.org/patch/529561/
=

 arch/arm/mach-omap2/board-omap4panda.c |  137 +++-
 1 files changed, 136 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap4panda.c 
b/arch/arm/mach-omap2/board-omap4panda.c
index e944025..b09d239 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -37,6 +37,7 @@
 #include plat/common.h
 #include plat/usb.h
 #include plat/mmc.h
+#include plat/panel-generic-dpi.h
 #include timer-gp.h
 
 #include hsmmc.h
@@ -76,6 +77,60 @@ static struct platform_device *panda_devices[] __initdata = {
leds_gpio,
 };
 
+/* Display DVI */
+#define PANDA_DVI_TFP410_POWER_DOWN_GPIO   0
+
+static int panda_enable_dvi(struct omap_dss_device *dssdev)
+{
+   gpio_set_value(dssdev-reset_gpio, 1);
+   return 0;
+}
+
+static void panda_disable_dvi(struct omap_dss_device *dssdev)
+{
+   gpio_set_value(dssdev-reset_gpio, 0);
+}
+
+/* Using generic display panel */
+static struct panel_generic_dpi_data dvi_panel = {
+   .name   = generic,
+   .platform_enable= panda_enable_dvi,
+   .platform_disable   = panda_disable_dvi,
+};
+
+struct omap_dss_device panda_dvi_device = {
+   .type   = OMAP_DISPLAY_TYPE_DPI,
+   .name   = dvi,
+   .driver_name= generic_dpi_panel,
+   .data   = dvi_panel,
+   .phy.dpi.data_lines = 24,
+   .reset_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
+   .channel= OMAP_DSS_CHANNEL_LCD2,
+};
+
+int __init panda_dvi_init(void)
+{
+   int r;
+
+   /* Requesting TFP410 DVI GPIO and disabling it, at bootup */
+   r = gpio_request_one(panda_dvi_device.reset_gpio,
+   GPIOF_OUT_INIT_LOW, DVI PD);
+   if (r)
+   pr_err(Failed to get DVI powerdown GPIO\n);
+
+   return r;
+}
+
+static struct omap_dss_device *panda_dss_devices[] = {
+   panda_dvi_device,
+};
+
+static struct omap_dss_board_info panda_dss_data = {
+   .num_devices= ARRAY_SIZE(panda_dss_devices),
+   .devices= panda_dss_devices,
+   .default_device = panda_dvi_device,
+};
+
 static void __init omap4_panda_init_irq(void)
 {
omap2_init_common_infrastructure();
@@ -375,6 +430,17 @@ static struct i2c_board_info __initdata 
omap4_panda_i2c_boardinfo[] = {
.platform_data = omap4_panda_twldata,
},
 };
+
+/*
+ * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
+ * is connected as I2C slave device, and can be accessed at address 0x50
+ */
+static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
+   {
+   I2C_BOARD_INFO(eeprom, 0x50),
+   },
+};
+
 static int __init omap4_panda_i2c_init(void)
 {
/*
@@ -384,13 +450,76 @@ static int __init omap4_panda_i2c_init(void)
omap_register_i2c_bus(1, 400, omap4_panda_i2c_boardinfo,
ARRAY_SIZE(omap4_panda_i2c_boardinfo));
omap_register_i2c_bus(2, 400, NULL, 0);
-   omap_register_i2c_bus(3, 400, NULL

[PATCH 2/4] OMAP: DSS: Renaming the dpll clk pointer in struct dss

2011-02-03 Thread Raghuveer Murthy 
The dss clk pointer dpll4_m4_ck is renamed to dpll_per_mx_ck, to be
generic for OMAP3xxx and OMAP44xx platforms. Variable and function
names containing dpll4/ dpll4_m4 are also renamed.

Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 drivers/video/omap2/dss/dss.c |   43 +
 1 files changed, 22 insertions(+), 21 deletions(-)

diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 24d6f98..add82e6 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -64,7 +64,8 @@ static struct {
int ctx_id;
int irq;
 
-   struct clk  *dpll4_m4_ck;
+   /* Points to DPLL4_M4 in OMAP3xxx, and DPLL_PER_M5 in OMAP44xx */
+   struct clk  *dpll_per_mx_ck;
struct clk  *dss_ick;
struct clk  *dss_fck;
struct clk  *dss_sys_clk;
@@ -225,27 +226,27 @@ void dss_sdi_disable(void)
 
 void dss_dump_clocks(struct seq_file *s)
 {
-   unsigned long dpll4_ck_rate;
-   unsigned long dpll4_m4_ck_rate;
+   unsigned long dpll_per_ck_rate;
+   unsigned long dpll_per_mx_ck_rate;
 
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 
-   dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
-   dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
+   dpll_per_ck_rate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
+   dpll_per_mx_ck_rate = clk_get_rate(dss.dpll_per_mx_ck);
 
seq_printf(s, - DSS -\n);
 
-   seq_printf(s, dpll4_ck %lu\n, dpll4_ck_rate);
+   seq_printf(s, dpll_per_ck %lu\n, dpll_per_ck_rate);
 
if (cpu_is_omap3630())
seq_printf(s, dss1_alwon_fclk = %lu / %lu  = %lu\n,
-   dpll4_ck_rate,
-   dpll4_ck_rate / dpll4_m4_ck_rate,
+   dpll_per_ck_rate,
+   dpll_per_ck_rate / dpll_per_mx_ck_rate,
dss_clk_get_rate(DSS_CLK_FCK));
else
seq_printf(s, dss1_alwon_fclk = %lu / %lu * 2 = %lu\n,
-   dpll4_ck_rate,
-   dpll4_ck_rate / dpll4_m4_ck_rate,
+   dpll_per_ck_rate,
+   dpll_per_ck_rate / dpll_per_mx_ck_rate,
dss_clk_get_rate(DSS_CLK_FCK));
 
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
@@ -323,7 +324,7 @@ int dss_calc_clock_rates(struct dss_clock_info *cinfo)
cinfo-fck_div == 0)
return -EINVAL;
 
-   prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
+   prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
 
cinfo-fck = prate / cinfo-fck_div;
 
@@ -336,10 +337,10 @@ int dss_set_clock_div(struct dss_clock_info *cinfo)
int r;
 
if (cpu_is_omap34xx()) {
-   prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
+   prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
DSSDBG(dpll4_m4 = %ld\n, prate);
 
-   r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo-fck_div);
+   r = clk_set_rate(dss.dpll_per_mx_ck, prate / cinfo-fck_div);
if (r)
return r;
}
@@ -355,7 +356,7 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
 
if (cpu_is_omap34xx()) {
unsigned long prate;
-   prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
+   prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
if (cpu_is_omap3630())
cinfo-fck_div = prate / (cinfo-fck);
else
@@ -367,10 +368,10 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
return 0;
 }
 
-unsigned long dss_get_dpll4_rate(void)
+unsigned long dss_get_dpll_per_rate(void)
 {
if (cpu_is_omap34xx())
-   return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
+   return clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
else
return 0;
 }
@@ -390,7 +391,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
int match = 0;
int min_fck_per_pck;
 
-   prate = dss_get_dpll4_rate();
+   prate = dss_get_dpll_per_rate();
 
fck = dss_clk_get_rate(DSS_CLK_FCK);
if (req_pck == dss.cache_req_pck 
@@ -620,10 +621,10 @@ static int dss_init(bool skip_init)
}
 
if (cpu_is_omap34xx()) {
-   dss.dpll4_m4_ck = clk_get(NULL, dpll4_m4_ck);
-   if (IS_ERR(dss.dpll4_m4_ck)) {
+   dss.dpll_per_mx_ck = clk_get(NULL, dpll4_m4_ck);
+   if (IS_ERR(dss.dpll_per_mx_ck)) {
DSSERR(Failed to get dpll4_m4_ck\n);
-   r = PTR_ERR(dss.dpll4_m4_ck);
+   r = PTR_ERR(dss.dpll_per_mx_ck);
goto fail2;
}
}
@@ -650,7 +651,7 @@ fail0

[PATCH 4/4] OMAP: DSS2: Get OMAP4 DPLL fclk for DPI interface

2011-02-03 Thread Raghuveer Murthy 
DSS DPLL fclk pointer is set, to configure pixel clock for DPI interface.

Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 drivers/video/omap2/dss/dss.c |7 +++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 654f5e6..d76bc26 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -628,6 +628,13 @@ static int dss_init(bool skip_init)
r = PTR_ERR(dss.dpll_per_mx_ck);
goto fail2;
}
+   } else if (cpu_is_omap44xx()) {
+   dss.dpll_per_mx_ck = clk_get(NULL, dpll_per_m5x2_ck);
+   if (IS_ERR(dss.dpll_per_mx_ck)) {
+   DSSERR(Failed to get dpll_per_mx_ck\n);
+   r = PTR_ERR(dss.dpll_per_mx_ck);
+   goto fail2;
+   }
}
 
dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
-- 
1.7.0.4

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[PATCH 3/4] OMAP: DSS2: Using dss_features to clean cpu checks for clocks

2011-02-03 Thread Raghuveer Murthy 
dss_features are used to substitute cpu_is_() checks for DPLL clock source

Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 drivers/video/omap2/dss/dss.c |   35 ++-
 1 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index add82e6..654f5e6 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -320,8 +320,9 @@ int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 {
unsigned long prate;
 
-   if (cinfo-fck_div  (cpu_is_omap3630() ? 32 : 16) ||
-   cinfo-fck_div == 0)
+   if (cinfo-fck_div 
+   (dss_has_feature(FEAT_DPLL_FCK_32_DIV) ? 32 : 16) ||
+   cinfo-fck_div == 0)
return -EINVAL;
 
prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
@@ -336,9 +337,9 @@ int dss_set_clock_div(struct dss_clock_info *cinfo)
unsigned long prate;
int r;
 
-   if (cpu_is_omap34xx()) {
+   if (dss_has_feature(FEAT_VAR_DPLL_FCK)) {
prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
-   DSSDBG(dpll4_m4 = %ld\n, prate);
+   DSSDBG(dpll_per_mx parent rate = %ld\n, prate);
 
r = clk_set_rate(dss.dpll_per_mx_ck, prate / cinfo-fck_div);
if (r)
@@ -354,10 +355,10 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
 {
cinfo-fck = dss_clk_get_rate(DSS_CLK_FCK);
 
-   if (cpu_is_omap34xx()) {
+   if (dss_has_feature(FEAT_VAR_DPLL_FCK)) {
unsigned long prate;
prate = clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
-   if (cpu_is_omap3630())
+   if (dss_has_feature(FEAT_DPLL_FCK_32_DIV))
cinfo-fck_div = prate / (cinfo-fck);
else
cinfo-fck_div = prate / (cinfo-fck / 2);
@@ -370,7 +371,7 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
 
 unsigned long dss_get_dpll_per_rate(void)
 {
-   if (cpu_is_omap34xx())
+   if (dss_has_feature(FEAT_VAR_DPLL_FCK))
return clk_get_rate(clk_get_parent(dss.dpll_per_mx_ck));
else
return 0;
@@ -395,8 +396,9 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 
fck = dss_clk_get_rate(DSS_CLK_FCK);
if (req_pck == dss.cache_req_pck 
-   ((cpu_is_omap34xx()  prate == dss.cache_prate) ||
-dss.cache_dss_cinfo.fck == fck)) {
+   ((dss_has_feature(FEAT_VAR_DPLL_FCK) 
+   prate == dss.cache_prate) ||
+   dss.cache_dss_cinfo.fck == fck)) {
DSSDBG(dispc clock info found from cache.\n);
*dss_cinfo = dss.cache_dss_cinfo;
*dispc_cinfo = dss.cache_dispc_cinfo;
@@ -417,7 +419,7 @@ retry:
memset(best_dss, 0, sizeof(best_dss));
memset(best_dispc, 0, sizeof(best_dispc));
 
-   if (cpu_is_omap24xx()) {
+   if (!dss_has_feature(FEAT_VAR_DPLL_FCK)) {
struct dispc_clock_info cur_dispc;
/* XXX can we change the clock on omap2? */
fck = dss_clk_get_rate(DSS_CLK_FCK);
@@ -432,12 +434,13 @@ retry:
best_dispc = cur_dispc;
 
goto found;
-   } else if (cpu_is_omap34xx()) {
-   for (fck_div = (cpu_is_omap3630() ? 32 : 16);
-   fck_div  0; --fck_div) {
+   } else {
+   for (fck_div =
+   (dss_has_feature(FEAT_DPLL_FCK_32_DIV) ? 32 : 16);
+   fck_div  0; --fck_div) {
struct dispc_clock_info cur_dispc;
 
-   if (cpu_is_omap3630())
+   if (dss_has_feature(FEAT_DPLL_FCK_32_DIV))
fck = prate / fck_div;
else
fck = prate / fck_div * 2;
@@ -465,8 +468,6 @@ retry:
goto found;
}
}
-   } else {
-   BUG();
}
 
 found:
@@ -650,7 +651,7 @@ fail0:
 
 static void dss_exit(void)
 {
-   if (cpu_is_omap34xx())
+   if (dss_has_feature(FEAT_VAR_DPLL_FCK))
clk_put(dss.dpll_per_mx_ck);
 
free_irq(dss.irq, NULL);
-- 
1.7.0.4

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[PATCH 1/4] OMAP: DSS2: Add dss_feature for variable DPLL fclk

2011-02-03 Thread Raghuveer Murthy 
This patch adds dss_feature for OMAP chips to distinguish between
those having a variable DPLL_PER functional clock (fclk). Additionally,
a feature for distiguishing the number of available dividers, 16 or 32,
for these fclk is added.

Signed-off-by: Archit Taneja arc...@ti.com
Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 drivers/video/omap2/dss/dss_features.c |9 ++---
 drivers/video/omap2/dss/dss_features.h |3 +++
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/video/omap2/dss/dss_features.c 
b/drivers/video/omap2/dss/dss_features.c
index f3ef929..4630f0c 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -157,7 +157,8 @@ static struct omap_dss_features omap3430_dss_features = {
.has_feature=
FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
-   FEAT_FUNCGATED | FEAT_COMMON_IRQ_DISPC_DSI,
+   FEAT_FUNCGATED | FEAT_COMMON_IRQ_DISPC_DSI |
+   FEAT_VAR_DPLL_FCK,
 
.num_mgrs = 2,
.num_ovls = 3,
@@ -173,7 +174,8 @@ static struct omap_dss_features omap3630_dss_features = {
FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
-   FEAT_COMMON_IRQ_DISPC_DSI,
+   FEAT_COMMON_IRQ_DISPC_DSI | FEAT_VAR_DPLL_FCK |
+   FEAT_DPLL_FCK_32_DIV,
 
.num_mgrs = 2,
.num_ovls = 3,
@@ -188,7 +190,8 @@ static struct omap_dss_features omap4_dss_features = {
 
.has_feature=
FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
-   FEAT_MGR_LCD2,
+   FEAT_MGR_LCD2 | FEAT_VAR_DPLL_FCK |
+   FEAT_DPLL_FCK_32_DIV,
 
.num_mgrs = 3,
.num_ovls = 3,
diff --git a/drivers/video/omap2/dss/dss_features.h 
b/drivers/video/omap2/dss/dss_features.h
index 1c93a49..76b5fce 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -34,6 +34,9 @@ enum dss_feat_id {
FEAT_FUNCGATED  = 1  6,
FEAT_MGR_LCD2   = 1  7,
FEAT_COMMON_IRQ_DISPC_DSI   = 1  8,
+   FEAT_VAR_DPLL_FCK   = 1  9, /* Variable DPLL Func CLK */
+   /* DPLL FCLK has max divider value 32 */
+   FEAT_DPLL_FCK_32_DIV= 1  10,
 };
 
 /* DSS register field id */
-- 
1.7.0.4

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[PATCH 0/4] OMAP4: DSS2: Adding fclk support for DPI interface

2011-02-03 Thread Raghuveer Murthy 
- Adding dss_feature for DPLL fclk
- Enabling pixel clock generation for DPI interface

-
Base

url = git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
branch master
commit 1bae4ce27c9c90344f23c65ea6966c50ffeae2f5
tag 2.6.38-rc2

Applies over:
-
1.
Patch mentioned in 
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg42384.html
[PATCH] OMAP: counter_32k: init clocksource as part of machine timer init
(This patch is required for OMAP bootup)

2.
v10 of OMAP2,3 DSS2 HWMOD
https://patchwork.kernel.org/patch/500191/

3.
v3 of DSS2: Generalize clock names
https://patchwork.kernel.org/patch/520191/

4.
v3 of DSS2: OMAP4 DSS HWMOD :
https://patchwork.kernel.org/patch/511211/

5.
OMAP: DSS2: Common IRQ handler for all OMAPs
https://patchwork.kernel.org/patch/526241/
-

Raghuveer Murthy (4):
  OMAP: DSS2: Add dss_feature for variable DPLL fclk
  OMAP: DSS: Renaming the dpll clk pointer in struct dss
  OMAP: DSS2: Using dss_features to clean cpu checks for clocks
  OMAP: DSS2: Get OMAP4 DPLL fclk for DPI interface

 drivers/video/omap2/dss/dss.c  |   85 +--
 drivers/video/omap2/dss/dss_features.c |9 ++-
 drivers/video/omap2/dss/dss_features.h |3 +
 3 files changed, 56 insertions(+), 41 deletions(-)

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[PATCH 0/4] OMAP: DSS2: Fix for DISPC core functional clock divider

2011-02-03 Thread Raghuveer Murthy 
OMAP4 has 2 LCD channels and corresponding DISPC_DIVISOR1 and DISPC_DIVISOR2
registers to configure the pixel clock frequency, for the respective LCD
displays.

There is also DISPC_DIVISOR register, which by default has the ENABLE bit
set to zero, for backward compatibility mode. Hence the logical clock divider of
DISPC_DIVISOR1.LCD, gets used for core func clk configuration. The default value
of DISPC_DIVISOR1.LCD is 4.

If only the secondary LCD is enabled, at high pixel resolutions the core clk
lags behind the pixel clock, causing stair-step effect (diagonal lines with
tearing) on the display.

Hence DISPC_DIVISOR.ENABLE is set to 1, and the core functional clock is set
independently and exclusively in DISPC_DIVISOR.LCD.

- Added the above as dss_features

-
Base

url = git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
branch master
commit 1bae4ce27c9c90344f23c65ea6966c50ffeae2f5
tag 2.6.38-rc2

Applies over:
-
1.
Patch mentioned in 
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg42384.html
[PATCH] OMAP: counter_32k: init clocksource as part of machine timer init
(This patch is required for OMAP bootup)

2.
v10 of OMAP2,3 DSS2 HWMOD
https://patchwork.kernel.org/patch/500191/

3.
v3 of DSS2: Generalize clock names
https://patchwork.kernel.org/patch/520191/

4.
v3 of DSS2: OMAP4 DSS HWMOD :
https://patchwork.kernel.org/patch/511211/

5.
OMAP: DSS2: Common IRQ handler for all OMAPs
https://patchwork.kernel.org/patch/526241/

6.
OMAP4: DSS2: Adding fclk support for DPI interface
https://patchwork.kernel.org/patch/529381/
-

Raghuveer Murthy (4):
  OMAP: DSS2: Adding dss_features for independent core clk divider
  OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch)
  OMAP: DSS2: Adding macro for DISPC_DIVISOR register
  OMAP4: DSS2: Using dss_features to set independent core clock divider

 drivers/video/omap2/dss/dispc.c|   57 ---
 drivers/video/omap2/dss/dss_features.c |2 +-
 drivers/video/omap2/dss/dss_features.h |2 +
 3 files changed, 47 insertions(+), 14 deletions(-)

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[PATCH 4/4] OMAP4: DSS2: Using dss_features to set independent core clock divider

2011-02-03 Thread Raghuveer Murthy 
Using dss_features to select independent core clock divider and setting
it. Added the register used, to DISPC context save and restore group

---
In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as:

DISPC_CORE_CLK = max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...)

Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the
maximum horizontal downscaling done through MANAGERi

Based on the usecase, core clk can be increased or decreased at runtime
to save power. Such mechanism are not yet implemented. Hence, we set the
core clock divisor to 1, to support maximum range of resolutions


Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 drivers/video/omap2/dss/dispc.c |   15 +++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 6225d12..cda1d2e 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -388,6 +388,9 @@ void dispc_save_context(void)
SR(VID_FIR_COEF_V(1, 7));
 
SR(VID_PRELOAD(1));
+
+   if (dss_has_feature(FEAT_CORE_CLK_DIV))
+   SR(DIVISOR);
 }
 
 void dispc_restore_context(void)
@@ -547,6 +550,9 @@ void dispc_restore_context(void)
 
RR(VID_PRELOAD(1));
 
+   if (dss_has_feature(FEAT_CORE_CLK_DIV))
+   RR(DIVISOR);
+
/* enable last, because LCD  DIGIT enable are here */
RR(CONTROL);
if (dss_has_feature(FEAT_MGR_LCD2))
@@ -3268,6 +3274,15 @@ static void _omap_dispc_initial_config(void)
l = FLD_MOD(l, 1, 0, 0);/* AUTOIDLE */
dispc_write_reg(DISPC_SYSCONFIG, l);
 
+   /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
+   if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
+   l = dispc_read_reg(DISPC_DIVISOR);
+   /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
+   l = FLD_MOD(l, 1, 0, 0);
+   l = FLD_MOD(l, 1, 23, 16);
+   dispc_write_reg(DISPC_DIVISOR, l);
+   }
+
/* FUNCGATED */
if (dss_has_feature(FEAT_FUNCGATED))
REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
-- 
1.7.0.4

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[PATCH 3/4] OMAP: DSS2: Adding macro for DISPC_DIVISOR register

2011-02-03 Thread Raghuveer Murthy 
Added macro for DISPC_DIVISOR. This is different from DISPC_DIVISOR1 and
DISPC_DIVISOR2. OMAP4 supports all the above 3 registers.

DISPC_DIVISOR1 and DISPC_DIVISOR2 registers are accessed through
DISPC_DIVISORo(ch) macro

Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 drivers/video/omap2/dss/dispc.c |   11 +++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index e52a413..6225d12 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -132,6 +132,17 @@ struct dispc_reg { u16 idx; };
 
 #define DISPC_VID_PRELOAD(n)   DISPC_REG(0x230 + (n)*0x04)
 
+/*
+ * The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
+ * However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK.
+ * This allows DISPC_CORE_CLK to be independent of logical clock dividers (lcd)
+ * of LCD1 (primary) and LCD2 (secondary) displays.
+ *
+ * To derive pixel clocks for Primary and Secondary LCD channels, configure the
+ * lcd and pcd in DISPC_DIVISOR1 and DISPC_DIVISOR2 respectively, using the
+ * DISPC_DIVISORo(ch).
+ */
+#define DISPC_DIVISOR  DISPC_REG(0x0804)
 
 #define DISPC_IRQ_MASK_ERROR(DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 DISPC_IRQ_OCP_ERR | \
-- 
1.7.0.4

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[PATCH 2/4] OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch)

2011-02-03 Thread Raghuveer Murthy 
Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction
of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers
DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2.

Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch).

OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and
DISPC_DIVISOR2

Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 drivers/video/omap2/dss/dispc.c |   31 ++-
 1 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index cc58208..e52a413 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -72,7 +72,12 @@ struct dispc_reg { u16 idx; };
 #define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
 #define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
 #define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
-#define DISPC_DIVISOR(ch)  DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
+/*
+ * Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be
+ * configured. OMAP4 TRM uses DISPC_DIVISORo generically to refer 
DISPC_DIVISOR1
+ * and DISPC_DIVISOR2
+ */
+#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
 #define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
 #define DISPC_SIZE_DIG DISPC_REG(0x0078)
 #define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
@@ -229,7 +234,7 @@ void dispc_save_context(void)
SR(TIMING_H(0));
SR(TIMING_V(0));
SR(POL_FREQ(0));
-   SR(DIVISOR(0));
+   SR(DIVISORo(0));
SR(GLOBAL_ALPHA);
SR(SIZE_DIG);
SR(SIZE_LCD(0));
@@ -241,7 +246,7 @@ void dispc_save_context(void)
SR(TIMING_H(2));
SR(TIMING_V(2));
SR(POL_FREQ(2));
-   SR(DIVISOR(2));
+   SR(DIVISORo(2));
SR(CONFIG2);
}
 
@@ -388,7 +393,7 @@ void dispc_restore_context(void)
RR(TIMING_H(0));
RR(TIMING_V(0));
RR(POL_FREQ(0));
-   RR(DIVISOR(0));
+   RR(DIVISORo(0));
RR(GLOBAL_ALPHA);
RR(SIZE_DIG);
RR(SIZE_LCD(0));
@@ -399,7 +404,7 @@ void dispc_restore_context(void)
RR(TIMING_H(2));
RR(TIMING_V(2));
RR(POL_FREQ(2));
-   RR(DIVISOR(2));
+   RR(DIVISORo(2));
RR(CONFIG2);
}
 
@@ -2292,7 +2297,7 @@ static void dispc_set_lcd_divisor(enum omap_channel 
channel, u16 lck_div,
BUG_ON(pck_div  2);
 
enable_clocks(1);
-   dispc_write_reg(DISPC_DIVISOR(channel),
+   dispc_write_reg(DISPC_DIVISORo(channel),
FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
enable_clocks(0);
 }
@@ -2301,7 +2306,7 @@ static void dispc_get_lcd_divisor(enum omap_channel 
channel, int *lck_div,
int *pck_div)
 {
u32 l;
-   l = dispc_read_reg(DISPC_DIVISOR(channel));
+   l = dispc_read_reg(DISPC_DIVISORo(channel));
*lck_div = FLD_GET(l, 23, 16);
*pck_div = FLD_GET(l, 7, 0);
 }
@@ -2327,7 +2332,7 @@ unsigned long dispc_lclk_rate(enum omap_channel channel)
unsigned long r;
u32 l;
 
-   l = dispc_read_reg(DISPC_DIVISOR(channel));
+   l = dispc_read_reg(DISPC_DIVISORo(channel));
 
lcd = FLD_GET(l, 23, 16);
 
@@ -2342,7 +2347,7 @@ unsigned long dispc_pclk_rate(enum omap_channel channel)
unsigned long r;
u32 l;
 
-   l = dispc_read_reg(DISPC_DIVISOR(channel));
+   l = dispc_read_reg(DISPC_DIVISORo(channel));
 
lcd = FLD_GET(l, 23, 16);
pcd = FLD_GET(l, 7, 0);
@@ -2458,7 +2463,7 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_TIMING_H(0));
DUMPREG(DISPC_TIMING_V(0));
DUMPREG(DISPC_POL_FREQ(0));
-   DUMPREG(DISPC_DIVISOR(0));
+   DUMPREG(DISPC_DIVISORo(0));
DUMPREG(DISPC_GLOBAL_ALPHA);
DUMPREG(DISPC_SIZE_DIG);
DUMPREG(DISPC_SIZE_LCD(0));
@@ -2470,7 +2475,7 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_TIMING_H(2));
DUMPREG(DISPC_TIMING_V(2));
DUMPREG(DISPC_POL_FREQ(2));
-   DUMPREG(DISPC_DIVISOR(2));
+   DUMPREG(DISPC_DIVISORo(2));
DUMPREG(DISPC_SIZE_LCD(2));
}
 
@@ -2712,8 +2717,8 @@ int dispc_get_clock_div(enum omap_channel channel,
 
fck = dispc_fclk_rate();
 
-   cinfo-lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16);
-   cinfo-pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0);
+   cinfo-lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
+   cinfo-pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
 
cinfo-lck = fck / cinfo-lck_div;
cinfo-pck = cinfo-lck / cinfo-pck_div;
-- 
1.7.0.4

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[PATCH 1/4] OMAP: DSS2: Adding dss_features for independent core clk divider

2011-02-03 Thread Raghuveer Murthy 
In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div)
field. The lcd_div is common, for deciding the DISPC core functional clock
frequency, and the final pixel clock frequency for LCD display.

In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1
and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR.

The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core
functional clock configuration. For pixel clock configuration of primary and
secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used
respectively

Signed-off-by: Archit Taneja arc...@ti.com
Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 drivers/video/omap2/dss/dss_features.c |2 +-
 drivers/video/omap2/dss/dss_features.h |2 ++
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/video/omap2/dss/dss_features.c 
b/drivers/video/omap2/dss/dss_features.c
index 4630f0c..39864f6 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -191,7 +191,7 @@ static struct omap_dss_features omap4_dss_features = {
.has_feature=
FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
FEAT_MGR_LCD2 | FEAT_VAR_DPLL_FCK |
-   FEAT_DPLL_FCK_32_DIV,
+   FEAT_DPLL_FCK_32_DIV | FEAT_CORE_CLK_DIV,
 
.num_mgrs = 3,
.num_ovls = 3,
diff --git a/drivers/video/omap2/dss/dss_features.h 
b/drivers/video/omap2/dss/dss_features.h
index 76b5fce..ed5c880 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -37,6 +37,8 @@ enum dss_feat_id {
FEAT_VAR_DPLL_FCK   = 1  9, /* Variable DPLL Func CLK */
/* DPLL FCLK has max divider value 32 */
FEAT_DPLL_FCK_32_DIV= 1  10,
+   /* Independent core clk divider */
+   FEAT_CORE_CLK_DIV   = 1  11,
 };
 
 /* DSS register field id */
-- 
1.7.0.4

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Re: [PATCH v10 18/18] OMAP2,3: DSS2: Get DSS IRQ from platform device

2011-01-27 Thread Raghuveer Murthy 

Hi Sumit,

On Monday 24 January 2011 11:52 AM, Sumit Semwal wrote:

From: Senthilvadivu Guruswamysvad...@ti.com

DSS IRQ number can be obtained from platform_get_irq().  This API in turn
picks the right IRQ number belonging to HW IP from the hwmod database.
So hardcoding of IRQ number could be removed.

Reviewed-by: Paul Walmsleyp...@pwsan.com
Reviewed-by: Kevin Hilmankhil...@ti.com
Tested-by: Kevin Hilmankhil...@ti.com
Signed-off-by: Senthilvadivu Guruswamysvad...@ti.com
Signed-off-by: Sumit Semwalsumit.sem...@ti.com
---
  drivers/video/omap2/dss/dss.c |   21 ++---
  1 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 4d7a816..f9390b4 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -563,7 +563,7 @@ void dss_set_dac_pwrdn_bgz(bool enable)

  static int dss_init(bool skip_init)
  {
-   int r;
+   int r, dss_irq;
u32 rev;
struct resource *dss_mem;

@@ -609,11 +609,18 @@ static int dss_init(bool skip_init)
REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);  /* venc clock mode = normal */
  #endif

-   r = request_irq(INT_24XX_DSS_IRQ,
-   cpu_is_omap24xx()
-   ? dss_irq_handler_omap2
-   : dss_irq_handler_omap3,
-   0, OMAP DSS, NULL);
+   dss_irq = platform_get_irq(dss.pdev, 0);
+   if (dss_irq  0) {
+   DSSERR(omap2 dss: platform_get_irq failed\n);
+   r = -ENODEV;
+   goto fail1;
+   }
+
+   r = request_irq(dss_irq,
+   cpu_is_omap24xx()
+   ? dss_irq_handler_omap2
+   : dss_irq_handler_omap3,


it should be

cpu_is_omap24xx()
? dss_irq_handler_omap3
: dss_irq_handler_omap2,

I am seeing a crash on Panda, which gets rectified with this
change. The root cause is access to DSS_IRQSTATUS register in the
dss_irq_handler_omap3 handler, which is not valid for OMAP4.

Regards,
Raghuveer


+   0, OMAP DSS, NULL);

if (r  0) {
DSSERR(omap2 dss: request_irq failed\n);
@@ -641,7 +648,7 @@ static int dss_init(bool skip_init)
return 0;

  fail2:
-   free_irq(INT_24XX_DSS_IRQ, NULL);
+   free_irq(dss_irq, NULL);
  fail1:
iounmap(dss.base);
  fail0:


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Re: [PATCH v10 18/18] OMAP2, 3: DSS2: Get DSS IRQ from platform device

2011-01-27 Thread Raghuveer Murthy 

On Thursday 27 January 2011 06:29 PM, Russell King - ARM Linux wrote:

On Thu, Jan 27, 2011 at 06:19:21PM +0530, Raghuveer Murthy wrote:

+   r = request_irq(dss_irq,
+   cpu_is_omap24xx()
+   ? dss_irq_handler_omap2
+   : dss_irq_handler_omap3,


it should be

cpu_is_omap24xx()
? dss_irq_handler_omap3
: dss_irq_handler_omap2,

I am seeing a crash on Panda, which gets rectified with this
change. The root cause is access to DSS_IRQSTATUS register in the
dss_irq_handler_omap3 handler, which is not valid for OMAP4.


That really doesn't look right.  Let me translate the code you've just
written:

if (cpu_is_omap24xx())
handler = dss_irq_handler_omap3;
else
handler = dss_irq_handler_omap2;

Which means: if we have an OMAP24xx device, use the OMAP3 handler,
otherwise use the OMAP2 handler.  That's got to be wrong.


I agree, that the logic seems counter-intuitive. I was doing a quick test.

However, to  keep the correct sequence, the logic inside the respective 
handlers need to be looked at.


Regards,
Raghuveer
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[PATCH] OMAP4: Pandaboard: Fixing MMC card detect gpio line

2010-12-07 Thread Raghuveer Murthy 
The .gpio_cd member of omap2_hsmmc_info is not initialized. This
will default to zero. On Pandaboard this interferes with gpio line
assigned for powering TFP410 DVI chip.

This fix was missed out in the previous commit bf56f0a6668cd, from
Nishanth Menon

Signed-off-by: Kishore Kadiyala kishore.kadiy...@ti.com
Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
Acked-by: Nishanth Menon n...@ti.com
---
 arch/arm/mach-omap2/board-omap4panda.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap4panda.c 
b/arch/arm/mach-omap2/board-omap4panda.c
index ad6b5cc..0ccc24f 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -142,6 +142,7 @@ static struct omap2_hsmmc_info mmc[] = {
.mmc= 1,
.caps   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_wp= -EINVAL,
+   .gpio_cd= -EINVAL,
},
{}  /* Terminator */
 };
-- 
1.7.0.4

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[PATCH] OMAP4: Pandaboad: Add omap_reserve functionality

2010-12-07 Thread Raghuveer Murthy 
This patch adds omap_reserve functionality to board-omap4panda.c.
Helps in the reserving boot time memory in SDRAM, used here for
framebuffer allocation.

Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 arch/arm/mach-omap2/board-omap4panda.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap4panda.c 
b/arch/arm/mach-omap2/board-omap4panda.c
index 1ecd0a6..ad6b5cc 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -392,6 +392,7 @@ MACHINE_START(OMAP4_PANDA, OMAP4 Panda board)
/* Maintainer: David Anders - Texas Instruments Inc */
.boot_params= 0x8100,
.map_io = omap4_panda_map_io,
+   .reserve= omap_reserve,
.init_irq   = omap4_panda_init_irq,
.init_machine   = omap4_panda_init,
.timer  = omap_timer,
-- 
1.7.0.4

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[PATCH v2] OMAP4: Pandaboard: Add omap_reserve functionality

2010-12-07 Thread Raghuveer Murthy 
This patch adds omap_reserve functionality to board-omap4panda.c.
Helps in the reserving boot time memory in SDRAM, used here for
framebuffer allocation.

This patch is in similar lines to commit id 71ee7dad9b6991, from
Russell king

Cc: Russell King rmk+ker...@arm.linux.org.uk
Cc: linux-...@lists.arm.linux.org.uk
Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 arch/arm/mach-omap2/board-omap4panda.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap4panda.c 
b/arch/arm/mach-omap2/board-omap4panda.c
index da24745..0ccc24f 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -393,6 +393,7 @@ MACHINE_START(OMAP4_PANDA, OMAP4 Panda board)
/* Maintainer: David Anders - Texas Instruments Inc */
.boot_params= 0x8100,
.map_io = omap4_panda_map_io,
+   .reserve= omap_reserve,
.init_irq   = omap4_panda_init_irq,
.init_machine   = omap4_panda_init,
.timer  = omap_timer,
-- 
1.7.0.4

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[PATCH v2 resend] OMAP4: Pandaboard: Add omap_reserve functionality

2010-12-07 Thread Raghuveer Murthy 
This patch adds omap_reserve functionality to board-omap4panda.c.
Helps in the reserving boot time memory in SDRAM, used here for
framebuffer allocation.

This patch is in similar lines to commit id 71ee7dad9b6991, from
Russell king

Cc: Russell King rmk+ker...@arm.linux.org.uk
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Raghuveer Murthy raghuveer.mur...@ti.com
---
 arch/arm/mach-omap2/board-omap4panda.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap4panda.c 
b/arch/arm/mach-omap2/board-omap4panda.c
index da24745..0ccc24f 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -393,6 +393,7 @@ MACHINE_START(OMAP4_PANDA, OMAP4 Panda board)
/* Maintainer: David Anders - Texas Instruments Inc */
.boot_params= 0x8100,
.map_io = omap4_panda_map_io,
+   .reserve= omap_reserve,
.init_irq   = omap4_panda_init_irq,
.init_machine   = omap4_panda_init,
.timer  = omap_timer,
-- 
1.7.0.4

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