[PATCH 1/3] ARM: dts: Add vendor prefix for Grinn
Grinn is a company located in Poland, Europe producing System on Modules. Webpage: http://www.grinn-global.com/ Signed-off-by: Rostislav Lisovy lis...@jablotron.cz --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389ca13..f6a9f25 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -77,6 +77,7 @@ giantplus Giantplus Technology Co., Ltd. globalscaleGlobalscale Technologies, Inc. gmtGlobal Mixed-mode Technology, Inc. google Google, Inc. +grinn Grinn gumstixGumstix, Inc. gw Gateworks Corporation hannstar HannStar Display Corporation -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] ARM: dts: am335x: Add Chiliboard DTS
Chiliboard uses ChiliSOM as its base.
Hardware specification:
* ChiliSOM (am335x, PMIC, DRAM, NAND)
* Ethernet PHY (id 0)
* USB host (usb1)
* microSD slot
* 2x GPIO LED
Signed-off-by: Rostislav Lisovy lis...@jablotron.cz
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/am335x-chiliboard.dts | 112
2 files changed, 114 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/am335x-chiliboard.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a1c776b..b316b38 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -401,7 +401,8 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-evmsk.dtb \
am335x-nano.dtb \
am335x-pepper.dtb \
- am335x-lxm.dtb
+ am335x-lxm.dtb \
+ am335x-chiliboard.dtb
dtb-$(CONFIG_ARCH_OMAP4) += \
omap4-duovero-parlor.dtb \
omap4-panda.dtb \
diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts
b/arch/arm/boot/dts/am335x-chiliboard.dts
new file mode 100644
index 000..2cf8ee2
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-chiliboard.dts
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Author: Rostislav Lisovy lis...@jablotron.cz
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include am335x-chilisom.dtsi
+
+/ {
+ model = AM335x Chiliboard;
+ compatible = grinn,am335x-chiliboard, grinn,am335x-chilisom,
+ti,am33xx;
+
+ leds {
+ compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 = led_gpio_pins;
+
+ led0 {
+ label = led0;
+ gpios = gpio3 7 GPIO_ACTIVE_LOW;
+ default-state = keep;
+ linux,default-trigger = heartbeat;
+ };
+
+ led1 {
+ label = led1;
+ gpios = gpio3 8 GPIO_ACTIVE_LOW;
+ default-state = keep;
+ };
+ };
+};
+
+am33xx_pinmux {
+ usb1_drvvbus: usb1_drvvbus {
+ pinctrl-single,pins =
+ 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /*
usb1_drvvbus.usb1_drvvbus */
+ ;
+ };
+
+ sd_pins: pinmux_sd_card {
+ pinctrl-single,pins =
+ 0xf0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+ 0xf4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+ 0xf8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+ 0xfc (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+ 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+ 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+ 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+ ;
+ };
+
+ led_gpio_pins: led_gpio_pins {
+ pinctrl-single,pins =
+ 0x1e4 (PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */
+ 0x1e8 (PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */
+ ;
+ };
+};
+
+ldo4_reg {
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+};
+
+/* Ethernet */
+cpsw_emac0 {
+ phy_id = davinci_mdio, 0;
+ phy-mode = rmii;
+};
+
+phy_sel {
+ rmii-clock-ext;
+};
+
+/* USB */
+usb {
+ status = okay;
+};
+
+usb_ctrl_mod {
+ status = okay;
+};
+
+usb1_phy {
+ status = okay;
+};
+
+usb1 {
+ pinctrl-names = default;
+ pinctrl-0 = usb1_drvvbus;
+
+ status = okay;
+ dr_mode = host;
+};
+
+cppi41dma {
+ status = okay;
+};
+
+/* microSD */
+mmc1 {
+ pinctrl-names = default;
+ pinctrl-0 = sd_pins;
+ vmmc-supply = ldo4_reg;
+ bus-width = 0x4;
+ cd-gpios = gpio0 6 GPIO_ACTIVE_HIGH;
+ status = okay;
+};
--
2.1.0
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[PATCH 2/3] ARM: dts: am335x: Add DTS for ChiliSOM module
Since this is a SOM (System on Module) that will be part
of another embedded board (and can't really exist on its own)
define it as a dtsi that will be included in the Device tree
describing the whole system later on.
Hardware specification:
* AM335x SoC
* up to 512 MB RAM
* NAND Flash (8x interface, cs0)
* UART0
* PMIC
* I2C0 (for PMIC)
* 1x Ethernet MAC
Signed-off-by: Rostislav Lisovy lis...@jablotron.cz
---
arch/arm/boot/dts/am335x-chilisom.dtsi | 239 +
1 file changed, 239 insertions(+)
create mode 100644 arch/arm/boot/dts/am335x-chilisom.dtsi
diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi
b/arch/arm/boot/dts/am335x-chilisom.dtsi
new file mode 100644
index 000..54c0c10
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-chilisom.dtsi
@@ -0,0 +1,239 @@
+/*
+ * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Author: Rostislav Lisovy lis...@jablotron.cz
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include am33xx.dtsi
+
+/ {
+ model = Grinn AM335x ChiliSOM;
+ compatible = grinn,am335x-chilisom, ti,am33xx;
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = dcdc2_reg;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x8000 0x2000; /* 512 MB */
+ };
+};
+
+am33xx_pinmux {
+ pinctrl-names = default;
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins =
+ 0x188 (PIN_INPUT_PULLUP | MUX_MODE0)/*
i2c0_sda.i2c0_sda */
+ 0x18c (PIN_INPUT_PULLUP | MUX_MODE0)/*
i2c0_scl.i2c0_scl */
+ ;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins =
+ 0x170 (PIN_INPUT_PULLUP | MUX_MODE0)/*
uart0_rxd.uart0_rxd */
+ 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /*
uart0_txd.uart0_txd */
+ ;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins =
+ /* Slave 1 */
+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /*
mii1_crs.rmii1_crs */
+ 0x110 (PIN_INPUT_PULLUP | MUX_MODE1)/*
mii1_rxerr.rmii1_rxerr */
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /*
mii1_txen.rmii1_txen */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /*
mii1_txd1.rmii1_txd1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /*
mii1_txd0.rmii1_txd0 */
+ 0x13c (PIN_INPUT_PULLUP | MUX_MODE1)/*
mii1_rxd1.rmii1_rxd1 */
+ 0x140 (PIN_INPUT_PULLUP | MUX_MODE1)/*
mii1_rxd0.rmii1_rxd0 */
+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
rmii1_ref_clk.rmii_ref_clk */
+ ;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins =
+ /* Slave 1 reset value */
+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ ;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins =
+ /* mdio_data.mdio_data */
+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
+ /* mdio_clk.mdio_clk */
+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)
+ ;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins =
+ /* MDIO reset value */
+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ ;
+ };
+
+ nandflash_pins: nandflash_pins {
+ pinctrl-single,pins =
+ 0x00 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad0.gpmc_ad0 */
+ 0x04 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad1.gpmc_ad1 */
+ 0x08 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad2.gpmc_ad2 */
+ 0x0c (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
gpmc_ad5
[PATCH RESEND] ARM: omap2+: gpmc-nand: Use dynamic platform_device_alloc()
GPMC controller supports up to 8 memory devices connected to it.
Since there is one statically allocated struct platform_device
gpmc_nand_device it is not possible to configure the system to
use more than one NAND device connected to the GPMC. This
modification makes it possible to use up to 8 NAND devices
connected to the GPMC controller.
Signed-off-by: Rostislav Lisovy lis...@merica.cz
---
Tested on custom AM335x board with two different NAND chips
(128 + 256 MiB) using GPMC configuration in FDT -- behaves
correctly.
arch/arm/mach-omap2/gpmc-nand.c | 79 +++--
1 file changed, 37 insertions(+), 42 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 4349e82..c5481a8 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -24,25 +24,6 @@
/* minimum size for IO mapping */
#defineNAND_IO_SIZE4
-static struct resource gpmc_nand_resource[] = {
- {
- .flags = IORESOURCE_MEM,
- },
- {
- .flags = IORESOURCE_IRQ,
- },
- {
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device gpmc_nand_device = {
- .name = omap2-nand,
- .id = 0,
- .num_resources = ARRAY_SIZE(gpmc_nand_resource),
- .resource = gpmc_nand_resource,
-};
-
static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
{
/* platforms which support all ECC schemes */
@@ -93,43 +74,41 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
{
int err = 0;
struct gpmc_settings s;
- struct device *dev = gpmc_nand_device.dev;
-
- memset(s, 0, sizeof(struct gpmc_settings));
+ struct platform_device *pdev;
+ struct resource gpmc_nand_res[] = {
+ { .flags = IORESOURCE_MEM, },
+ { .flags = IORESOURCE_IRQ, },
+ { .flags = IORESOURCE_IRQ, },
+ };
- gpmc_nand_device.dev.platform_data = gpmc_nand_data;
+ BUG_ON(gpmc_nand_data-cs = GPMC_CS_NUM);
err = gpmc_cs_request(gpmc_nand_data-cs, NAND_IO_SIZE,
- (unsigned long *)gpmc_nand_resource[0].start);
+ (unsigned long *)gpmc_nand_res[0].start);
if (err 0) {
- dev_err(dev, Cannot request GPMC CS %d, error %d\n,
- gpmc_nand_data-cs, err);
+ pr_err(omap2-gpmc: Cannot request GPMC CS %d, error %d\n,
+ gpmc_nand_data-cs, err);
return err;
}
-
- gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
- NAND_IO_SIZE - 1;
-
- gpmc_nand_resource[1].start =
- gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
- gpmc_nand_resource[2].start =
- gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
+ gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1;
+ gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
+ gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
if (gpmc_t) {
err = gpmc_cs_set_timings(gpmc_nand_data-cs, gpmc_t);
if (err 0) {
- dev_err(dev, Unable to set gpmc timings: %d\n, err);
+ pr_err(omap2-gpmc: Unable to set gpmc timings: %d\n,
err);
return err;
}
}
+ memset(s, 0, sizeof(struct gpmc_settings));
if (gpmc_nand_data-of_node)
gpmc_read_settings_dt(gpmc_nand_data-of_node, s);
else
gpmc_set_legacy(gpmc_nand_data, s);
s.device_nand = true;
-
err = gpmc_cs_program_settings(gpmc_nand_data-cs, s);
if (err 0)
goto out_free_cs;
@@ -141,18 +120,34 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
gpmc_update_nand_reg(gpmc_nand_data-reg, gpmc_nand_data-cs);
if (!gpmc_hwecc_bch_capable(gpmc_nand_data-ecc_opt)) {
- dev_err(dev, Unsupported NAND ECC scheme selected\n);
- return -EINVAL;
+ pr_err(omap2-nand: Unsupported NAND ECC scheme selected\n);
+ err = -EINVAL;
+ goto out_free_cs;
}
- err = platform_device_register(gpmc_nand_device);
- if (err 0) {
- dev_err(dev, Unable to register NAND device\n);
- goto out_free_cs;
+
+ pdev = platform_device_alloc(omap2-nand, gpmc_nand_data-cs);
+ if (pdev) {
+ err = platform_device_add_resources(pdev, gpmc_nand_res,
+ ARRAY_SIZE(gpmc_nand_res));
+ if (!err)
+ pdev-dev.platform_data = gpmc_nand_data;
+ } else
[PATCH] ARM: omap2+: gpmc-nand: Use dynamic platform_device_alloc()
GPMC controller supports up to 8 memory devices connected to it.
Since there is one statically allocated struct platform_device
gpmc_nand_device it is not possible to configure the system to
use more than one NAND device connected to the GPMC. This
modification makes it possible to use up to 8 NAND devices
connected to the GPMC controller.
Signed-off-by: Rostislav Lisovy lis...@merica.cz
---
Tested on custom AM335x board with two different NAND chips
(128 + 256 MiB) using GPMC configuration in FDT -- behaves
correctly.
arch/arm/mach-omap2/gpmc-nand.c | 79 +++--
1 file changed, 37 insertions(+), 42 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 4349e82..c5481a8 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -24,25 +24,6 @@
/* minimum size for IO mapping */
#defineNAND_IO_SIZE4
-static struct resource gpmc_nand_resource[] = {
- {
- .flags = IORESOURCE_MEM,
- },
- {
- .flags = IORESOURCE_IRQ,
- },
- {
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device gpmc_nand_device = {
- .name = omap2-nand,
- .id = 0,
- .num_resources = ARRAY_SIZE(gpmc_nand_resource),
- .resource = gpmc_nand_resource,
-};
-
static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
{
/* platforms which support all ECC schemes */
@@ -93,43 +74,41 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
{
int err = 0;
struct gpmc_settings s;
- struct device *dev = gpmc_nand_device.dev;
-
- memset(s, 0, sizeof(struct gpmc_settings));
+ struct platform_device *pdev;
+ struct resource gpmc_nand_res[] = {
+ { .flags = IORESOURCE_MEM, },
+ { .flags = IORESOURCE_IRQ, },
+ { .flags = IORESOURCE_IRQ, },
+ };
- gpmc_nand_device.dev.platform_data = gpmc_nand_data;
+ BUG_ON(gpmc_nand_data-cs = GPMC_CS_NUM);
err = gpmc_cs_request(gpmc_nand_data-cs, NAND_IO_SIZE,
- (unsigned long *)gpmc_nand_resource[0].start);
+ (unsigned long *)gpmc_nand_res[0].start);
if (err 0) {
- dev_err(dev, Cannot request GPMC CS %d, error %d\n,
- gpmc_nand_data-cs, err);
+ pr_err(omap2-gpmc: Cannot request GPMC CS %d, error %d\n,
+ gpmc_nand_data-cs, err);
return err;
}
-
- gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
- NAND_IO_SIZE - 1;
-
- gpmc_nand_resource[1].start =
- gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
- gpmc_nand_resource[2].start =
- gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
+ gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1;
+ gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
+ gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
if (gpmc_t) {
err = gpmc_cs_set_timings(gpmc_nand_data-cs, gpmc_t);
if (err 0) {
- dev_err(dev, Unable to set gpmc timings: %d\n, err);
+ pr_err(omap2-gpmc: Unable to set gpmc timings: %d\n,
err);
return err;
}
}
+ memset(s, 0, sizeof(struct gpmc_settings));
if (gpmc_nand_data-of_node)
gpmc_read_settings_dt(gpmc_nand_data-of_node, s);
else
gpmc_set_legacy(gpmc_nand_data, s);
s.device_nand = true;
-
err = gpmc_cs_program_settings(gpmc_nand_data-cs, s);
if (err 0)
goto out_free_cs;
@@ -141,18 +120,34 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
gpmc_update_nand_reg(gpmc_nand_data-reg, gpmc_nand_data-cs);
if (!gpmc_hwecc_bch_capable(gpmc_nand_data-ecc_opt)) {
- dev_err(dev, Unsupported NAND ECC scheme selected\n);
- return -EINVAL;
+ pr_err(omap2-nand: Unsupported NAND ECC scheme selected\n);
+ err = -EINVAL;
+ goto out_free_cs;
}
- err = platform_device_register(gpmc_nand_device);
- if (err 0) {
- dev_err(dev, Unable to register NAND device\n);
- goto out_free_cs;
+
+ pdev = platform_device_alloc(omap2-nand, gpmc_nand_data-cs);
+ if (pdev) {
+ err = platform_device_add_resources(pdev, gpmc_nand_res,
+ ARRAY_SIZE(gpmc_nand_res));
+ if (!err)
+ pdev-dev.platform_data = gpmc_nand_data;
+ } else
