Koen Kooi [EMAIL PROTECTED] writes:
Op 27 nov 2008, om 01:05 heeft Kevin Hilman het volgende geschreven:
Various bootloaders have been known to leave modules in a state
which prevents full-chip retention. This series forces
MMC, IVA2 and D2D/modem into known reset/idle states so that
the OMAP3 can hit full-chip idle.
Tested on OMAP3 Beagle, and custom OMAP3 hardware.
NOTE: this is similar to the set I posted for the PM branch
but this series is rebased onto linux-omap and includes
the MMC reset.
I'm having trouble applying these against current head
(5019ed843f3208482c64043e4052e89b3d5462a0), against which rev were
they generated?
regards,
Koen
Sorry...
This series applies on top of on addtional patch which I mistakenly
assumed was already in l-o. Here it is.
Kevin
From cbcf5c91b3e5156a9379d2312de9c9fa814bd3d8 Mon Sep 17 00:00:00 2001
From: Tero Kristo [EMAIL PROTECTED]
Date: Wed, 26 Nov 2008 14:41:28 -0800
Subject: [PATCH] OMAP2/3 clock: fix DPLL rate calculation
Noncore dpll can enter autoidle state, in which case the rate calculation
fails. Fixed by checking dpll mode instead of idle status.
Also, previously, the OMAP2xxx code returned the wrong value for the
DPLL rate under some conditions. Move the CORE_CLK rate recalculation
to clock24xx.c:omap2xxx_clk_get_core_rate().
Thanks to Peter de Schrijver [EMAIL PROTECTED] for help
debugging and Kevin Hilman [EMAIL PROTECTED] for reporting
the OMAP2 build problems with an earlier version of this patch.
Signed-off-by: Tero Kristo [EMAIL PROTECTED]
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
Cc: Kevin Hilman [EMAIL PROTECTED]
Cc: Peter de Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c | 29 ++
arch/arm/mach-omap2/clock.h |5
arch/arm/mach-omap2/clock24xx.c | 39 --
arch/arm/mach-omap2/clock24xx.h |4 +-
arch/arm/mach-omap2/sdrc2xxx.c |2 +
arch/arm/plat-omap/include/mach/clock.h | 13 +++---
6 files changed, 57 insertions(+), 35 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 42af286..54255fe 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -71,9 +71,15 @@
#define DPLL_FINT_UNDERFLOW-1
#define DPLL_FINT_INVALID -2
-/* Some OMAP2xxx CM_CLKSEL_PLL.ST_CORE_CLK bits - for omap2_get_dpll_rate() */
-#define ST_CORE_CLK_REF0x1
-#define ST_CORE_CLK_32K0x3
+/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
+#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
+#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
+#define OMAP2XXX_EN_DPLL_LOCKED0x3
+
+/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
+#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
+#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
+#define OMAP3XXX_EN_DPLL_LOCKED0x7
/* Bitmask to isolate the register type of clk.enable_reg */
#define PRCM_REGTYPE_MASK 0xf0
@@ -267,19 +273,20 @@ u32 omap2_get_dpll_rate(struct clk *clk)
return 0;
/* Return bypass rate if DPLL is bypassed */
- v = cm_read_mod_reg(clk-prcm_mod, dd-idlest_reg);
- v = dd-idlest_mask;
- v = __ffs(dd-idlest_mask);
+ v = cm_read_mod_reg(clk-prcm_mod, dd-control_reg);
+ v = dd-enable_mask;
+ v = __ffs(dd-enable_mask);
+
if (cpu_is_omap24xx()) {
- if (v == ST_CORE_CLK_REF)
- return clk-parent-rate; /* sys_clk */
- else if (v == ST_CORE_CLK_32K)
- return 32768;
+ if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
+ v == OMAP2XXX_EN_DPLL_FRBYPASS)
+ return clk-parent-rate;
} else if (cpu_is_omap34xx()) {
- if (!v)
+ if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+ v == OMAP3XXX_EN_DPLL_FRBYPASS)
return dd-bypass_clk-rate;
}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index bcb0c03..b7784d1 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,11 @@
/* The maximum error between a target DPLL rate and the rounded rate in Hz */
#define DEFAULT_DPLL_RATE_TOLERANCE5
+/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
+#define CORE_CLK_SRC_32K 0x0
+#define CORE_CLK_SRC_DPLL 0x1
+#define CORE_CLK_SRC_DPLL_X2 0x2
+
int omap2_clk_init(void);
int omap2_clk_enable(struct clk *clk);
void omap2_clk_disable(struct clk *clk);
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 32f6632..4bd21dd 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -60,19 +60,32 @@ static struct clk *sclk;
*
