Re: [PATCH 21/25] OMAP4: PM: Add MPUSS power domain OSWR support

2011-09-13 Thread Jean Pihet 
Hi Santosh,

On Tue, Sep 13, 2011 at 7:37 AM, Santosh santosh.shilim...@ti.com wrote:
 On Tuesday 13 September 2011 12:22 AM, Kevin Hilman wrote:

 Santosh Shilimkarsantosh.shilim...@ti.com  writes:

 This patch adds the MPUSS OSWR (Open Switch Retention) support. The MPUSS
 OSWR configuration is as below.
        - CPUx L1 and logic lost, MPUSS logic lost, L2 memory is retained

 OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more
 anymore just like CORE power domain. The deepest state supported is OSWR.
 On OMAP4430 secure devices too, MPUSS off mode can't be used because of
 a bug which alters Ducati and Tesla states. Hence MPUSS off mode as an
 independent state isn't supported on OMAP44XX devices.

 Ofcourse when MPUSS power domain transitions to OSWR along
 with device off mode, it eventually hits off state since memory
 contents are lost.

 Hence the MPUSS off mode independent state is not attempted without
 device off mode. All the necessary infrastructure code for MPUSS
 off mode is in place as part of this series.

 Signed-off-by: Santosh Shilimkarsantosh.shilim...@ti.com
 Cc: Kevin Hilmankhil...@ti.com

 Compile failure for the !CONFIG_PM case:

 [...]

 @@ -70,11 +71,18 @@ static inline int omap4_mpuss_init(void)
  {
        return 0;
  }
 -
 +static inline u32 omap4_mpuss_read_prev_context_state(void)
 +{
 +       return 0;
 +}

 added here

  static inline int omap4_finish_suspend(unsigned long cpu_state)
  {}
This one should return 0, as I already pointed out in the comments for [14/25].

Regards,
Jean

  static inline void omap4_cpu_resume(void)
  {}
 +static inline u32 omap4_mpuss_read_prev_context_state(void)
 +{
 +       return 0;
 +}

 same thing added here

 I noticed this yesterday and was planning to send a note on this
 patch. :(
 Have removed this already in the updated patches.
 Thanks for pointing it out.

 Regards
 Santosh

 --
 To unsubscribe from this list: send the line unsubscribe linux-omap in
 the body of a message to majord...@vger.kernel.org
 More majordomo info at  http://vger.kernel.org/majordomo-info.html

--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 21/25] OMAP4: PM: Add MPUSS power domain OSWR support

2011-09-13 Thread Santosh 

On Tuesday 13 September 2011 01:09 PM, Jean Pihet wrote:

Hi Santosh,

On Tue, Sep 13, 2011 at 7:37 AM, Santoshsantosh.shilim...@ti.com  wrote:

On Tuesday 13 September 2011 12:22 AM, Kevin Hilman wrote:




[..]




  static inline int omap4_finish_suspend(unsigned long cpu_state)
  {}

This one should return 0, as I already pointed out in the comments for [14/25].


Taken care already.

Regards
Santosh
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 21/25] OMAP4: PM: Add MPUSS power domain OSWR support

2011-09-12 Thread Kevin Hilman 
Santosh Shilimkar santosh.shilim...@ti.com writes:

 This patch adds the MPUSS OSWR (Open Switch Retention) support. The MPUSS
 OSWR configuration is as below.
   - CPUx L1 and logic lost, MPUSS logic lost, L2 memory is retained

 OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more
 anymore just like CORE power domain. The deepest state supported is OSWR.
 On OMAP4430 secure devices too, MPUSS off mode can't be used because of
 a bug which alters Ducati and Tesla states. Hence MPUSS off mode as an
 independent state isn't supported on OMAP44XX devices.

 Ofcourse when MPUSS power domain transitions to OSWR along
 with device off mode, it eventually hits off state since memory
 contents are lost.

 Hence the MPUSS off mode independent state is not attempted without
 device off mode. All the necessary infrastructure code for MPUSS
 off mode is in place as part of this series.

 Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
 Cc: Kevin Hilman khil...@ti.com

Compile failure for the !CONFIG_PM case:

[...]

 @@ -70,11 +71,18 @@ static inline int omap4_mpuss_init(void)
  {
   return 0;
  }
 -
 +static inline u32 omap4_mpuss_read_prev_context_state(void)
 +{
 + return 0;
 +}

added here

  static inline int omap4_finish_suspend(unsigned long cpu_state)
  {}
  static inline void omap4_cpu_resume(void)
  {}
 +static inline u32 omap4_mpuss_read_prev_context_state(void)
 +{
 + return 0;
 +}

same thing added here

Kevin
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 21/25] OMAP4: PM: Add MPUSS power domain OSWR support

2011-09-12 Thread Santosh 

On Tuesday 13 September 2011 12:22 AM, Kevin Hilman wrote:

Santosh Shilimkarsantosh.shilim...@ti.com  writes:


This patch adds the MPUSS OSWR (Open Switch Retention) support. The MPUSS
OSWR configuration is as below.
- CPUx L1 and logic lost, MPUSS logic lost, L2 memory is retained

OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more
anymore just like CORE power domain. The deepest state supported is OSWR.
On OMAP4430 secure devices too, MPUSS off mode can't be used because of
a bug which alters Ducati and Tesla states. Hence MPUSS off mode as an
independent state isn't supported on OMAP44XX devices.

Ofcourse when MPUSS power domain transitions to OSWR along
with device off mode, it eventually hits off state since memory
contents are lost.

Hence the MPUSS off mode independent state is not attempted without
device off mode. All the necessary infrastructure code for MPUSS
off mode is in place as part of this series.

Signed-off-by: Santosh Shilimkarsantosh.shilim...@ti.com
Cc: Kevin Hilmankhil...@ti.com


Compile failure for the !CONFIG_PM case:

[...]


@@ -70,11 +71,18 @@ static inline int omap4_mpuss_init(void)
  {
return 0;
  }
-
+static inline u32 omap4_mpuss_read_prev_context_state(void)
+{
+   return 0;
+}


added here


  static inline int omap4_finish_suspend(unsigned long cpu_state)
  {}
  static inline void omap4_cpu_resume(void)
  {}
+static inline u32 omap4_mpuss_read_prev_context_state(void)
+{
+   return 0;
+}


same thing added here


I noticed this yesterday and was planning to send a note on this
patch. :(
Have removed this already in the updated patches.
Thanks for pointing it out.

Regards
Santosh

--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 21/25] OMAP4: PM: Add MPUSS power domain OSWR support

2011-09-04 Thread Santosh Shilimkar 
This patch adds the MPUSS OSWR (Open Switch Retention) support. The MPUSS
OSWR configuration is as below.
- CPUx L1 and logic lost, MPUSS logic lost, L2 memory is retained

OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more
anymore just like CORE power domain. The deepest state supported is OSWR.
On OMAP4430 secure devices too, MPUSS off mode can't be used because of
a bug which alters Ducati and Tesla states. Hence MPUSS off mode as an
independent state isn't supported on OMAP44XX devices.

Ofcourse when MPUSS power domain transitions to OSWR along
with device off mode, it eventually hits off state since memory
contents are lost.

Hence the MPUSS off mode independent state is not attempted without
device off mode. All the necessary infrastructure code for MPUSS
off mode is in place as part of this series.

Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@ti.com
---
 arch/arm/mach-omap2/include/mach/omap4-common.h |   10 +++-
 arch/arm/mach-omap2/omap-mpuss-lowpower.c   |   65 +-
 arch/arm/mach-omap2/pm44xx.c|4 ++
 3 files changed, 75 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h 
b/arch/arm/mach-omap2/include/mach/omap4-common.h
index 14803c3..6651cb0 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -52,6 +52,7 @@ extern int omap4_enter_lowpower(unsigned int cpu, unsigned 
int power_state);
 extern int omap4_finish_suspend(unsigned long cpu_state);
 extern void omap4_cpu_resume(void);
 extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
+extern u32 omap4_mpuss_read_prev_context_state(void);
 #else
 static inline int omap4_enter_lowpower(unsigned int cpu,
unsigned int power_state)
@@ -70,11 +71,18 @@ static inline int omap4_mpuss_init(void)
 {
return 0;
 }
-
+static inline u32 omap4_mpuss_read_prev_context_state(void)
+{
+   return 0;
+}
 static inline int omap4_finish_suspend(unsigned long cpu_state)
 {}
 static inline void omap4_cpu_resume(void)
 {}
+static inline u32 omap4_mpuss_read_prev_context_state(void)
+{
+   return 0;
+}
 #endif
 
 #endif /* __ASSEMBLER__ */
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c 
b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index aea6deb..4dd9d0f 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -24,8 +24,8 @@
  * ON  ON  ON
  * ON(Inactive)OFF ON(Inactive)
  * OFF OFF CSWR
- * OFF OFF OSWR (*TBD)
- * OFF OFF OFF* (*TBD)
+ * OFF OFF OSWR
+ * OFF OFF OFF(Device OFF *TBD)
  * --
  *
  * Note: CPU0 is the master core and it is the last CPU to go down
@@ -56,7 +56,11 @@
 
 #include omap4-sar-layout.h
 #include pm.h
-#include powerdomain.h
+#include prcm_mpu44xx.h
+#include prminst44xx.h
+#include prcm44xx.h
+#include prm44xx.h
+#include prm-regbits-44xx.h
 
 #ifdef CONFIG_SMP
 
@@ -138,6 +142,48 @@ static void scu_pwrst_prepare(unsigned int cpu_id, 
unsigned int cpu_state)
__raw_writel(scu_pwr_st, pm_info-scu_sar_addr);
 }
 
+/* Helper functions for MPUSS OSWR */
+static inline void mpuss_clear_prev_logic_pwrst(void)
+{
+   u32 reg;
+
+   reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+   OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
+   omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
+   OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
+}
+
+static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
+{
+   u32 reg;
+
+   if (cpu_id) {
+   reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
+   OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+   omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
+   OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+   } else {
+   reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
+   OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+   omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
+   OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+   }
+}
+
+/**
+ * omap4_mpuss_read_prev_context_state:
+ * Function returns the MPUSS previous context state
+ */
+u32 omap4_mpuss_read_prev_context_state(void)
+{
+   u32 reg;
+
+   reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+   OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
+   reg = OMAP4430_LOSTCONTEXT_DFF_MASK;
+   return reg;
+}
+
 /*
  * Store the CPU cluster