Re: [PATCH V4 2/2] arm: dts: dra7: add crossbar device binding
* Lokesh Vutla lokeshvu...@ti.com [140709 23:00]: Hi Tony, On Wednesday 09 July 2014 09:14 PM, Tony Lindgren wrote: * Tony Lindgren t...@atomide.com [140626 03:28]: * Sricharan R r.sricha...@ti.com [140626 01:36]: Hi Tony, On Thursday 26 June 2014 01:14 PM, Tony Lindgren wrote: * Sricharan R r.sricha...@ti.com [140626 00:29]: From: R Sricharan r.sricha...@ti.com There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The Peripheral irq requests are connected to only one crossbar input and the output of the crossbar is connected to only one controller's input line. The crossbar device is used to map a peripheral input to a free mpu's interrupt controller line. Here, adding a new crossbar device node and replacing all the peripheral interrupt numbers with its fixed crossbar input lines. I think these two patches need to be a single patch to avoid breaking booting for git bisect inbetween these patches? This does not cause booting issues. irq_desc gets allocated linearly, but that does not create boot issues. OK These are now applied on top of Jason's immutable irqchip branch and merged and pushed out into omap-for-v3.17/dt. Can you guys please test? I have tested omap-for-v3.17/dt on DRA7 EVM. Crossbar is working fine. Looks good to me. lokesh@a0131933lt:~/working/mainline/linux$ git describe v3.16-rc1-34-g6464099 Please find the logs here: http://paste.ubuntu.com/7773616/ OK great thanks! Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 2/2] arm: dts: dra7: add crossbar device binding
* Tony Lindgren t...@atomide.com [140626 03:28]: * Sricharan R r.sricha...@ti.com [140626 01:36]: Hi Tony, On Thursday 26 June 2014 01:14 PM, Tony Lindgren wrote: * Sricharan R r.sricha...@ti.com [140626 00:29]: From: R Sricharan r.sricha...@ti.com There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The Peripheral irq requests are connected to only one crossbar input and the output of the crossbar is connected to only one controller's input line. The crossbar device is used to map a peripheral input to a free mpu's interrupt controller line. Here, adding a new crossbar device node and replacing all the peripheral interrupt numbers with its fixed crossbar input lines. I think these two patches need to be a single patch to avoid breaking booting for git bisect inbetween these patches? This does not cause booting issues. irq_desc gets allocated linearly, but that does not create boot issues. OK These are now applied on top of Jason's immutable irqchip branch and merged and pushed out into omap-for-v3.17/dt. Can you guys please test? Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 2/2] arm: dts: dra7: add crossbar device binding
Hi Tony, On Wednesday 09 July 2014 09:14 PM, Tony Lindgren wrote: * Tony Lindgren t...@atomide.com [140626 03:28]: * Sricharan R r.sricha...@ti.com [140626 01:36]: Hi Tony, On Thursday 26 June 2014 01:14 PM, Tony Lindgren wrote: * Sricharan R r.sricha...@ti.com [140626 00:29]: From: R Sricharan r.sricha...@ti.com There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The Peripheral irq requests are connected to only one crossbar input and the output of the crossbar is connected to only one controller's input line. The crossbar device is used to map a peripheral input to a free mpu's interrupt controller line. Here, adding a new crossbar device node and replacing all the peripheral interrupt numbers with its fixed crossbar input lines. I think these two patches need to be a single patch to avoid breaking booting for git bisect inbetween these patches? This does not cause booting issues. irq_desc gets allocated linearly, but that does not create boot issues. OK These are now applied on top of Jason's immutable irqchip branch and merged and pushed out into omap-for-v3.17/dt. Can you guys please test? I have tested omap-for-v3.17/dt on DRA7 EVM. Crossbar is working fine. Looks good to me. lokesh@a0131933lt:~/working/mainline/linux$ git describe v3.16-rc1-34-g6464099 Please find the logs here: http://paste.ubuntu.com/7773616/ Thanks and regards, Lokesh Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 2/2] arm: dts: dra7: add crossbar device binding
From: R Sricharan r.sricha...@ti.com
There is a IRQ crossbar device in the soc, which
maps the irq requests from the peripherals to the
mpu interrupt controller's inputs. The Peripheral irq
requests are connected to only one crossbar
input and the output of the crossbar is connected to only one
controller's input line. The crossbar device is used to map
a peripheral input to a free mpu's interrupt controller line.
Here, adding a new crossbar device node and replacing all the peripheral
interrupt numbers with its fixed crossbar input lines.
Signed-off-by: Sricharan R r.sricha...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Cc: Benoit Cousson bcous...@baylibre.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Tony Lindgren t...@atomide.com
---
arch/arm/boot/dts/dra7.dtsi | 138 +--
1 file changed, 80 insertions(+), 58 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 1cf4ee1..961be6b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -12,6 +12,9 @@
#include skeleton.dtsi
+#define MAX_SOURCES 400
+#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
+
/ {
#address-cells = 1;
#size-cells = 1;
@@ -80,8 +83,8 @@
ti,hwmods = l3_main_1, l3_main_2;
reg = 0x4400 0x100,
0x4500 0x1000;
- interrupts = GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH;
prm: prm@4ae06000 {
compatible = ti,dra7-prm;
@@ -156,10 +159,10 @@
sdma: dma-controller@4a056000 {
compatible = ti,omap4430-sdma;
reg = 0x4a056000 0x1000;
- interrupts = GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
#dma-cells = 1;
#dma-channels = 32;
#dma-requests = 127;
@@ -168,7 +171,7 @@
gpio1: gpio@4ae1 {
compatible = ti,omap4-gpio;
reg = 0x4ae1 0x200;
- interrupts = GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio1;
gpio-controller;
#gpio-cells = 2;
@@ -179,7 +182,7 @@
gpio2: gpio@48055000 {
compatible = ti,omap4-gpio;
reg = 0x48055000 0x200;
- interrupts = GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio2;
gpio-controller;
#gpio-cells = 2;
@@ -190,7 +193,7 @@
gpio3: gpio@48057000 {
compatible = ti,omap4-gpio;
reg = 0x48057000 0x200;
- interrupts = GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio3;
gpio-controller;
#gpio-cells = 2;
@@ -201,7 +204,7 @@
gpio4: gpio@48059000 {
compatible = ti,omap4-gpio;
reg = 0x48059000 0x200;
- interrupts = GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio4;
gpio-controller;
#gpio-cells = 2;
@@ -212,7 +215,7 @@
gpio5: gpio@4805b000 {
compatible = ti,omap4-gpio;
reg = 0x4805b000 0x200;
- interrupts = GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio5;
gpio-controller;
#gpio-cells = 2;
@@ -223,7 +226,7 @@
gpio6: gpio@4805d000 {
compatible = ti,omap4-gpio;
reg = 0x4805d000 0x200;
- interrupts = GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH;
+ interrupts =
Re: [PATCH V4 2/2] arm: dts: dra7: add crossbar device binding
* Sricharan R r.sricha...@ti.com [140626 00:29]: From: R Sricharan r.sricha...@ti.com There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The Peripheral irq requests are connected to only one crossbar input and the output of the crossbar is connected to only one controller's input line. The crossbar device is used to map a peripheral input to a free mpu's interrupt controller line. Here, adding a new crossbar device node and replacing all the peripheral interrupt numbers with its fixed crossbar input lines. I think these two patches need to be a single patch to avoid breaking booting for git bisect inbetween these patches? Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 2/2] arm: dts: dra7: add crossbar device binding
Hi Tony, On Thursday 26 June 2014 01:14 PM, Tony Lindgren wrote: * Sricharan R r.sricha...@ti.com [140626 00:29]: From: R Sricharan r.sricha...@ti.com There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The Peripheral irq requests are connected to only one crossbar input and the output of the crossbar is connected to only one controller's input line. The crossbar device is used to map a peripheral input to a free mpu's interrupt controller line. Here, adding a new crossbar device node and replacing all the peripheral interrupt numbers with its fixed crossbar input lines. I think these two patches need to be a single patch to avoid breaking booting for git bisect inbetween these patches? This does not cause booting issues. irq_desc gets allocated linearly, but that does not create boot issues. Regards, Sricharan -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 2/2] arm: dts: dra7: add crossbar device binding
* Sricharan R r.sricha...@ti.com [140626 01:36]: Hi Tony, On Thursday 26 June 2014 01:14 PM, Tony Lindgren wrote: * Sricharan R r.sricha...@ti.com [140626 00:29]: From: R Sricharan r.sricha...@ti.com There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The Peripheral irq requests are connected to only one crossbar input and the output of the crossbar is connected to only one controller's input line. The crossbar device is used to map a peripheral input to a free mpu's interrupt controller line. Here, adding a new crossbar device node and replacing all the peripheral interrupt numbers with its fixed crossbar input lines. I think these two patches need to be a single patch to avoid breaking booting for git bisect inbetween these patches? This does not cause booting issues. irq_desc gets allocated linearly, but that does not create boot issues. OK Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
