Re: [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration
Hi,
On Fri, Sep 2, 2011 at 10:43 AM, Tomi Valkeinen wrote:
> On Fri, 2011-09-02 at 10:41 +0530, K, Mythri P wrote:
>> Hi,
>>
>> On Thu, Sep 1, 2011 at 1:57 PM, Tomi Valkeinen wrote:
>> > On Mon, 2011-08-29 at 11:44 +0530, mythr...@ti.com wrote:
>> >> From: Mythri P K
>> >>
>> >> As the pll and the video configuration info are part of the ip_data those
>> >> structures are moved to the ip_data strtucure.Also the functions are
>> >> modified
>> >> accordingly to take care of this movement.
>> >
>> > structure typoed, and use a space after period.
>> >
>> >> Signed-off-by: Mythri P K
>> >> ---
>> >> drivers/video/omap2/dss/hdmi.c | 34 +++---
>> >> drivers/video/omap2/dss/hdmi.h | 18 ++
>> >> 2 files changed, 25 insertions(+), 27 deletions(-)
>
>> >> -static int hdmi_pll_program(struct hdmi_ip_data *ip_data,
>> >> - struct hdmi_pll_info *fmt)
>> >> +static int hdmi_pll_program(struct hdmi_ip_data *ip_data)
>> >> {
>> >> u16 r = 0;
>> >> enum hdmi_clk_refsel refsel;
>> >> @@ -399,7 +397,7 @@ static int hdmi_pll_program(struct hdmi_ip_data
>> >> *ip_data,
>> >>
>> >> refsel = HDMI_REFSEL_SYSCLK;
>> >>
>> >> - r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd);
>> >> + r = hdmi_pll_init(ip_data, refsel);
>> >
>> > I don't think I quite understood why refsel is not part of the pll info.
>> > And if it has to be hardcoded, you could as well do that in
>> > hdmi_pll_init().
>> >
>> Ok , yes that is better.
>
> So, why refsel is not part of the pll info? The HW doesn't support
> changing it? If so, is it only for OMAPs or for all SoCs?
It is a variable parameter ,H/w supports changing it but it is never tried,
I was considering hard-coding it in the hdmi.c and passing it,
so that there would be no hard-coding in IP functions.
Thanks and regards,
Mythri.
>
> Tomi
>
>
>
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Re: [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration
On Fri, 2011-09-02 at 10:41 +0530, K, Mythri P wrote:
> Hi,
>
> On Thu, Sep 1, 2011 at 1:57 PM, Tomi Valkeinen wrote:
> > On Mon, 2011-08-29 at 11:44 +0530, mythr...@ti.com wrote:
> >> From: Mythri P K
> >>
> >> As the pll and the video configuration info are part of the ip_data those
> >> structures are moved to the ip_data strtucure.Also the functions are
> >> modified
> >> accordingly to take care of this movement.
> >
> > structure typoed, and use a space after period.
> >
> >> Signed-off-by: Mythri P K
> >> ---
> >> drivers/video/omap2/dss/hdmi.c | 34 +++---
> >> drivers/video/omap2/dss/hdmi.h | 18 ++
> >> 2 files changed, 25 insertions(+), 27 deletions(-)
> >> -static int hdmi_pll_program(struct hdmi_ip_data *ip_data,
> >> - struct hdmi_pll_info *fmt)
> >> +static int hdmi_pll_program(struct hdmi_ip_data *ip_data)
> >> {
> >> u16 r = 0;
> >> enum hdmi_clk_refsel refsel;
> >> @@ -399,7 +397,7 @@ static int hdmi_pll_program(struct hdmi_ip_data
> >> *ip_data,
> >>
> >> refsel = HDMI_REFSEL_SYSCLK;
> >>
> >> - r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd);
> >> + r = hdmi_pll_init(ip_data, refsel);
> >
> > I don't think I quite understood why refsel is not part of the pll info.
> > And if it has to be hardcoded, you could as well do that in
> > hdmi_pll_init().
> >
> Ok , yes that is better.
So, why refsel is not part of the pll info? The HW doesn't support
changing it? If so, is it only for OMAPs or for all SoCs?
Tomi
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Re: [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration
Hi,
On Thu, Sep 1, 2011 at 1:57 PM, Tomi Valkeinen wrote:
> On Mon, 2011-08-29 at 11:44 +0530, mythr...@ti.com wrote:
>> From: Mythri P K
>>
>> As the pll and the video configuration info are part of the ip_data those
>> structures are moved to the ip_data strtucure.Also the functions are modified
>> accordingly to take care of this movement.
>
> structure typoed, and use a space after period.
>
>> Signed-off-by: Mythri P K
>> ---
>> drivers/video/omap2/dss/hdmi.c | 34 +++---
>> drivers/video/omap2/dss/hdmi.h | 18 ++
>> 2 files changed, 25 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
>> index 544f93e..084a47e 100644
>> --- a/drivers/video/omap2/dss/hdmi.c
>> +++ b/drivers/video/omap2/dss/hdmi.c
>> @@ -59,7 +59,6 @@ static struct {
>> u8 edid[HDMI_EDID_MAX_LENGTH];
>> u8 edid_set;
>> bool custom_set;
>> - struct hdmi_config cfg;
>>
>> struct clk *sys_clk;
>> } hdmi;
>> @@ -230,11 +229,11 @@ int hdmi_init_display(struct omap_dss_device *dssdev)
>> }
>>
>> static int hdmi_pll_init(struct hdmi_ip_data *ip_data,
>> - enum hdmi_clk_refsel refsel, int dcofreq,
>> - struct hdmi_pll_info *fmt, u16 sd)
>> + enum hdmi_clk_refsel refsel)
>> {
>> u32 r;
>> void __iomem *pll_base = hdmi_pll_base(ip_data);
>> + struct hdmi_pll_info *fmt = &ip_data->pll_data;
>>
>> /* PLL start always use manual mode */
>> REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
>> @@ -251,9 +250,9 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data,
>> r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
>> r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
>>
>> - if (dcofreq) {
>> + if (fmt->dcofreq) {
>> /* divider programming for frequency beyond 1000Mhz */
>> - REG_FLD_MOD(pll_base, PLLCTRL_CFG3, sd, 17, 10);
>> + REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
>> r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
>> } else {
>> r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
>> @@ -379,8 +378,7 @@ static int hdmi_phy_init(struct hdmi_ip_data *ip_data)
>> return 0;
>> }
>>
>> -static int hdmi_pll_program(struct hdmi_ip_data *ip_data,
>> - struct hdmi_pll_info *fmt)
>> +static int hdmi_pll_program(struct hdmi_ip_data *ip_data)
>> {
>> u16 r = 0;
>> enum hdmi_clk_refsel refsel;
>> @@ -399,7 +397,7 @@ static int hdmi_pll_program(struct hdmi_ip_data *ip_data,
>>
>> refsel = HDMI_REFSEL_SYSCLK;
>>
>> - r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd);
>> + r = hdmi_pll_init(ip_data, refsel);
>
> I don't think I quite understood why refsel is not part of the pll info.
> And if it has to be hardcoded, you could as well do that in
> hdmi_pll_init().
>
Ok , yes that is better.
> Tomi
>
>
>
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Re: [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration
On Mon, 2011-08-29 at 11:44 +0530, mythr...@ti.com wrote:
> From: Mythri P K
>
> As the pll and the video configuration info are part of the ip_data those
> structures are moved to the ip_data strtucure.Also the functions are modified
> accordingly to take care of this movement.
structure typoed, and use a space after period.
> Signed-off-by: Mythri P K
> ---
> drivers/video/omap2/dss/hdmi.c | 34 +++---
> drivers/video/omap2/dss/hdmi.h | 18 ++
> 2 files changed, 25 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
> index 544f93e..084a47e 100644
> --- a/drivers/video/omap2/dss/hdmi.c
> +++ b/drivers/video/omap2/dss/hdmi.c
> @@ -59,7 +59,6 @@ static struct {
> u8 edid[HDMI_EDID_MAX_LENGTH];
> u8 edid_set;
> bool custom_set;
> - struct hdmi_config cfg;
>
> struct clk *sys_clk;
> } hdmi;
> @@ -230,11 +229,11 @@ int hdmi_init_display(struct omap_dss_device *dssdev)
> }
>
> static int hdmi_pll_init(struct hdmi_ip_data *ip_data,
> - enum hdmi_clk_refsel refsel, int dcofreq,
> - struct hdmi_pll_info *fmt, u16 sd)
> + enum hdmi_clk_refsel refsel)
> {
> u32 r;
> void __iomem *pll_base = hdmi_pll_base(ip_data);
> + struct hdmi_pll_info *fmt = &ip_data->pll_data;
>
> /* PLL start always use manual mode */
> REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
> @@ -251,9 +250,9 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data,
> r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
> r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
>
> - if (dcofreq) {
> + if (fmt->dcofreq) {
> /* divider programming for frequency beyond 1000Mhz */
> - REG_FLD_MOD(pll_base, PLLCTRL_CFG3, sd, 17, 10);
> + REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
> r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
> } else {
> r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
> @@ -379,8 +378,7 @@ static int hdmi_phy_init(struct hdmi_ip_data *ip_data)
> return 0;
> }
>
> -static int hdmi_pll_program(struct hdmi_ip_data *ip_data,
> - struct hdmi_pll_info *fmt)
> +static int hdmi_pll_program(struct hdmi_ip_data *ip_data)
> {
> u16 r = 0;
> enum hdmi_clk_refsel refsel;
> @@ -399,7 +397,7 @@ static int hdmi_pll_program(struct hdmi_ip_data *ip_data,
>
> refsel = HDMI_REFSEL_SYSCLK;
>
> - r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd);
> + r = hdmi_pll_init(ip_data, refsel);
I don't think I quite understood why refsel is not part of the pll info.
And if it has to be hardcoded, you could as well do that in
hdmi_pll_init().
Tomi
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[PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration
From: Mythri P K
As the pll and the video configuration info are part of the ip_data those
structures are moved to the ip_data strtucure.Also the functions are modified
accordingly to take care of this movement.
Signed-off-by: Mythri P K
---
drivers/video/omap2/dss/hdmi.c | 34 +++---
drivers/video/omap2/dss/hdmi.h | 18 ++
2 files changed, 25 insertions(+), 27 deletions(-)
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index 544f93e..084a47e 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -59,7 +59,6 @@ static struct {
u8 edid[HDMI_EDID_MAX_LENGTH];
u8 edid_set;
bool custom_set;
- struct hdmi_config cfg;
struct clk *sys_clk;
} hdmi;
@@ -230,11 +229,11 @@ int hdmi_init_display(struct omap_dss_device *dssdev)
}
static int hdmi_pll_init(struct hdmi_ip_data *ip_data,
- enum hdmi_clk_refsel refsel, int dcofreq,
- struct hdmi_pll_info *fmt, u16 sd)
+ enum hdmi_clk_refsel refsel)
{
u32 r;
void __iomem *pll_base = hdmi_pll_base(ip_data);
+ struct hdmi_pll_info *fmt = &ip_data->pll_data;
/* PLL start always use manual mode */
REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
@@ -251,9 +250,9 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data,
r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
- if (dcofreq) {
+ if (fmt->dcofreq) {
/* divider programming for frequency beyond 1000Mhz */
- REG_FLD_MOD(pll_base, PLLCTRL_CFG3, sd, 17, 10);
+ REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
} else {
r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
@@ -379,8 +378,7 @@ static int hdmi_phy_init(struct hdmi_ip_data *ip_data)
return 0;
}
-static int hdmi_pll_program(struct hdmi_ip_data *ip_data,
- struct hdmi_pll_info *fmt)
+static int hdmi_pll_program(struct hdmi_ip_data *ip_data)
{
u16 r = 0;
enum hdmi_clk_refsel refsel;
@@ -399,7 +397,7 @@ static int hdmi_pll_program(struct hdmi_ip_data *ip_data,
refsel = HDMI_REFSEL_SYSCLK;
- r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd);
+ r = hdmi_pll_init(ip_data, refsel);
if (r)
return r;
@@ -1015,8 +1013,7 @@ static void hdmi_wp_video_config_timing(struct
hdmi_ip_data *ip_data,
hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
}
-static void hdmi_basic_configure(struct hdmi_ip_data *ip_data,
- struct hdmi_config *cfg)
+static void hdmi_basic_configure(struct hdmi_ip_data *ip_data)
{
/* HDMI */
struct omap_video_timings video_timing;
@@ -1026,6 +1023,7 @@ static void hdmi_basic_configure(struct hdmi_ip_data
*ip_data,
struct hdmi_core_infoframe_avi avi_cfg;
struct hdmi_core_video_config v_core_cfg;
struct hdmi_core_packet_enable_repeat repeat_cfg;
+ struct hdmi_config *cfg = &ip_data->cfg;
hdmi_wp_init(&video_timing, &video_format,
&video_interface);
@@ -1034,8 +1032,7 @@ static void hdmi_basic_configure(struct hdmi_ip_data
*ip_data,
&avi_cfg,
&repeat_cfg);
- hdmi_wp_video_init_format(&video_format,
- &video_timing, cfg);
+ hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
hdmi_wp_video_config_timing(ip_data, &video_timing);
@@ -1161,7 +1158,6 @@ static void hdmi_compute_pll(struct omap_dss_device
*dssdev, int phy,
static int hdmi_power_on(struct omap_dss_device *dssdev)
{
int r, code = 0;
- struct hdmi_pll_info pll_data;
struct omap_video_timings *p;
unsigned long phy;
@@ -1183,16 +1179,16 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
}
code = get_timings_index();
dssdev->panel.timings = cea_vesa_timings[code].timings;
- update_hdmi_timings(&hdmi.cfg, p, code);
+ update_hdmi_timings(&hdmi.hdmi_data.cfg, p, code);
phy = p->pixel_clock;
- hdmi_compute_pll(dssdev, phy, &pll_data);
+ hdmi_compute_pll(dssdev, phy, &hdmi.hdmi_data.pll_data);
hdmi_wp_video_start(&hdmi.hdmi_data, 0);
/* config the PLL and PHY hdmi_set_pll_pwrfirst */
- r = hdmi_pll_program(&hdmi.hdmi_data, &pll_data);
+ r = hdmi_pll_program(&hdmi.hdmi_data);
if (r) {
DSSDBG("Failed to lock PLL\n");
goto err;
@@ -1204,9 +1200,9 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
goto err;
}
- hdmi.cfg.cm.mode = hdmi.mode;
- hdmi.cfg.cm.code = hdmi.code;
-
