From: Tero Kristo <tero.kri...@nokia.com>
Add missing SDRC register offset macros.
Signed-off-by: Tero Kristo <tero.kri...@nokia.com>
Signed-off-by: Kevin Hilman <khil...@deeprootsystems.com>
[p...@pwsan.com: added commit message]
Signed-off-by: Paul Walmsley <p...@pwsan.com>
---
arch/arm/plat-omap/include/mach/sdrc.h | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h
b/arch/arm/plat-omap/include/mach/sdrc.h
index 0be18e4..8fff90a 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -21,19 +21,28 @@
/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
#define SDRC_SYSCONFIG 0x010
+#define SDRC_CS_CFG 0x040
+#define SDRC_SHARING 0x044
+#define SDRC_ERR_TYPE 0x04C
#define SDRC_DLLA_CTRL 0x060
#define SDRC_DLLA_STATUS 0x064
#define SDRC_DLLB_CTRL 0x068
#define SDRC_DLLB_STATUS 0x06C
#define SDRC_POWER 0x070
+#define SDRC_MCFG_0 0x080
#define SDRC_MR_0 0x084
+#define SDRC_EMR2_0 0x08c
#define SDRC_ACTIM_CTRL_A_0 0x09c
#define SDRC_ACTIM_CTRL_B_0 0x0a0
#define SDRC_RFR_CTRL_0 0x0a4
+#define SDRC_MANUAL_0 0x0a8
+#define SDRC_MCFG_1 0x0B0
#define SDRC_MR_1 0x0B4
+#define SDRC_EMR2_1 0x0BC
#define SDRC_ACTIM_CTRL_A_1 0x0C4
#define SDRC_ACTIM_CTRL_B_1 0x0C8
#define SDRC_RFR_CTRL_1 0x0D4
+#define SDRC_MANUAL_1 0x0D8
/*
* These values represent the number of memory clock cycles between
--
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