Re: [PATCH v2 07/11] mmc: host: omap_hsmmc: add tuning support

2015-08-25 Thread Ulf Hansson
On 25 August 2015 at 11:05, Kishon Vijay Abraham I kis...@ti.com wrote:
 From: Balaji T K balaj...@ti.com

 MMC tuning procedure is required to support SD card
 UHS1-SDR104 mode and EMMC HS200 mode.

 The tuning function omap_execute_tuning() will only
 be called by the MMC/SD core if the corresponding
 speed modes are supported by the OMAP silicon which
 is set in the mmc host caps field.

 Signed-off-by: Balaji T K balaj...@ti.com
 Signed-off-by: Viswanath Puttagunta vi...@ti.com
 Signed-off-by: Sourav Poddar sourav.pod...@ti.com
 [kis...@ti.com : cleanup the tuning sequence]
 Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
 ---
  drivers/mmc/host/omap_hsmmc.c |  234 
 -
  1 file changed, 232 insertions(+), 2 deletions(-)

 diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
 index c042b91..43485c3 100644
 --- a/drivers/mmc/host/omap_hsmmc.c
 +++ b/drivers/mmc/host/omap_hsmmc.c
 @@ -18,6 +18,7 @@
  #include linux/module.h
  #include linux/init.h
  #include linux/kernel.h
 +#include linux/slab.h
  #include linux/debugfs.h
  #include linux/dmaengine.h
  #include linux/seq_file.h
 @@ -49,6 +50,7 @@
  /* OMAP HSMMC Host Controller Registers */
  #define OMAP_HSMMC_SYSSTATUS   0x0014
  #define OMAP_HSMMC_CON 0x002C
 +#define OMAP_HSMMC_DLL 0x0034
  #define OMAP_HSMMC_SDMASA  0x0100
  #define OMAP_HSMMC_BLK 0x0104
  #define OMAP_HSMMC_ARG 0x0108
 @@ -66,6 +68,7 @@
  #define OMAP_HSMMC_ISE 0x0138
  #define OMAP_HSMMC_AC120x013C
  #define OMAP_HSMMC_CAPA0x0140
 +#define OMAP_HSMMC_CAPA2   0x0144

  #define VS18   (1  26)
  #define VS30   (1  25)
 @@ -114,6 +117,7 @@

  /* AC12 */
  #define AC12_V1V8_SIGEN(1  19)
 +#define AC12_SCLK_SEL  (1  23)
  #define AC12_UHSMC_MASK(7  16)
  #define AC12_UHSMC_SDR12   (0  16)
  #define AC12_UHSMC_SDR25   (1  16)
 @@ -122,6 +126,18 @@
  #define AC12_UHSMC_DDR50   (4  16)
  #define AC12_UHSMC_RES (0x7  16)

 +/* DLL */
 +#define DLL_SWT(1  20)
 +#define DLL_FORCE_SR_C_SHIFT   13
 +#define DLL_FORCE_SR_C_MASK0x7f
 +#define DLL_FORCE_VALUE(1  12)
 +#define DLL_CALIB  (1  1)
 +
 +#define MAX_PHASE_DELAY0x7c
 +
 +/* CAPA2 */
 +#define CAPA2_TSDR50   (1  13)
 +
  /* Interrupt masks for IE and ISE register */
  #define CC_EN  (1  0)
  #define TC_EN  (1  1)
 @@ -202,6 +218,7 @@ struct omap_hsmmc_host {
 int vqmmc_enabled;
 resource_size_t mapbase;
 spinlock_t  irq_lock; /* Prevent races with irq handler */
 +   struct completion   buf_ready;
 unsigned intdma_len;
 unsigned intdma_sg_idx;
 unsigned char   bus_mode;
 @@ -229,6 +246,9 @@ struct omap_hsmmc_host {
 struct omap_hsmmc_next  next_data;
 struct  omap_hsmmc_platform_data*pdata;

 +   u32 *tuning_data;
 +   int tuning_size;
 +
 /* return MMC cover switch state, can be NULL if not supported.
  *
  * possible return values:
 @@ -245,8 +265,39 @@ struct omap_mmc_of_data {
 u8 controller_flags;
  };

 +static const u8 ref_tuning_4bits[] = {
 +   0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 +   0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 +   0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 +   0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 +   0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 +   0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 +   0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 +   0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 +};
 +
 +static const u8 ref_tuning_8bits[] = {
 +   0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 +   0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 +   0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 +   0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 +   0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 +   0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 +   0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 +   0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 +   0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 +   0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 +   0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 +   0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 +   0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 +   0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 +   0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 +   0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 +};

These bit patterns already exists in the mmc core as a part of the
mmc_send_tuning() API.

 +
  static void 

[PATCH v2 07/11] mmc: host: omap_hsmmc: add tuning support

2015-08-25 Thread Kishon Vijay Abraham I
From: Balaji T K balaj...@ti.com

MMC tuning procedure is required to support SD card
UHS1-SDR104 mode and EMMC HS200 mode.

The tuning function omap_execute_tuning() will only
be called by the MMC/SD core if the corresponding
speed modes are supported by the OMAP silicon which
is set in the mmc host caps field.

Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Viswanath Puttagunta vi...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
[kis...@ti.com : cleanup the tuning sequence]
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
 drivers/mmc/host/omap_hsmmc.c |  234 -
 1 file changed, 232 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index c042b91..43485c3 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -18,6 +18,7 @@
 #include linux/module.h
 #include linux/init.h
 #include linux/kernel.h
+#include linux/slab.h
 #include linux/debugfs.h
 #include linux/dmaengine.h
 #include linux/seq_file.h
@@ -49,6 +50,7 @@
 /* OMAP HSMMC Host Controller Registers */
 #define OMAP_HSMMC_SYSSTATUS   0x0014
 #define OMAP_HSMMC_CON 0x002C
+#define OMAP_HSMMC_DLL 0x0034
 #define OMAP_HSMMC_SDMASA  0x0100
 #define OMAP_HSMMC_BLK 0x0104
 #define OMAP_HSMMC_ARG 0x0108
@@ -66,6 +68,7 @@
 #define OMAP_HSMMC_ISE 0x0138
 #define OMAP_HSMMC_AC120x013C
 #define OMAP_HSMMC_CAPA0x0140
+#define OMAP_HSMMC_CAPA2   0x0144
 
 #define VS18   (1  26)
 #define VS30   (1  25)
@@ -114,6 +117,7 @@
 
 /* AC12 */
 #define AC12_V1V8_SIGEN(1  19)
+#define AC12_SCLK_SEL  (1  23)
 #define AC12_UHSMC_MASK(7  16)
 #define AC12_UHSMC_SDR12   (0  16)
 #define AC12_UHSMC_SDR25   (1  16)
@@ -122,6 +126,18 @@
 #define AC12_UHSMC_DDR50   (4  16)
 #define AC12_UHSMC_RES (0x7  16)
 
+/* DLL */
+#define DLL_SWT(1  20)
+#define DLL_FORCE_SR_C_SHIFT   13
+#define DLL_FORCE_SR_C_MASK0x7f
+#define DLL_FORCE_VALUE(1  12)
+#define DLL_CALIB  (1  1)
+
+#define MAX_PHASE_DELAY0x7c
+
+/* CAPA2 */
+#define CAPA2_TSDR50   (1  13)
+
 /* Interrupt masks for IE and ISE register */
 #define CC_EN  (1  0)
 #define TC_EN  (1  1)
@@ -202,6 +218,7 @@ struct omap_hsmmc_host {
int vqmmc_enabled;
resource_size_t mapbase;
spinlock_t  irq_lock; /* Prevent races with irq handler */
+   struct completion   buf_ready;
unsigned intdma_len;
unsigned intdma_sg_idx;
unsigned char   bus_mode;
@@ -229,6 +246,9 @@ struct omap_hsmmc_host {
struct omap_hsmmc_next  next_data;
struct  omap_hsmmc_platform_data*pdata;
 
+   u32 *tuning_data;
+   int tuning_size;
+
/* return MMC cover switch state, can be NULL if not supported.
 *
 * possible return values:
@@ -245,8 +265,39 @@ struct omap_mmc_of_data {
u8 controller_flags;
 };
 
+static const u8 ref_tuning_4bits[] = {
+   0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
+   0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
+   0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
+   0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
+   0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
+   0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
+   0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
+   0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
+};
+
+static const u8 ref_tuning_8bits[] = {
+   0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
+   0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
+   0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
+   0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
+   0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
+   0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
+   0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
+   0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
+   0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
+   0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
+   0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
+   0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
+   0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
+   0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
+   0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
+   0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
+};
+
 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host, int iov);
+static void omap_hsmmc_disable_tuning(struct omap_hsmmc_host *host);
 
 static int omap_hsmmc_card_detect(struct device *dev)
 {
@@ -609,8 +660,12 @@