Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.
Hi Mark, On Tuesday 10 December 2013 04:01 PM, Mark Brown wrote: On Tue, Dec 10, 2013 at 09:55:15AM +0530, Sourav Poddar wrote: I posted this for review along with other code changes. I will post them seperately to Benoit. Please wait until the driver updates have been reviewed. I was thinking of sending this dts patches seperately to benoit, so that we can enable atleast 1/4 bit mode for our controller. Anyways, there is no memory mapped specific binding used. Once, we get our driver updates reviewed and *if* there is anything memory mapped specific added, I can send them as a seperate patch. Anyways with spi nor framework in sight the driver uodates can go anyewhere and might take some time. . Does this sound Ok to you? -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.
On Tuesday 10 December 2013 04:01 PM, Mark Brown wrote: On Tue, Dec 10, 2013 at 09:55:15AM +0530, Sourav Poddar wrote: I posted this for review along with other code changes. I will post them seperately to Benoit. Please wait until the driver updates have been reviewed. Ok. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.
On Tue, Dec 10, 2013 at 09:55:15AM +0530, Sourav Poddar wrote: > I posted this for review along with other code changes. > I will post them seperately to Benoit. Please wait until the driver updates have been reviewed. signature.asc Description: Digital signature
Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.
On Monday 09 December 2013 11:12 PM, Tony Lindgren wrote:
* Sourav Poddar [131206 06:29]:
These add device tree entry for qspi controller driver on dra7.
FYI these .dts changes need to be queued separately by Benoit and
should be posted as a seprate series in general to avoid confusion.
Ok, thanks!
I posted this for review along with other code changes.
I will post them seperately to Benoit.
Regards,
Tony
Signed-off-by: Sourav Poddar
---
v1->v2:
use "MUX_MODE1" instead of numeric value
arch/arm/boot/dts/dra7-evm.dts | 32
arch/arm/boot/dts/dra7.dtsi| 13 +
2 files changed, 45 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..4a57fdf 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,21 @@
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>;
};
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins =<
+ 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
+ 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
+ 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
+ 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
+ 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
+ 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+ 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
+ 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
+ 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs2.qspi1_cs0 */
+ 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs3.qspi1_cs1 */
+ >;
+ };
};
&i2c1 {
@@ -273,3 +288,20 @@
&cpu0 {
cpu0-supply =<&smps123_reg>;
};
+
+&qspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 =<&qspi1_pins>;
+
+ spi-max-frequency =<4800>;
+ m25p80@0 {
+ compatible = "s25fl256s1";
+ spi-max-frequency =<4800>;
+ reg =<0>;
+ spi-tx-bus-width =<1>;
+ spi-rx-bus-width =<4>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 67275c8..b06d899 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -582,6 +582,19 @@
dma-names = "tx0", "rx0";
status = "disabled";
};
+
+ qspi: qspi@4b30 {
+ compatible = "ti,dra7xxx-qspi";
+ reg =<0x4b30 0x100>,<0x4a002558 0x4>,
+ <0x5c00 0x3ff>;
+ reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
+ #address-cells =<1>;
+ #size-cells =<0>;
+ ti,hwmods = "qspi";
+ num-cs =<4>;
+ interrupts =<0 124 0x4>;
+ status = "disabled";
+ };
};
clocks {
--
1.7.1
--
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Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.
* Sourav Poddar [131206 06:29]:
> These add device tree entry for qspi controller driver on dra7.
FYI these .dts changes need to be queued separately by Benoit and
should be posted as a seprate series in general to avoid confusion.
Regards,
Tony
> Signed-off-by: Sourav Poddar
> ---
> v1->v2:
> use "MUX_MODE1" instead of numeric value
> arch/arm/boot/dts/dra7-evm.dts | 32
> arch/arm/boot/dts/dra7.dtsi| 13 +
> 2 files changed, 45 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
> index 5babba0..4a57fdf 100644
> --- a/arch/arm/boot/dts/dra7-evm.dts
> +++ b/arch/arm/boot/dts/dra7-evm.dts
> @@ -93,6 +93,21 @@
> 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
> >;
> };
> +
> + qspi1_pins: pinmux_qspi1_pins {
> + pinctrl-single,pins = <
> + 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
> + 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
> + 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
> + 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
> + 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
> + 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
> + 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
> + 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
> + 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /*
> gpmc_cs2.qspi1_cs0 */
> + 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /*
> gpmc_cs3.qspi1_cs1 */
> + >;
> + };
> };
>
> &i2c1 {
> @@ -273,3 +288,20 @@
> &cpu0 {
> cpu0-supply = <&smps123_reg>;
> };
> +
> +&qspi {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&qspi1_pins>;
> +
> + spi-max-frequency = <4800>;
> + m25p80@0 {
> + compatible = "s25fl256s1";
> + spi-max-frequency = <4800>;
> + reg = <0>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>;
> + spi-cpol;
> + spi-cpha;
> + };
> +};
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 67275c8..b06d899 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -582,6 +582,19 @@
> dma-names = "tx0", "rx0";
> status = "disabled";
> };
> +
> + qspi: qspi@4b30 {
> + compatible = "ti,dra7xxx-qspi";
> + reg = <0x4b30 0x100>, <0x4a002558 0x4>,
> + <0x5c00 0x3ff>;
> + reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ti,hwmods = "qspi";
> + num-cs = <4>;
> + interrupts = <0 124 0x4>;
> + status = "disabled";
> + };
> };
>
> clocks {
> --
> 1.7.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majord...@vger.kernel.org
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[PATCHv2 09/10] arm: dts: dra7: Add qspi device.
These add device tree entry for qspi controller driver on dra7.
Signed-off-by: Sourav Poddar
---
v1->v2:
use "MUX_MODE1" instead of numeric value
arch/arm/boot/dts/dra7-evm.dts | 32
arch/arm/boot/dts/dra7.dtsi| 13 +
2 files changed, 45 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..4a57fdf 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,21 @@
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>;
};
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins = <
+ 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
+ 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
+ 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
+ 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
+ 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
+ 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+ 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
+ 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
+ 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs2.qspi1_cs0 */
+ 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs3.qspi1_cs1 */
+ >;
+ };
};
&i2c1 {
@@ -273,3 +288,20 @@
&cpu0 {
cpu0-supply = <&smps123_reg>;
};
+
+&qspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi1_pins>;
+
+ spi-max-frequency = <4800>;
+ m25p80@0 {
+ compatible = "s25fl256s1";
+ spi-max-frequency = <4800>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 67275c8..b06d899 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -582,6 +582,19 @@
dma-names = "tx0", "rx0";
status = "disabled";
};
+
+ qspi: qspi@4b30 {
+ compatible = "ti,dra7xxx-qspi";
+ reg = <0x4b30 0x100>, <0x4a002558 0x4>,
+ <0x5c00 0x3ff>;
+ reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "qspi";
+ num-cs = <4>;
+ interrupts = <0 124 0x4>;
+ status = "disabled";
+ };
};
clocks {
--
1.7.1
--
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