Re: DM3730 without PMIC oops on idle
Hi Kevin, thank you for your help. 2012/6/27 Kevin Hilman khil...@ti.com: jean-philippe francois jp.franc...@cynove.com writes: Hi, My board does not have any Power Management IC. Without the following patch, the bood ends with an oops. How can I further debug this, ie trace through the assembly in arch/arm/mach-omap2/sleep34xx.S ? The assembly code that is faulting has nothing to do with interaction with the PMIC. Some more comments below ... -- Patch needed to boot to userspace : Index: linux-3.4.3/arch/arm/mach-omap2/pm34xx.c === --- linux-3.4.3.orig/arch/arm/mach-omap2/pm34xx.c 2012-06-17 20:21:44.0 +0200 +++ linux-3.4.3/arch/arm/mach-omap2/pm34xx.c 2012-06-22 16:26:38.0 +0200 @@ -403,7 +403,7 @@ trace_power_start(POWER_CSTATE, 1, smp_processor_id()); trace_cpu_idle(1, smp_processor_id()); - omap_sram_idle(); + // omap_sram_idle(); FYI... you can get the same effect without patching the kernel by adding 'nohlt' to the kernel command line. That avoids entering the idle loop alltogether. Good to know :) clock: disabling unused clocks to save power Unable to handle kernel NULL pointer dereference at virtual address pgd = c0004000 [] *pgd= Internal error: Oops: 8005 [#1] PREEMPT ARM Modules linked in: CPU: 0 Tainted: G W (3.4.3 #2) PC is at 0x0 LR is at omap34xx_do_sram_idle+0x8/0x10 This is a branch to 0x0, probably in omap34xx_cpu_suspend (in sleep34xx.S) which was just called by omap34xx_do_sram_idle. My first guess would be that the omap3_do_wfi_sram address is zero. Can you dump the value in omap_push_sram_idle()? If that looks good, do you have a debugger setup so you can single step into omap34xx_cpu_suspend() to find out where this is failing? Thank you for pointing me in the right direction. My board code was not calling omap_sdrc_init(...), which in turns calls omap_sram_init, where all the sram pushing takes place. Now I safely boot to userspace, but have random crashes when waking up from idle, where random refers to the oops log, not the occurence. I suspect memory corruption problem, which could be due to ddr going into self refresh, right ? Currently I call omap_sdrc_init with NULL arguments, but a lot of boards do the same thing. How are the omap_sdrc_init args related to self refreh ? In other words, if ddr parameters are correctly set in x-loader, do I also need omap_sdrc_params in linux for idle to work ? Regards, Jean-Philippe François -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: DM3730 without PMIC oops on idle
jean-philippe francois jp.franc...@cynove.com writes: Hi, My board does not have any Power Management IC. Without the following patch, the bood ends with an oops. How can I further debug this, ie trace through the assembly in arch/arm/mach-omap2/sleep34xx.S ? The assembly code that is faulting has nothing to do with interaction with the PMIC. Some more comments below ... -- Patch needed to boot to userspace : Index: linux-3.4.3/arch/arm/mach-omap2/pm34xx.c === --- linux-3.4.3.orig/arch/arm/mach-omap2/pm34xx.c 2012-06-17 20:21:44.0 +0200 +++ linux-3.4.3/arch/arm/mach-omap2/pm34xx.c 2012-06-22 16:26:38.0 +0200 @@ -403,7 +403,7 @@ trace_power_start(POWER_CSTATE, 1, smp_processor_id()); trace_cpu_idle(1, smp_processor_id()); - omap_sram_idle(); + // omap_sram_idle(); FYI... you can get the same effect without patching the kernel by adding 'nohlt' to the kernel command line. That avoids entering the idle loop alltogether. trace_power_end(smp_processor_id()); trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); -- Bootlog without patch : Booting Linux on physical CPU 0 Linux version 3.4.3 (cynove@jp) (gcc version 4.3.2 (Sourcery G++ Lite 2008q3-41) ) #2 PREEMPT Fri Jun 22 16:33:06 CEST 2012 CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7d CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache Machine: Cynove CYDM3730 Reserving 4194304 bytes SDRAM for VRAM Memory policy: ECC disabled, Data cache writeback OMAP3630 ES1.2 (l2cache iva sgx neon isp 192mhz_clk ) Clocking rate (Crystal/Core/MPU): 19.2/400/832 MHz Built 1 zonelists in Zone order, mobility grouping on. Total pages: 45056 Kernel command line: console=ttyO2,115200n8 rdinit=/sbin/init initrd=0x8300,1536k mtdparts=omap2-nand.0:1024k(bootloaders),3072k(linux),1536k(ramfs),-(usr) ubi.mtd=3,2048 mem=55M@0x8000 mem=128M@0x8800 PID hash table entries: 1024 (order: 0, 4096 bytes) Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) Memory: 55MB 123MB = 178MB total Memory: 174688k/174688k available, 12704k reserved, 0K highmem Virtual kernel memory layout: vector : 0x - 0x1000 ( 4 kB) fixmap : 0xfff0 - 0xfffe ( 896 kB) vmalloc : 0xd080 - 0xff00 ( 744 MB) lowmem : 0xc000 - 0xd000 ( 256 MB) modules : 0xbf00 - 0xc000 ( 16 MB) .text : 0xc0008000 - 0xc03c5080 (3829 kB) .init : 0xc03c6000 - 0xc03ef000 ( 164 kB) .data : 0xc03f - 0xc042b6c8 ( 238 kB) .bss : 0xc042b6ec - 0xc043bdc8 ( 66 kB) NR_IRQS:440 IRQ: Found an INTC at 0xfa20 (revision 4.0) with 96 interrupts Total of 96 interrupts on 1 active controller OMAP clockevent source: GPTIMER1 at 32768 Hz sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms Console: colour dummy device 80x30 Calibrating delay loop... 831.32 BogoMIPS (lpj=3246080) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok Setting up static identity map for 0x802ad4b0 - 0x802ad508 devtmpfs: initialized dummy: NET: Registered protocol family 16 GPMC revision 5.0 gpiochip_add: registered GPIOs 0 to 31 on device: gpio OMAP GPIO hardware version 2.5 gpiochip_add: registered GPIOs 32 to 63 on device: gpio gpiochip_add: registered GPIOs 64 to 95 on device: gpio gpiochip_add: registered GPIOs 96 to 127 on device: gpio gpiochip_add: registered GPIOs 128 to 159 on device: gpio gpiochip_add: registered GPIOs 160 to 191 on device: gpio omap_mux_init: Add partition: #1: core, flags: 0 GPMC CS4: cs_on : 2 ticks, 10 ns (was 1 ticks) 10 ns GPMC CS4: cs_rd_off : 12 ticks, 60 ns (was 16 ticks) 60 ns GPMC CS4: cs_wr_off : 12 ticks, 60 ns (was 16 ticks) 60 ns GPMC CS4: adv_on: 0 ticks, 0 ns (was 1 ticks) 0 ns GPMC CS4: adv_rd_off: 0 ticks, 0 ns (was 2 ticks) 0 ns GPMC CS4: adv_wr_off: 0 ticks, 0 ns (was 2 ticks) 0 ns GPMC CS4: oe_on : 2 ticks, 10 ns (was 3 ticks) 10 ns GPMC CS4: oe_off: 12 ticks, 60 ns (was 16 ticks) 60 ns GPMC CS4: we_on : 2 ticks, 10 ns (was 3 ticks) 10 ns GPMC CS4: we_off: 12 ticks, 60 ns (was 16 ticks) 60 ns GPMC CS4: rd_cycle : 14 ticks, 70 ns (was 17 ticks) 70 ns GPMC CS4: wr_cycle : 14 ticks, 70 ns (was 17 ticks) 70 ns GPMC CS4: access: 12 ticks, 60 ns (was 15 ticks) 60 ns GPMC CS4: page_burst_access: 0 ticks, 0 ns (was 1 ticks) 0 ns GPMC CS4: wr_data_mux_bus: 0 ticks, 0 ns (was 3 ticks) 0 ns GPMC CS4: wr_access : 2 ticks, 10 ns (was 15 ticks) 10 ns OMAP DMA hardware revision 5.0 bio: create slab bio-0 at 0 SCSI subsystem initialized omap2_mcspi omap2_mcspi.1: master is unqueued,
DM3730 without PMIC oops on idle
Hi, My board does not have any Power Management IC. Without the following patch, the bood ends with an oops. How can I further debug this, ie trace through the assembly in arch/arm/mach-omap2/sleep34xx.S ? -- Patch needed to boot to userspace : Index: linux-3.4.3/arch/arm/mach-omap2/pm34xx.c === --- linux-3.4.3.orig/arch/arm/mach-omap2/pm34xx.c 2012-06-17 20:21:44.0 +0200 +++ linux-3.4.3/arch/arm/mach-omap2/pm34xx.c2012-06-22 16:26:38.0 +0200 @@ -403,7 +403,7 @@ trace_power_start(POWER_CSTATE, 1, smp_processor_id()); trace_cpu_idle(1, smp_processor_id()); - omap_sram_idle(); + // omap_sram_idle(); trace_power_end(smp_processor_id()); trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); -- Bootlog without patch : Booting Linux on physical CPU 0 Linux version 3.4.3 (cynove@jp) (gcc version 4.3.2 (Sourcery G++ Lite 2008q3-41) ) #2 PREEMPT Fri Jun 22 16:33:06 CEST 2012 CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7d CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache Machine: Cynove CYDM3730 Reserving 4194304 bytes SDRAM for VRAM Memory policy: ECC disabled, Data cache writeback OMAP3630 ES1.2 (l2cache iva sgx neon isp 192mhz_clk ) Clocking rate (Crystal/Core/MPU): 19.2/400/832 MHz Built 1 zonelists in Zone order, mobility grouping on. Total pages: 45056 Kernel command line: console=ttyO2,115200n8 rdinit=/sbin/init initrd=0x8300,1536k mtdparts=omap2-nand.0:1024k(bootloaders),3072k(linux),1536k(ramfs),-(usr) ubi.mtd=3,2048 mem=55M@0x8000 mem=128M@0x8800 PID hash table entries: 1024 (order: 0, 4096 bytes) Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) Memory: 55MB 123MB = 178MB total Memory: 174688k/174688k available, 12704k reserved, 0K highmem Virtual kernel memory layout: vector : 0x - 0x1000 ( 4 kB) fixmap : 0xfff0 - 0xfffe ( 896 kB) vmalloc : 0xd080 - 0xff00 ( 744 MB) lowmem : 0xc000 - 0xd000 ( 256 MB) modules : 0xbf00 - 0xc000 ( 16 MB) .text : 0xc0008000 - 0xc03c5080 (3829 kB) .init : 0xc03c6000 - 0xc03ef000 ( 164 kB) .data : 0xc03f - 0xc042b6c8 ( 238 kB) .bss : 0xc042b6ec - 0xc043bdc8 ( 66 kB) NR_IRQS:440 IRQ: Found an INTC at 0xfa20 (revision 4.0) with 96 interrupts Total of 96 interrupts on 1 active controller OMAP clockevent source: GPTIMER1 at 32768 Hz sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms Console: colour dummy device 80x30 Calibrating delay loop... 831.32 BogoMIPS (lpj=3246080) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok Setting up static identity map for 0x802ad4b0 - 0x802ad508 devtmpfs: initialized dummy: NET: Registered protocol family 16 GPMC revision 5.0 gpiochip_add: registered GPIOs 0 to 31 on device: gpio OMAP GPIO hardware version 2.5 gpiochip_add: registered GPIOs 32 to 63 on device: gpio gpiochip_add: registered GPIOs 64 to 95 on device: gpio gpiochip_add: registered GPIOs 96 to 127 on device: gpio gpiochip_add: registered GPIOs 128 to 159 on device: gpio gpiochip_add: registered GPIOs 160 to 191 on device: gpio omap_mux_init: Add partition: #1: core, flags: 0 GPMC CS4: cs_on : 2 ticks, 10 ns (was 1 ticks) 10 ns GPMC CS4: cs_rd_off : 12 ticks, 60 ns (was 16 ticks) 60 ns GPMC CS4: cs_wr_off : 12 ticks, 60 ns (was 16 ticks) 60 ns GPMC CS4: adv_on: 0 ticks, 0 ns (was 1 ticks) 0 ns GPMC CS4: adv_rd_off: 0 ticks, 0 ns (was 2 ticks) 0 ns GPMC CS4: adv_wr_off: 0 ticks, 0 ns (was 2 ticks) 0 ns GPMC CS4: oe_on : 2 ticks, 10 ns (was 3 ticks) 10 ns GPMC CS4: oe_off: 12 ticks, 60 ns (was 16 ticks) 60 ns GPMC CS4: we_on : 2 ticks, 10 ns (was 3 ticks) 10 ns GPMC CS4: we_off: 12 ticks, 60 ns (was 16 ticks) 60 ns GPMC CS4: rd_cycle : 14 ticks, 70 ns (was 17 ticks) 70 ns GPMC CS4: wr_cycle : 14 ticks, 70 ns (was 17 ticks) 70 ns GPMC CS4: access: 12 ticks, 60 ns (was 15 ticks) 60 ns GPMC CS4: page_burst_access: 0 ticks, 0 ns (was 1 ticks) 0 ns GPMC CS4: wr_data_mux_bus: 0 ticks, 0 ns (was 3 ticks) 0 ns GPMC CS4: wr_access : 2 ticks, 10 ns (was 15 ticks) 10 ns OMAP DMA hardware revision 5.0 bio: create slab bio-0 at 0 SCSI subsystem initialized omap2_mcspi omap2_mcspi.1: master is unqueued, this is deprecated omap2_mcspi omap2_mcspi.2: master is unqueued, this is deprecated omap2_mcspi omap2_mcspi.3: master is unqueued, this is deprecated omap2_mcspi omap2_mcspi.4: master is unqueued, this is deprecated omap_i2c omap_i2c.1: bus 1 rev1.4.0 at 100 kHz Linux media interface: v0.10 Linux video capture interface: v2.00 omap-iommu omap-iommu.0: isp registered Switching to clocksource 32k_counter NET:
