RE: [PATCH 5/6] save and restore etm state across core OFF modes
Hi,
> > + bne debug_restore /* loop till done */
> > + str r5, [r6, #ETMMR_OSSRR] /* clear lock */
I had informed Alexander about the missing OSLAR to clear the lock and also
the do_etm_save value does not retain across coreoff since sram size may vary
across coreoffs. We need to save this do_etm_save value to sdram along with the
jtag etm debug context and restore it to do_etm_save.
Thanks
Gowda
From: Eduardo Valentin [eduardo.valen...@nokia.com]
Sent: Wednesday, October 06, 2010 2:22 PM
To: Valentin Eduardo (Nokia-MS/Helsinki)
Cc: ext virtu...@slind.org; t...@atomide.com; linux-omap@vger.kernel.org;
khil...@deeprootsystems.com; r-woodru...@ti.com; Gowda Madhusudhan.1
(EXT-Elektrobit/Helsinki)
Subject: Re: [PATCH 5/6] save and restore etm state across core OFF modes
Hey,
I think Gowda had also some thoughts about this patch. Cc'ing him.
BR,
On Wed, Oct 06, 2010 at 10:35:09AM +0200, Valentin Eduardo (Nokia-D/Helsinki)
wrote:
> Hello Alexander,
>
> Few points as follows,
>
> On Sat, May 01, 2010 at 07:38:20PM +0200, ext virtu...@slind.org wrote:
> > From: Alexander Shishkin
> >
> > This prevents ETM stalls whenever core enters OFF mode. Original patch
> > author is Richard Woodruff .
> >
> > This version of the patch makes use of the ETM OS save/restore mechanism,
> > which takes about 55 words in omap3_arm_context[] instead of 128. Also,
> > saving ETM context can be switched on/off at runtime.
> >
> > Signed-off-by: Alexander Shishkin
> > CC: Richard Woodruff
> > ---
> > arch/arm/mach-omap2/Kconfig |9 ++
> > arch/arm/mach-omap2/control.c |2 +-
> > arch/arm/mach-omap2/sleep34xx.S | 135
> > +
> > arch/arm/plat-omap/include/plat/control.h |2 +-
> > 4 files changed, 146 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> > index 2455dcc..5460bfe 100644
> > --- a/arch/arm/mach-omap2/Kconfig
> > +++ b/arch/arm/mach-omap2/Kconfig
> > @@ -150,6 +150,15 @@ config MACH_OMAP_4430SDP
> > bool "OMAP 4430 SDP board"
> > depends on ARCH_OMAP4
> >
> > +config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> > + bool "Enable hardware emulation context save and restore"
> > + depends on ARCH_OMAP3
> > + default y
> > + help
> > + This option enables JTAG & ETM debugging across power states.
> > + With out this option emulation features are reset across OFF
> > + mode state changes.
> > +
> > config OMAP3_EMU
> > bool "OMAP3 debugging peripherals"
> > depends on ARCH_OMAP3
> > diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> > index 43f8a33..70b1674 100644
> > --- a/arch/arm/mach-omap2/control.c
> > +++ b/arch/arm/mach-omap2/control.c
> > @@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
> > * The address is stored in scratchpad, so that it can be used
> > * during the restore path.
> > */
> > -u32 omap3_arm_context[128];
> > +u32 omap3_arm_context[256];
> >
> > struct omap3_control_regs {
> > u32 sysconfig;
> > diff --git a/arch/arm/mach-omap2/sleep34xx.S
> > b/arch/arm/mach-omap2/sleep34xx.S
> > index d522cd7..cd6a1d4 100644
> > --- a/arch/arm/mach-omap2/sleep34xx.S
> > +++ b/arch/arm/mach-omap2/sleep34xx.S
> > @@ -28,6 +28,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include "cm.h"
> > #include "prm.h"
> > @@ -226,6 +227,18 @@ loop:
> > nop
> > bl wait_sdrc_ok
> >
> > +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> > + /*
> > +* Restore Coresight debug registers
> > +*/
> > + ldr r6, debug_vbase /* base Vaddr of CortexA8-Debug */
> > + ldr r4, debug_xlar_key /* get lock key for OSLAR */
> > + bl unlock_debug/* remove global lock if set */
> > + ldr r6, etm_vbase /* base Vaddr of ETM */
> > + bl unlock_debug/* remove global lock if set */
> > + str r6, [r6, #ETMMR_OSLAR] /* clear OSLAR lock using non-key */
> > +#endif
> > +
> > ldmfd sp!, {r0-r12, pc} @ restore regs and return
> > restore_es3:
> > /*b restore_es3*/ @ Enable to debug restore code
> > @@ -385,6 +398,44 @@ logic_l1_restore:
> > /*normal memory remap register */
> > MCR p15, 0, r5, c10, c2, 1
>
Re: [PATCH 5/6] save and restore etm state across core OFF modes
Hey,
I think Gowda had also some thoughts about this patch. Cc'ing him.
BR,
On Wed, Oct 06, 2010 at 10:35:09AM +0200, Valentin Eduardo (Nokia-D/Helsinki)
wrote:
> Hello Alexander,
>
> Few points as follows,
>
> On Sat, May 01, 2010 at 07:38:20PM +0200, ext virtu...@slind.org wrote:
> > From: Alexander Shishkin
> >
> > This prevents ETM stalls whenever core enters OFF mode. Original patch
> > author is Richard Woodruff .
> >
> > This version of the patch makes use of the ETM OS save/restore mechanism,
> > which takes about 55 words in omap3_arm_context[] instead of 128. Also,
> > saving ETM context can be switched on/off at runtime.
> >
> > Signed-off-by: Alexander Shishkin
> > CC: Richard Woodruff
> > ---
> > arch/arm/mach-omap2/Kconfig |9 ++
> > arch/arm/mach-omap2/control.c |2 +-
> > arch/arm/mach-omap2/sleep34xx.S | 135
> > +
> > arch/arm/plat-omap/include/plat/control.h |2 +-
> > 4 files changed, 146 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> > index 2455dcc..5460bfe 100644
> > --- a/arch/arm/mach-omap2/Kconfig
> > +++ b/arch/arm/mach-omap2/Kconfig
> > @@ -150,6 +150,15 @@ config MACH_OMAP_4430SDP
> > bool "OMAP 4430 SDP board"
> > depends on ARCH_OMAP4
> >
> > +config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> > + bool "Enable hardware emulation context save and restore"
> > + depends on ARCH_OMAP3
> > + default y
> > + help
> > + This option enables JTAG & ETM debugging across power states.
> > + With out this option emulation features are reset across OFF
> > + mode state changes.
> > +
> > config OMAP3_EMU
> > bool "OMAP3 debugging peripherals"
> > depends on ARCH_OMAP3
> > diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> > index 43f8a33..70b1674 100644
> > --- a/arch/arm/mach-omap2/control.c
> > +++ b/arch/arm/mach-omap2/control.c
> > @@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
> > * The address is stored in scratchpad, so that it can be used
> > * during the restore path.
> > */
> > -u32 omap3_arm_context[128];
> > +u32 omap3_arm_context[256];
> >
> > struct omap3_control_regs {
> > u32 sysconfig;
> > diff --git a/arch/arm/mach-omap2/sleep34xx.S
> > b/arch/arm/mach-omap2/sleep34xx.S
> > index d522cd7..cd6a1d4 100644
> > --- a/arch/arm/mach-omap2/sleep34xx.S
> > +++ b/arch/arm/mach-omap2/sleep34xx.S
> > @@ -28,6 +28,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include "cm.h"
> > #include "prm.h"
> > @@ -226,6 +227,18 @@ loop:
> > nop
> > bl wait_sdrc_ok
> >
> > +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> > + /*
> > +* Restore Coresight debug registers
> > +*/
> > + ldr r6, debug_vbase /* base Vaddr of CortexA8-Debug */
> > + ldr r4, debug_xlar_key /* get lock key for OSLAR */
> > + bl unlock_debug/* remove global lock if set */
> > + ldr r6, etm_vbase /* base Vaddr of ETM */
> > + bl unlock_debug/* remove global lock if set */
> > + str r6, [r6, #ETMMR_OSLAR] /* clear OSLAR lock using non-key */
> > +#endif
> > +
> > ldmfd sp!, {r0-r12, pc} @ restore regs and return
> > restore_es3:
> > /*b restore_es3*/ @ Enable to debug restore code
> > @@ -385,6 +398,44 @@ logic_l1_restore:
> > /*normal memory remap register */
> > MCR p15, 0, r5, c10, c2, 1
> >
> > +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> > + /*
> > +* Restore Coresight debug registers
> > +*/
> > + ldr r6, debug_pbase /* base paddr of CortexA8-Debug */
> > + ldr r4, debug_xlar_key /* get lock key for OSLAR */
> > + bl unlock_debug/* remove global lock if set */
> > + str r4, [r6, #ETMMR_OSLAR] /* reset-pointer (already locked) */
> > + ldr r4, [r6, #ETMMR_OSSRR] /* dummy read */
> > + ldr r4, [r3], #4/* load save size */
> > + cmp r4, #0 /* check for zero */
> > +debug_restore:
> > + itttne /* t2/compat if-then block */
> > + ldrne r5, [r3], #4/* get saved value */
> > + strne r5, [r6,#ETMMR_OSSRR] /* restore saved value */
> > + subnes r4, r4, #1 /* decrement loop */
> > + bne debug_restore /* loop till done */
> > + str r5, [r6, #ETMMR_OSSRR] /* clear lock */
>
> Maybe you mean ETMMR_OSLAR?
>
> > + /*
> > +* Restore CoreSight ETM registers
> > +*/
> > + ldr r6, etm_pbase /* base paddr of ETM */
> > + ldr r4, debug_xlar_key /* get lock key for OSLAR */
> > + bl unlock_debug/* remove global lock if set */
> > + str r4, [r6, #ETMMR_OSLAR] /* reset-pointer (already locked) */
> > + ldr r4, [r6, #ETMMR_OSSRR] /* dummy read */
> > + ldr r4, [r3],
Re: [PATCH 5/6] save and restore etm state across core OFF modes
Hello Alexander,
Few points as follows,
On Sat, May 01, 2010 at 07:38:20PM +0200, ext virtu...@slind.org wrote:
> From: Alexander Shishkin
>
> This prevents ETM stalls whenever core enters OFF mode. Original patch
> author is Richard Woodruff .
>
> This version of the patch makes use of the ETM OS save/restore mechanism,
> which takes about 55 words in omap3_arm_context[] instead of 128. Also,
> saving ETM context can be switched on/off at runtime.
>
> Signed-off-by: Alexander Shishkin
> CC: Richard Woodruff
> ---
> arch/arm/mach-omap2/Kconfig |9 ++
> arch/arm/mach-omap2/control.c |2 +-
> arch/arm/mach-omap2/sleep34xx.S | 135
> +
> arch/arm/plat-omap/include/plat/control.h |2 +-
> 4 files changed, 146 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 2455dcc..5460bfe 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -150,6 +150,15 @@ config MACH_OMAP_4430SDP
> bool "OMAP 4430 SDP board"
> depends on ARCH_OMAP4
>
> +config ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> + bool "Enable hardware emulation context save and restore"
> + depends on ARCH_OMAP3
> + default y
> + help
> + This option enables JTAG & ETM debugging across power states.
> + With out this option emulation features are reset across OFF
> + mode state changes.
> +
> config OMAP3_EMU
> bool "OMAP3 debugging peripherals"
> depends on ARCH_OMAP3
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index 43f8a33..70b1674 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -93,7 +93,7 @@ void *omap3_secure_ram_storage;
> * The address is stored in scratchpad, so that it can be used
> * during the restore path.
> */
> -u32 omap3_arm_context[128];
> +u32 omap3_arm_context[256];
>
> struct omap3_control_regs {
> u32 sysconfig;
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index d522cd7..cd6a1d4 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -28,6 +28,7 @@
> #include
> #include
> #include
> +#include
>
> #include "cm.h"
> #include "prm.h"
> @@ -226,6 +227,18 @@ loop:
> nop
> bl wait_sdrc_ok
>
> +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> + /*
> + * Restore Coresight debug registers
> + */
> + ldr r6, debug_vbase /* base Vaddr of CortexA8-Debug */
> + ldr r4, debug_xlar_key /* get lock key for OSLAR */
> + bl unlock_debug/* remove global lock if set */
> + ldr r6, etm_vbase /* base Vaddr of ETM */
> + bl unlock_debug/* remove global lock if set */
> + str r6, [r6, #ETMMR_OSLAR] /* clear OSLAR lock using non-key */
> +#endif
> +
> ldmfd sp!, {r0-r12, pc} @ restore regs and return
> restore_es3:
> /*b restore_es3*/ @ Enable to debug restore code
> @@ -385,6 +398,44 @@ logic_l1_restore:
> /*normal memory remap register */
> MCR p15, 0, r5, c10, c2, 1
>
> +#ifdef CONFIG_ENABLE_OFF_MODE_JTAG_ETM_DEBUG
> + /*
> + * Restore Coresight debug registers
> + */
> + ldr r6, debug_pbase /* base paddr of CortexA8-Debug */
> + ldr r4, debug_xlar_key /* get lock key for OSLAR */
> + bl unlock_debug/* remove global lock if set */
> + str r4, [r6, #ETMMR_OSLAR] /* reset-pointer (already locked) */
> + ldr r4, [r6, #ETMMR_OSSRR] /* dummy read */
> + ldr r4, [r3], #4/* load save size */
> + cmp r4, #0 /* check for zero */
> +debug_restore:
> + itttne /* t2/compat if-then block */
> + ldrne r5, [r3], #4/* get saved value */
> + strne r5, [r6,#ETMMR_OSSRR] /* restore saved value */
> + subnes r4, r4, #1 /* decrement loop */
> + bne debug_restore /* loop till done */
> + str r5, [r6, #ETMMR_OSSRR] /* clear lock */
Maybe you mean ETMMR_OSLAR?
> + /*
> + * Restore CoreSight ETM registers
> + */
> + ldr r6, etm_pbase /* base paddr of ETM */
> + ldr r4, debug_xlar_key /* get lock key for OSLAR */
> + bl unlock_debug/* remove global lock if set */
> + str r4, [r6, #ETMMR_OSLAR] /* reset-pointer (already locked) */
> + ldr r4, [r6, #ETMMR_OSSRR] /* dummy read */
> + ldr r4, [r3], #4/* load save size */
> + cmp r4, #0 /* check for zero */
> + beq etm_skip
> +etm_restore:
> + ldrne r5, [r3], #4/* get saved value */
> + strne r5, [r6, #ETMMR_OSSRR] /* restore saved value */
> + subnes r4, r4, #1 /*
