RE: [PATCH 1/3] OMAP4: Add L2 Cache support
> > Since this code was used only ones in init, I haven't converted it to
> > function. With clobber list as well as you know adding r12 to clobber
> > list, compiler don't generate the save code and r11 can't be added to
> > clobber list.
>
> Well, we seem to have two places with the same code structure. Let's
> pull them together into a common function, such as:
>
> void omap_smc1(u32 fn, u32 arg)
> {
> register u32 r12 asm("r12") = fn;
> register u32 r0 asm("r0") = arg;
> asm volatile(
> "str r11, [sp], #-4\n"
> "dsb\n"
> "smc\n"
> "ldr r11, [sp, #4]!"
> : "+r" (r0), "+r" (r12)
> :
> : "r0-r10", "lr", "cc");
> }
> EXPORT_SYMBOL(omap_smc1);
>
> The code there probably may not be Thumb-2 compatible.
I will re-arrange the series and sent combined the errata + l2 support
with above change since dependency.
Regards,
Santosh
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Re: [PATCH 1/3] OMAP4: Add L2 Cache support
* Santosh Shilimkar [100129 03:44]:
> This patch adds L2 Cache support for OMAP4. External L2 cache
> is used in OMPA4
>
> Signed-off-by: Santosh Shilimkar
> ---
> arch/arm/mach-omap2/board-4430sdp.c| 33
>
> arch/arm/mm/Kconfig|2 +-
> arch/arm/plat-omap/include/plat/omap44xx.h |1 +
> 3 files changed, 35 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-4430sdp.c
> b/arch/arm/mach-omap2/board-4430sdp.c
> index 0c6be6b..194d633 100644
> --- a/arch/arm/mach-omap2/board-4430sdp.c
> +++ b/arch/arm/mach-omap2/board-4430sdp.c
> @@ -28,6 +28,7 @@
> #include
> #include
> #include
> +#include
>
> static struct platform_device sdp4430_lcd_device = {
> .name = "sdp4430_lcd",
> @@ -49,6 +50,38 @@ static struct omap_lcd_config sdp4430_lcd_config
> __initdata = {
> static struct omap_board_config_kernel sdp4430_config[] __initdata = {
> { OMAP_TAG_LCD, &sdp4430_lcd_config },
> };
> +#ifdef CONFIG_CACHE_L2X0
> +static int __init omap_l2_cache_init(void)
> +{
> + void __iomem *l2cache_base;
Since this is an initcall, you need to return here early to avoid
running on other omaps:
if (!cpu_is_omap44xx())
return -ENODEV;
> +
> + /* Static mapping, never released */
> + l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
> + BUG_ON(!l2cache_base);
> +
> + /* Enable L2 Cache using secure api
> + * r0 contains the value to be modified and "r12" contains
> + * the monitor API number. This API uses few CPU registers
> + * internally and hence they need be backed up including
> + * link register "lr".
> + */
> + __asm__ __volatile__(
> + "stmfd r13!, {r0-r12, r14}\n"
> + "mov r0, #1\n"
> + "ldr r12, =0x102\n"
> + "dsb\n"
> + "smc\n"
> + "ldmfd r13!, {r0-r12, r14}");
> +
> + /* 32KB way size, 16-way associativity,
> + * parity disabled
> + */
> + l2x0_init(l2cache_base, 0x0e05, 0xcfff);
> +
> + return 0;
> +}
> +early_initcall(omap_l2_cache_init);
> +#endif
Regards,
Tony
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Re: [PATCH 1/3] OMAP4: Add L2 Cache support
On Fri, Jan 29, 2010 at 05:56:55PM +0530, Shilimkar, Santosh wrote:
> Thanks for quick comment.
> > -Original Message-
> > From: Catalin Marinas [mailto:catalin.mari...@arm.com]
> > Sent: Friday, January 29, 2010 5:46 PM
> > To: Shilimkar, Santosh
> > Cc: t...@atomide.com; linux-arm-ker...@lists.infradead.org;
> > r...@arm.linux.org.uk; linux-
> > o...@vger.kernel.org
> > Subject: Re: [PATCH 1/3] OMAP4: Add L2 Cache support
> >
> > On Fri, 2010-01-29 at 11:46 +, Santosh Shilimkar wrote:
> > > +#ifdef CONFIG_CACHE_L2X0
> > > +static int __init omap_l2_cache_init(void)
> > > +{
> > > + void __iomem *l2cache_base;
> > > +
> > > + /* Static mapping, never released */
> > > + l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
> > > + BUG_ON(!l2cache_base);
> > > +
> > > + /* Enable L2 Cache using secure api
> > > +* r0 contains the value to be modified and "r12" contains
> > > +* the monitor API number. This API uses few CPU registers
> > > +* internally and hence they need be backed up including
> > > +* link register "lr".
> > > +*/
> > > + __asm__ __volatile__(
> > > + "stmfd r13!, {r0-r12, r14}\n"
> > > + "mov r0, #1\n"
> > > + "ldr r12, =0x102\n"
> > > + "dsb\n"
> > > + "smc\n"
> > > + "ldmfd r13!, {r0-r12, r14}");
> >
> > Same comments as on the cache-l2x0.c changes - can you not let the
> > compiler choose what to saved by declaring the clobbered register in the
> > asm directive?
>
> Since this code was used only ones in init, I haven't converted it to
> function. With clobber list as well as you know adding r12 to clobber
> list, compiler don't generate the save code and r11 can't be added to
> clobber list.
Well, we seem to have two places with the same code structure. Let's
pull them together into a common function, such as:
void omap_smc1(u32 fn, u32 arg)
{
register u32 r12 asm("r12") = fn;
register u32 r0 asm("r0") = arg;
asm volatile(
"str r11, [sp], #-4\n"
"dsb\n"
"smc\n"
"ldr r11, [sp, #4]!"
: "+r" (r0), "+r" (r12)
:
: "r0-r10", "lr", "cc");
}
EXPORT_SYMBOL(omap_smc1);
The code there probably may not be Thumb-2 compatible.
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RE: [PATCH 1/3] OMAP4: Add L2 Cache support
Thanks for quick comment.
> -Original Message-
> From: Catalin Marinas [mailto:catalin.mari...@arm.com]
> Sent: Friday, January 29, 2010 5:46 PM
> To: Shilimkar, Santosh
> Cc: t...@atomide.com; linux-arm-ker...@lists.infradead.org;
> r...@arm.linux.org.uk; linux-
> o...@vger.kernel.org
> Subject: Re: [PATCH 1/3] OMAP4: Add L2 Cache support
>
> On Fri, 2010-01-29 at 11:46 +, Santosh Shilimkar wrote:
> > --- a/arch/arm/mach-omap2/board-4430sdp.c
> > +++ b/arch/arm/mach-omap2/board-4430sdp.c
> > @@ -28,6 +28,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > static struct platform_device sdp4430_lcd_device = {
> > .name = "sdp4430_lcd",
> > @@ -49,6 +50,38 @@ static struct omap_lcd_config sdp4430_lcd_config
> > __initdata = {
> > static struct omap_board_config_kernel sdp4430_config[] __initdata = {
> > { OMAP_TAG_LCD, &sdp4430_lcd_config },
> > };
> > +#ifdef CONFIG_CACHE_L2X0
> > +static int __init omap_l2_cache_init(void)
> > +{
> > + void __iomem *l2cache_base;
> > +
> > + /* Static mapping, never released */
> > + l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
> > + BUG_ON(!l2cache_base);
> > +
> > + /* Enable L2 Cache using secure api
> > +* r0 contains the value to be modified and "r12" contains
> > +* the monitor API number. This API uses few CPU registers
> > +* internally and hence they need be backed up including
> > +* link register "lr".
> > +*/
> > + __asm__ __volatile__(
> > + "stmfd r13!, {r0-r12, r14}\n"
> > + "mov r0, #1\n"
> > + "ldr r12, =0x102\n"
> > + "dsb\n"
> > + "smc\n"
> > + "ldmfd r13!, {r0-r12, r14}");
>
> Same comments as on the cache-l2x0.c changes - can you not let the
> compiler choose what to saved by declaring the clobbered register in the
> asm directive?
Since this code was used only ones in init, I haven't converted it to function.
With clobber list
as well as you know adding r12 to clobber list, compiler don't generate the
save code
and r11 can't be added to clobber list.
But I can do the same change as I did in the "cache-l2x0.c" Will send updated
version.
Regards,
Santosh
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Re: [PATCH 1/3] OMAP4: Add L2 Cache support
On Fri, 2010-01-29 at 11:46 +, Santosh Shilimkar wrote:
> --- a/arch/arm/mach-omap2/board-4430sdp.c
> +++ b/arch/arm/mach-omap2/board-4430sdp.c
> @@ -28,6 +28,7 @@
> #include
> #include
> #include
> +#include
>
> static struct platform_device sdp4430_lcd_device = {
> .name = "sdp4430_lcd",
> @@ -49,6 +50,38 @@ static struct omap_lcd_config sdp4430_lcd_config
> __initdata = {
> static struct omap_board_config_kernel sdp4430_config[] __initdata = {
> { OMAP_TAG_LCD, &sdp4430_lcd_config },
> };
> +#ifdef CONFIG_CACHE_L2X0
> +static int __init omap_l2_cache_init(void)
> +{
> + void __iomem *l2cache_base;
> +
> + /* Static mapping, never released */
> + l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
> + BUG_ON(!l2cache_base);
> +
> + /* Enable L2 Cache using secure api
> +* r0 contains the value to be modified and "r12" contains
> +* the monitor API number. This API uses few CPU registers
> +* internally and hence they need be backed up including
> +* link register "lr".
> +*/
> + __asm__ __volatile__(
> + "stmfd r13!, {r0-r12, r14}\n"
> + "mov r0, #1\n"
> + "ldr r12, =0x102\n"
> + "dsb\n"
> + "smc\n"
> + "ldmfd r13!, {r0-r12, r14}");
Same comments as on the cache-l2x0.c changes - can you not let the
compiler choose what to saved by declaring the clobbered register in the
asm directive?
--
Catalin
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